Integrated deep trench capacitor with high capacitance density and voltage linearity

Abstract

The invention relates to an integrated deep trench capacitor with high capacitance density and voltage linearity. A microelectronic device (100) includes an integrated deep trench capacitor (102) in a substrate (104). The integrated deep trench capacitor (102) includes a plurality of trenches extending into the substrate (104), the trenches being filled with a conductive trench fill material (140). A first subset of the trenches (129) is located in the N-type well (114) and a second subset of the trenches (131) is located in the P-type well (118). A first capacitor terminal (186) connects the conductive trench filling material (140) in the first subset of trenches (129) with the conductive trench filling material (140) in the second subset of trenches (131). A second capacitor terminal (184) connects the N-type well (114) and the P-type well (118).

Description

Technical Field

[0001] The present disclosure relates to the field of microelectronic devices. More particularly, but not exclusively, the present disclosure relates to integrated capacitors in microelectronic devices. Background Art

[0002] Integrated capacitors are used in some microelectronic devices. Such capacitors, including deep trench capacitors, have capacitance-to-voltage (CV) characteristics that are typically somewhat nonlinear. In some applications, such nonlinearity may be undesirable. Summary of the invention

[0003] The present disclosure describes an integrated circuit that includes an integrated deep trench capacitor, hereinafter referred to as a "trench capacitor," in a substrate. The trench capacitor includes a plurality of deep trenches extending into the substrate, the trenches being filled with a conductive trench fill material. A first subset of the trenches is located in an N-type well, and a second subset of the trenches is located in a P-type well. A first capacitor terminal connects the conductive trench fill material in the first subset of trenches and the conductive trench fill material in the second subset of trenches. A second capacitor terminal connects the N-type well and the P-type well. Trench capacitors consistent with the present disclosure may provide improved linearity of capacitance to voltage compared to baseline trench capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figures 1A to 1J are cross-sections of an exemplary microelectronic device having a trench capacitor depicted at successive stages of an exemplary formation method.

[0005] Figure 2 A top view of a layout of a microelectronic device containing trench capacitors is disclosed.

[0006] Figure 3 Capacitance versus voltage (CV) characteristics of devices consistent with the described examples are shown.

[0007] Figure 4 An integrated circuit (IC) including a trench capacitor is shown. DETAILED DESCRIPTION

[0008] The present disclosure is described with reference to the accompanying drawings. The figures are not drawn to scale, and they are provided only for the purpose of illustrating the present disclosure. Several aspects of the present disclosure are described below with reference to exemplary applications for illustration. It should be understood that many specific details, relationships and methods are set forth to provide an understanding of the present disclosure. The present disclosure is not limited by the description order of actions or events, because some actions can occur in different orders and / or simultaneously with other actions or events. In addition, not all described actions or events are necessary for implementing the method according to the present disclosure.

[0009] In addition, although some of the examples described herein are shown in two-dimensional views of various regions with depth and width, it should be clearly understood that these regions are only illustrations of a portion of a device that is actually a three-dimensional structure. Therefore, when manufactured on an actual device, these regions will have three dimensions, including length, width, and depth. In addition, although the present disclosure is described by examples directed to active devices, these descriptions are not intended to limit the scope or applicability of the present disclosure. It is not intended to limit the active devices of the various described examples to the physical structures shown. These structures are included to demonstrate the practicality and application of various embodiments.

[0010] A microelectronic device is formed in and on a substrate having a semiconductor material. The microelectronic device includes a trench capacitor in the substrate. The trench capacitor consists of a first deep trench and a second deep trench. The first deep trench and the second deep trench are lined with a dielectric material. The first deep trench is in a first conductivity type region, the first conductivity type region forms a first bottom plate of a capacitor, and the first bottom plate of the capacitor is connected to a first capacitor terminal in a conductive manner. The second deep trench is in a second conductivity type region forming a second bottom plate of a capacitor, and the second bottom plate of the capacitor is connected to a second capacitor terminal in a conductive manner. In various examples, and as described below, the first conductivity type is p-type and the second conductivity type is n-type, while in other examples, the conductivity types are opposite, so that the first conductivity type is n-type and the second conductivity type is p-type. The conductive capacitor filling material in the first trench and the second trench forms a top plate of the capacitor. The top plate of the capacitor is electrically connected to the second capacitor terminal. The first capacitor terminal and the third capacitor terminal may be electrically in contact with each other, or the first capacitor terminal and the third capacitor terminal may be electrically isolated from each other. Advantageously, the first trench and the second trench have floors of opposite conductivity, as opposite conductivity may provide improved capacitor linearity for applied voltage.

[0011] The microelectronic device has a field oxide layer on the semiconductor material, the field oxide layer extending between the deep trenches. The field oxide layer also covers a portion of the trench fill material in each of the deep trenches, wherein a trench contact opening is located above the trench fill material in each deep trench. The trench fill material extends through each trench contact opening. A metal silicide layer is located on the trench fill material in each trench contact opening. A silicide barrier layer is located above the field oxide layer and overlaps the capacitor dielectric layer. The silicide barrier layer does not contain a metal silicide layer. The trench capacitor does not contain a metal silicide layer between the deep trenches.

[0012] It should be noted that terms such as top, over, on, below, and under may be used in the present disclosure. These terms should not be construed as limiting the position or orientation of structures or elements, but are used to provide spatial relationships between structures or elements.

[0013] Figures 1A to 1J is a cross-section of an exemplary microelectronic device 100 having a trench capacitor 102 depicted at successive stages of an exemplary formation method. Figure 1A , the microelectronic device 100 is formed in and on a substrate 106. In this example, the substrate 106 may include a base wafer 104, such as a silicon wafer. The base wafer 104 may have a first conductivity type, which in this example is a p-type, such as in Figure 1A In an alternative version of this example, the base wafer 104 may include a dielectric material, such as silicon dioxide or sapphire, to provide a silicon-on-insulator substrate. The substrate 106 of this example also includes a semiconductor material 108 formed on the base wafer 104. The semiconductor material 108 mainly includes silicon and may consist essentially of silicon and a dopant such as boron. The semiconductor material 108 may be an epitaxial layer and may be lightly doped, such as 10 15 to 10 16 cm -3 The semiconductor material 108 extends to a top surface 110 of the substrate 106, which is located on a surface of the semiconductor material 108 opposite the boundary between the semiconductor material 108 and the base wafer 104. In this example, the semiconductor material 108 may be doped with boron to have a first conductivity type, such as a P-type, as in Figure 1A For example, the semiconductor material 108 may be 5 μm to 15 μm thick.

[0014] A first buried layer 112 may be formed in the substrate 106. In the exemplary microelectronic device 100, the first buried layer 112 has a second conductivity type, such as an N-type. A second buried layer 116 may be formed in the substrate 106. The second buried layer has a first conductivity type, such as a P-type. The first buried layer 112 may be formed by implanting a dopant of a second conductivity type, such as phosphorus, arsenic, or antimony, into the substrate 106. The second buried layer 116 may be formed by implanting a dopant of a first conductivity type, such as boron or indium, into the substrate 106.

[0015] A first deep well 114 may be formed in the semiconductor material 108, the first deep well extending from the top surface 110 of the substrate 106 and contacting the first buried layer 112. The first deep well 114 has a second conductivity type. The first deep well 114 may be formed by implanting a second conductivity type dopant, such as phosphorus, into the semiconductor material 108, followed by a thermal drive to diffuse the implanted dopant into the first buried layer 112 and activate the implanted dopant. The first deep well 114 may have an average concentration of the second conductivity type dopant greater than twice the average concentration of the dopant in the semiconductor material 108 outside the first deep well 114.

[0016] A second deep well 118 may be formed in the semiconductor material 108, the second deep well extending from the top surface 110 of the substrate 106 and contacting the second buried layer 116. The second deep well 118 may have a first conductivity type. The second deep well 118 may be formed by implanting a dopant of the first conductivity type, such as boron or indium, into the semiconductor material 108, followed by a thermal drive to diffuse the implanted dopant into the second buried layer 116 and activate the implanted dopant. The second deep well 118 may have an average concentration of dopants of the first conductivity type greater than twice the average concentration of dopants in the semiconductor material 108 outside the second deep well 118.

[0017] refer to Figure 1B , a pad oxide layer 120 may be formed on the top surface 110 of the substrate 106. For example, the pad oxide layer 120 may mainly include silicon dioxide, may be formed by a thermal oxidation process or a thermal chemical vapor deposition (CVD) process, and may have a thickness of 50nm to 200nm. A nitride cap layer 122 may be formed on the pad oxide layer 120. The nitride cap layer 122 may mainly include silicon nitride, may be formed by a low pressure chemical vapor deposition (LPCVD) furnace process, and may have a thickness of 100nm to 500nm. A hard mask layer 124 may be formed on the nitride cap layer 122. The hard mask layer 124 may mainly include silicon dioxide, may be formed by a plasma enhanced chemical vapor deposition (PECVD) process, and may have a thickness of 1μm to 3μm. The pad oxide layer 120 may provide stress relief between the semiconductor material 108 and the combination of the nitride cap layer 122 and the hard mask layer 124. The nitride cap layer 122 may provide a stop layer for subsequent etching and planarization processes. The hard mask layer 124 may provide a hard mask during a subsequent deep trench etching process 130 to form a first deep trench 129 and a second deep trench 131 .

[0018] A resist layer 126 having deep trench openings 128 may be formed on the hard mask layer 124. The resist layer 126 may include photoresist and may optionally include an anti-reflective material such as a bottom anti-reflective coating (BARC). The resist layer 126 may be formed by a photolithography process.

[0019] A deep trench etching process 130 is performed to form a plurality of trenches, a first deep trench 129 being a subset of the plurality of trenches located in the first deep well 114, and a second deep trench 131 being a subset of the plurality of trenches located in the second deep well 118. The deep trench etching process 130 may include a plurality of steps. The first deep trench 129 extends from the top surface 110 into the first deep well 114 and the first buried layer 112, and is surrounded by doping of the first conductivity type. The second deep trench 131 extends from the top surface 110 into the second deep well 118 and the second buried layer 116, and may be located in the substrate 106 below the second buried layer 116. The second deep trench 131 is surrounded by doping of the second conductivity. Although the exemplary microelectronic device 100 describes an exemplary method of obtaining a first deep trench 129 surrounded by a doping of the second conductivity type and a second deep trench 131 surrounded by a doping of the first conductivity type, other methods of achieving equivalent doping of the semiconductor material 108 contacting the first deep trench 129 and the second deep trench 131 are also within the scope of the present disclosure.

[0020] refer to Figure 1C , a capacitor dielectric layer 132 is formed in the first deep trench 129 and the second deep trench 131, the capacitor dielectric layer contacting the semiconductor material 108 of the substrate 106. The capacitor dielectric layer 132 may extend over the hard mask layer 124, the nitride cap layer 122, and the pad oxide layer 120. The capacitor dielectric layer 132 includes a silicon nitride compound and may include silicon dioxide or other dielectric materials. In this example, the capacitor dielectric layer 132 may include an outer layer 134 contacting the semiconductor material 108 of the substrate 106, a center layer 136 on the outer layer 134, and an inner layer 138 on the center layer 136.

[0021] The outer layer 134 may include silicon dioxide and may be formed by a thermal oxidation process that oxidizes silicon in the substrate 106 at the surfaces of the first deep trench 129 and the second deep trench 131. The outer layer 134 may be at least 3 nm thick to provide low leakage current in the trench capacitor 102 during operation of the microelectronic device 100, and may be 6 nm to 10 nm thick, depending on the operating potential of the trench capacitor 102.

[0022] The core layer 136 includes a silicon-nitrogen compound, which can be implemented as silicon nitride or silicon oxynitride. The core layer 136 can be formed by a CVD process or an LPCVD process using a silicon-containing reagent gas and a nitrogen-containing reagent gas, which are not specifically shown. The silicon-containing reagent gas can be implemented as silane or dichlorosilane. The nitrogen-containing reagent gas can be implemented as ammonia or hydrazine. Alternatively, the silicon-containing reagent gas and the nitrogen-containing reagent gas can be implemented as bis(tert-butyl-amino)silane (BTBAS). The thickness of the core layer 136 can be selected to provide the desired capacitance density and breakdown potential for the trench capacitor 102. For example, the core layer 136 can be 12nm thick to provide a breakdown potential greater than 12 volts. In another version of this example, the core layer 136 can be 8nm to 40nm thick. Compared to a dielectric layer without a silicon-nitrogen compound, having a silicon-nitrogen compound in the capacitor dielectric layer 132 can advantageously provide higher reliability and higher operating potential.

[0023] The inner layer 138 may include primarily silicon dioxide or silicon oxynitride to reduce charge trapping in the capacitor dielectric layer 132 and to provide a Figure 1D 138 is formed by a CVD process or an LPCVD process using a silicon-containing reagent gas and an oxygen-containing reagent gas and optionally a nitrogen-containing reagent gas (if nitrogen is required to form the inner layer 138). The oxygen-containing reagent gas may be implemented as oxygen or nitrous oxide. Alternatively, the silicon-containing reagent gas and the oxygen-containing reagent gas may be implemented as tetraethoxysilane (TEOS), also known as tetraethyl orthosilicate. The inner layer 138 may have a thickness of 40nm to 60nm just after formation. A trench dielectric etching process (not specifically shown) may be performed after the inner layer 138 is formed to improve the thickness uniformity of the inner layer 138 along the sidewalls of the first deep trench 129 and the second deep trench 131.

[0024] refer to Figure 1D , a trench filling material 140 is formed in the first deep trench 129 and the second deep trench 131 on the capacitor dielectric layer 132. The trench filling material 140 is conductive. The trench filling material 140 mainly includes silicon, and can be implemented as polycrystalline silicon, which is generally referred to as polysilicon. Alternatively, the trench filling material 140 can be implemented as amorphous silicon, or semi-amorphous silicon. The trench filling material 140 can have a first conductivity type, which is p-type in this example, as in Figure 1D For example, the trench filling material 140 may have a 5×10 18 cm -3 and 1×10 20 cm -3 The average dopant concentration is 0.0447 W / m to provide a low equivalent series resistance for the trench capacitor 102.

[0025] The trench filling material 140 may be formed by thermal decomposition of a silicon-containing reagent gas containing a dopant. The trench filling material 140 fills the first deep trench 129 and the second deep trench 131 and may extend outside the first deep trench 129 and the second deep trench 131 over the substrate 106, such as Figure 1D Described in.

[0026] refer to Figure 1E , the trench filling material 140 and the capacitor dielectric layer 132 are removed from the outside of the first deep trench 129 and the second deep trench 131. The trench filling material 140 and the capacitor dielectric layer 132 may be removed by a planarization process such as a chemical mechanical polishing (CMP) process 146, such as in Figure 1E . Alternatively, the trench filling material 140 and the capacitor dielectric layer 132 may be removed by an etch-back process. The process of removing the trench filling material 140 and the capacitor dielectric layer 132 leaves the trench filling material 140 on the capacitor dielectric layer 132 in the first deep trench 129 and the second deep trench 131. The process of removing the trench filling material 140 and the capacitor dielectric layer 132 may leave the nitride capping layer 122 and the pad oxide layer 120 on the top surface 110 of the substrate 106. The nitride capping layer 122 may provide a stop layer for the CMP process 158. After removing the trench filling material 140 and the capacitor dielectric layer 132 from the outside of the first deep trench 129 and the second deep trench 131, the nitride capping layer 122 and the pad oxide layer 120 may be removed in a separate process. The trench filling material 140 remaining in the first deep trench 129 and the second deep trench 131 after the CMP process 158 is subsequently referred to as the first trench filling material 142 and the second trench filling material 144. Although the first trench filling material 142 and the second trench filling material 144 of the exemplary device are formed of a common trench filling material 140, it is within the scope of the present disclosure that the first trench filling material 142 and the second trench filling material 144 have different doping concentrations and conductivities.

[0027] refer to Figure 1F , a CMP stop layer 148 is formed over the top surface 110 of the substrate 106, the capacitor dielectric layer 132, and the trench filling material 140. The CMP stop layer 148 may include a silicon dioxide layer (not specifically shown) on the substrate 106, the capacitor dielectric layer 132, and the trench filling material 140, and a silicon nitride layer (not specifically shown) on the silicon dioxide layer. The silicon dioxide layer may be 5 nm to 20 nm thick and may be formed by a thermal oxidation process. The silicon nitride layer may be 100 nm to 200 nm thick and may be formed by a LPCVD process. Other material layers having a high CMP selectivity to silicon dioxide may replace the silicon nitride layer.

[0028] A field oxide mask 150 having a field oxide mask opening 154 is formed over the CMP stop layer 148, exposing the CMP stop layer 148 in areas for field oxide trenches, which are often referred to as shallow trenches or shallow trench isolation (STI) trenches. The field oxide mask 150 may include a photoresist and may be formed by a photolithography process. The CMP stop layer 148 exposed by the field oxide mask 150 is removed. A trench etching process 152 removes the semiconductor material 108 and material from the top of the first trench fill material 142 and the second trench fill material 144 in the areas exposed by the field oxide mask to form shallow trenches 155 in the substrate 106, the first trench fill material 142, and the second trench fill material 144. For example, the shallow trench 155 may extend to a depth of 250 nm to 1 μm in the semiconductor material 108 and to a depth of 200 nm to 800 nm in the first trench fill material 142 and the second trench fill material 144 .

[0029] The trench etching process 152 may be implemented as a two-step process, wherein a first etching step removes the CMP stop layer 148, and a second etching step removes the semiconductor material 108 and the trench filling material 140. For example, the first etching step may be implemented as a reactive ion etching (RIE) process using fluorine and oxygen. For example, the second etching step may be implemented as an RIE process using one or more halogens. The trench etching process 152 removes the capacitor dielectric layer 132 at a rate lower than the semiconductor material 108 and at a rate lower than the trench filling material 140, such that a portion 132a of the capacitor dielectric layer 132 extends into the shallow trench 155. A portion 108a of the semiconductor material 108 that contacts the portion 132a of the capacitor dielectric layer 132 may extend into the shallow trench 155 as a secondary result of the low etching rate of the capacitor dielectric layer 132. Portions 144a of trench fill material 140 that contact portions 132a of capacitor dielectric layer 132 may extend into shallow trenches 155 as another secondary result of the low etch rate of capacitor dielectric layer 132. After shallow trenches 155, field oxide mask 150 may be removed.

[0030] refer to Figure 1G , a field oxide layer 156 is formed in the shallow trench 155. The field oxide layer 156 may be planarized by a CMP process 158. The field oxide layer 156 may mainly include silicon dioxide or a silicon dioxide-based dielectric material, which is formed by one or more CVD processes alternating with an etch-back process to completely fill the shallow trench 155. After planarizing the field oxide layer 156, the CMP stop layer 148 is removed. In various examples, the field oxide layer 156 is an STI structure.

[0031] refer to Figure 1H, a silicide blocking layer 162 is formed over the top surface 110 of the substrate 106. The silicide blocking layer 162 may include one or more layers of silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric materials that are substantially non-reactive with the metal used to form the metal silicide, such as titanium, cobalt, nickel, or platinum. One or more of the portions 132a of the capacitor dielectric layer 132, along with one or more of the portions 108a of the semiconductor material 108, or one or more of the portions 142a of the first trench fill material 142, or both, may contact the silicide blocking layer 162, or may be separated from the silicide blocking layer 162 by less than 10 nm of silicon dioxide.

[0032] A silicide blocking mask 160 is formed over the silicide blocking layer 162, covering the silicide blocking layer 162 over the portion 132a of the capacitor dielectric layer 132, and exposing the silicide blocking layer 162 in areas for the first substrate contact region 166, the second substrate contact region 170, the first trench contact region 168, and the second trench contact region 172. The silicide blocking mask 160 may include a photoresist and may be formed by a photolithography process.

[0033] The silicide blocking layer 162 exposed by the silicide blocking mask 160 is removed, thereby leaving the silicide blocking layer 162 over the portion 132a of the capacitor dielectric layer 132. The silicide blocking layer 162 may be removed by an RIE process 164 using fluorine and optionally oxygen. After removing the silicide blocking layer 162 exposed by the silicide blocking mask 160, the silicide blocking mask 160 is removed.

[0034] refer to Fig. 1I The implant of the second conductivity type with energy and dosage similar to the source / drain implant forms the first substrate contact region 166 in the first deep well 114. For example, the first substrate contact region 166 may be N-type and may be heavily doped (e.g., 10 19 cm -3 The implant having the same conductivity as the first trench fill material 142 and having energy and dosage similar to the source / drain implant forms the first trench contact region 168 in the first trench fill material 142. For example, the first trench contact region 168 may be of P type and may be heavily doped (e.g., 10 19 cm -3 Similarly, an implant of the first conductivity type having an energy and a dose similar to the source / drain implant forms a second substrate contact region 170 in the second deep well 118. An implant having the same conductivity as the second trench fill material 144 and having an energy and a dose similar to the source / drain implant forms a second trench contact region 172 in the second trench fill material 144.

[0035] In some examples, a metal silicide layer 174 can be formed on the first substrate contact region 166, the first trench contact region 168, the second substrate contact region 170, and the second trench contact region 172. The metal silicide layer 174 can provide an ohmic electrical connection with the first substrate contact region 166, the first trench contact region 168, the second substrate contact region 170, and the second trench contact region 172, which reduces the lower resistance compared to a similar microelectronic device without the metal silicide layer 174.

[0036] refer to Figure 1J , a pre-metal dielectric (PMD) layer 176 is formed above the top surface 110 of the substrate 106. The PMD layer 176 may include one or more dielectric layers, such as silicon nitride, silicon oxynitride, silicon dioxide, etc. In some examples, the PMD layer 176 includes a PMD liner and a main dielectric proton layer formed on the PMD liner. Subsequently, the PMD layer 176 may be planarized by a CMP process. A contact 178, such as a tungsten plug, is formed in the PMD layer 174 to provide electrical connections to the first substrate contact area 166, the second substrate contact area 170, the first trench contact area 168, and the second trench contact area 172.

[0037] An interconnect 180 electrically connected to the contact 178 is formed over the PMD layer 176 using any suitable metallization scheme. The first trench contact region 168 and the second trench contact region 172 are connected to an interconnect trace 184 through the contact 178 and the interconnect 180, which provides a first terminal of the trench capacitor 102. The interconnect trace 182 electrically connected to the first substrate contact region 166 and the interconnect trace 186 electrically connected to the second substrate contact region 172 provide a second terminal of the trench capacitor 102. The interconnect trace 182 and the interconnect trace 186 can be similar to Figure 2 The interconnect traces 282 shown in FIG. 1 and 2 may be electrically connected, or the interconnect traces 182 and 186 may remain separate in applications where a three-terminal device is desired. Other components of the microelectronic device 100 may also be connected via the interconnect 180 .

[0038] Figure 2 A top view of a microelectronic device 200 is disclosed, the microelectronic device containing a trench capacitor 202 consistent with the trench capacitor 102. The trench capacitor 202 includes a field oxide layer 256 above the semiconductor material 208. A silicide block region 262 is above a portion of the capacitor dielectric layer 232a, and the silicide block region 262 extends into the field oxide layer 256 on both sides of the capacitor dielectric layer 232a. As shown in reference Figures 1A to 1JAs disclosed, the contact 278 and the interconnect trace 280 provide electrical connections between the first trench contact area 268, the second trench contact area 272, and the first terminal 284. The field oxide layer 256 includes a portion surrounding each of the contact areas 268, 272. In other examples not explicitly shown, the first trench contact area 268 can be connected to a first interconnect trace that can serve as one terminal, and the second trench contact area 272 can be connected to a second interconnect trace that can serve as another separate terminal. The additional contact 278 and the interconnect trace 280 provide electrical connections between the substrate contact area 266 and the second terminal 282.

[0039] Figure 3 CV characteristics of capacitors constructed according to the principles of the present disclosure are demonstrated. The characteristics demonstrate that the capacitance varies only about 0.1% over a range of about ±90 V, less than 500 ppm over a range of about ±50 V, and less than 10 ppm over a range of about ±5 V. This operating characteristic is a significant improvement over baseline trench capacitors and reduces the need for circuit resources that would otherwise be required to accommodate the large variability of capacitance with operating voltage.

[0040] Figure 4 An IC 400 including a trench capacitor 102 is shown. The IC 400 includes a semiconductor substrate 410, such as an epitaxial layer above a bulk silicon material 405. As previously described, the trench capacitor 102 is constructed within the semiconductor substrate 410. The IC 400 also includes an electrical component 430, such as a transistor extending into a well region of the semiconductor substrate 410. The component 430 represents any number of electrical components located above the semiconductor substrate 410, including transistors, resistors, capacitors, and / or inductors. Unreferenced vertical interconnects or contacts connect the terminals of the trench capacitor 102 to metal interconnect traces 420, which in turn connect to the terminals of the component 430. In some other examples, the interconnect traces may be implemented at the polysilicon level. The trench capacitor 102 and the component 430 are configured to cooperate to provide the electrical functions of the IC 400. The small variation in capacitance of the trench capacitor 102 with voltage advantageously provides stable characteristics of the integrated circuit at different operating voltages.

[0041] Although various examples of the present disclosure have been described above, it should be understood that the examples are presented only by way of example and not limitation. Without departing from the spirit or scope of the present disclosure, many changes may be made to the disclosed examples according to the disclosure herein. Therefore, the breadth and scope of the present invention should not be limited by any of the above examples. In fact, the scope of the present disclosure should be defined according to the attached claims and their equivalents.

Claims

1. An integrated circuit, comprising: An N-type well extending into the semiconductor substrate having a top surface; A P-type well extending into the semiconductor substrate; a plurality of trenches extending into the semiconductor substrate, the trenches being filled with a conductive trench filling material, a first subset of the trenches being located in the N-type well and a second subset of the trenches being located in the P-type well; a first capacitor terminal connected to the conductive trench fill material in the first subset of trenches and the conductive trench fill material in the second subset of trenches; as well as A second capacitor terminal is connected to the N-type well and the P-type well. 2 . The integrated circuit of claim 1 , wherein the N-type well is connected to an N-type buried layer.

3. The integrated circuit of claim 1, wherein the P-type well is connected to a P-type buried layer. 4 . The integrated circuit of claim 3 , wherein the second subset of trenches extends through the P-type buried layer to a lightly doped epitaxial layer.

5. The integrated circuit of claim 1, wherein the second subset of trenches extends through the P-type buried layer into the lightly doped epitaxial layer.

6. The integrated circuit of claim 1 , further comprising: a plurality of contacts each connected to the conductive trench fill material in a corresponding one of the trenches; and an isolation structure surrounding each of the contacts.

7. The integrated circuit of claim 1, wherein both the N-type well and the P-type well have an average dopant density greater than twice an average dopant concentration of the semiconductor substrate.

8. The integrated circuit of claim 1, wherein the first capacitor terminal or the second capacitor terminal is connected to a transistor terminal.

9. The integrated circuit of claim 1, wherein a capacitance between the first capacitor terminal and the second capacitor terminal varies by less than 500 ppm with a voltage across the first capacitor terminal and the second capacitor terminal in the range of -5V to +5V.

10. A method of forming an integrated circuit, comprising: forming an N-type well extending into a semiconductor substrate having a top surface; forming a P-type well, wherein the P-type well extends into the semiconductor substrate; forming a plurality of trenches extending into the semiconductor substrate, a first subset of the trenches being located in the N-type well and a second subset of the trenches being located in the P-type well; filling the trench with a conductive trench filling material; forming a first capacitor terminal connected to the conductive trench fill material in the first subset of trenches and the conductive trench fill material in the second subset of trenches; as well as A second capacitor terminal is formed, the second capacitor terminal being connected to the N-type well and the P-type well. The method according to claim 10 , wherein the N-type well is connected to an N-type buried layer. The method according to claim 10 , wherein the P-type well is connected to a P-type buried layer.

13. The method of claim 12, wherein the second subset of trenches extends through the P-type buried layer into the lightly doped epitaxial layer.

14. The method of claim 10, wherein the second subset of trenches extends through the P-type buried layer into the lightly doped epitaxial layer.

15. The method according to claim 10, further comprising: forming a plurality of contacts each connected to the conductive trench fill material in a corresponding one of the trenches; and forming an isolation structure surrounding each of the contacts. 16 . The method of claim 10 , wherein both the N-type well and the P-type well have an average dopant density greater than twice an average dopant concentration of the semiconductor substrate.

17. The method of claim 10, further comprising connecting the first capacitor terminal or the second capacitor terminal to a transistor terminal.

18. The method of claim 10, wherein a capacitance between the first capacitor terminal and the second capacitor terminal varies by less than 500 ppm with a voltage across the first capacitor terminal and the second capacitor terminal in a range of -5V to +5V.

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