Method for adjusting multi-interrupt timing of arc sampling process, arc detection method and photovoltaic system

Abstract

The application relates to a multi-interrupt timing adjustment method of a pull arc sampling process, a pull arc detection method and a photovoltaic system. The multi-interrupt timing adjustment method of the pull arc sampling process comprises the following steps: determining the timing of a first number of analog-to-digital converter (ADC) interrupts to be started at a first frequency, wherein the ADC interrupts are used to obtain sampling data after ADC conversion of the pull arc parameters; determining the timing of a timer interrupt to be started at a second frequency, wherein the second frequency is smaller than the first frequency; and adjusting the trigger position of the timer interrupt in timing to between two adjacent ADC interrupts based on the relative relationship between the timing of the timer interrupt and the timing of the ADC interrupts. The timing adjustment method can optimize the detection value exception condition in the pull arc detection process.

Description

Technical Field

[0001] This application relates to the field of arc detection technology, and in particular to a multi-interruption timing adjustment method for arc sampling process, an arc detection method, and a photovoltaic system. Background Technology

[0002] In the present technology, many electrical system fires are mainly caused by electric arcs. To improve the safety of electrical systems, existing electrical systems are usually equipped with arc detection devices to detect arcs in the DC side electrical signals of the electrical system.

[0003] A photovoltaic (PV) system comprises solar photovoltaic panels, PV cables, and PV inverters. It utilizes exposed solar panels to collect solar energy and convert it into electricity, thus generating power. However, an electric arc on the DC side of a PV system can easily cause a fire. In related technologies, arc fault detection technology primarily detects the occurrence of an arc fault by analyzing the differences in time-frequency domain characteristics of parameters before and after the fault occurred. If the sampling period or sampled values ​​used for arc fault analysis are deviated, the analysis results can easily be inaccurate, leading to false alarms. Summary of the Invention

[0004] To overcome the problems existing in related technologies, this application discloses a multi-interruption timing adjustment method, an arc detection method, and a photovoltaic system for the arc sampling process, so as to optimize the problem of abnormal detection values ​​during the arc detection process.

[0005] According to a first aspect of the embodiments of this application, a multi-interrupt timing adjustment method for an arc sampling process is provided. The method includes: determining the timing of a first number of digital-to-analog converter (ADC) interrupts to be activated at a first frequency, wherein the ADC interrupts are used to acquire sampled data after ADC conversion of the arc parameters; determining the timing of a timer interrupt activated at a second frequency, wherein the second frequency is less than the first frequency; and adjusting the trigger position of the timer interrupt in the timing sequence to between two adjacent ADC interrupts based on the relative relationship between the timing of the timer interrupt and the timing of the ADC interrupt.

[0006] According to a second aspect of the embodiments of this application, an arc detection method is provided, the method comprising: enabling the ADC interrupt and the timer interrupt according to the timing determined by any timing adjustment method in this application; and performing arc detection algorithm processing on the sampled data obtained through the ADC interrupt.

[0007] According to a third aspect of the embodiments of this application, a photovoltaic system is provided, comprising: a sampling device for collecting arcing parameters in the system; and a processor for executing the steps of any arcing detection method of this application.

[0008] The technical solution provided in this application embodiment may include the following beneficial effects: Based on the relative relationship between the timing of the timer interrupt and the timing of the ADC interrupt, this application adjusts the trigger position of the timer interrupt in the timing sequence to between two adjacent ADC interrupts, thereby avoiding the discontinuous current sampling caused by the insertion of timer interrupts during the execution of ADC interrupts, thus optimizing the abnormal detection value during the arc detection process.

[0009] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0011] Figure 1 This is a structural diagram of a photovoltaic system according to an exemplary embodiment of this application.

[0012] Figure 2 This is a flowchart illustrating a multi-interruption timing adjustment method in an arc sampling process according to an exemplary embodiment of this application.

[0013] Figure 3 This is a diagram illustrating the relative relationship between the trigger position of the delayed Time0 interrupt and the trigger positions of two adjacent ADC interrupts, according to an exemplary embodiment of this application.

[0014] Figure 4 This is a diagram showing the relative relationship between the timing of the ADC interrupt and the timing of the timer interrupt detected after the arc plate program upgrade was completed following timing adjustments.

[0015] Figure 5 This is a flowchart illustrating an arc detection method according to an exemplary embodiment of this application.

[0016] Figure 6 This is a timing diagram illustrating, according to an exemplary embodiment of this application, the scheduling of a task executed in a Time0 interrupt to be executed in a subsequent ADC interrupt. Detailed Implementation

[0017] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0018] Figure 1 This is a structural diagram of a photovoltaic system according to an exemplary embodiment of this application. Figure 1 As shown, the photovoltaic system 100 includes a photovoltaic panel PV 101, a current transformer CT 102, a photovoltaic inverter 103, and a power grid 104. The photovoltaic panel 101 converts received solar energy into electrical energy and outputs photovoltaic current through the photoelectric effect. The CT 102 monitors the current changes in the photovoltaic system 100 in real time, controlling the magnitude and direction of the current to ensure the safe operation of the photovoltaic system 100. The photovoltaic inverter 103 converts the DC current output from the photovoltaic panel 101 into AC current and outputs it to the power grid 104. The photovoltaic inverter 103 also uses an arc-detection plate to sample and detect arc-detection parameters such as the photovoltaic current monitored by the CT 102 to determine whether arcing has occurred in the photovoltaic system 100. The arc-detection plate is a circuit board capable of arc detection. It can be integrated into products such as photovoltaic inverters as part of the equipment to achieve arc detection, or it can be used independently outside the equipment to achieve arc detection.

[0019] In some embodiments, the arc detection process may include an arc parameter acquisition stage and an arc algorithm processing stage. In the arc parameter acquisition stage, the processor of the arc plate acquires sampled data after A / D conversion of the arc parameters monitored by CT 102 through a series of ADC interrupts. In the arc algorithm processing stage, the acquired arc parameters are processed using an arc algorithm to obtain the arc detection result. More specifically, after completing the initialization procedure, the arc plate performs the following processing to acquire the arc parameters and complete the arc detection:

[0020] 1) Enter the arcing parameter sampling stage, enable ADC interrupt, and complete the sampling of arcing parameters at 1024 sampling points through 1024 ADC interrupts.

[0021] 2) Disable ADC interrupt, process the collected arcing parameters using the arcing algorithm, and determine whether arcing has occurred.

[0022] 3) Repeat steps 1) and 2) above to perform the next round of arc-drawing parameter detection.

[0023] In related technologies, after upgrading the arc-pulling board's program on a cloud platform with technologies such as ARM (Advanced RISC Machine), DCAC (DC-to-AC), DC-CDC (DC-to-DC), or ARC (Advanced Renewable Computing), abnormal arc-pulling detection values ​​appeared. Normally, the arc-pulling value is less than 200, and the arc-pulling threshold is set at 400. However, after the arc-pulling board program upgrade, the arc-pulling detection value fluctuated significantly, even reaching 3900.

[0024] To address the aforementioned issues, the inventors analyzed and tested the photovoltaic system from various aspects, including hardware, software, structure, grounding, load, and battery pack. They discovered that the abnormal arc detection values ​​after upgrading the arc-pulling plate program were likely caused by long communication frames or other reasons leading to a shift in the current sampling point. Therefore, the inventors of this application propose a solution to adjust the timing of the timer interrupt in the arc-pulling plate program to between two adjacent ADC interrupts.

[0025] Figure 2 This is a flowchart illustrating a multi-interrupt timing adjustment method in the arc sampling process according to an exemplary embodiment of this application. The following will be combined with... Figure 2 The steps shown are explained.

[0026] In step 11, the timing of a first number of digital-to-analog converter (ADC) interrupts to be activated at a first frequency is determined, wherein the ADC interrupts are used to acquire sampled data after ADC conversion of the arcing parameters.

[0027] Here, the first frequency can be 250kHz, with a corresponding period of 4µs, meaning the interval between the trigger times of two adjacent ADC interrupts is 4µs. The first frequency can also be other values ​​that meet the requirements for arc detection, such as 220kHz or 280kHz. The first number of times is typically 1024, but can also be other numbers that meet the detection accuracy requirements, such as 512. In short, both the first frequency and the first number can be reasonably set based on the detection requirements and are not limited to the values ​​exemplified above in this application. The following explanation uses a first frequency of 250kHz as an example.

[0028] In some embodiments, the processor of the arc-extension plate enables an ADC interrupt at a first frequency to obtain the photovoltaic current output by the photovoltaic panel 101 as sampling data. The timing of the ADC interrupt can be obtained based on this first frequency to determine whether there is any overlap in timing with the timer interrupt.

[0029] In step 12, the timing of the timer interrupt enabled at a second frequency is determined, wherein the second frequency is less than the first frequency.

[0030] In some embodiments, the arc-drawing plate system program includes timer interrupts such as Time0 interrupts. Time0 interrupts can generate a time base signal in the system program with a period of 2ms, meaning there is a 2ms interval between the trigger times of two adjacent Time0 interrupts. It is understood that while the processor is acquiring sampled data using the ADC interrupt, the Time0 interrupt is also continuously running in the system program at a second frequency, performing tasks such as inter-chip communication. The second frequency is typically lower than the first frequency, for example, it could be 500Hz, 450Hz, 400Hz, etc.

[0031] Since the period of each ADC interrupt is approximately 4µs, a round of ADC interrupts, i.e., 1024 ADC interrupts, may last about 4.1ms. Therefore, at least two Time0 interrupts will be inserted during the entire process of an ADC interrupt from start to stop. If any of the inserted Time0 interrupts overlaps in timing with any of the 1024 ADC interrupts and interferes with that ADC interrupt, it may prolong the ADC interrupt period, causing detection point offset and abnormal arcing parameter detection.

[0032] In step 13, based on the relative relationship between the timing of the timer interrupt and the timing of the ADC interrupt, the trigger position of the timer interrupt in the timing sequence is adjusted to be between two adjacent ADC interrupts.

[0033] As mentioned earlier, if the Time0 interrupt interferes with a certain ADC interrupt, it may cause abnormal arcing parameter detection. The timing adjustment method described in this application is usually performed before the start of each round of acquisition. After adjusting the trigger position of the Time0 interrupt according to the above timing adjustment method, the ADC interrupt and Time0 interrupt of that round are started, and the arcing algorithm is performed on the sampled data obtained through the ADC interrupt.

[0034] In this embodiment, before a round of ADC interrupts is initiated, the timing of the ADC interrupts and the timing of the Time0 interrupts are determined. Based on the relative timing relationship between them, the trigger position of the Time0 interrupt, which may cause interference, is adjusted to be between two adjacent ADC interrupts to avoid interference from the Time0 interrupts. This prevents discontinuous current sampling caused by the insertion of timer interrupts during ADC interrupt execution, thereby optimizing the handling of abnormal detection values ​​during arc detection.

[0035] Here, the Time0 interrupt that interferes with the ADC interrupt is a Time0 interrupt that overlaps with the ADC interrupt in timing. For example, the trigger position of this Time0 interrupt may be before, after, or both of the trigger positions of an ADC interrupt; that is, any trigger position that causes the Time0 interrupt and an ADC interrupt to have a synchronized execution duration. For another example, if the priority of the ADC interrupt is defined as higher than that of the Time0 interrupt, then the trigger position of the Time0 interrupt is before the ADC interrupt is triggered.

[0036] In some embodiments, based on the relative relationship between the timing of the timer interrupt and the timing of the ADC interrupt, the trigger position of the timer interrupt is adjusted to be between two adjacent ADC interrupts. This includes: determining, based on the timing of the Time0 interrupt and the timing of the ADC interrupts, whether each inserted Time0 interrupt interferes with a certain ADC interrupt in timing during the current round of ADC interrupts, for example, interfering with the Nth ADC interrupt, where N is a natural number greater than or equal to 1. If interference exists, the processor delays the triggering of the Time0 interrupt, so that each Time0 interrupt runs between the Nth ADC interrupt and the (N+1)th ADC interrupt. Preferably, the trigger position of the Time0 interrupt is delayed to the interval after the Nth ADC interrupt ends and before the (N+1)th ADC interrupt is triggered.

[0037] By determining the triggering location of all Time0 interrupts that occur during a round of ADC interrupts, and delaying the triggering of Time0 interrupts that may interfere with a certain ADC interrupt to the interval between two adjacent ADC interrupts, the impact of Time0 interrupts on ADC interrupts can be better prevented.

[0038] Figure 3 This is a diagram illustrating the relative positions of the delayed Time0 interrupt trigger position and the trigger positions of two adjacent ADC interrupts, according to an exemplary embodiment of this application. See also... Figure 3The ADC interrupt cycle is 4µs, and the execution time of each ADC interrupt is approximately 0.8µs. Therefore, the interval between the end of the Nth ADC interrupt and the triggering of the (N+1)th ADC interrupt is approximately 3.2µs. Using the desired triggering position of the Time0 interrupt as the control target, preferably, the control target is set to 0.8µs after the end of the Nth ADC interrupt. If the execution time of the Time0 interrupt is 1.6µs, then the (N+1)th ADC interrupt will trigger 0.8µs after the end of the Time0 interrupt. At this time, the Time0 interrupt triggers 0.8µs after the end of the Nth ADC interrupt and ends 0.8µs before the triggering of the (N+1)th ADC interrupt, its execution time being exactly in the middle of the interval between the Nth and N+1th ADC interrupts. In other words, controlling the Time0 interrupt to trigger 1.6µs later than the triggering position of the Nth ADC interrupt will present... Figure 3 The timing relationship is shown.

[0039] Therefore, the delayed triggering time of the Time0 interrupt can be determined based on the expected position of the Time0 interrupt delay trigger. In some embodiments, since the clock periods of the Time0 interrupt and the ADC interrupt are the same, both being 60MHz, delaying the triggering of the corresponding Time0 interrupt, so that the Time0 interrupt runs between the Nth ADC interrupt and the (N+1)th ADC interrupt, can include:

[0040] Get the first clock cycle number temp1 from the current trigger position of the Time0 interrupt; get the second clock cycle number temp2 from the trigger position of the Nth ADC interrupt; then (temp2-temp1) is the number of clock cycles required to adjust the Time0 interrupt to trigger simultaneously with the Nth ADC interrupt. The value of N is determined by dividing temp1 by the ADC interrupt cycle, thus determining the trigger position of the Nth ADC interrupt.

[0041] If we determine the number of clock cycles temp3, which is the third clock cycle from the trigger position of the Nth ADC interrupt to the desired trigger position of the Time0 interrupt, then (temp2-temp1+temp3) is the number of clock cycles required to delay the Time0 interrupt to the desired trigger position. Preferably, temp3 is not less than the execution duration of the Nth ADC interrupt, which ensures that the delayed Time0 interrupt is triggered after the Nth ADC interrupt has finished executing, rather than during the execution process.

[0042] The above calculation method can be used to determine the number of clock cycles that the Time0 interrupt is delayed, ensuring that the trigger time of the Time0 interrupt is located in the interval between the two ADC interrupts.

[0043] like Figure 3 As shown, if the control target is that the Time0 interrupt is triggered 1.6us later than the Nth ADC interrupt, the Time0 interrupt needs to be delayed by (temp2-temp1+temp3) clock cycles. Therefore, the theoretical value of temp3 is 96 clock cycles, corresponding to 1.6us. However, during the process of obtaining temp1 and temp2, when assigning values ​​to TIM.all, the program runs synchronously, and both EPwm1Regs.TBCTR and TIM.all are decreasing or increasing. Therefore, temp3 cannot be directly obtained using the theoretical value and needs to be obtained through actual measurement using waveform debugging.

[0044] In some embodiments, the debugging process can be as follows: First, a value assignment test is performed on temp3 over 110 clock cycles. The test result shows that the Time0 interrupt starts 1.4us after the ADC interrupt ends. Then, a value assignment test is performed on temp3 over 170 clock cycles. The test result shows that the Time0 interrupt starts 2.36us after the ADC interrupt ends. The test results conform to the theoretical relationship that 60 clock cycles correspond to 1us.

[0045] Based on the previous test results showing that temp3 takes 110 clock cycles and the Time0 interrupt starts 1.4us after the ADC interrupt ends, if the expected triggering position of the Time0 interrupt is 0.8us after the ADC interrupt ends (i.e., 0.6us earlier than 1.4us), then the theoretical test value for temp3 is 110 - 60 * 0.6us = 74 clock cycles. Therefore, the theoretical test value for temp3 is 74 clock cycles. In actual tests with temp4 = 44 or 74, the Time0 interrupt starts 0.88us after the ADC interrupt ends, indicating that a certain interrupt jump time is required before the Time0 interrupt starts.

[0046] Therefore, based on the test results, the theoretical value of temp3 corresponding to delaying the Time0 interrupt to the desired trigger position is determined. This theoretical value is set as temp3, and the calculation result of (temp2-temp1+temp3) is determined as the number of clock cycles required to delay the Time0 interrupt to the desired position. By delaying the Time0 interrupt based on this number of clock cycles, the number of clock cycles for the Time0 interrupt delay can be adjusted according to the actual state of the program running in the system. This allows the Time0 interrupt to be triggered during the interval between two adjacent ADC interrupts, thereby avoiding interference between the Time0 interrupt and the ADC interrupt.

[0047] Figure 4The diagram shows the relative timing relationship between the ADC interrupt timing and the timer interrupt timing detected after the arc-pulling plate program upgrade was completed following the aforementioned timing adjustments. As shown, channel 1 represents the ADC interrupt timing, with a high level in channel 1 indicating ADC interrupt operation; channel 2 represents the timer interrupt timing, with a low level in channel 2 indicating Time0 interrupt operation; and channel 3 represents the timing of 485 communication in the photovoltaic system. After the timing adjustments and completion of the arc-pulling plate program upgrade, the interval between the end of the ADC interrupt and the triggering of the Time0 interrupt is 0.8µs, and the ADC sampling period remains approximately 4µs, essentially the same as before the upgrade, with no significant changes observed. It is evident that the measured data was indeed optimized after the timing adjustments described in this application.

[0048] Figure 5 This application illustrates an arc detection method according to an exemplary embodiment. The detection method includes the following steps:

[0049] In step 21, the ADC interrupt and timer interrupt are enabled according to the timing determined by the timing adjustment method described in this application.

[0050] As mentioned earlier, based on the relative relationship between the timing of the Time0 interrupt and the ADC interrupt, the trigger position of the Time0 interrupt, which interferes with the ADC interrupt, is adjusted to be between two adjacent ADC interrupts. After this adjustment, the ADC interrupt period returns to its normal duration before the program upgrade, and correspondingly, the abnormal arc detection value is optimized. Therefore, based on the adjusted timing, the ADC interrupt and Time0 interrupt are enabled, and the arc parameter acquisition phase begins.

[0051] In step 22, the sampled data obtained through the ADC interrupt is processed by the arcing algorithm.

[0052] After completing the arcing parameter sampling in step 21, the arcing algorithm processing stage begins, where the sampled data obtained through the ADC interrupt is processed using the arcing algorithm. In some embodiments, the arcing algorithm processing may include: performing a Fourier transform on the current parameter to obtain the spectrum corresponding to the current parameter; taking the modulus of the amplitude at each frequency point in the spectrum to obtain the characteristic value of the arcing; and determining whether an arcing has occurred based on the characteristic value of the arcing and a set arcing threshold.

[0053] Since the timing adjustment method of this application enables ADC interrupt and timer interrupt, the arc detection method described in this application ensures that even if the arc detection board program is upgraded, the arc detection value will not be abnormal after the upgrade.

[0054] Furthermore, the inventors discovered during their research that performing communication reception tasks, such as reading the FIFO, within the Time0 interrupt can prolong the execution time of the Time0 interrupt. This can still cause the interval between the trigger times of adjacent ADC interrupts to exceed 4µs, leading to abnormal arc detection values. Time data from testing the arc detection board in actual operation shows that an excessively long execution time of the Time0 interrupt can cause the interval between the trigger times of two adjacent ADC interrupts to reach 4.7µs. Therefore, reducing the execution time of the Time0 interrupt can also optimize the phenomenon of abnormal arc detection values.

[0055] In some embodiments, rescheduling some tasks executed in the Time0 interrupt to at least one ADC interrupt after the Time0 interrupt ends can shorten the execution time of the Time0 interrupt.

[0056] In the embodiments of this application, based on the timing of the Time0 interrupt and the timing of the ADC interrupt, it is determined whether the execution of each Time0 interrupt causes the period of the Mth ADC interrupt to be lengthened. The trigger time of the Time0 interrupt is after the Mth ADC interrupt and before the trigger time of the (M+1)th ADC interrupt. The period of the Mth ADC interrupt is lengthened specifically because the trigger time of the Time0 interrupt is within the period of the Mth ADC interrupt, and the end time of the Time0 interrupt is after the predetermined trigger time of the (M+1)th ADC interrupt, where M is a natural number greater than or equal to 1.

[0057] As mentioned earlier, during each round of ADC interrupts, a Time0 interrupt may be inserted. If the trigger time of this Time0 interrupt is close to the trigger time of the next ADC interrupt, or if the Time0 interrupt executes too many tasks or has a long execution time, then the trigger time of the ADC interrupt immediately following the Time0 interrupt will be postponed. In this case, the ADC interrupt cycle is lengthened. Therefore, it is necessary to determine whether the execution of each Time0 interrupt will cause the cycle of a certain ADC interrupt in that round (e.g., the Mth ADC interrupt) to be lengthened based on the relative relationship between the timing of the ADC interrupts and the timing of the Time0 interrupts. If the cycle of the ADC interrupt is lengthened, some tasks of the Time0 interrupt will be reassigned to subsequent ADC interrupts for execution.

[0058] The following steps S1301-S1306 further illustrate the specific process of task allocation during an interrupt.

[0059] In step S1301, the trigger time of the Mth ADC interrupt is obtained. The period of the Mth ADC interrupt is lengthened due to the insertion of the Time0 interrupt.

[0060] In some embodiments, the Mth ADC interrupt with an extended cycle is determined by the trigger time and execution duration of the Time0 interrupt. The execution period of the Time0 interrupt in terms of timing can be obtained based on its trigger time and execution duration. If the scheduled trigger time of any ADC interrupt in this round falls within the execution period of the Time0 interrupt, it means that the execution of the Time0 interrupt will delay the triggering of that ADC interrupt. The ADC interrupt immediately preceding this one is then the Mth ADC interrupt. The trigger time of this Mth interrupt is used for subsequent task scheduling.

[0061] In step S1302, based on the trigger time of the Mth ADC interrupt and the period of the ADC interrupt, the first end time of the Time0 interrupt after the task is allocated is determined, wherein the duration from the trigger time of the Mth ADC interrupt to the first end time of the Time0 interrupt after the task is allocated is not greater than the period of the ADC interrupt. Here, the period of the ADC interrupt is determined based on the first frequency.

[0062] Understandably, if the Time0 interrupt ends before the (M+1)th ADC interrupt is triggered, the period of the Mth ADC interrupt will not be extended. Therefore, the first end time of the Time0 interrupt is determined based on this condition, ensuring that the execution of the Time0 interrupt does not exceed the period of the Mth ADC interrupt. Preferably, there is a certain time margin between the first end time and the trigger time of the (M+1)th ADC interrupt, such as 0.8µs or 1µs.

[0063] In step S1303, the second end time of the Time0 interrupt before the task is scheduled is obtained, and the minimum execution time of the task to be scheduled from the Time0 interrupt is determined based on the first end time and the second end time.

[0064] Before allocating tasks, the second end time of the Time0 interrupt is located after the trigger time of the (M+1)th ADC interrupt. Therefore, a portion of the tasks needs to be allocated from the Time0 interrupt so that the first end time of the Time0 interrupt ends before the trigger time of the (M+1)th ADC interrupt. That is, the execution duration of the allocated tasks cannot be less than the time difference between the second and first end times. This ensures that, during actual operation, the Time0 interrupt after task allocation will not prolong the ADC interrupt cycle.

[0065] In step S1304, a first task is determined based on the minimum execution time, wherein the execution time of the first task is not less than the minimum execution time.

[0066] After obtaining the minimum execution duration, it is necessary to select the first task with an execution duration greater than or equal to the minimum execution duration from the tasks executed in the Time0 interrupt. If the execution duration of the first task allocated is less than the minimum execution duration, it may still lengthen the ADC interrupt cycle of the Time0 interrupt after the task is allocated. Therefore, the allocated tasks cannot be selected arbitrarily; it is necessary to confirm whether their execution durations meet the requirements.

[0067] In step S1305, based on the execution duration of the allocated task, a second number of ADC interrupts required to complete the task is determined, and a second task to be completed by each of the second number of ADC interrupts is determined, wherein the first task includes the second task, and the execution duration of the second number of ADC interrupts allocated the second task is not greater than the period of the ADC interrupt.

[0068] Since the first task allocated needs to be executed in the ADC interrupt following the Time0 interrupt, and the ADC interrupt cycle cannot be lengthened due to task allocation, the first task may need to be allocated to multiple ADC interrupts to ensure the ADC interrupt cycle remains normal while completing the task. Therefore, based on the size of the first task allocated, it is allocated to a second number of ADC interrupts for execution. This second number ensures that the cycle of the ADC interrupt receiving the task allocation is not lengthened. After determining the second number, the second task allocated to each ADC interrupt can be further determined. The ADC interrupt receiving the task allocation needs to complete the second task allocated from the Time0 interrupt as well as its original task of acquiring sampled data. Therefore, the execution time of the ADC interrupt receiving the task allocation needs to be limited to no more than the ADC interrupt cycle, i.e., no more than 4µs. Preferably, it can be 3.2µs or 3.8µs, etc.

[0069] In step S1306, starting from the M+1th ADC interrupt immediately following the Time0 interrupt, the task dispatched from the Time0 interrupt is executed in the second number of ADC interrupts.

[0070] After the adjustment of steps S1301-S1306, the execution time of the Time0 interrupt is shortened, and its end time is timed apart from the trigger time of the subsequent ADC interrupt, so it will not affect the subsequent ADC interrupt from triggering according to the predetermined cycle.

[0071] Figure 6 This is a timing diagram illustrating, according to an exemplary embodiment of this application, the rescheduling of a task executed in a Time0 interrupt to a subsequent ADC interrupt. For example... Figure 6As shown, after reassigning some tasks from the Time0 interrupt, the maximum execution time of the Time0 interrupt is shortened to 0.63us. Normally, the maximum execution time of an ADC interrupt is 1.33us. Since the Nth ADC interrupt immediately preceding this Time0 interrupt is executing normally, and the Time0 interrupt starts approximately 0.76us after the Nth ADC interrupt ends, there is still a margin of (4us - 1.33us - 0.63us - 0.76us =) 1.28us between the execution interval of the N+1th ADC interrupt and the time between the Nth and N+1th ADC interrupts. In other words, the trigger and end times of the Time0 interrupt are both within the execution interval between the Nth and N+1th ADC interrupts, and will not interfere with the ADC interrupts, thus preventing abnormal arc detection.

[0072] Correspondingly, the ADC interrupts following the Time0 interrupt are prolonged because they are reassigned to tasks originally executed during the Time0 interrupt. Since the interval between the trigger times of two adjacent ADC interrupts cannot exceed 4µs, the execution duration of ADC interrupts with reassigned tasks is also limited. Tasks need to be reassigned to multiple ADC interrupts to shorten the execution duration of the Time0 interrupt to a suitable length. The N+1th ADC interrupt immediately following the Time0 interrupt, and subsequent ADC interrupts, may be prolonged. For example, the maximum execution duration of the first ADC interrupt after the Time0 interrupt, i.e., the N+1th ADC interrupt, will reach 3.2µs, and the execution duration of subsequent ADC interrupts will also be prolonged, even reaching 3.85µs, until the last ADC interrupt with reassigned tasks finishes execution, at which point the ADC interrupts return to their normal execution duration.

[0073] As described above, according to the embodiments of this application, when the execution time of the Time0 interrupt is too long, causing the ADC interrupt cycle to be lengthened, some tasks in the Time0 interrupt are reassigned to subsequent ADC interrupts for execution. This shortens the execution time of the Time0 interrupt, allowing it to end before the next ADC interrupt is triggered, thus avoiding arc detection anomalies caused by the lengthened ADC interrupt cycle. Furthermore, the tasks reassigned from the Time0 interrupt are distributed to multiple ADC interrupts for execution, ensuring that the execution time of the ADC interrupts that receive task reassignment does not exceed the ADC interrupt cycle.

[0074] It should be noted that since the Time0 interrupt period is 2ms, there may be hundreds of ADC interrupts between two adjacent Time0 interrupts. Therefore, there is no need to worry about a new Time0 interrupt requiring task reassignment before the last ADC task being reassigned completes. In other words, there will be enough ADC interrupts after a Time0 interrupt to accept task reassignment, and there will be no situation where a new Time0 interrupt is adjacent to a previously extended ADC interrupt.

[0075] During the arc-drawing algorithm processing phase following the completion of the arc-drawing parameter acquisition phase, the Time0 interrupt continues to execute at the second frequency. Since there is no data acquisition task during this phase, in some embodiments, the ADC interrupt is disabled during the arc-drawing algorithm processing phase.

[0076] In other embodiments, the ADC interrupt is not completely disabled during the arcing algorithm processing phase. For example, at least one ADC interrupt is initiated after the Time0 interrupt, and some tasks executed in the Time0 interrupt are reassigned to the ADC interrupt initiated after the Time0 interrupt ends.

[0077] The number of ADC interrupts initiated is determined based on the size of the allocated task. In some embodiments, during the arcing algorithm processing, after each Time0 interrupt is executed, the number of ADC interrupts required to complete the allocated task is determined based on the size of the task allocated from the Time0 interrupt. Based on the determined number of ADC interrupts, the corresponding ADC interrupt is initiated. The execution frequency of the ADC interrupts can be a first frequency or other suitable frequency required by the system task, without limitation.

[0078] The arc-pulling algorithm processing phase typically lasts about 5.2ms. During this period, according to the Time0 interrupt cycle, there may be 2 to 3 Time0 interrupts. After each Time0 interrupt is completed, a certain number of ADC interrupts are started to execute the tasks allocated from the Time0 interrupt.

[0079] By handling the task allocation described above, we can avoid excessive execution time caused by too many or too large tasks interrupted by Time0. By shortening the execution time of Time0 interrupts, we can keep the time interval between ADC interrupts within 4µs, thereby optimizing the arc detection anomaly caused by this.

[0080] In addition to the reasons mentioned above, the abnormal arc detection may also be caused by the fact that the time interval between the first ADC interrupt and the second ADC interrupt is random after entering the arc parameter acquisition stage, which may lead to abnormal sampling data of the first ADC.

[0081] As mentioned earlier, the arcing detection process is cyclical. After one round of arcing parameter sampling, the sampled arcing parameters are processed by the arcing algorithm to determine whether an arc has occurred. Then, a new round of arcing parameter sampling begins, and arcing detection is continuously performed in the photovoltaic system. During the cyclic execution of arcing detection, the triggering and termination of the ADC interrupt are controlled by setting the ADC interrupt register in the arcing plate circuit.

[0082] In some embodiments, the ADC interrupt register has an enable bit and a trigger bit. Setting the enable bit in the ADC interrupt register enables or disables the interrupt line, allowing the ADC interrupt to be triggered. Setting the trigger bit in the interrupt register directly triggers the ADC interrupt, causing the processor to respond to the interrupt request. Each round of ADC interrupts is enabled based on the setting of the enable bit, and the trigger bit is repeatedly set at 4µs intervals, causing the ADC interrupt to be periodically triggered at 4µs intervals after being enabled, forming a process of sampling arcing parameters at multiple sampling points at a frequency of 250kHz. After completing a predetermined number of ADC interrupts, such as 1024, the enable bit is cleared, and the ADC interrupt for that round is disabled.

[0083] In the system program, the interrupt register enable bit is only set after the previous round of arcing algorithm processing ends and a new round of arcing parameter sampling begins. Since the processing time of the previous round of arcing algorithm is determined by the task completion status in the system program (usually around 5.2ms), the actual processing time of each round of arcing algorithm processing is unpredictable. Therefore, the ADC interrupt enable time cannot be predetermined, and consequently, the trigger time of the first ADC interrupt is unpredictable. However, the trigger bit in the interrupt register is repeatedly set at predetermined time intervals, thereby triggering subsequent ADC interrupts. In other words, from the second ADC interrupt to the 1024th ADC interrupt, the trigger time is fixed. Therefore, in each round of arcing parameter sampling, the interval between the trigger times of the first and second ADC interrupts is uncontrollable. This can also lead to abnormal arcing detection.

[0084] Based on this, in the embodiments of this application, after collecting the arcing parameters at preset time intervals using a data sampling device such as a current sensor, the first collected arcing parameter is discarded and not included in the sampling data group. Starting from the second arcing parameter, the collection of 1024 arcing parameters in this round is performed, that is, one more sampling of arcing parameters is performed thereafter. This can further optimize the abnormal situation of arcing detection. In some embodiments, after enabling the ADC interrupt, the ADC interrupt is executed 1025 times and then the round of ADC interrupts is turned off. The sampling data obtained from the 2nd to the 1025th ADC interrupts in this round of ADC interrupts are used for data processing in the arcing algorithm processing stage, and the arcing result is judged.

[0085] After adjusting the arc detection process according to the above-described manner in the embodiments of this application, the arc detection process is simulated and tested. The detection results of the simulation test are compared with the detection results before the above-described adjustment to verify the optimization effect after adjustment. The data comparison before and after adjustment is described in detail below.

[0086] Before making improvements according to the method described in the embodiments of this application, the timing relationship between the ADC interrupt and the Time0 interrupt is detected. Table 1 records the relevant time data of the ADC interrupt and the Time0 interrupt in this detection.

[0087] Table 1

[0088]

[0089] As can be seen from Table 1, the execution duration of the Time0 interrupt overlaps with that of the ADC interrupt, resulting in a delayed triggering of the ADC interrupt and extending its period to approximately 6µs.

[0090] Therefore, it can be seen that before the timing adjustment method of this application embodiment is implemented, the sampling period of the ADC interrupt exceeds the expected sampling period of 4us by about 2us.

[0091] After improvements were made according to the method described in the embodiments of this application, the timing relationship between the ADC interrupt and the Time0 interrupt was detected. Table 2 records the relevant time data of the ADC interrupt and the Time0 interrupt in the detection.

[0092] Table 2

[0093]

[0094] As can be seen from the data recorded in Table 2, after applying the timing adjustment method of this embodiment, the sampling period of the ADC interrupt is 4µs, which is basically the same as the expected sampling period and meets the requirements for the sampling period of the ADC interrupt. This proves that the timing adjustment method of this embodiment can indeed optimize the abnormal situation of the arc detection results.

[0095] The multi-interruption timing adjustment method and arc detection method disclosed in this application can be used in arc detection of photovoltaic systems. In embodiments of this application, the photovoltaic system includes: a sampling device for collecting arc parameters in the system; and a processor for executing the steps of any of the arc detection methods disclosed in this application. In some embodiments, the photovoltaic system includes photovoltaic panels, a photovoltaic inverter, and a power grid, and the timing adjustment method and arc detection method can be specifically used in the arc detection plate of the photovoltaic inverter.

[0096] It should be understood that the phrases "some embodiments," "one embodiment," or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0097] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0098] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A multi-interrupt timing adjustment method for an arc sampling process, characterized in that, The method includes: Determine the timing of a first number of digital-to-analog converter (ADC) interrupts to be activated at a first frequency, wherein the ADC interrupts are used to acquire sampled data after ADC conversion using arcing parameters; Determine the timing of a timer interrupt that is enabled at a second frequency, wherein the second frequency is less than the first frequency; Based on the relative relationship between the timing of the timer interrupt and the timing of the ADC interrupt, the trigger position of the timer interrupt in the timing sequence is adjusted to be between two adjacent ADC interrupts; The step of adjusting the trigger position of the timer interrupt to be between two adjacent ADC interrupts based on the relative relationship between the timing of the timer interrupt and the timing of the ADC interrupt includes: Based on the timing of the timer interrupt and the timing of the ADC interrupt, determine whether there is any timing interference between each timer interrupt and the Nth ADC interrupt, where N is a natural number greater than or equal to 1; If there is timing interference between the timer interrupt and the Nth ADC interrupt, the corresponding timer interrupt is triggered with a delay, so that each timer interrupt runs between the Nth ADC interrupt and the (N+1)th ADC interrupt.

2. The method according to claim 1, characterized in that, The timer interrupt corresponding to the delay trigger, causing the timer interrupt to run between the Nth ADC interrupt and the (N+1)th ADC interrupt, includes: Obtain the first clock cycle number temp1 from the trigger position of the timer interrupt; Obtain the second clock cycle number temp2, which is the distance from the Nth ADC interrupt trigger position; The number of clock cycles temp3, which is the distance from the trigger position of the timer interrupt after the delay to the trigger position of the Nth ADC interrupt, is determined, wherein temp3 is not less than the execution duration of the Nth ADC interrupt; Based on temp1, temp2, and temp3, determine the number of clock cycles temp4 that the timer interrupt needs to be delayed; Based on temp4, the timer interrupt is triggered with a delay.

3. The method according to claim 2, characterized in that, The step of determining temp3, which is the distance between the trigger position after the timer interrupt delay and the trigger position of the Nth ADC interrupt, includes: The timer interrupt delay trigger test is performed based on the preset first clock cycle number, temp3, temp1, temp2 and the assigned temp3. Based on the actual location and expected location of the timer interrupt delay trigger in the test, the theoretical value of temp3 is obtained. The theoretical test value is determined as temp3, which is then used to determine temp4.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: During the first number of ADC interrupts, at least one of the tasks executed in the timer interrupt is rescheduled to at least one ADC interrupt after the timer interrupt ends, in order to shorten the duration of the timer interrupt execution.

5. A method for detecting arcing, characterized in that, The method includes: The timing determined by the method according to any one of claims 1 to 4 is used to enable the ADC interrupt and the timer interrupt; and The sampled data obtained through the ADC interrupt is processed using an arc-pull algorithm.

6. The method according to claim 5, characterized in that, The method further includes: During the arc-pulling algorithm processing, the ADC interrupt is disabled.

7. The method according to claim 5, characterized in that, The method further includes: During the arcing algorithm processing, at least one ADC interrupt is executed after the timer interrupt, and at least one of the tasks executed in the timer interrupt is rescheduled to be executed in the at least one ADC interrupt after the timer interrupt ends.

8. The method according to any one of claims 5 to 7, characterized in that, The method further includes: The arc-drawing parameters are collected at preset time intervals using a data acquisition device; Discard the first collected arcing parameter; and Starting with the second arc-drawing parameter, the first number of arc-drawing parameters are collected.

9. A photovoltaic system, characterized in that, include: A sampling device for collecting arcing parameters in the system; A processor for performing the steps of the arc detection method according to any one of claims 5 to 8.

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