Power amplifier with high linearity and high efficiency

Abstract

The invention provides a power amplifier with high linearity and high efficiency. The power amplifier comprises an input matching circuit, an inter-stage matching circuit and an output matching circuit, according to the invention, loss of second, third and fourth harmonic energy is recovered while high efficiency is ensured, linearity is improved through an input and output matching network, phase distortion is reduced while high-power output is performed, high-frequency and high-power working conditions are met, and the linearity of the radio frequency power amplifier is better; the matching depth of input matching at a center frequency point is higher, the working bandwidth of a chip is expanded, the linearity of the circuit is effectively improved, the reactance component of the output end is increased through the J-type capacitor, the working mode of the circuit is converted into the J-type mode from a depth AB-type mode, 45-degree phase shift is generated between a voltage waveform and an original voltage waveform, and the output frequency of the circuit is improved. Converting a voltage waveform in a time domain; energy waste of second harmonics can be effectively restrained, impedance points of the second harmonics are located in a high-efficiency area, and meanwhile the influence of main harmonic signals on fundamental frequency is reduced.

Description

Technical Field

[0001] The invention relates to the technical field of power amplifiers, in particular to a power amplifier with high linearity and high efficiency. Background Art

[0002] As an important component of the transmitter front end in the communication system, the RF power amplifier has the main function of converting low-power RF signals into high-power RF signals. Its typical application is to drive the antenna in the transmitter, amplify the modulated RF signal to the required power value and transmit it through the antenna. The design indicators of the RF power amplifier usually include gain, saturated output power, power added efficiency, linearity, bandwidth, etc. The linearity of the RF power amplifier refers to the linear relationship between its output power and input power. Ideally, the RF power amplifier only increases the power level of the input signal without changing the content of the signal, which requires the RF power amplifier to maintain the same gain within its operating frequency band. However, the gain of most power amplifier components decreases with increasing frequency, so it is impossible to achieve ideal linearity; RF signals using complex modulation methods have higher requirements for the linearity of RF power amplifiers.

[0003] However, the traditional GaAs HBT process has been significantly optimized by current bias technology due to its excellent high-frequency characteristics and current handling capabilities. Current bias technology can accurately control the working state of the transistor, thereby improving the linearity and stability of the power amplifier. However, when this technology is tried to be applied to the HEMT process, it faces many challenges. The HEMT process performs well in the microwave and millimeter wave bands with its high electron mobility and low noise characteristics, but it is not as convenient as the HBT process when applying current bias technology. The gate voltage control of HEMT devices is more sensitive, and their nonlinear characteristics are more significant, which makes it difficult for current bias technology to accurately adjust the operating point of the HEMT to achieve ideal linearity and efficiency.

[0004] Secondly, traditional design ideas often improve the linearity of power amplifiers by optimizing current bias technology. However, this approach is often accompanied by additional power consumption problems. Current bias technology optimizes the AC characteristics of transistors by precisely controlling the DC operating point of transistors, thereby improving linearity. However, in this process, additional current is often required to maintain the stable working state of the transistor, which will lead to an increase in the overall power consumption of the power amplifier. Especially at high power output, the problem of additional power consumption is more significant, which will not only reduce the efficiency of the power amplifier, but also increase the heat dissipation of the system, posing a threat to the stability and reliability of the system. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides a power amplifier with high linearity and high efficiency. The present invention can improve the linearity of the power amplifier, reduce phase distortion while outputting high power, meet high-frequency and high-power working conditions, and make the linearity of the RF power amplifier better.

[0006] The technical solution of the present invention is: a power amplifier with high linearity and high efficiency, comprising an input matching circuit, an inter-stage matching circuit, and an output matching circuit; the input matching circuit comprises an LC series resonant network and a high-pass network; one end of the LC series resonant network is connected to a signal input end RF in The other end of the LC series resonant network is connected to a high-pass network; the high-pass network is connected to a transistor M1 through an RC parallel resonant network; the transistor M1 is connected to an interstage matching circuit; the interstage matching circuit is connected to an output matching circuit; the output matching circuit includes a transistor M2, a second harmonic network, a third harmonic network, a fourth harmonic network, and a J-type capacitor C9. The second harmonic network can effectively suppress the energy waste of the second harmonic and make the second harmonic impedance point fall in a high-efficiency area; under the conditions of the third and fourth harmonics, the third harmonic network and the fourth harmonic network are equivalent to an LC series resonant network, so that the third harmonic network and the fourth harmonic network are approximately short-circuited, thereby approaching the high-efficiency impedance point of an ideal high-order harmonic load traction, thereby reducing the influence of the main harmonic signal on the fundamental frequency.

[0007] Preferably, the LC series resonant network comprises an inductor L1 and a capacitor C1, one end of the inductor L1 is connected to the signal input terminal RF in The other end is connected to capacitor C1.

[0008] Preferably, the high-pass network includes a capacitor C2 and an inductor L2, one end of the capacitor C2 and the inductor L2 are connected in parallel to one end of the capacitor C1; the other end of the inductor L2 is grounded, and the other end of the capacitor C2 is connected to the RC parallel resonant network and the first bypass.

[0009] Preferably, the RC parallel resonant network includes a resistor R3 and a capacitor C4, the resistor R3 and the capacitor C4 are connected in parallel to the other end of the capacitor C2, the other ends of the resistor R3 and the capacitor C4 are connected in parallel to the gate of the transistor M1; the source of the transistor M1 is grounded; the drain of the transistor M1 is connected to the inter-stage matching circuit.

[0010] Preferably, the first bypass includes a choke resistor R2, an inductor L3, a resistor R1, and a capacitor C3; one end of the choke resistor R2 is connected to the capacitor C2; the other end of the choke resistor R2 is connected to the inductor L3, and the choke resistor R2 is used to limit the breakdown of the transistor M1 when the DC signal is too large; the other end of the inductor L3 is respectively connected to the resistor R1 and the first-stage gate feed VG1; the other end of the resistor R1 is grounded through the capacitor C3.

[0011] Preferably, the inter-stage matching circuit includes an inductor L4 and a capacitor C6, and the inductor L4 and the capacitor C6 are connected in parallel to the drain of the transistor M1; the other end of the inductor L4 is respectively connected to the drain power supply VD1 and the second bypass; the other end of the capacitor C6 is respectively connected to the gate of the transistor M2 and the third bypass.

[0012] Preferably, the second bypass includes a capacitor C5 and a resistor R4, one end of the capacitor C5 is connected to the inductor L4; the other end of the capacitor C5 is connected to the resistor R4, and the other end of the resistor R4 is grounded.

[0013] Preferably, the third bypass includes a choke resistor R6, an inductor L5, a resistor R5 and a capacitor C7, one end of the choke resistor R6 is connected to the capacitor C6, and the other end is connected to the second-stage gate feed VG2 and the resistor R5 respectively through the inductor L5, and the other end of the resistor R5 is grounded through the resistor C5.

[0014] Preferably, the second harmonic network includes an inductor L6, a capacitor C8, an inductor L9 and a capacitor C12, one end of the inductor L6 is connected to the drain of the transistor M2, and the other end of the inductor L6 is respectively connected to the capacitor C8 and the drain power supply VD2; the other end of the capacitor C8 is grounded via a resistor R7,

[0015] The drain of the transistor M2 is also connected in parallel with the inductor L9 and the capacitor C12 via the inductor L7 and the inductor L8. The other ends of the inductor L9 and the capacitor C12 are connected in parallel with the capacitor C13. The other end of the capacitor C13 is connected to the signal output terminal RFout. The capacitor C13 is also grounded via the inductor L10.

[0016] Preferably, the drain of the transistor M2 is also connected to a Class J capacitor C9, and the other end of the Class J capacitor C9 is grounded; the reactance component at the output end is increased, so that the circuit working mode is converted from a deep Class AB mode to a Class J mode, and the voltage waveform is 45° phase shifted from the original voltage waveform, thereby converting the voltage waveform in the time domain.

[0017] Preferably, the third harmonic network includes a microstrip line MLIN1 and a capacitor C10, one end of the microstrip line MLIN1 is connected to the inductor L7, and the other end of the microstrip line MLIN1 is grounded via the capacitor C10.

[0018] Preferably, the fourth harmonic network includes a microstrip line MLIN2 and a capacitor C11, one end of the microstrip line MLIN2 is connected to the inductor L8, and the other end of the microstrip line MLIN2 is grounded via the capacitor C11.

[0019] The beneficial effects of the present invention are:

[0020] 1. The present invention reduces the overlap of the non-zero parts of the voltage and current, thereby reducing the overall circuit power consumption, making the circuit structure more compact and easy to implement and integrate;

[0021] 2. The present invention recovers the energy loss of the second, third and fourth harmonics while ensuring high efficiency in the class J power amplifier mode, and successfully improves the linearity through the input and output matching network of the present invention, which can reduce phase distortion while outputting high power, meet high-frequency and high-power working conditions, and make the linearity of the RF power amplifier better;

[0022] 3. The input matching network of the present invention makes the input matching at the center frequency point have a higher matching depth, which can not only expand the working bandwidth of the chip, but also effectively improve the linearity of the circuit, and is suitable for the miniaturization requirements of the current power amplifier chip design;

[0023] 4. The present invention adds choke resistors R2 and R6 to limit the breakdown of transistors M1 and M2 caused by excessive DC signals, thereby improving the reliability of the overall circuit;

[0024] 5. The present invention introduces a Class J capacitor C9, which increases the reactance component at the output end, so that the circuit operation mode is converted from a deep Class AB mode to a Class J mode, and the voltage waveform is 45° phase-shifted from the original voltage waveform, thereby converting the voltage waveform in the time domain;

[0025] 6. The output matching circuit of the present invention can effectively suppress the energy waste of the second harmonic, make the second harmonic impedance point fall in the high efficiency area, and at the same time reduce the influence of the main harmonic signal on the fundamental frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a circuit diagram of a power amplifier according to an embodiment of the present invention;

[0027] Figure 2 A comparison diagram of the AM-PM effect of the power amplifier of the embodiment of the present invention and the existing power amplifier;

[0028] Figure 3This is a graph comparing the output power-efficiency of the power amplifier according to the embodiment of the present invention and the existing power amplifier;

[0029] Figure 4 A frequency-efficiency comparison diagram of a power amplifier according to an embodiment of the present invention and a conventional power amplifier;

[0030] Figure 5 A comparison diagram of the input power-output power effect between the power amplifier of the embodiment of the present invention and the existing power amplifier;

[0031] Figure 6 The figure is a comparison diagram of the frequency-gain effect between the power amplifier of the embodiment of the present invention and the existing power amplifier. DETAILED DESCRIPTION

[0032] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings:

[0033] like Figure 1 As shown, this embodiment provides a power amplifier with high linearity and high efficiency, and the amplifier is made by GaAs pHemt process. In this embodiment, the power amplifier includes an input matching circuit, an inter-stage matching circuit, and an output matching circuit.

[0034] The input matching circuit includes an LC series resonant network and a high-pass network; the input matching circuit makes the input matching at the center frequency point have a higher matching depth, which can not only expand the working bandwidth of the chip, but also effectively improve the linearity of the circuit, and is suitable for the miniaturization requirements of current power amplifier chip design.

[0035] One end of the LC series resonant network is connected to the signal input terminal RF in The other end of the LC series resonant network is connected to a high-pass network; the high-pass network is connected to a transistor M1 through an RC parallel resonant network; the transistor M1 is connected to an inter-stage matching circuit; the inter-stage matching circuit is connected to an output matching circuit.

[0036] The output matching circuit includes a transistor M2, a second harmonic network, a third harmonic network, a fourth harmonic network, and a J-type capacitor C9. In this embodiment, the second harmonic network and the J-type capacitor C9 are connected in parallel to the drain of the transistor M2. The second harmonic network can effectively suppress the energy waste of the second harmonic, so that the second harmonic impedance point falls in the high-efficiency area; under the conditions of the third and fourth harmonics, the third harmonic network and the fourth harmonic network are equivalent to an LC series resonant network, so that the third harmonic network and the fourth harmonic network are approximately short-circuited, thereby approaching the high-efficiency impedance point of the ideal high-order harmonic load traction, thereby reducing the influence of the main harmonic signal on the fundamental frequency.

[0037] As a preferred embodiment of the present invention, the LC series resonant network includes an inductor L1 and a capacitor C1, one end of the inductor L1 is connected to the signal input terminal RF in The high-pass network includes a capacitor C2 and an inductor L2, one end of the capacitor C2 and the inductor L2 are connected in parallel to one end of the capacitor C1; the other end of the inductor L2 is grounded, and the other end of the capacitor C2 is connected to the RC parallel resonant network and the first bypass. The input matching depth at the center frequency point is made higher, which can not only expand the working bandwidth of the chip, but also effectively improve the linearity of the circuit, which is suitable for the miniaturization requirements of the current power amplifier chip design.

[0038] As a preferred embodiment of the present invention, the RC parallel resonant network includes a resistor R3 and a capacitor C4, the resistor R3 and the capacitor C4 are connected in parallel to the other end of the capacitor C2, the other ends of the resistor R3 and the capacitor C4 are connected in parallel to the gate of the transistor M1; the source of the transistor M1 is grounded; the drain of the transistor M1 is connected to the inter-stage matching circuit. The RC parallel resonant network improves the stability of the circuit in the full frequency band.

[0039] As a preferred embodiment of the present invention, the first bypass includes a choke resistor R2, an inductor L3, a resistor R1, and a capacitor C3; one end of the choke resistor R2 is connected to the capacitor C2; the other end of the choke resistor R2 is connected to the inductor L3, and the choke resistor R2 is used to limit the breakdown of the transistor M1 when the DC signal is too large; the other end of the inductor L3 is respectively connected to the resistor R1 and the first-stage gate feed VG1; the other end of the resistor R1 is grounded through the capacitor C3.

[0040] As a preferred embodiment of the present invention, the inter-stage matching circuit includes an inductor L4 and a capacitor C6, and the inductor L4 and the capacitor C6 are connected in parallel to the drain of the transistor M1; the other end of the inductor L4 is respectively connected to the drain power supply VD1 and the second bypass; the other end of the capacitor C6 is respectively connected to the gate of the transistor M2 and the third bypass.

[0041] As a preferred embodiment of the present invention, the second bypass includes a capacitor C5 and a resistor R4, one end of the capacitor C5 is connected to the inductor L4; the other end of the capacitor C5 is connected to the resistor R4, and the other end of the resistor R4 is grounded.

[0042] As a preferred embodiment of the present invention, the third bypass includes a choke resistor R6, an inductor L5, a resistor R5 and a capacitor C7, one end of the choke resistor R6 is connected to the capacitor C6, and the other end is connected to the second-stage gate feed VG2 and the resistor R5 through the inductor L5, and the other end of the resistor R5 is grounded through the resistor C5. In the present embodiment, the choke resistor R6 is used to limit the breakdown of the transistor M2 when the DC signal is too large, thereby improving the reliability of the overall circuit.

[0043] As a preferred embodiment of the present invention, the drain of the transistor M2 is also connected to a Class J capacitor C9, and the other end of the Class J capacitor C9 is grounded; the reactance component at the output end is increased, so that the circuit operating mode is converted from a deep Class AB mode to a Class J mode, and the voltage waveform is 45° phase shifted from the original voltage waveform, thereby converting the voltage waveform in the time domain.

[0044] As preferred in this embodiment, in order to suppress the influence of the second, third, fourth and other higher harmonics on the fundamental frequency signal, this embodiment designs a second harmonic network, which includes an inductor L6, a capacitor C8, an inductor L9 and a capacitor C12, one end of the inductor L6 is connected to the drain of the transistor M2, and the other end of the inductor L6 is respectively connected to the capacitor C8 and the drain power supply VD2; the other end of the capacitor C8 is grounded via a resistor R7, the drain of the transistor M2 is also connected in parallel with the inductor L7 and the inductor L8, the other end of the inductor L9 and the capacitor C12 is connected in parallel with a capacitor C13, the other end of the capacitor C13 is connected to the signal output terminal RFout, and the capacitor C13 is also grounded via the inductor L10. The second harmonic network can effectively suppress the energy waste of the second harmonic, so that the second harmonic impedance point falls in the high efficiency area.

[0045] As a preferred embodiment of the present invention, the third harmonic network includes a microstrip line MLIN1 and a capacitor C10, one end of the microstrip line MLIN1 is connected to the inductor L7, and the other end of the microstrip line MLIN1 is grounded via the capacitor C10.

[0046] The fourth harmonic network includes a microstrip line MLIN2 and a capacitor C11. One end of the microstrip line MLIN2 is connected to the inductor L8, and the other end of the microstrip line MLIN2 is grounded via the capacitor C11.

[0047] Under the conditions of the third and fourth harmonics, the third harmonic network and the fourth harmonic network are equivalent to an LC series resonant network, so that the third and fourth harmonics are approximately short-circuited, thus approaching the high-efficiency impedance point of ideal high-order harmonic load traction, thereby reducing the impact of the main harmonic signal on the fundamental frequency and achieving high efficiency and high linearity.

[0048] like Figure 2As shown, the angle distortion of the AM-PM of the existing power amplifier reaches 9° when the saturation power reaches 26dbm, and the distortion becomes more serious as the power is higher. However, the phase distortion of the AM-PM of the power amplifier of this embodiment is well suppressed when the saturation power reaches 29dbm, and can be controlled within 3°, thus meeting the linearity requirement of the RF power amplifier.

[0049] like Figure 3 As shown, with the increase of output power, the peak efficiency of the existing power amplifier is only 48% when it is saturated to the maximum, while the peak efficiency of the power amplifier of this embodiment exceeds 60% when it reaches the saturation power.

[0050] like Figure 4 The figure shows the maximum peak efficiency of the two power amplifiers in different frequency ranges. The existing power amplifier reaches a maximum peak efficiency of 52% at 2.5 GHz, while the power amplifier of this embodiment has an average efficiency of more than 60% in the range of 1.55 GHz to 2.25 GHz, and its efficiency bandwidth is better than that of the existing power amplifier.

[0051] like Figure 5 The figure shows the maximum saturated power that can be obtained by the two power amplifiers under the same input power mode. The existing power amplifier reaches a saturated output power of 26.5dBm when the input power is 4dBm, while the power amplifier of this embodiment can reach a saturated output power of nearly 29dBm when the input power is 4dBm, which shows that this new design concept can reduce energy loss and achieve higher saturated output power.

[0052] like Figure 6 The figure shows the effect of two power amplifiers on the gain. The peak gain of the existing power amplifier circuit near the fundamental frequency reaches 33dB, and the gain at the second, third and other higher harmonic frequencies is not processed. The gain of the power amplifier of this embodiment near the fundamental frequency reaches 38dB. This is because the energy of the second, third, fourth and other higher harmonics is suppressed and recovered, so that the gain near the fundamental frequency is improved, energy loss is avoided, and the saturated output power and efficiency of the power amplifier are effectively improved.

[0053] The above embodiments and descriptions are only for illustrating the principles and best embodiments of the present invention. Without departing from the spirit and scope of the present invention, the present invention may be subject to various changes and improvements, all of which fall within the scope of the present invention to be protected.

Claims

1. A power amplifier with high linearity and high efficiency, characterized in that, It includes an input matching circuit, an inter-stage matching circuit, and an output matching circuit; the input matching circuit includes an LC series resonant network and a high-pass network; one end of the LC series resonant network is connected to the signal input end RF in connection; the other end of the LC series resonant network is connected to a high-pass network; the high-pass network is connected to the transistor M1 through an RC parallel resonant network; The transistor M1 is connected to the inter-stage matching circuit; the inter-stage matching circuit is connected to the output matching circuit; The output matching circuit includes a transistor M2, a second harmonic network, a third harmonic network, a fourth harmonic network, and a J-type capacitor C9.

2. A power amplifier with high linearity and high efficiency according to claim 1, characterized in that: The LC series resonant network includes an inductor L1 and a capacitor C1. One end of the inductor L1 is connected to the signal input terminal RF in The other end is connected to capacitor C1.

3. A power amplifier with high linearity and high efficiency according to claim 2, characterized in that: The high-pass network includes a capacitor C2 and an inductor L2, one end of the capacitor C2 and the inductor L2 are connected in parallel to one end of the capacitor C1; the other end of the inductor L2 is grounded, and the other end of the capacitor C2 is connected to the RC parallel resonant network and the first bypass.

4. A power amplifier with high linearity and high efficiency according to claim 3, characterized in that: The RC parallel resonant network includes a resistor R3 and a capacitor C4, the resistor R3 and the capacitor C4 are connected in parallel to the other end of the capacitor C2, and the other ends of the resistor R3 and the capacitor C4 are connected in parallel to the gate of the transistor M1; the source of the transistor M1 is grounded; and the drain of the transistor M1 is connected to the inter-stage matching circuit.

5. A power amplifier with high linearity and high efficiency according to claim 4, characterized in that: The first bypass includes a choke resistor R2, an inductor L3, a resistor R1, and a capacitor C3; one end of the choke resistor R2 is connected to the capacitor C2; the other end of the choke resistor R2 is connected to the inductor L3, and the other end of the inductor L3 is respectively connected to the resistor R1 and the first-stage gate feed VG1; the other end of the resistor R1 is grounded through the capacitor C3.

6. A power amplifier with high linearity and high efficiency according to claim 4, characterized in that: The inter-stage matching circuit includes an inductor L4 and a capacitor C6, and the inductor L4 and the capacitor C6 are connected in parallel to the drain of the transistor M1; the other end of the inductor L4 is respectively connected to the drain power supply VD1 and the second bypass; the other end of the capacitor C6 is respectively connected to the gate of the transistor M2 and the third bypass.

7. A power amplifier with high linearity and high efficiency according to claim 6, characterized in that: The third bypass includes a choke resistor R6, an inductor L5, a resistor R5 and a capacitor C7. One end of the choke resistor R6 is connected to the capacitor C6, and the other end is connected to the second-stage gate feed VG2 and the resistor R5 respectively through the inductor L5. The other end of the resistor R5 is grounded through the resistor C5.

8. The power amplifier with high linearity and high efficiency according to claim 1, characterized in that: The second harmonic network includes an inductor L6, a capacitor C8, an inductor L9 and a capacitor C12, one end of the inductor L6 is connected to the drain of the transistor M2, and the other end of the inductor L6 is respectively connected to the capacitor C8 and the drain power supply VD2; the other end of the capacitor C8 is grounded via a resistor R7, the drain of the transistor M2 is also connected in parallel with the inductor L7 and the inductor L8, the other end of the inductor L9 and the capacitor C12 is connected in parallel with a capacitor C13, the other end of the capacitor C13 is connected to the signal output terminal RFout, and the capacitor C13 is also grounded via an inductor L10; The drain of the transistor M2 is also connected to a Class J capacitor C9, and the other end of the Class J capacitor C9 is grounded; the reactance component at the output end is increased, so that the circuit working mode is converted from a deep Class AB mode to a Class J mode, and the voltage waveform is 45° phase shifted from the original voltage waveform, thereby converting the voltage waveform in the time domain.

9. The power amplifier with high linearity and high efficiency according to claim 1, characterized in that: The third harmonic network includes a microstrip line MLIN1 and a capacitor C10. One end of the microstrip line MLIN1 is connected to the inductor L7, and the other end of the microstrip line MLIN1 is grounded via the capacitor C10.

10. The power amplifier with high linearity and high efficiency according to claim 1, characterized in that: The fourth harmonic network includes a microstrip line MLIN2 and a capacitor C11. One end of the microstrip line MLIN2 is connected to the inductor L8, and the other end of the microstrip line MLIN2 is grounded via the capacitor C11.

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