CMOS power amplifier

Abstract

The invention discloses a CMOS power amplifier which comprises a transconductance tube and a common gate tube, the transconductance tube comprises a first CMOS transistor and a second CMOS transistor, the common gate tube comprises a third CMOS transistor and a fourth CMOS transistor, and sources of the first CMOS transistor and the second CMOS transistor are grounded respectively to form a pseudo differential pair; the drain electrode of the first CMOS transistor and the drain electrode of the second CMOS transistor are connected with the source electrode of the third CMOS transistor and the source electrode of the fourth CMOS transistor respectively to form a common-gate structure. A pre-stage driving amplifier of the CMOS power amplifier outputs a main path and an auxiliary path, the main path is connected with the grid electrode of the first CMOS transistor and the grid electrode of the second CMOS transistor through AC double capacitors, and the auxiliary path outputs direct current bias voltage through an envelope detection circuit to be connected to the grid electrode of the third CMOS transistor and the grid electrode of the fourth CMOS transistor.

Description

Technical Field

[0001] The present application relates to the technical field of CMOS power amplifiers, and in particular to a CMOS power amplifier. Background Art

[0002] With the continuous improvement of CMOS technology and the continuous advancement of circuit design technology, the use of CMOS technology to realize on-chip integrated wireless connection chips (Bluetooth, WiFi, etc.) power amplifiers has become mainstream. The power amplifier is an important unit in the wireless transceiver. According to the different system modulation methods, it can be divided into nonlinear power amplifiers and linear power amplifiers. In protocols such as Bluetooth 2.1 and wireless LAN, linear power amplifiers must be used due to the existence of amplitude modulation. Since the power amplifier is at the last stage of the RF transmitter, its linearity performance determines the linearity of the entire transmitter. In addition, the power amplifier is often the most power-consuming module in the wireless transceiver, so improving efficiency, especially improving linear efficiency, is also particularly important.

[0003] The disadvantages of the prior art are as follows Figure 1 As shown in the figure, vb changes with the output swing of the driver amplifier. When vb is low, the small signal gain of the power amplifier is relatively low. When vb increases, the small signal gain becomes larger, resulting in serious AM-AM distortion in the power amplifier. In addition, due to the change of vb, the load capacitance seen by the output signal of the driver amplifier, that is, the gate capacitance of M1 and M2, changes accordingly, changing the phase characteristics, resulting in obvious AM-PM distortion. Summary of the invention

[0004] In view of the technical problems existing in the above-mentioned prior art, the present disclosure provides a CMOS power amplifier.

[0005] According to one aspect of the present application, a CMOS power amplifier is provided, comprising: a transconductor and a common-gate transistor, wherein the transconductor comprises a first CMOS transistor and a second CMOS transistor, and the common-gate transistor comprises a third CMOS transistor and a fourth CMOS transistor, wherein

[0006] Sources of the first CMOS transistor and the second CMOS transistor are respectively connected to a ground potential to form a pseudo differential pair;

[0007] The drains of the first CMOS transistor and the second CMOS transistor are connected to the sources of the third CMOS transistor and the fourth CMOS transistor respectively to form a common gate structure;

[0008] The front-stage driver amplifier of the CMOS power amplifier outputs a main path and an auxiliary path. The main path is connected to the gates of the first CMOS transistor and the second CMOS transistor respectively through AC dual capacitors, and the auxiliary path is connected to the gates of the third CMOS transistor and the fourth CMOS transistor through the envelope detection circuit output DC bias voltage.

[0009] Optionally, the CMOS power amplifier further includes: a fixed bias voltage, which is connected to the gates of the first CMOS transistor and the second CMOS transistor respectively through AC dual capacitors to provide a voltage bias for the transconductor.

[0010] Optionally, the CMOS power amplifier further includes: a Balun connected to the drains of the third CMOS transistor and the fourth CMOS transistor, wherein the Balun realizes differential to single-ended conversion.

[0011] Optionally, the DC bias voltage increases with increasing input power, thereby increasing the linearity of the first CMOS transistor.

[0012] Optionally, the gate voltage of the first CMOS transistor is:

[0013] vd=vbc-vgs3

[0014] Wherein, vd is the gate voltage of the first CMOS transistor, vbc is the DC bias voltage output by the envelope detection circuit, and vgs3 is the source voltage of the third CMOS transistor.

[0015] Therefore, the present application adopts envelope tracking bias for the third CMOS transistor M3 and the fourth CMOS transistor M4 of the common-gate tube, that is, the DC bias voltage vbc increases with the increase of input power, which will improve the linearity of the first CMOS transistor M1. After adopting ET bias in the present application, the increase of input power vin leads to an increase of DC bias voltage, and the drain voltage of the first CMOS transistor is equal to the DC bias voltage minus the source voltage of the third CMOS transistor, which means that the increase of DC bias voltage will increase the drain voltage of the first CMOS transistor, thereby improving the linearity of the entire power amplifier.

[0016] Based on the detailed description of the specific embodiments of the present application in combination with the accompanying drawings below, those skilled in the art will become more aware of the above and other objects, advantages and features of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Hereinafter, some specific embodiments of the present application will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings:

[0018] Figure 1 is a circuit diagram of a conventional CMOS power amplifier according to an embodiment of the present application;

[0019] Figure 2 is a circuit diagram of a CMOS power amplifier according to an embodiment of the present application;

[0020] Figure 3 It is a schematic diagram of simulation results of a CMOS power amplifier using the present application according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0022] In order to enable those skilled in the art to better understand the scheme of the present disclosure, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present disclosure.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0025] Figure 2 is a circuit diagram of a CMOS power amplifier according to an embodiment of the present application. Figure 1As shown, a CMOS power amplifier includes: a transconductor and a common-gate transistor, the transconductor includes a first CMOS transistor and a second CMOS transistor, the common-gate transistor includes a third CMOS transistor and a fourth CMOS transistor, wherein

[0026] Sources of the first CMOS transistor and the second CMOS transistor are respectively connected to a ground potential to form a pseudo differential pair;

[0027] The drains of the first CMOS transistor and the second CMOS transistor are connected to the sources of the third CMOS transistor and the fourth CMOS transistor respectively to form a common gate structure;

[0028] The front-stage driver amplifier of the CMOS power amplifier outputs a main path and an auxiliary path. The main path is connected to the gates of the first CMOS transistor and the second CMOS transistor respectively through AC dual capacitors, and the auxiliary path is connected to the gates of the third CMOS transistor and the fourth CMOS transistor through the envelope detection circuit output DC bias voltage.

[0029] Optionally, the gate voltage of the first CMOS transistor is:

[0030] vd=vbc-vgs3

[0031] Wherein, vd is the gate voltage of the first CMOS transistor, vbc is the DC bias voltage output by the envelope detection circuit, and vgs3 is the source voltage of the third CMOS transistor.

[0032] Specifically, envelope tracking bias is adopted for the third CMOS transistor M3 and the fourth CMOS transistor M4 of the common-gate tube, that is, the DC bias voltage vbc increases with the increase of input power, which will improve the linearity of the first CMOS transistor M1. Figure 1 As shown, in the prior art, it is assumed that the third CMOS transistor M3 and the fourth CMOS transistor M4 are biased with a fixed voltage. Then, when the input power vin increases, since the first CMOS transistor M1 and the second CMOS transistor M2 will need to provide more dynamic current, the drain voltage vd of the first CMOS transistor M1 decreases, reducing the transconductance of the first CMOS transistor M1, and the gain begins to compress. If the input power vin continues to increase, the first CMOS transistor M1 completely enters the linear region. After the ET bias is adopted in the present application, the increase in the input power vin causes the DC bias voltage vbc to increase, and the drain voltage vd of the first CMOS transistor M1 is equal to vbc minus vgs3, which means that the increase in vbc will increase vd, thereby improving the linearity of the entire power amplifier.

[0033] Optionally, the CMOS power amplifier further includes: a fixed bias voltage, which is connected to the gates of the first CMOS transistor and the second CMOS transistor respectively through AC dual capacitors to provide a voltage bias for the transconductor.

[0034] Specifically, the present invention modifies the biasing mode of the power amplifier, wherein a fixed bias voltage vb is used for the input first CMOS transistor M1, which means that when the input power is small, the transconductance of the first CMOS transistor M1 and the second CMOS transistor M2 is a constant, thereby indicating that the small signal gain of the power amplifier is constant. At the same time, the fixed bias voltage vb greatly reduces the change of the gate capacitance of the first CMOS transistor M1 and the second CMOS transistor M2 with the input power, thereby reducing AM-PM distortion.

[0035] Optionally, the CMOS power amplifier further includes: a Balun connected to the drains of the third CMOS transistor and the fourth CMOS transistor, wherein the Balun realizes differential to single-ended conversion.

[0036] Optionally, the DC bias voltage increases with increasing input power, thereby increasing the linearity of the first CMOS transistor.

[0037] Specifically, the first CMOS transistor M1 and the second CMOS transistor M2 are transconductors of the power amplifier. The source ground potential of the first CMOS transistor M1 and the second CMOS transistor M2 forms a pseudo differential pair. The drains of the first CMOS transistor M1 and the second CMOS transistor M2 are respectively connected to the source of the third CMOS transistor M3 and the fourth CMOS transistor M4 to form a common source and common gate structure. The input of the power amplifier comes from the output of the pre-stage circuit DA. The DA output is divided into two paths, in which the main path is connected to the gates of the first CMOS transistor M1 and the second CMOS transistor M2 respectively through AC dual capacitors, and a fixed bias voltage vb is used to provide voltage bias through a resistor. The auxiliary path first passes through a package detection circuit ET, and the output of ET provides a DC bias voltage of vbc, which is directly connected to the gates of the third CMOS transistor M3 and the fourth CMOS transistor M4, and the different linearities of the amplifier are adjusted with the different DC bias voltages vbc. The drains of the third CMOS transistor M3 and the fourth CMOS transistor M4 are connected to the output Balun, and the differential to single-ended conversion is realized through Balun, and then the power is transmitted through the antenna.

[0038] also, Figure 3 The figure is a schematic diagram of the specific simulation results, where the dotted line represents the simulation results under constant bias, the power amplifier gain is 10.3dB, the output 1dB compression point is 8.7dBm, and the efficiency is 12.9%. The solid line represents the simulation results under constant bias. Figure 1 The simulation results after the bias technology shown in the figure show that the power amplifier gain is 9.6dB, the output 1dB compression point is 11.4dBm, and the efficiency reaches 20%. Figure 1 After the bias mode, the AM-AM distortion is significantly reduced.

[0039] Therefore, the present invention can reduce the AM-AM distortion of the power amplifier, reduce the AM-PM distortion, and increase the output 1dB compression point, thereby comprehensively improving the linearity of the power amplifier. 1. Applicable to radio frequency systems and chips with different frequency bands and different uses (such as short-range wireless communication, Bluetooth, wifi, etc.).

[0040] Unless otherwise specifically stated, the relative arrangement of the parts and steps described in these embodiments, numerical expressions and numerical values ​​do not limit the scope of the present disclosure. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship. The technology, methods and equipment known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the technology, methods and equipment should be regarded as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0041] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0042] In the description of the present disclosure, it is necessary to understand that the orientation or positional relationship indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the scope of protection of the present disclosure; the directional words "inside and outside" refer to the inside and outside relative to the outline of each component itself.

[0043] The above is only a preferred specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A CMOS power amplifier, achieving improved linearity, characterized in that: include: A transconductor and a common-gate transistor, wherein the transconductor includes a first CMOS transistor and a second CMOS transistor, and the common-gate transistor includes a third CMOS transistor and a fourth CMOS transistor, wherein The sources of the first CMOS transistor and the second CMOS transistor are respectively connected to a ground potential to form a pseudo differential pair; The drains of the first CMOS transistor and the second CMOS transistor are connected to the sources of the third CMOS transistor and the fourth CMOS transistor respectively to form a common gate structure; The front-stage driver amplifier of the CMOS power amplifier outputs a main path and an auxiliary path. The main path is connected to the gates of the first CMOS transistor and the second CMOS transistor respectively through the AC dual capacitors, and the auxiliary path is connected to the gates of the third CMOS transistor and the fourth CMOS transistor through the envelope detection circuit output DC bias voltage.

2. The CMOS power amplifier according to claim 1, characterized in that: Also includes: A fixed bias voltage is connected to the gate of the first CMOS transistor and the gate of the second CMOS transistor respectively through AC dual capacitors to provide a voltage bias for the transconductor.

3. The CMOS power amplifier according to claim 1, characterized in that: Also includes: A Balun connected to the drains of the third CMOS transistor and the fourth CMOS transistor, wherein the Balun realizes differential to single-ended conversion.

4. The CMOS power amplifier according to claim 1, characterized in that: The DC bias voltage increases with the increase of input power, thereby increasing the linearity of the first CMOS transistor.

5. The CMOS power amplifier according to claim 4, characterized in that: The gate voltage of the first CMOS transistor is: vd=vbc-vgs3 Wherein, vd is the gate voltage of the first CMOS transistor, vbc is the DC bias voltage output by the envelope detection circuit, and vgs3 is the source voltage of the third CMOS transistor.

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