All-gallium nitride integrated driving circuit with dead time control, chip and equipment

Abstract

The invention discloses a full gallium nitride integrated driving circuit with dead time control, a chip and equipment, the circuit comprises a power supply management module, a driving module and an output voltage clamping module, the input end of the power supply management module is connected to an external power supply end, and the output end of the driving module is connected to an external power supply end; the output end of the power management module is connected with the first input end of the driving module; the first input end of the driving module is connected to the input end of the output voltage clamping module, the second input end of the driving module is connected to an external control signal end, and the output end of the driving module is connected to the input end of the output voltage clamping module and the output end of the all-gallium nitride integrated driving circuit. The dead zone time is controlled through the driving module, so that the problem that the last driving stage is communicated up and down due to the fact that the dead zone time is too short can be avoided, and the problem that the time delay of the driving circuit is large due to the fact that the dead zone time is too long can also be avoided.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a full gallium nitride integrated drive circuit, chip and device with dead time control. Background Art

[0002] As a representative material of the third-generation semiconductors, GaN has the advantages of high breakdown voltage, wide bandgap and high electron mobility. The High Electron Mobility Transistor (HEMT) device prepared using it has the advantages of low cost and high performance compared to traditional Si-based power devices, and has great potential in high-voltage and high-power electronic power applications.

[0003] At present, power electronic systems are developing towards small size, high power and high efficiency. However, due to the limitation of silicon material characteristics, silicon-based device circuits have become increasingly difficult to meet the needs of current power electronic conversion systems. As the third-generation semiconductor material gallium nitride has superior properties such as high frequency, high efficiency, high power, high voltage resistance, high temperature resistance and strong radiation resistance, power devices in power conversion systems have gradually been replaced by silicon-based power devices. Gallium nitride materials have also become the key core materials supporting the transformation and upgrading of industries such as the new generation of new energy vehicles and energy Internet.

[0004] However, due to the lack of mature GaN technology and the low channel hole mobility of P-type GaN devices, current GaN power devices and their driving solutions are mainly based on silicon-based driving circuits or RTL logic integrated driving circuits composed of all-N-type GaN and resistors. Among them, the silicon-based drive plus GaN power device solution cannot fully utilize the high frequency and high efficiency advantages of GaN power devices due to large parasitics. Therefore, current research focuses on all-N-type integrated GaN drive and power devices.

[0005] In order to improve the current driving capability and reduce power consumption and delay, the driving circuit of the single-tube GaN power device is mainly based on push-pull output drive. Since the current output of the last stage is very large, considering the safety of the system, it is very important to prevent the last stage device from connecting. For the traditional driving circuit with fixed dead time control, if the dead time is too short, connecting cannot be avoided. If the dead time is too long, it will cause a large transmission delay. Summary of the invention

[0006] The purpose of this application is to provide a full gallium nitride integrated drive circuit, chip and device with dead time control to solve the problem in the related art that the dead time of the traditional drive circuit cannot be flexibly adjusted.

[0007] In order to achieve the above objectives, this application provides the following technical solutions:

[0008] In a first aspect, the present application provides a full gallium nitride integrated driving circuit with dead time control, comprising: a power management module, a driving module and an output voltage clamping module, wherein the input end of the power management module is connected to an external power supply end, and the output end of the power management module is connected to the first input end of the driving module; the second input end of the driving module is connected to an external control signal end, and the output end of the driving module is connected to the input end of the output voltage clamping module and the output end of the full gallium nitride integrated driving circuit; the driving module comprises: an RS trigger, a first NOR gate, a second NOR gate, a first bootstrap buffer, a second bootstrap buffer, a seventh gallium nitride transistor and an eighth gallium nitride transistor, wherein the first input end of the RS trigger is connected to the external control signal end, and the second input end of the RS trigger is connected to the output end of the power management module, The first output terminal of the RS trigger is connected to the first input terminal of the first NOR gate, and the second output terminal of the RS trigger is connected to the second input terminal of the second NOR gate; the second input terminal of the first NOR gate is connected to the gate of the seventh GaN transistor, and the output terminal of the first NOR gate is connected to the input terminal of the first bootstrap buffer; the first output terminal of the first bootstrap buffer is connected to the gate of the seventh GaN transistor, and the second output terminal of the first bootstrap buffer is connected to the first input terminal of the second NOR gate; the output terminal of the second NOR gate is connected to the input terminal of the second bootstrap buffer; the first output terminal of the second bootstrap buffer is connected to the gate of the eighth GaN transistor; the drain of the seventh GaN transistor is connected to the external power supply terminal, and the source of the seventh GaN transistor is connected to the drain of the eighth GaN transistor; the source of the eighth GaN transistor is grounded.

[0009] Further, the power management module includes: a first resistor, a second resistor, a third resistor, a first hysteresis inverter, a second hysteresis inverter, a first inverter and a first OR gate, wherein the first resistor, the second resistor and the third resistor are connected in series in sequence, the first end of the first resistor is connected to the external power supply end, and the second end of the third resistor is grounded; the input end of the first hysteresis inverter is connected to the common end of the first resistor and the second resistor, and the output end of the first hysteresis inverter is connected to the input end of the first inverter; the input end of the second hysteresis inverter is connected to the common end of the second resistor and the third resistor, and the output end of the second hysteresis inverter is connected to the second input end of the first OR gate; the first input end of the first OR gate is connected to the output end of the first inverter, and the output end of the first OR gate is connected to the output end of the power management module.

[0010] Further, the first hysteresis inverter includes: a fourth resistor, a first gallium nitride transistor, a second gallium nitride transistor, and a third gallium nitride transistor, wherein a first end of the fourth resistor is connected to the external power supply terminal and the drain of the third gallium nitride transistor, and a second end of the fourth resistor is connected to a gate of the third gallium nitride transistor, a drain of the first gallium nitride transistor, and an output end of the first hysteresis inverter; a gate of the first gallium nitride transistor is connected to a gate of the second gallium nitride transistor and an input end of the first hysteresis inverter, a source of the first gallium nitride transistor is connected to a drain of the second gallium nitride transistor and a source of the third gallium nitride transistor; and a source of the second gallium nitride transistor is grounded.

[0011] Further, the second hysteresis inverter includes: a fifth resistor, a fourth gallium nitride transistor, a fifth gallium nitride transistor, and a sixth gallium nitride transistor, wherein a first end of the fifth resistor is connected to the external power supply terminal and the drain of the sixth gallium nitride transistor, a second end of the fifth resistor is connected to a gate of the sixth gallium nitride transistor, a drain of the fourth gallium nitride transistor, and an output end of the second hysteresis inverter; a gate of the fourth gallium nitride transistor is connected to a gate of the fifth gallium nitride transistor and an input end of the second hysteresis inverter, a source of the fourth gallium nitride transistor is connected to a drain of the fifth gallium nitride transistor and a source of the sixth gallium nitride transistor; and a source of the fifth gallium nitride transistor is grounded.

[0012] Furthermore, the first bootstrap buffer includes: a second inverter, a first bootstrap voltage generating circuit, and a first push-pull output circuit, wherein the input end of the second inverter is connected to the input end of the first bootstrap buffer, the output end of the second inverter is connected to the input end of the first bootstrap voltage generating circuit and the first input end of the first push-pull output circuit; the output end of the first bootstrap voltage generating circuit is connected to the second input end of the first push-pull output circuit; the first output end of the first push-pull output circuit is connected to the first output end of the first bootstrap buffer, and the second output end of the first push-pull output circuit is connected to the second output end of the first bootstrap buffer.

[0013] Further, the first bootstrap voltage generating circuit includes: a sixth resistor, a ninth gallium nitride transistor, a tenth gallium nitride transistor and a first capacitor, wherein a first end of the sixth resistor, a gate of the ninth gallium nitride transistor and a drain of the ninth gallium nitride transistor are connected to the external power supply terminal, a second end of the first resistor is connected to the drain of the ninth gallium nitride transistor and a second end of the first capacitor; a gate of the ninth gallium nitride transistor is connected to an input end of the first bootstrap voltage generating circuit, a source of the ninth gallium nitride transistor is grounded; and a source of the tenth gallium nitride transistor is connected to a first end of the first capacitor and an output end of the first bootstrap voltage generating circuit.

[0014] Further, the first push-pull output circuit includes: a seventh resistor, an eleventh gallium nitride transistor, a twelfth gallium nitride transistor, a thirteenth gallium nitride transistor, a fourteenth gallium nitride transistor, and a fifteenth gallium nitride transistor, wherein a first end of the seventh resistor is connected to the drain of the twelfth gallium nitride transistor and the output end of the first bootstrap voltage generating circuit, a second end of the seventh resistor is connected to the drain of the eleventh gallium nitride transistor and the gate of the twelfth gallium nitride transistor; the gate of the eleventh gallium nitride transistor is connected to the gate of the thirteenth gallium nitride transistor and the gate of the fifteenth gallium nitride transistor. The source of the eleventh gallium nitride transistor is connected to the source of the thirteenth gallium nitride transistor, the source of the fifteenth gallium nitride transistor and the ground terminal; the source of the twelfth gallium nitride transistor is connected to the drain of the thirteenth gallium nitride transistor, the gate of the fourteenth gallium nitride transistor and the first output terminal of the first push-pull output circuit; the drain of the fourteenth gallium nitride transistor is connected to the external power supply terminal, and the source of the fourteenth gallium nitride transistor is connected to the drain of the fifteenth gallium nitride transistor and the second output terminal of the first push-pull output circuit.

[0015] Furthermore, the second bootstrap buffer includes: a third inverter, a second bootstrap voltage generating circuit, and a second push-pull output circuit, wherein the input end of the third inverter is connected to the input end of the second bootstrap buffer, and the output end of the third inverter is connected to the input end of the second bootstrap voltage generating circuit and the first input end of the second push-pull output circuit; the output end of the second bootstrap voltage generating circuit is connected to the second input end of the second push-pull output circuit; the first output end of the second push-pull output circuit is connected to the first output end of the second bootstrap buffer, and the second output end of the second push-pull output circuit is connected to the second output end of the second bootstrap buffer.

[0016] Further, the output voltage clamping module includes: a sixteenth gallium nitride transistor, a seventeenth gallium nitride transistor, an eighteenth gallium nitride transistor and a nineteenth gallium nitride transistor, wherein the drain of the sixteenth gallium nitride transistor is connected to the gate of the sixteenth gallium nitride transistor and the output end of the full gallium nitride integrated driving circuit, the source of the sixteenth gallium nitride transistor is connected to the drain of the seventeenth gallium nitride transistor and the gate of the seventeenth gallium nitride transistor; the source of the seventeenth gallium nitride transistor is connected to the drain of the eighteenth gallium nitride transistor, the gate of the eighteenth gallium nitride transistor and the gate of the nineteenth gallium nitride transistor; the source of the eighteenth gallium nitride transistor and the source of the nineteenth gallium nitride transistor are grounded.

[0017] In a second aspect, the present application further provides a chip, wherein the chip comprises a full gallium nitride integrated drive circuit as described above.

[0018] In a third aspect, the present application also provides an electronic device, wherein the electronic device includes the chip as described above.

[0019] The present application provides a full gallium nitride integrated drive circuit, chip and device with dead time control, which has the following beneficial effects:

[0020] 1. The all-GaN integrated driving circuit based on driving delay to generate self-adjusting dead time of the present invention adopts all-N-type GaN device design, which can realize the monolithic integration of driving circuit and GaN power device, reduce parasitics, and give full play to the high-speed and high-efficiency characteristics of GaN power device.

[0021] 2. The all-gallium nitride integrated driving circuit of the present invention that generates self-adjusting dead time based on driving delay detects the level of the gate of the last-stage power tube and feeds it back to the previous-stage NOR gate, so that the circuit can achieve self-adjusting dead time. At the same time, no capacitor is required to generate delay, which greatly reduces the area of ​​the driving circuit.

[0022] 3. The all-gallium nitride integrated driving circuit of the present invention that generates self-adjusting dead time based on driving delay integrates a power management module and an output voltage clamping module, thereby ensuring that the power supply voltage of the driving circuit is within a reasonable range and reducing the situation where the output voltage is too high, causing the performance degradation or even damage of the power tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural schematic diagram of a full gallium nitride integrated driving circuit with dead time control according to an embodiment of the present application;

[0024] Figure 2 is a schematic diagram of the circuit structure of the power management module in an embodiment of the present application;

[0025] Figure 3 is a schematic diagram of the circuit structure of the first hysteresis inverter in an embodiment of the present application;

[0026] Figure 4 is a schematic diagram of the circuit structure of the second hysteresis inverter in an embodiment of the present application;

[0027] Figure 5 is a schematic diagram of the circuit structure of the driving module in an embodiment of the present application;

[0028] Figure 6 is a schematic diagram of the circuit structure of the first bootstrap buffer in an embodiment of the present application;

[0029] Figure 7 is a schematic structural diagram of a first bootstrap circuit generating circuit in an embodiment of the present application;

[0030] Figure 8 is a schematic structural diagram of a first push-pull output circuit in an embodiment of the present application;

[0031] Fig. 9 is a schematic diagram of the circuit structure of the second bootstrap buffer in an embodiment of the present application;

[0032] Fig.10 is a schematic diagram of the circuit structure of the output voltage clamping module in an embodiment of the present application;

[0033] Fig.11 A schematic diagram of automatically adjusting dead time generated by drive circuits with different drive level sizes provided in an embodiment of the present application.

[0034] Reference numerals: 100, all-gallium nitride integrated driving circuit; 10, power management module; 20, driving module; 30, output voltage clamping module; 14, first hysteresis inverter; 15, second hysteresis inverter; 16, first inverter; 17, first OR gate; 21, RS trigger; 22, first NOR gate; 23, second NOR gate; 24, first bootstrap buffer; 241, second inverter; 242, first bootstrap voltage generating circuit; 243, The first push-pull output circuit; 25, the second bootstrap buffer; 251, the third inverter; 252, the second bootstrap voltage generating circuit; 253, the second push-pull output circuit; C1, the first capacitor; R11, the first resistor; R12, the second resistor; R13, the third resistor; R14, the fourth resistor; R15, the fifth resistor; R16, the sixth resistor; R17, the seventh resistor; Q1-Q19, the first gallium nitride transistor-the nineteenth gallium nitride transistor. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0037] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include: one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0039] The terms used in one or more embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of the present application. The singular forms "a", "said" and "the" used in one or more embodiments of the present application are also intended to include: plural forms, unless the context clearly indicates other meanings.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of the template are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0041] It should be understood that, although the terms first, second, etc. may be used to describe various information in one or more embodiments of the present application, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of the present application, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when the time of".

[0042] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes are not repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0043] Please refer to Figure 1 The embodiment of the present application provides a full gallium nitride integrated driving circuit 100 with dead time control, comprising: a power management module 10, a driving module 20 and an output voltage clamping module 30, wherein:

[0044] The input end of the power management module 10 is connected to an external power supply end, the voltage of the power supply end is VCC, and the output end of the power management module 10 is connected to the first input end of the driving module 20;

[0045] The second input end of the driving module 20 is connected to the external control signal end, and the control signal outputted by the control signal end is PWM_IN. The output end of the driving module 20 is connected to the input end of the output voltage clamping module 30 and the output end of the full gallium nitride integrated driving circuit 100, and the voltage outputted by the output end of the full gallium nitride integrated driving circuit 100 is PWM_VG.

[0046] See also Figure 2In a certain embodiment, the power management module 10 includes: a first resistor R11, a second resistor R12, a third resistor R13, a first hysteresis inverter 14, a second hysteresis inverter 15, a first inverter 16 and a first OR gate 17, wherein the first resistor R11, the second resistor R12 and the third resistor R13 are connected in series in sequence, a first end of the first resistor R11 is connected to the external power supply end, and a second end of the third resistor R13 is grounded; an input end of the first hysteresis inverter is connected to a common end of the first resistor R11 and the second resistor R12, and an output end of the first hysteresis inverter 14 is connected to an input end of the first inverter 16; an input end of the second hysteresis inverter 15 is connected to a common end of the second resistor R12 and the third resistor R13, and an output end of the second hysteresis inverter 15 is connected to a second input end of the first OR gate 17; a first input end of the first OR gate 17 is connected to an output end of the first inverter 16, and an output end of the first OR gate 17 is connected to an output end of the power management module 10.

[0047] Specifically, the working principle of the power management module 10 is as follows: the input end of the power management module 10 is connected to the external power supply end, the power supply voltage of the external power supply end is VCC, and the VCC voltage is divided by the first resistor R11, the second resistor R12 and the third resistor R13 in the power management module 10, wherein the voltage VA of the common end of the second resistor R12 and the third resistor R13 is R13*VCC / (R11+R12+R13), and the voltage VB of the common end of the first resistor R11 and the second resistor R12 is (R13+R12)*VCC / (R11+R12+R13). When VCC is very low, the voltages of VA and VB are both less than the threshold voltages of the first hysteresis inverter 14 and the second hysteresis inverter 15, then the voltage VC of the first input end of the first OR gate 17 is is low level, the voltage VD at the second input end of the first OR gate 17 is high level, after passing through the first OR gate 17, the output voltage VCC_OK is high level, and the subsequent driver is controlled to be turned off; with the increase of VCC, when the voltage of VB is greater than the threshold voltage of the first hysteresis inverter 14 and the voltage of VA is less than the threshold voltage of the second hysteresis inverter 15, VC is high level, VD is high level, after passing through the first OR gate 17, the output voltage VCC_OK is high level, and the subsequent driver is controlled to work normally; when VCC continues to increase, when the voltage of VB is greater than the threshold voltage of the first hysteresis inverter 14 and the voltage of VA is greater than the threshold voltage of the second hysteresis inverter 15, VC is high level, VD is low level, after passing through the first OR gate 17, the output voltage VCC_OK is high level, and the subsequent driver is controlled to be turned off. The control signal is generated by the power management module 10 to ensure that the power supply VCC is within a reasonable voltage range and the drive circuit works normally.

[0048] In a specific embodiment, see Figure 3 The first hysteresis inverter 14 includes: a fourth resistor R14, a first gallium nitride transistor Q1, a second gallium nitride transistor Q2, and a third gallium nitride transistor Q3, wherein a first end of the fourth resistor R14 is connected to the external power supply terminal VCC and the drain of the third gallium nitride transistor Q3, a second end of the fourth resistor R14 is connected to the gate of the third gallium nitride transistor Q3, the drain of the first gallium nitride transistor Q1, and the output end of the first hysteresis inverter 14; a gate of the first gallium nitride transistor Q1 is connected to a gate of the second gallium nitride transistor Q2 and an input end of the first hysteresis inverter 14, a source of the first gallium nitride transistor Q1 is connected to a drain of the second gallium nitride transistor Q2 and a source of the third gallium nitride transistor Q3; and a source of the second gallium nitride transistor Q2 is grounded.

[0049] In a specific embodiment, see Figure 4 The second hysteresis inverter 15 includes: a fifth resistor R15, a fourth GaN transistor Q4, a fifth GaN transistor Q5, and a sixth GaN transistor Q6, wherein a first end of the fifth resistor R15 is connected to the external power supply terminal and the drain of the sixth GaN transistor Q6, a second end of the fifth resistor R15 is connected to the gate of the sixth GaN transistor Q6, the drain of the fourth GaN transistor Q4, and the output end of the second hysteresis inverter 15; a gate of the fourth GaN transistor Q4 is connected to a gate of the fifth GaN transistor Q5 and the input end of the second hysteresis inverter 15, a source of the fourth GaN transistor Q4 is connected to the drain of the fifth GaN transistor Q5 and the source of the sixth GaN transistor Q6; and a source of the fifth GaN transistor Q5 is grounded.

[0050] In one embodiment, see Figure 5The driving module 20 includes: an RS trigger 21, a first NOR gate 22, a second NOR gate 23, a first bootstrap buffer 24, a second bootstrap buffer 25, a seventh GaN transistor Q7, and an eighth GaN transistor Q8, wherein the first input end of the RS trigger 21 is connected to the external control signal end, the second input end of the RS trigger 21 is connected to the output end of the power management module 10, the first output end of the RS trigger 21 is connected to the first input end of the first NOR gate 22, and the second output end of the RS trigger 21 is connected to the second input end of the second NOR gate 23; the second input end of the first NOR gate 22 is connected to the gate of the seventh GaN transistor Q7, and the first NOR gate 23 is connected to the gate of the seventh GaN transistor Q7. The output end of the gate 22 is connected to the input end of the first bootstrap buffer 24; the first output end of the first bootstrap buffer 24 is connected to the gate of the seventh gallium nitride transistor Q7, and the second output end of the first bootstrap buffer 24 is connected to the first input end of the second NOR gate 23; the output end of the second NOR gate 23 is connected to the input end of the second bootstrap buffer 25; the first output end of the second bootstrap buffer 25 is connected to the gate of the eighth gallium nitride transistor Q8; the drain of the seventh gallium nitride transistor Q7 is connected to the external power supply terminal, the source of the seventh gallium nitride transistor Q7 is connected to the drain of the eighth gallium nitride transistor Q8; the source of the eighth gallium nitride transistor Q8 is grounded.

[0051] Specifically, the working principle of the driving module 20 is as follows: the second input terminal of the RS trigger 21 is connected to the output terminal of the power management module 10, and the output voltage signal of the output terminal of the power management module 10 is the first target signal VCC_OK. When the first target signal VCC_OK is at a low level, the RS trigger 21 is reset. Assuming that the battery of the second output terminal Q of the RS trigger 21 is at a low level in the initial state, according to the output logic of the NOR gate, the voltage VOL output by the first output terminal of the second bootstrap buffer 25 is at a low level, and the voltage VOH output by the second output terminal of the first bootstrap buffer 24 is at a high level. The first output terminal Q point of the RS trigger 21 is converted from a low level to a high level, so that the voltage VOH changes from a high level to a low level. Similarly, the first output terminal Q of the RS trigger 21 is converted from a high level to a low level, so that the voltage VOL is converted from a high level to a low level, and then the voltage VOH is converted from a low level to a high level. Therefore, unless VOL changes to a low level, VOH cannot change to a high level. At the same time, unless VOH changes to a low level, VOL cannot change to a high level. By detecting the gate level of the last driving stage (the gate voltage of the seventh gallium nitride transistor Q7 and the seventh gallium nitride transistor Q7), the gate voltage is fed back to the first NOR gate 22 and the second NOR gate 23 to generate a dead time based on the driving delay, so as to prevent the seventh gallium nitride transistor Q7 and the eighth gallium nitride transistor Q7 from being connected up and down.

[0052] In a specific embodiment, see Figure 6 The first bootstrap buffer 24 includes: a second inverter 241, a first bootstrap voltage generating circuit 242, and a first push-pull output circuit 243, wherein the input end of the second inverter 241 is connected to the input end of the first bootstrap buffer 24, the output end of the second inverter 241 is connected to the input end of the first bootstrap voltage generating circuit 242 and the first input end of the first push-pull output circuit 243; the output end of the first bootstrap voltage generating circuit 242 is connected to the second input end of the first push-pull output circuit 243; the first output end of the first push-pull output circuit 243 is connected to the first output end of the first bootstrap buffer 24, and the second output end of the first push-pull output circuit 243 is connected to the second output end of the first bootstrap buffer 24.

[0053] Specifically, the working principle of the first bootstrap buffer 24 is as follows: the first bootstrap voltage generating circuit 242 generates a bootstrap voltage to power the first push-pull output circuit 243, the first end of the first push-pull output circuit 243 outputs an OUT voltage between 0 and VCC, driving the eighth gallium nitride transistor Q8 to turn on, and the second end of the first push-pull output circuit 243 outputs an OUT_BST voltage between 0 and (2*VCC-VD) to drive the eighth gallium nitride transistor Q8 to turn on.

[0054] In a specific embodiment, see Figure 7 The first bootstrap voltage generating circuit 242 includes: a sixth resistor R16, a ninth gallium nitride transistor Q9, a tenth gallium nitride transistor Q9 and a first capacitor C1, wherein a first end of the sixth resistor R16, a gate of the ninth gallium nitride transistor Q9 and a drain of the ninth gallium nitride transistor Q9 are connected to the external power supply terminal, a second end of the sixth resistor R16 is connected to the drain of the ninth gallium nitride transistor Q9 and a second end of the first capacitor C1; a gate of the ninth gallium nitride transistor Q9 is connected to an input terminal of the first bootstrap voltage generating circuit 242, and a source of the ninth gallium nitride transistor Q9 is grounded; a source of the tenth gallium nitride transistor Q10 is connected to a first end of the first capacitor C1 and an output terminal of the first bootstrap voltage generating circuit 242.

[0055] Specifically, the working principle of the first bootstrap voltage generating circuit 242 is as follows: when the input of the first bootstrap voltage generating circuit 242 is a high level, the ninth gallium nitride transistor Q9 is turned on, and VCC charges the first capacitor C1 through the tenth gallium nitride transistor Q10 connected in the form of a diode. The voltage VBOOT at the first end (upper plate) of the first capacitor C1 is VCC-VD, where VD is the conduction voltage drop of the tenth gallium nitride transistor Q10 connected in the form of a diode. When the input of the first bootstrap voltage generating circuit 242 is a low level, the ninth gallium nitride transistor Q9 is turned on and off, and the voltage at the second end (lower plate) of the first capacitor C1 is VCC. Due to the characteristic that the voltage across the first capacitor C1 cannot change suddenly, the upper plate voltage VBOOT of the first capacitor C1 is raised to 2*VCC-VD at this time, ensuring that the pull-up tenth gallium nitride transistor Q10 in the first push-pull output circuit 243 can be fully turned on.

[0056] In a specific embodiment, see Figure 8The first push-pull output circuit 243 includes: a seventh resistor R17, an eleventh GaN transistor Q11, a twelfth GaN transistor Q12, a thirteenth GaN transistor Q13, a fourteenth GaN transistor Q14, and a fifteenth GaN transistor Q15, wherein a first end of the seventh resistor R17 is connected to the drain of the twelfth GaN transistor Q12 and the output end of the first bootstrap voltage generating circuit 242, a second end of the seventh resistor R17 is connected to the drain of the eleventh GaN transistor Q11 and the gate of the twelfth GaN transistor Q12; the gate of the eleventh GaN transistor is connected to the gate of the thirteenth GaN transistor and the gate of the fifteenth GaN transistor Q15. The source of the eleventh gallium nitride transistor Q11 is connected to the source of the thirteenth gallium nitride transistor Q13, the source of the fifteenth gallium nitride transistor Q15 and the ground terminal; the source of the twelfth gallium nitride transistor Q12 is connected to the drain of the thirteenth gallium nitride transistor Q13, the gate of the fourteenth gallium nitride transistor Q14 and the first output terminal of the first push-pull output circuit 243; the drain of the fourteenth gallium nitride transistor Q14 is connected to the external power supply terminal, and the source of the fourteenth gallium nitride transistor Q14 is connected to the drain of the fifteenth gallium nitride transistor Q15 and the second output terminal of the first push-pull output circuit 243.

[0057] Specifically, the working principle of the first push-pull output circuit 243 is as follows: when the input of the first push-pull output circuit 243 is a high level, the eleventh gallium nitride transistor Q11, the thirteenth gallium nitride transistor Q13 and the fifteenth gallium nitride transistor Q15 are turned on, the twelfth gallium nitride transistor Q12 and the fourteenth gallium nitride transistor Q14 are turned off, the second output terminal OUT of the first push-pull output circuit 243 outputs a low level, and the first output terminal OUT_BST of the first push-pull output circuit 243 outputs a low level; when the input of the first push-pull output circuit 243 is a low level, the eleventh gallium nitride transistor Q11, the thirteenth gallium nitride transistor Q13 and the fifteenth gallium nitride transistor Q15 are turned off, the twelfth gallium nitride transistor Q12 and the fourteenth gallium nitride transistor Q14 are turned on, the second output terminal OUT of the first push-pull output circuit 243 outputs a high level, and the first output terminal OUT_BST of the first push-pull output circuit 243 outputs a high level.

[0058] In one embodiment, see Fig. 9The second bootstrap buffer 25 includes: a third inverter 251, a second bootstrap voltage generating circuit 252, and a second push-pull output circuit 253, wherein the input end of the third inverter 251 is connected to the input end of the second bootstrap buffer 25, the output end of the third inverter 251 is connected to the input end of the second bootstrap voltage generating circuit 252 and the first input end of the second push-pull output circuit 253; the output end of the second bootstrap voltage generating circuit 252 is connected to the second input end of the second push-pull output circuit; the first output end of the second push-pull output circuit 253 is connected to the first output end of the second bootstrap buffer 25, and the second output end of the second push-pull output circuit 253 is connected to the second output end of the second bootstrap buffer 25.

[0059] It should be noted that the structure and function of the second bootstrap voltage generating circuit 252 are similar to those of the first bootstrap voltage generating circuit 242, and the specific working principle can refer to the description of the first bootstrap voltage generating circuit 242; the structure and function of the second push-pull output circuit 253 are similar to those of the first push-pull output circuit 243, and the specific working principle can refer to the description of the first push-pull output circuit 243.

[0060] In one embodiment, see Fig.10 The output voltage clamp module 30 includes: a sixteenth GaN transistor Q16, a seventeenth GaN transistor Q17, an eighteenth GaN transistor Q18 and a nineteenth GaN transistor Q19, wherein the drain of the sixteenth GaN transistor Q16 is connected to the gate of the sixteenth GaN transistor Q16 and the output end of the all-GaN integrated driving circuit 100, the source of the sixteenth GaN transistor Q16 is connected to the drain of the seventeenth GaN transistor Q17 and the gate of the seventeenth GaN transistor Q17; the source of the seventeenth GaN transistor Q17 is connected to the drain of the eighteenth GaN transistor Q18, the gate of the eighteenth GaN transistor Q18 and the gate of the nineteenth GaN transistor Q19; the source of the eighteenth GaN transistor Q18 and the source of the nineteenth GaN transistor Q19 are grounded.

[0061] Specifically, the working principle of the output voltage clamping module 30 is as follows: when the driving module 20 fails, so that the voltage PWM_VG output by the full gallium nitride integrated driving circuit 100 is higher than 3*VGS, the sixteenth gallium nitride transistor Q16, the seventeenth gallium nitride transistor Q17, and the eighteenth gallium nitride transistor Q18 are turned on, thereby turning on the switch tube nineteenth gallium nitride transistor Q19, so that the PWM_VG voltage drops quickly to a reasonable voltage range, the sixteenth gallium nitride transistor Q16, the seventeenth gallium nitride transistor Q17, and the eighteenth gallium nitride transistor Q18 are turned off, and the switch tube nineteenth gallium nitride transistor Q19 is also turned off, and the circuit operates normally.

[0062] See also Fig.11 ,from Fig.11 It can be seen that when the size of the integrated GaN HEMT power device increases, in order to match the corresponding driving capability, the size of the driving stage increases, the driving circuit delay increases, and the corresponding dead time is automatically adjusted with the circuit delay, which can effectively prevent the last driving stage from being connected up and down.

[0063] The present application provides a full gallium nitride integrated driving circuit with dead time control, which has the following beneficial effects:

[0064] 1. The all-GaN integrated driving circuit based on driving delay to generate self-adjusting dead time of the present invention adopts all-N-type GaN device design, which can realize the monolithic integration of driving circuit and GaN power device, reduce parasitics, and give full play to the high-speed and high-efficiency characteristics of GaN power device.

[0065] 2. The all-gallium nitride integrated driving circuit of the present invention that generates self-adjusting dead time based on driving delay detects the level of the gate of the last-stage power tube and feeds it back to the previous-stage NOR gate, so that the circuit can achieve self-adjusting dead time. At the same time, no capacitor is required to generate delay, which greatly reduces the area of ​​the driving circuit.

[0066] 3. The all-gallium nitride integrated driving circuit of the present invention that generates self-adjusting dead time based on driving delay integrates a power management module and an output voltage clamping module, thereby ensuring that the power supply voltage of the driving circuit is within a reasonable range and reducing the situation where the output voltage is too high, causing the performance degradation or even damage of the power tube.

[0067] The present application also provides a chip, wherein the chip comprises: a full gallium nitride integrated drive circuit as described in any one of the above.

[0068] The present application also provides an electronic device, which includes: the chip as described above.

[0069] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limiting, and thus other examples of the exemplary embodiments may have different values.

[0070] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0071] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include: one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0072] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0073] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

[0074] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A full gallium nitride integrated drive circuit with dead time control, characterized in that: include: Power management module, drive module and output voltage clamp module, among which, The input end of the power management module is connected to the external power supply end, and the output end of the power management module is connected to the first input end of the driving module; The second input terminal of the driving module is connected to the external control signal terminal, and the output terminal of the driving module is connected to the input terminal of the output voltage clamping module and the output terminal of the full gallium nitride integrated driving circuit; The driving module includes: an RS trigger, a first NOR gate, a second NOR gate, a first bootstrap buffer, a second bootstrap buffer, a seventh gallium nitride transistor and an eighth gallium nitride transistor, wherein: The first input terminal of the RS trigger is connected to the external control signal terminal, the second input terminal of the RS trigger is connected to the output terminal of the power management module, the first output terminal of the RS trigger is connected to the first input terminal of the first NOR gate, and the second output terminal of the RS trigger is connected to the second input terminal of the second NOR gate; The second input terminal of the first NOR gate is connected to the gate of the seventh GaN transistor, and the output terminal of the first NOR gate is connected to the input terminal of the first bootstrap buffer; A first output terminal of the first bootstrap buffer is connected to the gate of the seventh gallium nitride transistor, and a second output terminal of the first bootstrap buffer is connected to the first input terminal of the second NOR gate; The output terminal of the second NOR gate is connected to the input terminal of the second bootstrap buffer; A first output terminal of the second bootstrap buffer is connected to a gate of the eighth gallium nitride transistor; The drain of the seventh gallium nitride transistor is connected to the external power supply terminal, and the source of the seventh gallium nitride transistor is connected to the drain of the eighth gallium nitride transistor; A source of the eighth gallium nitride transistor is grounded.

2. The all-gallium nitride integrated drive circuit according to claim 1, characterized in that: The power management module includes: a first resistor, a second resistor, a third resistor, a first hysteresis inverter, a second hysteresis inverter, a first inverter and a first OR gate, wherein: The first resistor, the second resistor and the third resistor are connected in series in sequence, a first end of the first resistor is connected to the external power supply terminal, and a second end of the third resistor is grounded; The input end of the first hysteresis inverter is connected to the common end of the first resistor and the second resistor, and the output end of the first hysteresis inverter is connected to the input end of the first inverter; The input end of the second hysteresis inverter is connected to the common end of the second resistor and the third resistor, and the output end of the second hysteresis inverter is connected to the second input end of the first OR gate; The first input end of the first OR gate is connected to the output end of the first inverter, and the output end of the first OR gate is connected to the output end of the power management module.

3. The all-gallium nitride integrated drive circuit according to claim 2, characterized in that: The first hysteresis inverter includes: a fourth resistor, a first gallium nitride transistor, a second gallium nitride transistor, and a third gallium nitride transistor, wherein: A first end of the fourth resistor is connected to the external power supply terminal and the drain of the third gallium nitride transistor, and a second end of the fourth resistor is connected to the gate of the third gallium nitride transistor, the drain of the first gallium nitride transistor, and the output end of the first hysteresis inverter; The gate of the first gallium nitride transistor is connected to the gate of the second gallium nitride transistor and the input end of the first hysteresis inverter, and the source of the first gallium nitride transistor is connected to the drain of the second gallium nitride transistor and the source of the third gallium nitride transistor; A source of the second gallium nitride transistor is grounded.

4. The all-gallium nitride integrated drive circuit according to claim 2, characterized in that: The second hysteresis inverter includes: a fifth resistor, a fourth gallium nitride transistor, a fifth gallium nitride transistor, and a sixth gallium nitride transistor, wherein: A first end of the fifth resistor is connected to the external power supply terminal and the drain of the sixth gallium nitride transistor, and a second end of the fifth resistor is connected to the gate of the sixth gallium nitride transistor, the drain of the fourth gallium nitride transistor, and the output end of the second hysteresis inverter; The gate of the fourth gallium nitride transistor is connected to the gate of the fifth gallium nitride transistor and the input end of the second hysteresis inverter, and the source of the fourth gallium nitride transistor is connected to the drain of the fifth gallium nitride transistor and the source of the sixth gallium nitride transistor; A source of the fifth gallium nitride transistor is grounded.

5. The all-gallium nitride integrated drive circuit according to claim 1, characterized in that: The first bootstrap buffer comprises: a second inverter, a first bootstrap voltage generating circuit, and a first push-pull output circuit, wherein: The input end of the second inverter is connected to the input end of the first bootstrap buffer, and the output end of the second inverter is connected to the input end of the first bootstrap voltage generating circuit and the first input end of the first push-pull output circuit; The output terminal of the first bootstrap voltage generating circuit is connected to the second input terminal of the first push-pull output circuit; The first output end of the first push-pull output circuit is connected to the first output end of the first bootstrap buffer, and the second output end of the first push-pull output circuit is connected to the second output end of the first bootstrap buffer.

6. The all-gallium nitride integrated driving circuit according to claim 5, characterized in that: The first bootstrap voltage generating circuit includes: a sixth resistor, a ninth gallium nitride transistor, a tenth gallium nitride transistor and a first capacitor, wherein: The first end of the sixth resistor, the gate of the ninth gallium nitride transistor and the drain of the ninth gallium nitride transistor are connected to the external power supply terminal, and the second end of the first resistor is connected to the drain of the ninth gallium nitride transistor and the second end of the first capacitor; The gate of the ninth gallium nitride transistor is connected to the input end of the first bootstrap voltage generating circuit, and the source of the ninth gallium nitride transistor is grounded; A source of the tenth gallium nitride transistor is connected to the first end of the first capacitor and the output end of the first bootstrap voltage generating circuit.

7. The all-gallium nitride integrated drive circuit according to claim 5, characterized in that: The first push-pull output circuit includes: a seventh resistor, an eleventh gallium nitride transistor, a twelfth gallium nitride transistor, a thirteenth gallium nitride transistor, a fourteenth gallium nitride transistor, and a fifteenth gallium nitride transistor, wherein: A first end of the seventh resistor is connected to the drain of the twelfth gallium nitride transistor and the output end of the first bootstrap voltage generating circuit, and a second end of the seventh resistor is connected to the drain of the eleventh gallium nitride transistor and the gate of the twelfth gallium nitride transistor; The gate of the eleventh gallium nitride transistor is connected to the gate of the thirteenth gallium nitride transistor, the gate of the fifteenth gallium nitride transistor and the output end of the first bootstrap voltage generating circuit, and the source of the eleventh gallium nitride transistor is connected to the source of the thirteenth gallium nitride transistor, the source of the fifteenth gallium nitride transistor and the ground end; The source of the twelfth gallium nitride transistor is connected to the drain of the thirteenth gallium nitride transistor, the gate of the fourteenth gallium nitride transistor and the first output end of the first push-pull output circuit; The drain of the fourteenth gallium nitride transistor is connected to the external power supply terminal, and the source of the fourteenth gallium nitride transistor is connected to the drain of the fifteenth gallium nitride transistor and the second output terminal of the first push-pull output circuit.

8. The all-gallium nitride integrated drive circuit according to claim 1, characterized in that: The second bootstrap buffer comprises: a third inverter, a second bootstrap voltage generating circuit, and a second push-pull output circuit, wherein: The input end of the third inverter is connected to the input end of the second bootstrap buffer, and the output end of the third inverter is connected to the input end of the second bootstrap voltage generating circuit and the first input end of the second push-pull output circuit; The output terminal of the second bootstrap voltage generating circuit is connected to the second input terminal of the second push-pull output circuit; The first output end of the second push-pull output circuit is connected to the first output end of the second bootstrap buffer, and the second output end of the second push-pull output circuit is connected to the second output end of the second bootstrap buffer.

9. The all-gallium nitride integrated drive circuit according to claim 1, characterized in that: The output voltage clamp module includes: a sixteenth gallium nitride transistor, a seventeenth gallium nitride transistor, an eighteenth gallium nitride transistor and a nineteenth gallium nitride transistor, wherein: The drain of the sixteenth gallium nitride transistor is connected to the gate of the sixteenth gallium nitride transistor and the output end of the full gallium nitride integrated driving circuit, and the source of the sixteenth gallium nitride transistor is connected to the drain of the seventeenth gallium nitride transistor and the gate of the seventeenth gallium nitride transistor; The source of the seventeenth gallium nitride transistor is connected to the drain of the eighteenth gallium nitride transistor, the gate of the eighteenth gallium nitride transistor and the gate of the nineteenth gallium nitride transistor; A source of the eighteenth gallium nitride transistor and a source of the nineteenth gallium nitride transistor are grounded.

10. A chip, characterized in that: The chip includes: the full gallium nitride integrated drive circuit according to any one of claims 1-9.

11. An electronic device, characterized in that: The electronic device comprises: the chip as claimed in claim 10.

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