Low-power-consumption SAR ADC switch control circuit based on common-mode level

Abstract

The invention discloses a common-mode-level-based low-power-consumption SAR ADC (Synthetic Aperture Radar Analog to Digital Converter) switch control circuit, which comprises a first trigger module, a second trigger module, a third trigger module, a digital logic gate module and a bottom plate control switch module, and is characterized in that the first trigger module is used for generating a comparator latch signal and a first output signal; the second trigger module is used for storing the comparison result and generating a second output signal, the third trigger module is used for indicating the current conversion position according to the first output signal and generating a third output signal, and the digital logic gate module is used for generating a switch control signal. And the bottom plate control switch module is used for connecting the capacitor bottom plate to a corresponding reference level according to the switch control signal. According to the invention, the output signal of the first trigger module is multiplexed as the input of the third trigger module, the current conversion position is dynamically indicated, the area and power consumption of the switch control circuit in the SAR ADC can be optimized, and the circuit can be widely applied to the field of mixed signal circuit design.

Description

Technical Field

[0001] The invention relates to the field of mixed signal circuit design, in particular to a low-power SAR ADC switch control circuit based on a common mode level. Background Art

[0002] In the design of low-power SAR ADC (Successive Approximation Register ADC), the switch timing design of CDAC is particularly critical. The traditional implementation method of mobile guessing logic is simple, the switch on-resistance is low, and the reference voltage is established quickly, but each comparison requires a preset position. During the establishment process, the continuous change of the capacitor bottom plate potential from the negative reference voltage VREFN to the positive reference voltage VREFP and then to the negative reference voltage VREFN makes the power consumption of the capacitor switch high, and also puts forward higher requirements for the design of the reference voltage buffer.

[0003] The prior art proposes a switch switching strategy based on the common mode level. In the sampling stage, the upper plate of the capacitor is connected to the input signal, and all the lower plates of the capacitors are connected to the common mode level. In the conversion stage, the upper plate of the capacitor is disconnected from the input signal. After the lower plate is compared by the comparator, according to the comparison result, the bottom plate of the capacitor on the MSB (most significant bit in the SAR ADC conversion process) side is connected to the positive reference voltage VREFP, and the other side is connected to the negative reference voltage VREFN. After the DAC is established again and the comparator is compared again, according to the comparison result, the bottom plate of the capacitor on the MSB-1 side is connected to the positive reference voltage VREFP, and the other side is connected to the negative reference voltage VREFN. Repeat the above process until the last comparison result is obtained. The switch switching strategy based on the common mode level does not have a continuous change of positive and negative reference voltages, does not require a preset position, and saves more power. However, since the corresponding switch control circuits need to be designed for the top plate sampling and the bottom plate sampling respectively, and due to different accuracy and sampling rate requirements, the switch control circuits of the switch switching strategy based on the common mode level are different. In actual circuit design, a manual full-customization design method is often used to implement it. Summary of the invention

[0004] In order to solve the above technical problems, the purpose of the present invention is to provide a low-power SARADC switch control circuit based on common mode level, which can reduce circuit power consumption and simplify circuit design.

[0005] To achieve the above-mentioned purpose, one aspect of an embodiment of the present application proposes a low-power SARADC switch control circuit based on a common-mode level, comprising a first trigger module, a second trigger module, a third trigger module, a digital logic gate module and a bottom plate control switch module, wherein the input ends of the second trigger module and the third trigger module are both connected to the output end of the first trigger module, the output ends of the second trigger module and the third trigger module are both connected to the input end of the digital logic gate module, the output end of the digital logic gate module is connected to the input end of the bottom plate control switch module, the first trigger module is used to generate a comparator latch signal and a first output signal, the second trigger module is used to store a comparison result according to the comparator latch signal, and generate a second output signal, the third trigger module is used to indicate a current conversion position according to the first output signal, and generate a third output signal, the digital logic gate module is used to obtain a switch control signal according to the second output signal and the third output signal, and the bottom plate control switch module is used to connect the capacitor bottom plate to the corresponding reference level according to the switch control signal.

[0006] In some embodiments, the first trigger module includes a first trigger, a first end of the first trigger is used to access the sampling and holding signal, a second end of the first trigger is grounded, a third end of the first trigger is used to access the external clock signal, a fourth end of the first trigger is used to access the system signal, a fifth end of the first trigger is connected to the input end of the second trigger module, and the fifth end of the first trigger is used to generate the comparator latch signal.

[0007] In some embodiments, the first trigger module also includes multiple second triggers, the first end of each second trigger is used to access the system signal, the second end of each second trigger is connected to the sixth end of the previous second trigger or the first trigger, the third end of each second trigger is used to access the external clock signal, the fourth end of each second trigger is used to access the sampling and holding signal, the fifth end of each second trigger is connected to the input end of the second trigger module, the sixth end of each second trigger is also connected to the input end of the third trigger module, the fifth end of each second trigger is used to generate the comparator latch signal, and the sixth end of each second trigger is used to generate the first output signal.

[0008] In some embodiments, the second output signal includes a first interface output signal and a second interface output signal.

[0009] In some embodiments, the comparison result includes a first comparison result, the second trigger module includes a third trigger and multiple fourth triggers, the first end of the third trigger and each of the fourth triggers are connected to the output end of the first trigger module, the second end of the third trigger is connected to the third end of the third trigger, the second end of each of the fourth triggers is used to access the first comparison result, the third end of each of the fourth triggers is connected to the sixth end of the previous fourth trigger or the third trigger, the fourth end of the third trigger and each of the fourth triggers is used to access the sampling and holding signal, the sixth end of each of the fourth triggers is also connected to the input end of the digital logic gate module, the second end of each of the fourth triggers is used to store the first comparison result according to the comparator latch signal, and the sixth end of each of the fourth triggers is used to generate the first interface output signal.

[0010] In some embodiments, the second trigger module also includes a fifth trigger, a first end of the fifth trigger is connected to the output end of the first trigger module, a second end of the fifth trigger is used to access the first comparison result, a third end of the fifth trigger is connected to the sixth end of the fourth trigger, a fourth end of the fifth trigger is used to access the system signal, the sixth end of the fifth trigger is connected to the input end of the digital logic gate module, the second end of the fifth trigger is used to store the first comparison result according to the comparator latch signal, and the sixth end of the fifth trigger is used to generate the first interface output signal.

[0011] In some embodiments, the comparison result includes a second comparison result, and the second trigger module includes a sixth trigger and multiple seventh triggers. The first end of the sixth trigger and each of the seventh triggers is connected to the output end of the first trigger module, the second end of the sixth trigger is connected to the third end of the sixth trigger, the second end of each of the seventh triggers is used to access the second comparison result, the third end of each of the seventh triggers is connected to the sixth end of the previous seventh trigger or the sixth trigger, the fourth end of the sixth trigger and each of the seventh triggers is used to access the sampling and holding signal, the sixth end of each of the seventh triggers is also connected to the input end of the digital logic gate module, the second end of each of the seventh triggers is used to store the second comparison result according to the comparator latch signal, and the sixth end of each of the seventh triggers is used to generate the second interface output signal.

[0012] In some embodiments, the second trigger module also includes an eighth trigger, a first end of the eighth trigger is connected to the output end of the first trigger module, a second end of the eighth trigger is used to access the second comparison result, a third end of the eighth trigger is connected to the sixth end of the seventh trigger, a fourth end of the eighth trigger is used to access the system signal, a sixth end of the eighth trigger is connected to the input end of the digital logic gate module, a second end of the eighth trigger is used to store the second comparison result according to the comparator latch signal, and a sixth end of the eighth trigger is used to generate the second interface output signal.

[0013] In some embodiments, the third trigger module includes multiple ninth triggers, the first end of each of the ninth triggers is used to access the system signal, the second end of each of the ninth triggers is used to access the power supply, the third end of each of the ninth triggers is connected to the output end of each of the first trigger modules, the fourth end of each of the ninth triggers is used to access the sampling and holding signal, the sixth end of each of the ninth triggers is connected to the input end of the digital logic gate module, the third end of the ninth trigger is used to indicate the current conversion position according to the first output signal, and the sixth end of the ninth trigger is used to generate the third output signal.

[0014] In some embodiments, the digital logic gate module includes a plurality of first NAND gates, second NAND gates, first AND gates, second AND gates and first NOT gates, the output ends of the second trigger module and the third trigger module are connected to the input ends of the first NAND gates, the output ends of the second trigger module and the third trigger module are connected to the input ends of the second NAND gates, the output ends of the second trigger module and the third trigger module are connected to the input ends of the first AND gates, the output ends of the second trigger module and the third trigger module are connected to the input ends of the second AND gates, and the third trigger module The output end of is connected to the input end of each first NOT gate, the output ends of each first NAND gate, each second NAND gate, each first AND gate, each second AND gate and each first NOT gate are all connected to the input end of the base plate control switch module, each first NAND gate and each second AND gate are used to obtain the switch control signal according to the third output signal and the first interface output signal, each second NAND gate and each first AND gate are used to obtain the switch control signal according to the third output signal and the second interface output signal, and each first NOT gate is used to obtain the switch control signal according to the third output signal.

[0015] The beneficial effects of the present invention are as follows: a low-power SAR ADC switch control circuit based on common-mode level of the present invention comprises a first trigger module, a second trigger module, a third trigger module, a digital logic gate module and a bottom plate control switch module, wherein a comparator latch signal and a first output signal are generated by the first trigger module, a comparison result is stored by the second trigger module according to the comparator latch signal, and a second output signal is generated, a current conversion position is indicated by the third trigger module according to the first output signal, and a third output signal is generated, a switch control signal is obtained by the digital logic gate module according to the second output signal and the third output signal, and the bottom plate of the capacitor is connected to the corresponding reference level according to the switch control signal by the bottom plate control switch module. The present invention innovatively reuses the first output signal in the first trigger module as the input signal of the third trigger module, dynamically indicates the current conversion position, can greatly optimize the area and power consumption of the switch control circuit in the traditional SAR ADC, and simplifies the circuit design without sacrificing circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solution in the embodiments of the present invention, the following introduction is made to the drawings required for use in the embodiments of the present invention. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solution of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A structural block diagram of a low-power SAR ADC switch control circuit based on common-mode level provided in an embodiment of the present invention;

[0018] Figure 2 A schematic diagram of a circuit structure of a low-power SAR ADC switch control circuit based on a common-mode level provided in an embodiment of the present invention;

[0019] Figure 3 The current simulation results of the digital logic part of the two SAR ADCs provided in the embodiments of the present invention in a certain sampling-conversion cycle;

[0020] Figure 4 The total circuit current simulation results of the two SAR ADCs provided in the embodiments of the present invention within a certain sampling-conversion cycle. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0022] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0023] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0024] Before describing the embodiments of the present application in detail, some nouns and terms involved in the embodiments of the present application are first described. The nouns and terms involved in the embodiments of the present application are subject to the following explanations.

[0025] SAR ADC (Successive Approximation Register ADC) is a compromise solution that provides a good balance between speed, resolution and power. It has the characteristics of low power consumption, small size, moderate resolution and speed, and short sampling delay.

[0026] In recent years, analog front-end signal acquisition and processing circuit technology, as the key to wearable biomedical chips, has received attention and research from many institutions and scholars, and is in a rapid development stage. In order to meet the requirements of the use time of portable EEG interface devices, the ADC in the EEG interface chip needs to be designed with ultra-low power consumption to extend the service life of the device under limited power supply.

[0027] SAR ADC was first realized by Gray's team in 1975. Due to its simple digital structure and the development of technology, it has outstanding performance in advanced semiconductor technology and has become a research hotspot for domestic and foreign companies and universities in recent years. The working mechanism of SAR ADC is based on a binary search algorithm, which uses a successive approximation method through multiple clock cycles to produce quantitative results. Since SAR ADC does not require the use of precise amplification operational amplifiers, it has a simple structure and low power consumption. It is currently widely used in the design of wearable biomedical chips.

[0028] In the design of low-power SAR ADC (Successive Approximation Register ADC), the switch timing design of CDAC is particularly critical. The traditional implementation method of mobile guessing logic is simple, the switch on-resistance is low, and the reference voltage is established quickly, but each comparison requires a preset position. During the establishment process, the continuous change of the capacitor bottom plate potential from the negative reference voltage VREFN to the positive reference voltage VREFP and then to the negative reference voltage VREFN makes the power consumption of the capacitor switch high, and also puts forward higher requirements for the design of the reference voltage buffer.

[0029] The prior art proposes a switch switching strategy based on the common mode level. In the sampling stage, the upper plate of the capacitor is connected to the input signal, and all the lower plates of the capacitors are connected to the common mode level. In the conversion stage, the upper plate of the capacitor is disconnected from the input signal. After the lower plate is compared by the comparator, according to the comparison result, the bottom plate of the capacitor on the MSB (most significant bit in the SAR ADC conversion process) side is connected to the positive reference voltage VREFP, and the other side is connected to the negative reference voltage VREFN. After the DAC is established again and the comparator is compared again, according to the comparison result, the bottom plate of the capacitor on the MSB-1 side is connected to the positive reference voltage VREFP, and the other side is connected to the negative reference voltage VREFN. Repeat the above process until the last comparison result is obtained. The switch switching strategy based on the common mode level does not have a continuous change of positive and negative reference voltages, does not require a preset position, and saves more power. However, since the corresponding switch control circuits need to be designed for the top plate sampling and the bottom plate sampling respectively, and due to different accuracy and sampling rate requirements, the switch control circuits of the switch switching strategy based on the common mode level are different. In actual circuit design, a manual full-customization design method is often used to implement it.

[0030] To this end, an embodiment of the present invention proposes a low-power SAR ADC switch control circuit based on a common-mode level, a first trigger module, a second trigger module, a third trigger module, a digital logic gate module, and a bottom plate control switch module, wherein a comparator latch signal and a first output signal are generated by the first trigger module, a comparison result is stored by the second trigger module according to the comparator latch signal, and a second output signal is generated, a current conversion position is indicated by the third trigger module according to the first output signal, and a third output signal is generated, a switch control signal is obtained by the digital logic gate module according to the second output signal and the third output signal, and the bottom plate of the capacitor is connected to the corresponding reference level according to the switch control signal by the bottom plate control switch module. The present invention innovatively reuses the first output signal in the first trigger module as the input signal of the third trigger module, dynamically indicates the current conversion position, can greatly optimize the area and power consumption of the switch control circuit in the traditional SAR ADC, and simplifies the circuit design without sacrificing circuit performance.

[0031] Reference Figure 1 , Figure 1 A structural block diagram of a low-power SAR ADC switch control circuit based on a common-mode level provided in an embodiment of the present invention. An embodiment of the present invention proposes a low-power SAR ADC switch control circuit based on a common-mode level, comprising a first trigger module, a second trigger module, a third trigger module, a digital logic gate module and a bottom plate control switch module, wherein the input ends of the second trigger module and the third trigger module are both connected to the output end of the first trigger module, the output ends of the second trigger module and the third trigger module are both connected to the input end of the digital logic gate module, the output end of the digital logic gate module is connected to the input end of the bottom plate control switch module, the first trigger module is used to generate a comparator latch signal and a first output signal, the second trigger module is used to store a comparison result according to the comparator latch signal and generate a second output signal, the third trigger module is used to indicate a current conversion position according to the first output signal and generate a third output signal, the digital logic gate module is used to obtain a switch control signal according to the second output signal and the third output signal, and the bottom plate control switch module is used to connect the capacitor bottom plate to a corresponding reference level according to the switch control signal.

[0032] Specifically, the first trigger module is used for, in the conversion phase, each D trigger in the first trigger module shifts the high level outputted by the sixth terminal (Q terminal) to the right through the external clock signal CLK, and the low level outputted by the fifth terminal (QN terminal) is also shifted to the right, so as to generate a comparator latch signal SC for the second trigger module. <9> -SC <0> ;

[0033] The second trigger module is used to receive the QN terminal signal (i.e., the comparator latch signal) of each D trigger in the first trigger module during the conversion phase, so that the first terminal (SN terminal) of the front part of the D trigger in the second trigger module is successively selected, thereby successively setting the Q terminal output (second output signal) of the front part of the D trigger to a high level. Starting from a certain D trigger in the front part, the rising edge of the Q terminal output (second output signal) changing from a low level to a high level will trigger the previous D trigger, thereby storing the first comparison result DCOMP_QN in the previous D trigger, and similarly, the second comparison result DCOMP_Q is also stored in the rear part of the D trigger;

[0034] The third trigger module is used for, in the conversion phase, the third output signal CC output by each D trigger in the third trigger module <8> -CC <0> Sequentially receive the first output signal C outputted from the first trigger module <8> -C <0> , thereby indicating the current conversion position;

[0035] A digital logic gate module, which is used for, in a conversion phase, each logic gate in the digital logic gate module is continuously adjusted according to the second output signal and the third output signal output by the second trigger module and the third trigger module, so as to correctly generate a switch control signal;

[0036] The bottom plate control switch module is used to connect the capacitor bottom plate to the corresponding reference level according to the switch control signal output by the digital logic gate module during the conversion phase to ensure the correct establishment of the DAC again.

[0037] Reference Figure 2 , Figure 2 A circuit structure diagram of a low-power SAR ADC switch control circuit based on a common-mode level provided in an embodiment of the present invention, further as an optional implementation manner, a first trigger module includes a first trigger, a first end of the first trigger is used to access a sampling and holding signal, a second end of the first trigger is grounded, a third end of the first trigger is used to access an external clock signal, a fourth end of the first trigger is used to access a system signal, a fifth end of the first trigger is connected to an input end of the second trigger module, and the fifth end of the first trigger is used to generate a comparator latch signal.

[0038] Reference Figure 2, further as an optional implementation, the first trigger module also includes multiple second triggers, the first end of each second trigger is used to access the system signal, the second end of each second trigger is connected to the sixth end of the previous second trigger or the first trigger, the third end of each second trigger is used to access the external clock signal, the fourth end of each second trigger is used to access the sampling and holding signal, the fifth end of each second trigger is connected to the input end of the second trigger module, the sixth end of each second trigger is also connected to the input end of the third trigger module, the fifth end of each second trigger is used to generate a comparator latch signal, and the sixth end of each second trigger is used to generate a first output signal.

[0039] In some optional embodiments, such as Figure 2 As shown, a 10-bit SAR ADC is used for illustration. The first trigger is a D trigger DFF10, and the second trigger includes a D trigger DFF1, a D trigger DFF2, a D trigger DFF3, a D trigger DFF4, a D trigger DFF5, a D trigger DFF6, a D trigger DFF7, a D trigger DFF8, and a D trigger DFF9.

[0040] Specifically, the external clock signal CLK is connected to the third end (CK end) of the D flip-flops DFF10-DFF1, the sampling and holding signal CK_SH is connected to the first end (SN end) of the D flip-flop DFF10 and the fourth end (RN end) of the D flip-flops DFF9-DFF1, and the system signal SYS is connected to the fourth end (RN end) of the D flip-flop DFF10 and the first end (SN end) of the D flip-flops DFF9-DFF1 at the same time. The second end (D end) of the D flip-flop DFF10 is grounded, and the sixth end (Q end) of the D flip-flop DFF10 is connected to the second end (D end) of the D flip-flop DFF9. The sixth end (Q end) of the D flip-flops DFF9-DFF2 is respectively connected to the second end (D end) of the previous D flip-flops DFF8-DFF1, and the sixth end (Q end) of the D flip-flops DFF9-DFF1 is also connected to the input end of the third flip-flop module, and the wiring is named C <8> -C <0> , that is, output the first output signal to the third trigger module. The fifth terminal (QN terminal) of the D trigger DFF10-DFF1 is connected to the input terminal of the second trigger module, and the wiring is called SC <9> -SC <0> , that is, outputting the comparator latch signal to the second trigger module.

[0041] As a further optional implementation, the second output signal includes a first interface output signal and a second interface output signal.

[0042] Reference Figure 2, further as an optional implementation, the comparison result includes a first comparison result, the second trigger module includes a third trigger and multiple fourth triggers, the first end of the third trigger and each fourth trigger is connected to the output end of the first trigger module, the second end of the third trigger is connected to the third end of the third trigger, the second end of each fourth trigger is used to access the first comparison result, the third end of each fourth trigger is connected to the sixth end of the previous fourth trigger or the third trigger, the fourth end of the third trigger and each fourth trigger is used to access the sampling and holding signal, the sixth end of each fourth trigger is also connected to the input end of the digital logic gate module, the second end of each fourth trigger is used to store the first comparison result according to the comparator latch signal, and the sixth end of each fourth trigger is used to generate a first interface output signal.

[0043] Reference Figure 2 , further as an optional implementation, the second trigger module also includes a fifth trigger, the first end of the fifth trigger is connected to the output end of the first trigger module, the second end of the fifth trigger is used to access the first comparison result, the third end of the fifth trigger is connected to the sixth end of the fourth trigger, the fourth end of the fifth trigger is used to access the system signal, the sixth end of the fifth trigger is connected to the input end of the digital logic gate module, the second end of the fifth trigger is used to store the first comparison result according to the comparator latch signal, and the sixth end of the fifth trigger is used to generate a first interface output signal.

[0044] In some optional embodiments, such as Figure 2 As shown, the third trigger is D trigger DFF11, the fourth trigger includes D trigger DFF12, D trigger DFF13, D trigger DFF14, D trigger DFF15, D trigger DFF16, D trigger DFF17, D trigger DFF18, and D trigger DFF19, and the fifth trigger is D trigger DFF20.

[0045] Specifically, the sampling and holding signal CK_SH is connected to the fourth terminal (RN terminal) of the D flip-flops DFF19-DFF11, and the system signal SYS is connected to the fourth terminal (RN terminal) of the D flip-flop DFF20. The first terminal (SN terminal) of the D flip-flops DFF20-DFF11 is respectively connected to the fifth terminal (QN terminal) of the D flip-flops DFF10-DFF1 in the first flip-flop module, and the wiring is called SC <9> -SC <0> , that is, the comparator latch signal output by the first trigger module is input. The first comparison result DCOMP_QN is connected to the second end (D end) of the D trigger DFF20-DFF12 at the same time. The sixth end (Q end) of the D trigger DFF20-DFF12 is connected to the input end of the digital logic gate module, and the wiring is named A <8> -A <0> , that is, outputting the first interface output signal to the digital logic gate module. The sixth end (Q end) of the D flip-flop DFF11 is connected to the third end (CK end) of the D flip-flop DFF12, and the second end (D end) of the D flip-flop DFF11 is connected to the third end (CK end) of the D flip-flop DFF12.

[0046] Reference Figure 2 , further as an optional implementation, the comparison result includes a second comparison result, the second trigger module includes a sixth trigger and multiple seventh triggers, the first ends of the sixth trigger and each seventh trigger are connected to the output end of the first trigger module, the second end of the sixth trigger is connected to the third end of the sixth trigger, the second end of each seventh trigger is used to access the second comparison result, the third end of each seventh trigger is connected to the sixth end of the previous seventh trigger or the sixth trigger, the fourth end of the sixth trigger and each seventh trigger is used to access the sampling and holding signal, the sixth end of each seventh trigger is also connected to the input end of the digital logic gate module, the second end of each seventh trigger is used to store the second comparison result according to the comparator latch signal, and the sixth end of each seventh trigger is used to generate a second interface output signal.

[0047] Reference Figure 2 , further as an optional implementation, the second trigger module also includes an eighth trigger, the first end of the eighth trigger is connected to the output end of the first trigger module, the second end of the eighth trigger is used to access the second comparison result, the third end of the eighth trigger is connected to the sixth end of the seventh trigger, the fourth end of the eighth trigger is used to access the system signal, the sixth end of the eighth trigger is connected to the input end of the digital logic gate module, the second end of the eighth trigger is used to store the second comparison result according to the comparator latch signal, and the sixth end of the eighth trigger is used to generate a second interface output signal.

[0048] In some optional embodiments, such as Figure 2As shown, the sixth trigger is D trigger DFF21, the seventh trigger includes D trigger DFF22, D trigger DFF23, D trigger DFF24, D trigger DFF25, D trigger DFF26, D trigger DFF27, D trigger DFF28, and D trigger DFF29, and the eighth trigger is D trigger DFF30.

[0049] Specifically, the sampling and holding signal CK_SH is connected to the fourth terminal (RN terminal) of the D flip-flops DFF29-DFF21, and the system signal SYS is connected to the fourth terminal (RN terminal) of the D flip-flop DFF30. The first terminal (SN terminal) of the D flip-flops DFF30-DFF21 is respectively connected to the fifth terminal (QN terminal) of the D flip-flops DFF10-DFF1 in the first flip-flop module, and the wiring is called SC <9> -SC <0> , that is, receiving the comparator latch signal output by the first trigger module. The second comparison result DCOMP_Q is connected to the second end (D end) of the D trigger DFF30-DFF22 at the same time. The sixth end (Q end) of the D trigger DFF30-DFF22 is connected to the input end of the digital logic gate module, and the wiring is named B <8> -B <0> , that is, outputting the second interface output signal to the digital logic gate module. The sixth end (Q end) of the D flip-flop DFF21 is connected to the third end (CK end) of the D flip-flop DFF22, and the second end (D end) of the D flip-flop DFF21 is connected to the third end (CK end) of the D flip-flop DFF22.

[0050] Reference Figure 2 , further as an optional implementation, the third trigger module includes multiple ninth triggers, the first end of each ninth trigger is used to access the system signal, the second end of each ninth trigger is used to access the power supply, the third end of each ninth trigger is connected to the output end of each first trigger module, the fourth end of each ninth trigger is used to access the sampling and holding signal, the sixth end of each ninth trigger is connected to the input end of the digital logic gate module, the third end of the ninth trigger is used to indicate the current conversion position according to the first output signal, and the sixth end of the ninth trigger is used to generate a third output signal.

[0051] In some optional embodiments, such as Figure 2 As shown, the ninth flip-flop includes a D flip-flop DFF31, a D flip-flop DFF32, a D flip-flop DFF33, a D flip-flop DFF34, a D flip-flop DFF35, a D flip-flop DFF36, a D flip-flop DFF37, a D flip-flop DFF38, and a D flip-flop DFF39.

[0052] Specifically, the power supply VDD is connected to the second end (D end) of the D flip-flop DFF39-DFF31, the sample hold signal CK_SH is connected to the fourth end (RN end) of the D flip-flop DFF39-DFF31, and the system signal SYS is connected to the first end (SN end) of the D flip-flop DFF39-DFF31. The sixth end (Q end) of the D flip-flop DFF39-DFF31 is connected to the input end of the digital logic gate module, and the wiring is called CC. <8> -CC <0> , that is, output the third output signal to the digital logic gate module. The third terminal (CK terminal) of the D flip-flop DFF39-DFF31 is connected to the sixth terminal (Q terminal) of the D flip-flop DFF9-DFF1 in the first flip-flop module, and the wiring is called C <8> -C <0> , that is, the first output signal output by the first trigger module is input.

[0053] Reference Figure 2 , further as an optional implementation, the digital logic gate module includes a plurality of first NAND gates, second NAND gates, first AND gates, second AND gates and first NOT gates, the output ends of the second trigger module and the third trigger module are connected to the input ends of the first NAND gates, the output ends of the second trigger module and the third trigger module are connected to the input ends of the second NAND gates, the output ends of the second trigger module and the third trigger module are connected to the input ends of the first AND gates, the output ends of the second trigger module and the third trigger module are connected to the input ends of the second AND gates, the output end of the third trigger module is connected to the input end of the first NOT gates, the output ends of the first NAND gates, the second NAND gates, the first AND gates, the second AND gates and the first NOT gates are connected to the input end of the backplane control switch module, the first NAND gates and the second AND gates are used to obtain a switch control signal according to the third output signal and the first interface output signal, the second NAND gates and the first AND gates are used to obtain a switch control signal according to the third output signal and the second interface output signal, and the first NOT gates are used to obtain a switch control signal according to the third output signal.

[0054] In some optional embodiments, such as Figure 2As shown, the first NAND gate includes NAND gate NAND1, NAND gate NAND2, NAND gate NAND3, NAND gate NAND4, NAND gate NAND5, NAND gate NAND6, NAND gate NAND7, NAND gate NAND8, and NAND gate NAND9; the second NAND gate includes NAND gate NAND10, NAND gate NAND11, NAND gate NAND12, NAND gate NAND13, NAND gate NAND14, NAND gate NAND15, NAND gate NAND16, NAND gate NAND17, and NAND gate NAND18; the first AND gate includes AND gate AND1, AND gate AND2, AND gate AND3, AND gate AND4, AND gate AND5, AND gate AND6, AND gate AND7, AND gate AND8, and AND gate AND9; the second AND gates include AND gates AND10, AND gates AND11, AND gates AND12, AND gates AND13, AND gates AND14, AND gates AND15, AND gates AND16, AND gates AND17, and AND gates AND18; the first NOT gates include NOT gates INV1, INV2, INV3, INV4, INV5, INV6, INV7, INV8, and INV9.

[0055] Specifically, the first input terminals of the NAND gates NAND1-NAND9 and the NAND gates NAND10-NAND18 are connected to the sixth terminals (Q terminals) of the D flip-flops DFF39-DFF31, respectively, and the wiring is named CC <8> -CC <0> , that is, the third output signal output by the third trigger module is input; the second input terminals of the NAND gates NAND1-NAND9 are respectively connected to the sixth terminals (Q terminals) of the D flip-flops DFF20-DFF12, and the wiring is named A <8> -A <0> , that is, the first interface output signal output by the second trigger module is input; the second input terminals of the NAND gates NAND10-NAND18 are respectively connected to the sixth terminals (Q terminals) of the D triggers DFF30-DFF22, and the wiring is named B <8> -B <0> , that is, input the second interface output signal output by the second trigger module; the output end of the NAND gate NAND1-NAND9 is connected to the input end of the base control switch module, and the wiring is called PSWP <8> -PSWP <0> The output of the NAND gates NAND10-NAND18 is connected to the input of the base control switch module. The wiring is called NSWP. <8> -NSWP <0> .

[0056] The first input terminals of AND gates AND1-AND9 and AND10-AND18 are connected to the sixth terminals (Q terminals) of D flip-flops DFF39-DFF31, respectively. The wiring is named CC <8> -CC <0> , that is, the third output signal output by the third trigger module is input; the second input terminals of the AND gates AND1-AND9 are respectively connected to the sixth terminals (Q terminals) of the D triggers DFF30-DFF22, and the wiring is named B <8> -B <0> , that is, the second interface output signal output by the second trigger module is input; the second input terminals of the AND gates AND10-AND18 are respectively connected to the sixth terminals (Q terminals) of the D flip-flops DFF20-DFF12, and the wiring is named A <8> -A <0> , that is, the first interface output signal output by the second trigger module is input; the output end of the AND gate AND1-AND9 is connected to the input end of the base control switch module, and the wiring is named PSWN <8> -PSWN <0> The output of AND gates AND10-AND18 is connected to the input of the base control switch module. The wiring is named NSWN. <8> -NSWN <0> .

[0057] The input end of the NOT gate INV1-INV9 is connected to the sixth end (Q end) of the D flip-flop DFF39-DFF31, and the wiring is called CC <8> -CC <0> , that is, the third output signal output by the third trigger module is input; the output end of the invertor INV1-INV9 is connected to the input end of the base control switch module, and the wiring is named SWCM <8> -SWCM <0> .

[0058] Further, if Figure 2 As shown in FIG. 1 , the base plate control switch module includes MOS tubes M1-M54. Figure 2The structure shown in FIG. 1 is used to illustrate that the positive reference voltage VREFP is connected to the drains of MOS tubes M1, M25, M28 and M52 at the same time; the negative reference voltage VREFN is connected to the sources of MOS tubes M2, M26, M29 and M53 at the same time; the common mode level VCM is connected to the sources of MOS tubes M3, M27, M30 and M54 at the same time. The source of MOS tube M1 is connected to the drains of MOS tubes M2 and M3 at the same time, and a lead point is provided on the wiring, and the lead point is used to output CSP <8> The source of MOS tube M25 is connected to the drain of MOS tube M26 and MOS tube M27 at the same time, and a lead point is set on the wiring, which is used to output CSP <0> The source of MOS tube M28 is connected to the drain of MOS tube M29 and MOS tube M30 at the same time, and a lead point is set on the wiring, which is used to output CSN <8> The source of MOS tube M52 is connected to the drain of MOS tube M53 and MOS tube M54 at the same time, and a lead point is set on the wiring, and the lead point is used to output CSN <0> The gate of each MOS tube is connected to the output end of the digital logic gate, which is used to input the switch control signal output by the digital logic gate module (including the PSWP output by the NAND gates NAND1-NAND9). <8> -PSWP <0> 、NSWP output by NAND gates NAND10-NAND18 <8> -NSWP <0> , PSWN output by AND gates AND1-AND9 <8> -PSWN <0> , NSWN output by AND gates AND10-AND18 <8> -NSWN <0> , SWCM output by invertor INV1-INV9 <8> -SWCM <0> ), the specific connection method is as follows Figure 2 As shown, no further elaboration is given here.

[0059] The structure of a low-power SAR ADC switch control circuit based on a common-mode level according to an embodiment of the present invention is described above, and its working principle is described below.

[0060] When the SAR ADC circuit is not working, the system signal SYS is set to 0, and after the SAR ADC circuit starts working, the system signal SYS is set to 1.

[0061] In the sampling phase, the sampling and holding signal CK_SH is at a low level, the sixth terminal (Q terminal) output of the D flip-flop DFF10 is set to a high level, and the fifth terminal (QN terminal) is set to a low level, and the sixth terminal (Q terminal) output of the D flip-flop DFF9 to the D flip-flop DFF1 is set to a low level, and the fifth terminal (QN terminal) is set to a high level. The first interface output signal A is output from the sixth terminal (Q terminal) of the D flip-flop DFF19 to DFF12. <7> To A <0> The third output signal CC output by the D flip-flop DFF39 to the D flip-flop DFF31 in the third flip-flop module <8> -CC <0> is set to a low level. At this time, the output PSWP from the NAND gate NAND1 to the NAND gate NAND9 in the digital logic gate module <8> -PSWP <0> is set to high level, the output NSWP of NAND gate NAND10 to NAND gate NAND18 <8> -NSWP <0> is set to high level, and the output PSWN of AND gates AND1 to AND gates AND9 <8> -PSWN <0> is set to low level, and the output NSWN of AND gate AND10 to AND gate AND18 <8> -NSWN <0> is set to low level, the output SWCM of invertor INV1 to invertor INV9 <8> -SWCM <0> is set to high level.

[0062] In the baseboard control switch module, CSP <8> -CSP <0> Both are connected to the common mode level VCM, CSN <8> -CSN <0> Both are connected to the common-mode level VCM.

[0063] In the conversion phase, the sampling and holding signal CK_SH changes from a low level to a high level, and the D flip-flops DFF10 to D flip-flops DFF1 move the high level output of the sixth terminal (Q terminal) to the right through the external clock signal CLK, and the low level of the fifth terminal (QN terminal) also moves to the right, so that the first terminal (SN terminal) of the D flip-flops DFF20 to D flip-flops DFF11 is successively selected, thereby successively setting the output of the sixth terminal (Q terminal) of the D flip-flops DFF20 to D flip-flops DFF11 to a high level. Starting from the D flip-flop DFF19, the rising edge of the output of the sixth terminal (Q terminal) from a low level to a high level will trigger the previous D flip-flop, thereby storing the first comparison result DCOMP_QN in the previous flip-flop. Each comparison result will be used as the input of the digital logic gate module, and the output of the digital logic gate module will be used as the input of the bottom plate control switch module, thereby connecting the capacitor bottom plate to the corresponding reference level and controlling the establishment of the DAC. The detailed process is as follows:

[0064] The first output signal C outputted from the D flip-flop DFF9 to the D flip-flop DFF1 in the first flip-flop module <8> -C <0> The third output signal CC output by the D flip-flop DFF39 to the D flip-flop DFF31 in the third flip-flop module rises from a low level to a high level in sequence. <8> -CC <0> It also rises from low level to high level in sequence, and just indicates the current conversion position.

[0065] When the nth bit is not converted, C <n>is set to low level, CC <n>is set to low level. At this time, PSWP in the digital logic gate module <n>is set high, NSWP <n>Set to high level, PSWN <n>is set to low, NSWN <n>is set to low level, SWCM <n>Set to high level. In the baseboard control switch module, CSP <n>Connected to VCM, CSN <n>Connected to VCM.

[0066] When switching to the nth position, C <n>is set to high level, CC <n>Then C <n>Set to high level. At this time, the nth comparison result is sent to the second trigger module. If the second comparison result DCOMP_Q=1, the first comparison result DCOMP_QN=0, then A <n>is set to low level, B <n>is set to high level, the PSWP in the digital logic gate module <n>is set high, NSWP <n>is set to low level, PSWN <n>is set high, NSWN <n>is set to low level, SWCM <n>Set to low level. In the baseboard control switch module, CSP <n>Connected to negative reference voltage VREFN, CSN <n>is connected to the positive reference voltage VREFP. If the second comparison result DCOMP_Q=0 and the first comparison result DCOMP_QN=1, then A <n>is set to high level, B <n>is set to low level, the PSWP in the digital logic gate module <n>is set to low level, NSWP <n>Set to high level, PSWN <n>is set to low, NSWN <n>is set high, SWCM <n>Set to low level. In the baseboard control switch module, CSP <n>Connected to VREFP, CSN <n>Connected to VREFN.

[0067] It should be noted that the above operation ensures the correct re-establishment of the DAC, and innovatively reuses the first output signal of the D flip-flop in the first flip-flop as the input signal of the third flip-flop module, dynamically indicating the current conversion position, which can greatly optimize the area and power consumption of the switch control circuit in the traditional SAR ADC, and simplifies the circuit design without sacrificing circuit performance.

[0068] Furthermore, for the differential structure, the first trigger module generating the comparator latch signal can be reused, while the digital logic gate module generating the switch control signal needs to be controlled by the second trigger module storing the comparator comparison result. Figure 2 The second comparison result DCOMP_Q and the first comparison result DCOMP_QN in the second trigger module correspond to the output of the SAR ADC dynamic comparator. Therefore, the D trigger DFF20 to D trigger DFF11 in the second trigger module stores the first comparison result DCOMP_QN, and the D trigger DFF30 to D trigger DFF21 stores the second comparison result DCOMP_Q. The two results are just opposite. The final conversion result only needs to convert the second interface output signal B stored in the D trigger DFF30 to D trigger DFF22 <8> To B <0> The second comparison result DCOMP_Q of the last bit is output in parallel by 10 D flip-flops controlled by the same clock, thus completing a complete conversion process.

[0069] The above describes the structure and working principle of a low-power SAR ADC switch control circuit based on a common-mode level in an embodiment of the present invention. It can be recognized that, compared with the traditional switch switching strategy, the present invention innovatively reuses the first output signal in the first trigger module as the input signal of the third trigger module, dynamically indicates the current conversion position, and can greatly optimize the area and power consumption of the switch control circuit in the traditional SAR ADC, thereby simplifying the circuit design without sacrificing circuit performance.

[0070] In order to further verify the low power consumption characteristics of the switch control circuit proposed in the embodiment of the present invention, the effect of the embodiment of the present invention is further described below in combination with experiments.

[0071] The embodiment of the present invention uses Cadence Virtuoso software to implement two low-power SAR ADCs with an accuracy of 10 bits and a sampling rate of 16KS / s under a 0.18μm CMOS process using traditional mobile guessing logic and the switch control circuit proposed in the embodiment of the present invention, with a power supply voltage of 1.8V.

[0072] Experiment 1: Digital logic current simulation experiment. Figure 3 The figure shows the current simulation result of the digital logic part of the low-power SAR ADC with an accuracy of 10 bits and a sampling rate of 16KS / s implemented using the traditional mobile guessing logic and the switch control circuit proposed in the embodiment of the present invention in a certain sampling-conversion cycle. The green figure is the current simulation result of the digital logic part of the SAR ADC implemented using the traditional mobile guessing logic in a certain sampling-conversion cycle. The calculated average current is 421.3nA and the average power consumption is 758.34nW. The blue figure is the current simulation result of the digital logic part of the SAR ADC implemented using the switch control circuit proposed in the embodiment of the present invention in a certain sampling-conversion cycle. The calculated average current is 248.5nA and the average power consumption is 447.3nW. It can be seen that the power consumption of the digital logic part of the SAR ADC implemented using the switch control circuit proposed in the embodiment of the present invention is significantly reduced compared with the power consumption of the digital logic part of the SAR ADC implemented using the traditional mobile guessing logic.

[0073] Experiment 2: Total current simulation experiment. Figure 4 The figure shows the simulation result of the total circuit current of a low-power SAR ADC with an accuracy of 10 bits and a sampling rate of 16KS / s implemented using the traditional mobile guessing logic and the switch control circuit proposed in the embodiment of the present invention in a certain sampling-conversion cycle. The orange color is the simulation result of the total circuit current of the SAR ADC implemented using the traditional mobile guessing logic in a certain sampling-conversion cycle. The calculated average current is 1.1μA and the average power consumption is 1.98μW. The red color is the simulation result of the total circuit current of the SAR ADC implemented using the switch control circuit proposed in the embodiment of the present invention in a certain sampling-conversion cycle. The calculated average current is 484.1nA and the average power consumption is 871.38nW. It can be seen that the total power consumption of the SAR ADC circuit implemented using the switch control circuit proposed in the embodiment of the present invention is significantly reduced compared with the total power consumption of the SAR ADC circuit implemented using the traditional mobile guessing logic.

[0074] Experiment 3: Dynamic parameter test. The outputs of the two circuits were tested for dynamic parameters. The test results showed that the SFDR of the SAR ADC implemented using the traditional moving guessing logic was 72.24 dBc, which can reach an effective number of bits of 9.81 bits; the SFDR of the SAR ADC implemented using the switch control circuit proposed in the embodiment of the present invention was 72.47 dBc, which can reach an effective number of bits of 9.82 bits, both meeting the design requirements.

[0075] From the above experiments, it can be seen that the switch control circuit proposed in the embodiment of the present invention can significantly optimize the area and power consumption of the switch control circuit in the traditional SAR ADC without sacrificing the circuit performance, simplify the circuit design, and can be widely used in the field of low-power SAR ADC design technology.

[0076] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0077] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0078] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A low-power SAR ADC switch control circuit based on common mode level, characterized in that: It includes a first trigger module, a second trigger module, a third trigger module, a digital logic gate module and a bottom plate control switch module, the input ends of the second trigger module and the third trigger module are both connected to the output end of the first trigger module, the output ends of the second trigger module and the third trigger module are both connected to the input end of the digital logic gate module, the output end of the digital logic gate module is connected to the input end of the bottom plate control switch module, the first trigger module is used to generate a comparator latch signal and a first output signal, the second trigger module is used to store a comparison result according to the comparator latch signal and generate a second output signal, the third trigger module is used to indicate a current conversion position according to the first output signal and generate a third output signal, the digital logic gate module is used to obtain a switch control signal according to the second output signal and the third output signal, and the bottom plate control switch module is used to connect the capacitor bottom plate to a corresponding reference level according to the switch control signal.

2. A low-power SAR ADC switch control circuit based on common mode level according to claim 1, characterized in that: The first trigger module includes a first trigger, a first end of the first trigger is used to access the sampling and holding signal, a second end of the first trigger is grounded, a third end of the first trigger is used to access the external clock signal, a fourth end of the first trigger is used to access the system signal, a fifth end of the first trigger is connected to the input end of the second trigger module, and the fifth end of the first trigger is used to generate the comparator latch signal.

3. The low-power SAR ADC switch control circuit based on common mode level according to claim 2, characterized in that: The first trigger module also includes multiple second triggers, the first end of each second trigger is used to access the system signal, the second end of each second trigger is connected to the sixth end of the previous second trigger or the first trigger, the third end of each second trigger is used to access the external clock signal, the fourth end of each second trigger is used to access the sampling and holding signal, the fifth end of each second trigger is connected to the input end of the second trigger module, the sixth end of each second trigger is also connected to the input end of the third trigger module, the fifth end of each second trigger is used to generate the comparator latch signal, and the sixth end of each second trigger is used to generate the first output signal.

4. The low-power SAR ADC switch control circuit based on common mode level according to claim 1, characterized in that: The second output signal includes a first interface output signal and a second interface output signal.

5. The low-power SAR ADC switch control circuit based on common mode level according to claim 4, characterized in that: The comparison result includes a first comparison result, and the second trigger module includes a third trigger and multiple fourth triggers. The first end of the third trigger and each of the fourth triggers is connected to the output end of the first trigger module, the second end of the third trigger is connected to the third end of the third trigger, the second end of each of the fourth triggers is used to access the first comparison result, the third end of each of the fourth triggers is connected to the sixth end of the previous fourth trigger or the third trigger, the fourth end of the third trigger and each of the fourth triggers is used to access the sampling and holding signal, the sixth end of each of the fourth triggers is also connected to the input end of the digital logic gate module, the second end of each of the fourth triggers is used to store the first comparison result according to the comparator latch signal, and the sixth end of each of the fourth triggers is used to generate the first interface output signal.

6. The low-power SAR ADC switch control circuit based on common mode level according to claim 5, characterized in that: The second trigger module also includes a fifth trigger, a first end of the fifth trigger is connected to the output end of the first trigger module, a second end of the fifth trigger is used to access the first comparison result, a third end of the fifth trigger is connected to the sixth end of the fourth trigger, a fourth end of the fifth trigger is used to access the system signal, the sixth end of the fifth trigger is connected to the input end of the digital logic gate module, the second end of the fifth trigger is used to store the first comparison result according to the comparator latch signal, and the sixth end of the fifth trigger is used to generate the first interface output signal.

7. The low-power SAR ADC switch control circuit based on common mode level according to claim 4, characterized in that: The comparison result includes a second comparison result, and the second trigger module includes a sixth trigger and multiple seventh triggers. The first ends of the sixth trigger and each of the seventh triggers are connected to the output end of the first trigger module, the second end of the sixth trigger is connected to the third end of the sixth trigger, the second end of each of the seventh triggers is used to access the second comparison result, the third end of each of the seventh triggers is connected to the sixth end of the previous seventh trigger or the sixth trigger, the fourth end of the sixth trigger and each of the seventh triggers is used to access the sampling and holding signal, the sixth end of each of the seventh triggers is also connected to the input end of the digital logic gate module, the second end of each of the seventh triggers is used to store the second comparison result according to the comparator latch signal, and the sixth end of each of the seventh triggers is used to generate the second interface output signal.

8. The low-power SAR ADC switch control circuit based on common mode level according to claim 7, characterized in that: The second trigger module also includes an eighth trigger, a first end of the eighth trigger is connected to the output end of the first trigger module, a second end of the eighth trigger is used to access the second comparison result, a third end of the eighth trigger is connected to the sixth end of the seventh trigger, a fourth end of the eighth trigger is used to access the system signal, a sixth end of the eighth trigger is connected to the input end of the digital logic gate module, a second end of the eighth trigger is used to store the second comparison result according to the comparator latch signal, and a sixth end of the eighth trigger is used to generate the second interface output signal.

9. The low-power SAR ADC switch control circuit based on common mode level according to claim 1, characterized in that: The third trigger module includes multiple ninth triggers, the first end of each of the ninth triggers is used to access the system signal, the second end of each of the ninth triggers is used to access the power supply, the third end of each of the ninth triggers is connected to the output end of each of the first trigger modules, the fourth end of each of the ninth triggers is used to access the sampling and holding signal, the sixth end of each of the ninth triggers is connected to the input end of the digital logic gate module, the third end of the ninth trigger is used to indicate the current conversion position according to the first output signal, and the sixth end of the ninth trigger is used to generate the third output signal.

10. The low-power SAR ADC switch control circuit based on common mode level according to claim 4, characterized in that: The digital logic gate module includes a plurality of first NAND gates, second NAND gates, first AND gates, second AND gates and first NOT gates. The output ends of the second trigger module and the third trigger module are connected to the input ends of the first NAND gates. The output ends of the second trigger module and the third trigger module are connected to the input ends of the second NAND gates. The output ends of the second trigger module and the third trigger module are connected to the input ends of the first AND gates. The output ends of the second trigger module and the third trigger module are connected to the input ends of the second AND gates. The output end of the third trigger module is connected to the input end of the first NOT gates. The output ends of the first NAND gates, the second NAND gates, the first AND gates, the second AND gates and the first NOT gates are connected to the input end of the backplane control switch module. The first NAND gates and the second AND gates are used to obtain the switch control signal according to the third output signal and the first interface output signal. The second NAND gates and the first AND gates are used to obtain the switch control signal according to the third output signal and the second interface output signal. The first NOT gates are used to obtain the switch control signal according to the third output signal.

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