Driving chip, bidirectional power device and manufacturing method

Abstract

The invention provides a driving chip, a bidirectional power device and a manufacturing method, and relates to the technical field of integrated circuit design. The driving chip is used for driving the bidirectional power device and modulating the substrate potential of the bidirectional power device, and the bidirectional power device comprises a first power end, a second power end, a control end and a substrate potential end; the driving chip comprises a driving circuit and a substrate potential modulation circuit, and the driving circuit and the substrate potential modulation circuit are formed in the same substrate; and the substrate potential modulation circuit receives signals in the control end, the first power end and / or the second power end, and is connected with the substrate potential end, so that the voltage of the substrate potential end of the bidirectional power device is basically consistent with the lower voltage in the voltages at the control end, the first power end and the second power end. According to the technical scheme, extra cost and parasitic parameters of the bidirectional power device are not increased, and the substrate potential of the bidirectional power device can be managed and controlled.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a driver chip, a bidirectional power device and a manufacturing method. Background Art

[0002] As the requirements for the size and energy efficiency of power devices increase, wide-bandgap semiconductor GaN devices have been widely used in power conversion devices due to their lower power loss and faster switching capabilities.

[0003] In some applications that require bidirectional switching, GaN HEMT (Gallium Nitride High Electron Mobility Transistor) devices can be equivalent to two transistors coupled in series back to back. Compared with the series connection that requires two Si-based transistors, Bi-GaN HEMT (Bipolar Gallium Nitride High Electron Mobility Transistor) has lower power consumption and a more compact size.

[0004] However, during the switching process, if the substrate of the Bi-GaN HEMT is floating, the substrate will accumulate charge during the switching process of the device, which will affect the switching performance of the device and cause degradation of dynamic resistance. In conventional power devices, in order to avoid the impact of substrate floating on the performance and reliability of the device, it is usually necessary to keep the substrate and source of the device at the same potential. But in bidirectional power devices, since the source and drain of the device are switched according to the working state of the circuit, the substrate cannot be directly electrically connected to the source or drain.

[0005] At present, most of the potential management structures are implanted inside the bidirectional power device to achieve the regulation of substrate potential. However, this clamping circuit will not only introduce additional parasitic capacitance, affecting the working efficiency of the device, but also increase the overall cost of the bidirectional power device. Summary of the invention

[0006] The present application provides a driving chip, a bidirectional power device and a manufacturing method, which are used to provide a technical solution that does not increase the extra cost and parasitic parameters of the bidirectional power device and can achieve modulation of the substrate potential.

[0007] In a first aspect, the present application provides a driver chip for driving a bidirectional power device and modulating a substrate potential of the bidirectional power device, wherein the bidirectional power device comprises a first power terminal, a second power terminal, a control terminal and a substrate potential terminal; the driver chip comprises: a driving circuit and a substrate potential modulation circuit,

[0008] The driving circuit and the substrate potential modulation circuit are formed in the same substrate;

[0009] The substrate potential modulation circuit receives signals from the control terminal, the first power terminal and / or the second power terminal, and is connected to the substrate potential terminal so that the voltage at the substrate potential terminal of the bidirectional power device is basically consistent with the lower voltage among the voltages at the control terminal, the first power terminal and the second power terminal.

[0010] In an optional embodiment, the substrate potential modulation circuit includes a switching module, a first end of the switching module is electrically connected to the end with a lower voltage between the first power end and the second power end, a second end of the switching module is electrically connected to the substrate potential end of the bidirectional power device, and a control end of the switching module is electrically connected to the control end of the bidirectional power device.

[0011] In an optional embodiment, the switching module includes a first transistor, a first end of the first transistor is electrically connected to one of the first power end and the second power end of the bidirectional power device, a second end of the first transistor is electrically connected to the substrate potential end of the bidirectional power device, and a control end of the first transistor is electrically connected to the control end of the bidirectional power device.

[0012] In an optional embodiment, the first transistor includes a first well region with a first doping type located in the substrate, a first source and drain region with a second doping type located in the first well region, and a first gate between the first source and drain regions; wherein the first gate is the control terminal of the first transistor.

[0013] In an optional embodiment, the switching module also includes a second transistor, a first end of the second transistor is electrically connected to the other end of the first power end and the second power end of the bidirectional power device, a second end of the second transistor is electrically connected to the substrate potential end of the bidirectional power device, and a control end of the second transistor is electrically connected to the control end of the bidirectional power device.

[0014] In an optional embodiment, the second transistor includes a second well region with a first doping type located in the substrate, a second source and drain region with a second doping type located in the second well region, and a second gate arranged on the upper surface of the substrate and located between the source and drain regions, wherein the second gate is the control terminal of the second transistor.

[0015] In an optional embodiment, the switch module further includes a diode, a cathode of the diode being electrically connected to the control end of the first transistor and / or the control end of the second transistor; and an anode of the diode being electrically connected to the substrate potential end of the bidirectional power device.

[0016] In an optional implementation, the diode includes a PN junction diode or a Schottky diode.

[0017] In an optional implementation, the driving circuit includes a third transistor and a fourth transistor, the second end of the third transistor is electrically connected to the first end of the fourth transistor, and is electrically connected to the substrate potential end and the control end of the bidirectional power device to drive the bidirectional power device;

[0018] The control end of the third transistor is electrically connected to the control end of the fourth transistor.

[0019] In a second aspect, the present application provides a bidirectional power device, comprising the driving chip in the first aspect, and a bidirectional power device, wherein the driving chip is used to drive the bidirectional power device and modulate the substrate potential of the bidirectional power device.

[0020] In a third aspect, the present application provides a method for manufacturing a driver chip, the method comprising providing a substrate,

[0021] A driving circuit and a substrate potential modulation circuit are formed in the substrate; the driving circuit is used to drive the bidirectional power device, and the substrate potential modulation circuit is used to modulate the substrate potential of the bidirectional power device;

[0022] The bidirectional power device includes a first power terminal, a second power terminal, a control terminal and a substrate potential terminal; the substrate potential modulation circuit receives the control terminal and the signal of the first power terminal and / or the second power terminal, and is connected to the substrate potential terminal so that the substrate potential terminal of the bidirectional power device is basically consistent with the lower voltage of the voltage at the first power terminal and the second power terminal.

[0023] In an optional implementation, the substrate potential modulation circuit includes a first transistor and / or a second transistor; the driving circuit includes a third transistor and a fourth transistor;

[0024] The forming of the driving circuit and the substrate potential modulation circuit in the substrate comprises:

[0025] forming a first source-drain region and / or a second source-drain region, a third source-drain region and a fourth source-drain region in the substrate respectively and simultaneously; wherein the first source-drain region is the first end and the second end of the first transistor, the second source-drain region is the first end and the second end of the second transistor, the third source-drain region is the first end and the second end of the third transistor, and the fourth source-drain region is the first end and the second end of the fourth transistor;

[0026] A first gate and / or a second gate, a third gate and a fourth gate are respectively and simultaneously formed on the upper surface of the substrate; wherein the first gate is the control end of the first transistor, the second gate is the control end of the second transistor, the third gate is the control end of the third transistor, and the fourth gate is the control end of the fourth transistor.

[0027] In an optional implementation, the forming of the first source and drain region and / or the second source and drain region, the third source and drain region and the fourth source and drain region in the substrate simultaneously includes:

[0028] forming a first well region and / or a second well region, a third well region and a fourth well region in the substrate respectively;

[0029] The first source and drain region is formed in the first well region, and / or the second source and drain region is formed in the second well region, the third source and drain region is formed in the third well region, and the fourth source and drain region is formed in the fourth well region respectively and simultaneously.

[0030] In an optional embodiment, the type of doping ions in the first well region and the second well region is the same;

[0031] The types of doping ions of the third well region and the fourth well region are opposite;

[0032] The doping ions of the first source / drain region and the first well region are of opposite types;

[0033] The types of doping ions of the second source / drain region and the second well region are opposite;

[0034] , the types of doping ions of the third source / drain region and the third well region are opposite;

[0035] The fourth source and drain regions and the fourth well region have opposite doping ion types.

[0036] In an optional implementation, the substrate potential modulation circuit further includes a diode;

[0037] While forming the first well region and / or the second well region, the third well region and the fourth well region in the substrate respectively, the method further comprises:

[0038] forming a fifth well region in the substrate;

[0039] While simultaneously forming the first source and drain region in the first well region, forming the second source and drain region in the second well region, forming the third source and drain region in the third well region, and forming the fourth source and drain region in the fourth well region, the method further comprises:

[0040] A first doping region and / or a second doping region are formed in the fifth well region.

[0041] In an optional embodiment, the fifth well region has an opposite type of doping ions to the first well region and the second well region;

[0042] The types of doping ions in the first doping region and the second doping region are opposite.

[0043] In an optional implementation, after simultaneously forming the first source and drain region in the first well region, and / or forming the second source and drain region in the second well region, forming the third source and drain region in the third well region, and forming the fourth source and drain region in the fourth well region, the method further comprises:

[0044] A dielectric layer is formed on the upper surface of the substrate.

[0045] In an optional implementation, the forming of the first gate and / or the second gate, the third gate and the fourth gate on the upper surface of the substrate respectively and simultaneously comprises:

[0046] The first gate and / or the second gate, the third gate and the fourth gate are formed on the upper surface of the dielectric layer respectively and simultaneously.

[0047] In an optional embodiment, the method further comprises: forming a first metal electrode, a second metal electrode, a third metal electrode and a fourth metal electrode penetrating the dielectric layer on upper surfaces of the first source and drain region and / or the second source and drain region, the third source and drain region and the fourth source and drain region respectively and simultaneously;

[0048] The first metal electrode is located on both sides of the first gate and is electrically connected to the first source and drain region; and / or the second metal electrode is located on both sides of the second gate and is electrically connected to the second source and drain region; the third metal electrode is located on both sides of the third gate and is electrically connected to the third source and drain region; the fourth metal electrode is located on both sides of the first gate and is electrically connected to the fourth source and drain region.

[0049] In an optional embodiment, while simultaneously forming a first metal electrode, a second metal electrode, a third metal electrode and a fourth metal electrode penetrating the dielectric layer on upper surfaces of the first source and drain region and / or the second source and drain region, the third source and drain region and the fourth source and drain region, the method further comprises:

[0050] forming an anode metal and a cathode metal penetrating the dielectric layer on the upper surface of the fifth well region;

[0051] The anode metal is formed on the upper surface of the first doping region and is electrically connected to the fifth well region, and / or the cathode metal is formed on the upper surface of the second doping region and is electrically connected to the fifth well region.

[0052] In an optional implementation, after simultaneously forming the first well region and / or the second well region in the substrate, and simultaneously forming the third well region and the fourth well region in the substrate, the method further includes:

[0053] At the same time, an isolation region is formed between two adjacent well regions among the first well region and / or the second well region, the third well region and the fourth well region.

[0054] In a fourth aspect, the present application further provides a method for manufacturing a bidirectional power device, wherein the bidirectional power device comprises the driver chip in the first aspect, and a bidirectional power device;

[0055] The method comprises:

[0056] providing a first substrate and a second substrate respectively;

[0057] The driving chip is prepared using the first substrate as a substrate, and the bidirectional power device is simultaneously prepared on the second substrate.

[0058] The technical solution provided in the present application is that the driving chip includes a driving circuit and a substrate potential modulation circuit. The substrate potential modulation circuit receives signals from the control terminal, the first power terminal and / or the second power terminal of the bidirectional power device, and is connected to the substrate potential terminal of the bidirectional power device so that the voltage at the substrate potential terminal of the bidirectional power device is basically consistent with the lower voltage among the voltages at the control terminal, the first power terminal and the second power terminal, thereby avoiding the influence of substrate floating on the performance and reliability of the bidirectional power device.

[0059] The present application integrates the potential modulation circuit into the driving chip of the bidirectional power device, which not only does not increase the cost and parasitic parameters of the bidirectional power device, but also can design the potential modulation circuit according to actual needs to better manage the substrate potential of the bidirectional power device.

[0060] Furthermore, by integrating the potential modulation circuit and the driving circuit of the bidirectional power device into the same chip and preparing the potential modulation circuit at the same time as the driving circuit, the manufacturing steps can be reduced to improve production efficiency, reduce the cost of independently manufacturing the potential modulation circuit, and thus reduce the overall manufacturing cost of the electric energy conversion device. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0062] Figure 1 A circuit structure diagram of a driver chip provided in an embodiment of the present application;

[0063] Figure 2 A circuit for a potential modulation circuit of a bidirectional power device integrated in a driver chip provided in an embodiment of the present application Figure 1 ;

[0064] Figure 3 A circuit for a potential modulation circuit of a bidirectional power device integrated in a driver chip provided in an embodiment of the present application Figure 2 ;

[0065] Figure 4 A schematic diagram of a substrate structure of a driver chip provided in an embodiment of the present application;

[0066] Figure 5 A schematic diagram of a structure in which a first well region and / or a second well region are formed in the substrate at the same time, and a third well region and a fourth well region are formed in the substrate at the same time, provided in an embodiment of the present application;

[0067] Figure 6a A structure for simultaneously forming corresponding source and drain regions in different well regions provided in an embodiment of the present application Figure 1 ;

[0068] Figure 6b A structure for simultaneously forming corresponding source and drain regions in different well regions provided in an embodiment of the present application Figure 2 ;

[0069] Figure 7a A structure for forming a dielectric layer on the upper surface of a substrate provided in an embodiment of the present application Figure 1 ;

[0070] Figure 7b A structure for forming a dielectric layer on the upper surface of a substrate provided in an embodiment of the present application Figure 2 ;

[0071] Figure 8a A structure for simultaneously forming a first gate and / or a second gate, a third gate and a fourth gate on the upper surface of a substrate provided in an embodiment of the present application Figure 1 ;

[0072] Figure 8b A structure for simultaneously forming a first gate and / or a second gate, a third gate and a fourth gate on the upper surface of a substrate provided in an embodiment of the present application Figure 2 ;

[0073] Figure 9aA structure for forming a first metal electrode, a second metal electrode, a third metal electrode and a fourth metal electrode respectively provided in an embodiment of the present application Figure 1 ;

[0074] Figure 9b A structure for forming a first metal electrode, a second metal electrode, a third metal electrode and a fourth metal electrode respectively provided in an embodiment of the present application Figure 2 ;

[0075] Fig.10 The present invention provides a structure in which a first substrate is used as a substrate to prepare a driver chip, and a bidirectional power device is prepared on a second substrate at the same time. Figure 1 ;

[0076] Fig.11 The present invention provides a structure in which a driver chip is prepared on a first substrate and a bidirectional power device is prepared on a second substrate. Figure 2 ;

[0077] Fig.12 The present invention provides a structure in which a driver chip is prepared on a first substrate and a bidirectional power device is prepared on a second substrate. Figure 3 ;

[0078] Fig.13 The present invention provides a structure in which a first substrate is used as a substrate to prepare a driver chip, and a bidirectional power device is prepared on a second substrate at the same time. Figure 4 .

[0079] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0080] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0081] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present application belongs. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. It is understood that the terms "first", "second", etc. used in the present application can be used to describe various information or data in this article, but these elements are not limited by these terms. These terms are only used to distinguish the first information from another information. For example, without departing from the scope of the present application, the first action information can be referred to as the second action information, and similarly, the second action information can be referred to as the first action information. Both the first action information and the second action information are action information, but they are not the same action information.

[0082] As the requirements for the size and energy efficiency of power devices increase, wide-bandgap semiconductor GaN devices have been widely used in power conversion devices due to their lower power loss and faster switching capabilities.

[0083] In some applications that require bidirectional switching, GaN HEMT (Gallium Nitride High Electron Mobility Transistor) devices can be equivalent to two transistors coupled in series back to back. Compared with the series connection that requires two Si-based transistors, Bi-GaN HEMT (Bipolar Gallium Nitride High Electron Mobility Transistor) has lower power consumption and a more compact size.

[0084] However, during the switching process, if the substrate of the Bi-GaN HEMT is floating, the substrate will accumulate charge during the switching process of the device, which will affect the switching performance of the device and cause degradation of dynamic resistance. In conventional GaN HEMT devices, in order to avoid the impact of substrate floating on the performance and reliability of the device, it is usually necessary to keep the substrate and source of the device at the same potential. But in bidirectional GaN HEMT devices, since the source and drain of the device are switched according to the working state of the circuit, the substrate cannot be directly electrically connected to the source or drain.

[0085] At present, most of them adopt additional manufacturing processes to implant a potential management structure inside the Bi-GaN HEMT to achieve the regulation of substrate potential. However, this clamping circuit will not only introduce additional parasitic capacitance, affecting the working efficiency of the device, but also increase the overall cost of GaN power devices.

[0086] In response to the above problems, the present application provides a driving chip for integrating the potential modulation circuit and driving circuit of a bidirectional power device into the same chip, so that the structure of the potential modulation circuit can be adjusted according to actual applications without increasing the cost and parasitic parameters of the bidirectional power device itself, so as to better achieve the control of the substrate potential.

[0087] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0088] First, refer to Figure 1 , shows a driving chip provided by an embodiment of the present application, the driving chip includes a driving circuit 30 and a substrate potential modulation circuit 20. The driving circuit is used to drive a bidirectional power device 10, and the substrate potential modulation circuit 20 is used to modulate the substrate potential of the bidirectional power device.

[0089] Among them, bidirectional power devices are a type of power electronic devices that can conduct current in two directions and control the flow of current. Among them, bidirectional power devices may include bidirectional MOSFETs, bidirectional IGBTs, or bidirectional SiC / GaN devices.

[0090] Optionally, the bidirectional power device 10 of the embodiment of the present application may be a bidirectional GaN device. It should be understood that the bidirectional power device 10 may also be other suitable bidirectional power devices, and the embodiment of the present application does not make any special limitation on this.

[0091] Optionally, the driving circuit 30 and the substrate potential modulation circuit 20 are formed in the same substrate, so that the potential modulation circuit can be prepared at the same time as the driving circuit, reducing the manufacturing steps, thereby improving production efficiency, reducing the cost of independently manufacturing the potential modulation circuit, and further reducing the overall manufacturing cost of the electric energy conversion device.

[0092] In some examples, reference Figure 1 The bidirectional power device 10 comprises a driving terminal G0, a first power terminal S / D1, a second power terminal S / D2 and a substrate potential terminal Sub. The driving circuit 30 is connected to the control terminal G0 and is used to drive the bidirectional power device 10. The substrate potential modulation circuit 20 receives signals from the control terminal G0, the first power terminal S / D1 and / or the second power terminal S / D2, and is connected to the substrate potential terminal Sub, so that the voltage of the substrate potential terminal Sub of the bidirectional power device is substantially consistent with the lower voltage among the voltages at the control terminal G0, the first power terminal S / D1 and the second power terminal S / D2.

[0093] Based on this, the substrate potential modulation circuit in the driving chip provided in the embodiment of the present application can make the voltage of the substrate potential terminal Sub of the bidirectional power device basically consistent with the lower voltage among the voltages at the control terminal G0, the first power S / D1 and the second power terminal S / D2, thereby avoiding the influence of substrate floating on the performance and reliability of the bidirectional power device.

[0094] In the embodiment of the present application, the potential modulation circuit is integrated into the driver chip of the bidirectional power device, which not only does not increase the cost and parasitic parameters of the bidirectional power device, but also can be designed according to actual needs to better manage the substrate potential of the bidirectional power device.

[0095] Reference Figure 2 and Figure 3 The potential modulation circuit 20 includes a switch module 21 .

[0096] The first end of the switch module 21 is electrically connected to the lower voltage end of the first power end S / D1 and the second power end S / D2 of the bidirectional power device 10, the second end of the switch module 21 is connected to the substrate potential end Sub of the bidirectional power device 10, and the control end of the switch module is electrically connected to the control end G0 of the bidirectional power device; the switch module 21 is used to connect the substrate potential end Sub to the lower voltage end of the first power end S / D1 and the second power end S / D2 when the bidirectional power device 10 is turned on, so that the potential of the substrate potential end Sub is maintained at the lower potential of the bidirectional power device 10. When the bidirectional power device 10 is turned off, the bidirectional power device is connected to the control end G0 via D0, so that the potential of the substrate potential end Sub is maintained at the lower potential of the bidirectional power device 10

[0097] It is worth noting that the first power terminal S / D1 may be one of the source terminal and the drain terminal of the bidirectional power device, and the second power terminal S / D2 may be the other of the drain terminal and the source terminal of the bidirectional power device.

[0098] In the embodiment of the present application, the input end of the switch module 21 is connected to the first power terminal S / D1 and the second power terminal S / D2 of the bidirectional power device 10, and the output end of the switch module 21 is connected to the substrate potential terminal Sub of the bidirectional power device 10, and is used to modulate the potential of the substrate potential terminal Sub according to the potential of the lower potential end of the first power terminal S / D1 and the second power terminal S / D2, so that the potential of the substrate potential terminal Sub is maintained at the lower potential of the first power terminal S / D1 and the second power terminal S / D2, thereby avoiding the influence of the floating of the substrate potential terminal Sub on the performance and reliability of the bidirectional power device 10.

[0099] Specifically, maintaining the potential of the substrate potential terminal Sub at a lower potential between the first power terminal S / D1 and the second power terminal S / D2 can not only reduce the thermal effect caused by parasitic effects, improve the thermal stability, reliability, and anti-interference ability of the device, and reduce the impact of external noise on device performance, but also reduce the on-resistance of the bidirectional power device 10, improve the conduction efficiency, reduce switching losses, and increase the switching speed, thereby improving the overall performance of the bidirectional power device 10.

[0100] Furthermore, the potential modulation circuit is integrated into the driving chip where the driving circuit 30 of the bidirectional power device 10 is located. The potential modulation circuit 20 is prepared while preparing the driving circuit 30, which can reduce the manufacturing steps and process complexity, thereby improving production efficiency, reducing the cost of independently manufacturing the potential modulation circuit, and reducing the overall manufacturing cost.

[0101] Optionally, when designing a driver chip, the potential modulation circuit of the bidirectional power device 10 can be designed as a submodule to ensure that its functions and performance meet the requirements. During the manufacturing process, the driving circuit 30 and the potential modulation circuit 20 can be prepared simultaneously using a unified doping and epitaxial growth process, and the structures of the potential modulation circuit 20 and the driving circuit 30 can be formed on the same chip through photolithography and etching processes. During the metallization and packaging stage, the connection points of the potential modulation circuit 20 and the driving circuit 30 are metallized and packaged.

[0102] The above content describes the overall structure and effect of the switch module 21 in detail, and the following content describes the specific structure and principle of the switch module 21 through several specific embodiments.

[0103] In an alternative embodiment, referring to Figure 2 The switch module 21 includes a first transistor T1 and a second transistor T2.

[0104] The first end of the first transistor T1 is electrically connected to one of the first power terminal S / D1 and the second power terminal S / D2 of the bidirectional power device 10, the second end of the first transistor T1 is connected to the substrate potential terminal Sub of the bidirectional power device 10, and the control terminal G1 of the first transistor T1 is electrically connected to the control terminal G0 of the bidirectional power device. The first end of the second transistor T2 is electrically connected to the other of the first power terminal S / D1 and the second power terminal S / D2 of the bidirectional power device, the second end of the second transistor T2 is electrically connected to the substrate potential terminal Sub of the bidirectional power device, and the control terminal G2 of the second transistor T2 is electrically connected to the control terminal G0 of the bidirectional power device.

[0105] For example, when the first end of the first transistor T1 is electrically connected to the first power end S / D1 of the bidirectional power device, the first end of the second transistor T2 is electrically connected to the second power end S / D2 .

[0106] When the bidirectional power device 10 is turned on and the voltage of the first power terminal S / D1 of the bidirectional power device 10 is lower than the voltage of the second power terminal S / D2 of the bidirectional power device 10, the first transistor T1 is turned on and the first power terminal S / D1 of the bidirectional power device 10 is connected to the substrate potential terminal Sub of the bidirectional power device 10.

[0107] When the control signal is a turn-on signal, the bidirectional power device 10 is turned on, and T1 and T2 are also turned on. When the voltage of the second power terminal S / D2 of the bidirectional power device 10 is lower than the voltage of the first power terminal S / D1 of the bidirectional power device 10, the current will flow from the first power terminal S / D1 to the second power terminal S / D2, and the voltage of the substrate potential terminal Sub is between the S / D1 and S / D2 potentials.

[0108] It should be understood that the voltage difference between the first power terminal S / D1 and the second power terminal S / D2 of the bidirectional power device 10 is small, so the substrate potential terminal Sub of the bidirectional power device 10 can be maintained at a relatively low potential.

[0109] Moreover, in this embodiment, when the control signal applied to the control terminal G0 of the bidirectional power device 10 is a turn-on signal, the first transistor T1 and the second transistor T2 will respond to the control signal at the same time. Based on this, synchronous control of the bidirectional power device 10, the first transistor T1, and the second transistor T2 can be achieved, which simplifies the control logic, reduces the signal transmission delay, and improves the response speed.

[0110] Exemplarily, the first transistor T1 and the second transistor T2 can both be one of a switching tube such as a bipolar junction transistor (BJT), a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a field effect transistor (JFET), etc., and the embodiment of the present application does not make any special limitation on this.

[0111] In an optional embodiment, referring to Figure 9b The first transistor includes a first well region 2011 with a first doping type located in the substrate, a first source and drain region 2012 with a second doping type located in the first well region 2011, and a first gate 2013 between the first source and drain regions 2012; wherein the first gate 2013 is the control terminal of the first transistor, and the first source and drain region 2012 is used to form the first end 20141 and the second end 20142 of the above-mentioned first transistor.

[0112] Reference Figure 9bThe second transistor includes a second well region 2021 with a first doping type located in the substrate, a second source and drain region 2022 with a second doping type located in the second well region 2021, and a second gate 2023 arranged on the upper surface of the substrate and located between the source and drain regions 2022, wherein the second gate 2023 is the control terminal of the second transistor, and the upper part of the second source and drain region 2022 is used to form a first end 20241 and a second end 20242 of the second transistor.

[0113] In the above embodiment, the control terminal G1 of the first transistor T1 and the control terminal G2 of the second transistor T2 are both connected to the control terminal G0 of the bidirectional power device 10 .

[0114] That is to say, when the control signal is applied to the control terminal G0 of the bidirectional power device 10, the first and second transistors T2 will respond to the control signal at the same time. Based on this, the bidirectional power device 10 and the first and second transistors T2 can be synchronously controlled, which simplifies the control logic, reduces the signal transmission delay, and improves the response speed.

[0115] Exemplarily, when the bidirectional power device 10 and the first and second transistors T2 are the same type of devices, the control signal can synchronously control the bidirectional power device 10, the first and second transistors T2 to turn on or off. That is, when the bidirectional power device 10 is turned on, the first transistor T1 and the second transistor T2 are turned on synchronously. At this time, if the potential of the first power terminal S / D1 is low, the current flows from S / D2 to S / D1, and the substrate potential is between S / D2 and S / D1, and is approximately equal to the potential of S / D1. If the potential of the second power terminal S / D2 is low, the current flows from S / D1 to S / D2, and the substrate potential is between S / D2 and S / D1, and is approximately equal to the potential of S / D2. It should be understood that when the bidirectional power device 10 is turned on, the voltage difference between the first power terminal S / D1 and the second power terminal S / D2 is small. Therefore, whether the voltage of the first power terminal S / D1 is greater than or less than the voltage of the second power terminal S / D2, it can be ensured that the substrate potential terminal Sub is always at a lower potential.

[0116] In another alternative embodiment, referring to Figure 3 The switch module 21 only includes a first transistor T1, one end of the first transistor T1 is connected to the first power end S / D1 of the bidirectional power device 10, and the second power end S / D2 of the first transistor T1 is connected to the substrate potential end Sub of the bidirectional power device 10.

[0117] Based on the structure of this embodiment, the control terminal G0 of the bidirectional power device 10 is connected to the control terminal G1 of the first transistor T1 .

[0118] When the bidirectional power device 10 is turned on, the voltage of the first power terminal S / D1 of the bidirectional power device 10 is substantially equal to the voltage of the second power terminal S / D2 of the bidirectional power device 10. Since the first transistor T1 is also turned on, the first power terminal S / D1 of the bidirectional power device 10 is connected to the substrate potential terminal Sub of the bidirectional power device 10 through the first transistor T1. The potential of the substrate potential terminal Sub is equal to the voltage of the first power terminal S / D1, that is, the voltage of the second power terminal S / D2. It should be understood that even if there is a voltage difference between S / D1 and S / D2, since the power device 10 is turned on, the voltage difference between S / D1 and S / D2 is also very small. Regardless of whether the first transistor T1 is connected to the first power terminal S / D1 or the second power terminal S / D2, the substrate potential will be at a lower potential.

[0119] When the bidirectional power device 10 is turned off, the substrate potential terminal Sub is connected to the control terminal G0 of the bidirectional power device 10 through a diode. It should be understood that when the bidirectional power device 10 is turned off, the voltage of the control terminal G0 is 0 or a negative voltage. Therefore, at this time, the substrate potential terminal Sub is equal to 0 or a negative voltage, which can ensure that the substrate potential terminal Sub is at a lower potential.

[0120] Based on the above description, the substrate potential terminal Sub of the bidirectional power device 10 can be maintained at a lower potential among the voltages at the control terminal G0 , the first power terminal S / D1 , and the second power terminal S / D3 .

[0121] It should be understood that since the control terminal G1 of the first transistor T1 is connected to the control terminal G0 of the bidirectional power device 10, when the control signal is applied to the control terminal G0 of the bidirectional power device 10, the first transistor T1 will respond to the control signal at the same time. Based on this, the bidirectional power device 10 and the first transistor T1 can be synchronously controlled, which simplifies the control logic, reduces the signal transmission delay, and improves the response speed.

[0122] The above content describes in detail the specific structure and working principle of the switch module 21. Based on this, it can ensure that the substrate potential terminal Sub of the bidirectional power device 10 is at a lower potential, thereby achieving control over the potential of the substrate potential terminal Sub without increasing the cost and parasitic parameters of the bidirectional power device 10 itself.

[0123] In the embodiments of this application, refer to Figure 2 The switch module further includes a diode D0, a cathode of the diode D0 being electrically connected to the control end of the first transistor T1 and / or the control end of the second transistor T2; and an anode of the diode D0 being electrically connected to the substrate potential end Sub of the bidirectional power device.

[0124] In the embodiments of this application, refer to Figure 3The switch module further includes a diode D0, a cathode of the diode D0 is electrically connected to the control end of the first transistor T1; an anode of the diode D0 is electrically connected to the substrate potential end Sub of the bidirectional power device.

[0125] When the control signal is a shutdown signal, the first transistor T1 and the second transistor T2 are in the off state, and the substrate potential terminal Sub voltage is connected to the control signal through the diode D0. Since the control signal potential is low, the substrate potential terminal Sub of the bidirectional power device 10 can be maintained at a low potential.

[0126] Exemplarily, the diode may be a PN junction transistor or a Schottky diode. It should be understood that the diode D0 may also be other components with similar functions, and the present embodiment does not specifically limit this.

[0127] In an alternative embodiment, referring to Figure 1 , the driving circuit 30 includes a third transistor T3 and a fourth transistor T4.

[0128] The second end of the third transistor T3 is electrically connected to the first end of the fourth transistor T4, and is electrically connected to the substrate potential terminal Sub and the control terminal G0 of the bidirectional power device 10 to drive the bidirectional power device 10; the control terminal of the third transistor T3 is electrically connected to the control terminal of the fourth transistor T4.

[0129] The second end (source or drain) of the third transistor is electrically connected to the first end (which may be the drain or source) of the fourth transistor to form an output path to drive the bidirectional power device.

[0130] The control end of the third transistor T3 is electrically connected to the control end of the fourth transistor T4, which means that the control end of the third transistor T3 and the fourth transistor T4 are synchronously controlled, that is, they are turned on or off at the same time. This synchronous control method ensures the stability and reliability of the driving circuit.

[0131] Based on this, the present application can control the on or off of the bidirectional power device through a driving circuit.

[0132] In a second aspect, an embodiment of the present application further provides a bidirectional power device, which includes a driving chip and a bidirectional power device, wherein the driving chip is used to drive the bidirectional power device and modulate the substrate potential of the bidirectional power device.

[0133] Among them, the driving chip is used to drive the bidirectional power device to be turned on or off, and to modulate the substrate potential of the bidirectional power device when the bidirectional power device is turned on and off, so that the voltage at the substrate potential end of the bidirectional power device is basically consistent with the lower voltage among the voltages at the control end, the first power end and the second power end, thereby avoiding the influence of substrate floating on the performance and reliability of the bidirectional power device.

[0134] It should be understood that the beneficial effects of the bidirectional power device of this embodiment are similar to those of the aforementioned Figure 1-Figure 3 The beneficial effects of the driver chip provided in the illustrated embodiment are the same and will not be described in detail here.

[0135] In a third aspect, the present application also provides a method for manufacturing a driver chip, the method comprising: A1, referring to Figure 4 , providing a substrate 100; wherein the substrate may be a silicon substrate.

[0136] It should be understood that the substrate, as the basis of the driver chip, carries the structure of the driver chip. It provides the planar or three-dimensional structure required for the driver chip manufacturing, so that other functional layers (such as epitaxial layers, doped regions, etc.) can be orderly formed or grown on the substrate.

[0137] A2, reference Figure 5-9b A driving circuit 30 and a substrate potential modulation circuit 20 are formed in a substrate 100; the driving circuit is used to drive the bidirectional power device, and the substrate potential modulation circuit is used to modulate the substrate potential of the bidirectional power device.

[0138] The bidirectional power device includes a first power terminal, a second power terminal, a control terminal and a substrate potential terminal; the substrate potential modulation circuit receives the control terminal and the signal of the first power terminal and / or the second power terminal, and is connected to the substrate potential terminal so that the substrate potential terminal of the bidirectional power device is basically consistent with the lower voltage of the voltage at the first power terminal and the second power terminal.

[0139] Based on this, the driving chip provided in the embodiment of the present application includes a driving circuit and a substrate potential modulation circuit integrated in the same driving chip. The substrate potential modulation circuit receives signals from the control end, the first power end and / or the second power end of the bidirectional power device, and is connected to the substrate potential end of the bidirectional power device so that the voltage at the substrate potential end of the bidirectional power device is basically consistent with the lower voltage among the voltages at the control end, the first power end and the second power end, thereby avoiding the influence of substrate floating on the performance and reliability of the bidirectional power device.

[0140] The embodiment of the present application integrates the potential modulation circuit and the driving circuit into the driving chip, which not only does not increase the cost and parasitic parameters of the bidirectional power device, but also can design the potential modulation circuit according to actual needs to better manage the substrate potential of the bidirectional power device.

[0141] Furthermore, by integrating the potential modulation circuit and the driving circuit of the bidirectional power device into the same chip and preparing the potential modulation circuit at the same time as the driving circuit, the manufacturing steps can be reduced to improve production efficiency, reduce the cost of independently manufacturing the potential modulation circuit, and thus reduce the overall manufacturing cost of the electric energy conversion device.

[0142] As an optional implementation, the substrate potential modulation circuit includes a first transistor and / or a second transistor; the driving circuit includes a third transistor and a fourth transistor;

[0143] The forming of the driving circuit and the substrate potential modulation circuit in the substrate includes: the above step A2 may include:

[0144] A21, reference Figure 5 , a first well region 2011 and / or a second well region 2021 , a third well region 3011 and a fourth well region 3021 are formed in the substrate 100 .

[0145] Based on this, the steps of manufacturing the driver chip can be reduced, thereby improving production efficiency, and helping to reduce manufacturing costs and shorten production cycles.

[0146] Optionally, the type of doping ions in the first well region 2011 and the second well region 2021 is the same;

[0147] The types of doping ions in the third well region 3011 and the fourth well region 3021 are opposite;

[0148] In some examples, the first well region 2011 , the second well region 2021 , and the third well region 3011 have the same ion doping type and can be formed simultaneously to reduce the process steps for manufacturing the driver chip and improve the efficiency of the manufacturing process.

[0149] It should be understood that the above doping strategy can allow the first transistor, the second transistor, the third transistor and the fourth transistor with different functions and characteristics to be implemented on the same driver chip, thereby meeting the application requirements of the driver chip.

[0150] A22, reference Figure 6a Figure 6b , respectively and simultaneously forming the first source and drain region 2012 in the first well region 2011, and / or forming the second source and drain region 2022 in the second well region 2021, forming the third source and drain region 3012 in the third well region 3011, and forming the fourth source and drain region 3022 in the fourth well region 3021.

[0151] Wherein, the doping ions of the first source / drain region 2012 and the first well region 2011 are of opposite types;

[0152] and / or, the types of doping ions in the second source / drain region 2022 and the second well region 2021 are opposite;

[0153] The types of doping ions in the third source / drain region 3012 and the third well region 3011 are opposite;

[0154] The fourth source and drain regions 3022 and the fourth well region 3021 have opposite doping ion types.

[0155] Through this step, corresponding source and drain regions can be formed in different well regions at the same time, so as to improve the efficiency of the manufacturing process.

[0156] Specifically, a first source-drain region 2012 is formed in the first well region 2011, and a second source-drain region 2022 is formed in the second well region 2021, so as to implement transistors of the same type (such as a plurality of NMOS or PMOS transistors) on the same driver chip. A third source-drain region 3012 is formed in the third well region 3011, and a fourth source-drain region 3022 is formed in the fourth well region 3021, so as to implement transistors of different types (such as NMOS and PMOS) on the same driver chip.

[0157] The above-mentioned well regions provide electrical isolation between different transistors, thereby reducing interference between different transistors.

[0158] Optionally, the substrate potential modulation circuit also includes a diode.

[0159] At this time, refer to Figure 5 , the method further comprises:

[0160] A fifth well region 2031 is formed in the substrate. The ion doping type of the fifth well region 2031 is the same as the ion doping type of the fourth well region 3021. Based on this, the fifth well region 2031 can be formed in the substrate while the fourth well region is formed, so as to reduce the process steps of manufacturing the driver chip and improve the efficiency of the manufacturing process.

[0161] It should be understood that the embodiment of the present application does not limit the formation order of the first well region 2011 , the second well region 2021 , the third well region 3011 , the fourth well region 3021 , and the fifth well region 2031 .

[0162] Reference Figure 6a or Figure 6b , while simultaneously forming the first source and drain region in the first well region, forming the second source and drain region in the second well region, forming the third source and drain region in the third well region, and forming the fourth source and drain region in the fourth well region, the method further comprises:

[0163] A first doping region 20321 and / or a second doping region 20322 is formed in the fifth well region 2031 .

[0164] In the embodiment of the present application, by forming the first doping region 20321 and / or the second doping region 20322 in the fifth well region, the area of ​​the driver chip can be better utilized to achieve higher integration and performance.

[0165] In some examples, the first doping region 20321 and the second doping region 20322 are used to subsequently form a functional region of a diode.

[0166] The types of doping ions in the first doping region 20321 and the second doping region 20332 are opposite.

[0167] Based on this, when two adjacent regions have opposite doping types (one is n-type and the other is p-type), a pn junction is formed between them, and this PN junction can form a PN junction diode, such as Figure 6b and 7b The first doped region 20321 and the second doped region 20322 in the.

[0168] A23, reference Figure 8a and Figure 8b , respectively and simultaneously forming a first gate 2013 and / or a second gate 2023, a third gate 3013 and a fourth gate 3023 on the upper surface of the substrate 100; wherein the first gate 2013 is the control end of the first transistor, the second gate 2023 is the control end of the second transistor, the third gate 3013 is the control end of the third transistor, and the fourth gate 3023 is the control end of the fourth transistor.

[0169] It should be understood that by completing the formation of multiple gates in the same process step, the number of process steps can be reduced, thereby reducing costs and shortening production time. And by forming multiple gates on the same substrate, multiple circuit functions and application requirements can be supported.

[0170] In some examples, reference Figure 7a and Figure 7b After the above step A22, the manufacturing method may further include:

[0171] A dielectric layer 101 is formed on the upper surface of the substrate 100 .

[0172] In the embodiment of the present application, the dielectric material of the dielectric layer 101 includes silicon dioxide (SiO2), silicon nitride (Si3N4) and other low dielectric constant materials. The selection of the material depends on the required electrical, mechanical and thermal properties.

[0173] Optionally, the dielectric layer 101 is used to isolate the source and drain regions from the corresponding gate.

[0174] Then, step A23 includes:

[0175] Reference Figure 8a and Figure 8b The first gate 2013 and / or the second gate 2023 , the third gate 3013 and the fourth gate 3023 are formed on the upper surface of the dielectric layer 101 at the same time.

[0176] The dielectric layer 101 helps to reduce interference and crosstalk between different gates and source and drain regions, thereby ensuring signal integrity.

[0177] In some optional implementations, the manufacturing method provided in the embodiments of the present application may further include:

[0178] A24, refer to Figure 9a and Figure 9b , respectively and simultaneously forming a first metal electrode (20141 and 20142), a second metal electrode (20241 and 20242), a third metal electrode (30141 and 30142) penetrating the dielectric layer on the upper surfaces of the first source and drain region and / or the second source and drain region, the third source and drain region, and the fourth source and drain region.

[0179] The first metal electrode (20141 and 20142) is located on both sides of the first gate 2013 and is electrically connected to the first source and drain region 2012; and / or, the second metal electrode (20241 and 20242) is located on both sides of the second gate 2023 and is electrically connected to the second source and drain region 2022; and / or, the third metal electrode (30141 and 30142) is located on both sides of the third gate 3013 and is electrically connected to the third source and drain region 3012; and / or, the fourth metal electrode (30241 and 30242) is located on both sides of the fourth gate 3023 and is electrically connected to the fourth source and drain region 3022.

[0180] Optionally, the metal electrodes provide electrical connections between the corresponding source and drain regions and external circuits. By forming penetrating metal electrodes in the dielectric layer, it is possible to ensure that current is effectively transmitted from the source and drain regions to the external circuits.

[0181] Optionally, while executing step A24, the manufacturing method provided in the embodiment of the present application may further include:

[0182] An anode metal (one of 2033 and 2034 ) and a cathode metal (the other of 2033 and 2034 ) penetrating the dielectric layer are formed on the upper surface of the fifth well region 2031 .

[0183] The cathode metal is formed on the upper surface of the first doping region 20321 and is electrically connected to the fifth well region 2031 and / or the anode metal is formed on the upper surface of the second doping region 20322 and is electrically connected to the fifth well region 2031 .

[0184] like Figure 6a and 7a As shown, the first doped region 20321 is in contact with the cathode metal 2034, and the anode metal 2033 is in contact with the upper surface of the fifth well region 2031 to form a Schottky diode.

[0185] In the embodiment of the present application, the electrical connection with the external circuit can be provided by the anode and cathode metal. By penetrating the dielectric layer, the anode and cathode metal can ensure that the current is effectively transmitted from the first and second doped regions to the external circuit.

[0186] Furthermore, the above operation can reduce the number of process steps, thereby reducing costs and shortening production time.

[0187] In some possible implementations, refer to Figure 5 After forming the first well region and / or the second well region in the substrate and forming the third well region and the fourth well region in the substrate, the method further comprises:

[0188] At the same time, an isolation region 102 is formed between two adjacent well regions among the first well region 2011 and / or the second well region 2021 , the third well region 3011 and the fourth well region 3012 .

[0189] Based on this, the isolation region 102 can be used to prevent current leakage between adjacent well regions, thereby ensuring that the devices in each well region can work independently without being affected by adjacent regions.

[0190] The isolation region may be implemented by shallow trench isolation (STI) or deep trench isolation (DTI) technology.

[0191] Through the above steps, the manufacturing of the driver chip is realized, and then the functional areas can be electrically connected in the following manner.

[0192] The first metal electrode on one of the source region and the drain region of the first source and drain region is grounded and electrically connected to one of the first power terminal and the second power terminal of the bidirectional power device, the first metal electrode on the other is connected to the anode metal on the fifth well region, and connected to the substrate potential terminal of the bidirectional power device, the second metal electrode on one of the source region and the drain region of the second source and drain region is electrically connected to the other of the first power terminal and the second power terminal of the bidirectional power device, the first metal electrode on the other is electrically connected to the anode metal on the fifth well region, and connected to the substrate potential terminal of the bidirectional power device, the first gate and the second gate are electrically connected to the control terminal of the bidirectional power device, and the control terminal of the bidirectional power device is also electrically connected to the cathode metal on the fifth well region. The third metal electrode on the third source and drain region is electrically connected to the cathode metal on the fifth well region, the fourth metal electrode on the fourth source and drain region is electrically connected to the cathode metal on the fifth well region, and the third gate and the fourth gate are electrically connected to the same control voltage terminal.

[0193] The cathode metal on the fifth well region is electrically connected to the first metal electrode and the second metal electrode, and the anode metal on the fifth well region is electrically connected to the substrate potential terminal of the bidirectional power device.

[0194] Based on this, a method for manufacturing a driving chip is provided, in which a potential modulation circuit and a driving circuit of a bidirectional power device are integrated into the same chip. The potential modulation circuit is prepared while the driving circuit is prepared, which can reduce the manufacturing steps and thus improve production efficiency, reduce the cost of independently manufacturing the potential modulation circuit, and thereby reduce the overall manufacturing cost of the electric energy conversion device.

[0195] In a fourth aspect, an embodiment of the present application further provides a method for manufacturing a bidirectional power device, wherein the bidirectional power device comprises the driver chip of the first aspect of the claim, and a bidirectional power device.

[0196] The method comprises:

[0197] A first substrate 100 and a second substrate 200 are provided respectively, wherein the substrate of the first chip is a Si substrate, and the second substrate can be a Si substrate, a sapphire substrate, a SiC substrate, etc.

[0198] Reference Fig.10 , using the first substrate as a substrate, preparing the driver chip, and simultaneously preparing the bidirectional power device on the second substrate.

[0199] Preparing the bidirectional power device on the second substrate may include:

[0200] A buffer layer 11 (GAN layer) is formed on the second substrate 200 .

[0201] forming a barrier layer 12 (AlGaN) on the buffer layer 11;

[0202] A dielectric layer 101 is formed on the upper surface of the barrier layer 12 .

[0203] Optionally, after forming a dielectric layer on the upper surface of the first substrate, the method further includes:

[0204] A fifth metal electrode 131, a sixth metal electrode 132, and a control electrode 14 are formed; wherein the fifth metal electrode is the first power end of the bidirectional power device, the sixth metal electrode is the second power end of the bidirectional power device, and the control electrode is the control end of the bidirectional power device.

[0205] Based on this, the manufacture of the bidirectional power device is realized, and then the bidirectional power device can be electrically connected to the driving chip in the following manner.

[0206] Reference Fig.10 and Fig.11 One of the third metal electrodes 3014 on the third source and drain region 3012 is grounded, the other is electrically connected to one of the fourth metal electrodes 3034 on the fourth source and drain region 3023 and the control electrode 14 of the bidirectional power device, and one of the fourth metal electrodes 3034 on the fourth source and drain region 3023 is connected to the voltage terminal V DD , the third gate and the fourth gate are electrically connected and connected to the same control voltage terminal V in .

[0207] One of the first metal electrodes 2014 on the first source and drain region 2012 is electrically connected to the second power terminal of the bidirectional power device, the other is electrically connected to one of the second metal electrodes 2024 and electrically connected to the substrate 200 of the bidirectional power device, the other of the second metal electrodes 2024 is connected to the first power terminal of the bidirectional power device, the first gate 2013 and the second gate 2023 are electrically connected to the control electrode 14 of the bidirectional power device, the anode metal 2033 is electrically connected to the substrate 200 of the bidirectional power device, and the cathode metal 2034 is electrically connected to the control electrode 14 of the bidirectional power device.

[0208] Reference Fig.12 and Fig.13 One of the third metal electrodes 3014 on the third source and drain region 3012 is grounded, the other is electrically connected to one of the fourth metal electrodes 3034 on the fourth source and drain region 3023 and the control electrode 14 of the bidirectional power device, and one of the fourth metal electrodes 3034 on the fourth source and drain region 3023 is connected to the voltage terminal V DD , the third gate and the fourth gate are electrically connected and connected to the same control voltage terminal V in .

[0209] One of the first metal electrodes 2014 on the first source and drain region 2012 is electrically connected to the second power terminal of the bidirectional power device, the other is electrically connected to the substrate 200 of the bidirectional power device, the first gate 2013 is electrically connected to the control electrode 14 of the bidirectional power device, the anode metal 2033 is electrically connected to the substrate 200 of the bidirectional power device, and the cathode metal 2034 is electrically connected to the control electrode 14 of the bidirectional power device.

[0210] Based on the above description, the embodiment of the present application uses the first substrate as the substrate to prepare the driver chip, and simultaneously prepares the bidirectional power device on the second substrate, which can achieve an efficient production process while ensuring that the performance and reliability of the driver chip and the bidirectional power device meet application requirements.

[0211] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A driver chip for driving a bidirectional power device and modulating the substrate potential of the bidirectional power device, wherein the bidirectional power device comprises a first power terminal, a second power terminal, a control terminal and a substrate potential terminal; characterized in that: The driving chip comprises: a driving circuit and a substrate potential modulation circuit; The driving circuit and the substrate potential modulation circuit are formed in the same substrate; The substrate potential modulation circuit receives signals from the control terminal, the first power terminal and / or the second power terminal, and is connected to the substrate potential terminal so that the voltage at the substrate potential terminal of the bidirectional power device is basically consistent with the lower voltage among the voltages at the control terminal, the first power terminal and the second power terminal.

2. The driver chip according to claim 1, characterized in that: The substrate potential modulation circuit includes a switch module, a first end of the switch module is electrically connected to the end with lower voltage between the first power end and the second power end, a second end of the switch module is electrically connected to the substrate potential end of the bidirectional power device, and a control end of the switch module is electrically connected to the control end of the bidirectional power device.

3. The driver chip according to claim 2, characterized in that: The switch module includes a first transistor, a first end of the first transistor is electrically connected to one of the first power end and the second power end of the bidirectional power device, a second end of the first transistor is electrically connected to the substrate potential end of the bidirectional power device, and a control end of the first transistor is electrically connected to the control end of the bidirectional power device.

4. The driver chip according to claim 3, characterized in that: The first transistor includes a first well region with a first doping type located in the substrate, a first source and drain region with a second doping type located in the first well region, and a first gate between the first source and drain regions; wherein the first gate is the control terminal of the first transistor.

5. The driver chip according to claim 3, characterized in that: The switch module also includes a second transistor, a first end of the second transistor is electrically connected to the other of the first power end and the second power end of the bidirectional power device, a second end of the second transistor is electrically connected to the substrate potential end of the bidirectional power device, and a control end of the second transistor is electrically connected to the control end of the bidirectional power device.

6. The driver chip according to claim 5, characterized in that: The second transistor includes a second well region with a first doping type located in the substrate, a second source and drain region with a second doping type located in the second well region, and a second gate arranged on the upper surface of the substrate and located between the source and drain regions, wherein the second gate is the control terminal of the second transistor.

7. The driver chip according to claim 5, characterized in that: The switch module further includes a diode, a cathode of the diode being electrically connected to the control end of the first transistor and / or the control end of the second transistor; and an anode of the diode being electrically connected to the substrate potential end of the bidirectional power device.

8. The driver chip according to claim 7, characterized in that: The diode includes a PN junction diode or a Schottky diode.

9. The driver chip according to claim 1, characterized in that: The driving circuit includes a third transistor and a fourth transistor, The second end of the third transistor is electrically connected to the first end of the fourth transistor, and is electrically connected to the substrate potential end and the control end of the bidirectional power device to drive the bidirectional power device; The control end of the third transistor is electrically connected to the control end of the fourth transistor.

10. A bidirectional power device, characterized in that: It comprises a driving chip as described in any one of claims 1 to 9, and a bidirectional power device, wherein the driving chip is used to drive the bidirectional power device and modulate the substrate potential of the bidirectional power device.

11. A method for manufacturing a driver chip, characterized in that: The method comprises providing a substrate; forming a driving circuit and a substrate potential modulation circuit in the substrate; The driving circuit is used to drive the bidirectional power device, and the substrate potential modulation circuit is used to modulate the substrate potential of the bidirectional power device; The bidirectional power device includes a first power terminal, a second power terminal, a control terminal and a substrate potential terminal; the substrate potential modulation circuit receives the control terminal and the signal of the first power terminal and / or the second power terminal, and is connected to the substrate potential terminal so that the substrate potential terminal of the bidirectional power device is basically consistent with the lower voltage of the voltage at the first power terminal and the second power terminal.

12. The method according to claim 11, characterized in that The substrate potential modulation circuit includes a first transistor and / or a second transistor; the driving circuit includes a third transistor and a fourth transistor; The forming of the driving circuit and the substrate potential modulation circuit in the substrate comprises: forming a first source-drain region and / or a second source-drain region, a third source-drain region and a fourth source-drain region in the substrate respectively and simultaneously; wherein the first source-drain region is the first end and the second end of the first transistor, the second source-drain region is the first end and the second end of the second transistor, the third source-drain region is the first end and the second end of the third transistor, and the fourth source-drain region is the first end and the second end of the fourth transistor; A first gate and / or a second gate, a third gate and a fourth gate are respectively and simultaneously formed on the upper surface of the substrate; wherein the first gate is the control end of the first transistor, the second gate is the control end of the second transistor, the third gate is the control end of the third transistor, and the fourth gate is the control end of the fourth transistor.

13. The method according to claim 12, characterized in that: The forming of the first source and drain region and / or the second source and drain region, the third source and drain region and the fourth source and drain region in the substrate respectively comprises: forming a first well region and / or a second well region, a third well region and a fourth well region in the substrate respectively; The first source and drain region is formed in the first well region, and / or the second source and drain region is formed in the second well region, the third source and drain region is formed in the third well region, and the fourth source and drain region is formed in the fourth well region respectively and simultaneously.

14. The method according to claim 13, characterized in that The type of doping ions in the first well region and the second well region is the same; The types of doping ions of the third well region and the fourth well region are opposite; The doping ions of the first source / drain region and the first well region are of opposite types; The types of doping ions of the second source / drain region and the second well region are opposite; The types of doping ions of the third source / drain region and the third well region are opposite; The fourth source and drain regions and the fourth well region have opposite doping ion types.

15. The method according to claim 14, characterized in that The substrate potential modulation circuit further includes a diode; While forming the first well region and / or the second well region, the third well region and the fourth well region in the substrate respectively, the method further comprises: forming a fifth well region in the substrate; While simultaneously forming the first source and drain region in the first well region, forming the second source and drain region in the second well region, forming the third source and drain region in the third well region, and forming the fourth source and drain region in the fourth well region, the method further comprises: A first doping region and / or a second doping region is formed in the fifth well region.

16. The method according to claim 15, characterized in that: The fifth well region has an opposite type of doping ions to the first well region and the second well region; The types of doping ions in the first doping region and the second doping region are opposite.

17. The method according to any one of claims 15 or 16, characterized in that: After simultaneously forming the first source and drain region in the first well region, and / or forming the second source and drain region in the second well region, forming the third source and drain region in the third well region, and forming the fourth source and drain region in the fourth well region, the method further comprises: A dielectric layer is formed on the upper surface of the substrate.

18. The method according to claim 17, characterized in that The forming of the first gate and / or the second gate, the third gate and the fourth gate on the upper surface of the substrate respectively and simultaneously comprises: The first gate and / or the second gate, the third gate and the fourth gate are formed on the upper surface of the dielectric layer respectively and simultaneously.

19. The method according to claim 18, characterized in that The method further comprises: forming a first metal electrode, a second metal electrode, a third metal electrode and a fourth metal electrode penetrating the dielectric layer on upper surfaces of the first source and drain region and / or the second source and drain region, the third source and drain region and the fourth source and drain region respectively and simultaneously; The first metal electrode is located on both sides of the first gate and is electrically connected to the first source and drain region; and / or the second metal electrode is located on both sides of the second gate and is electrically connected to the second source and drain region; the third metal electrode is located on both sides of the third gate and is electrically connected to the third source and drain region; the fourth metal electrode is located on both sides of the first gate and is electrically connected to the fourth source and drain region.

20. The method according to claim 19, characterized in that While simultaneously forming a first metal electrode, a second metal electrode, a third metal electrode and a fourth metal electrode penetrating the dielectric layer on the upper surfaces of the first source and drain region and / or the second source and drain region, the third source and drain region and the fourth source and drain region, the method further comprises: forming an anode metal and a cathode metal penetrating the dielectric layer on the upper surface of the fifth well region; The anode metal is formed on the upper surface of the first doping region and is electrically connected to the fifth well region, and / or the cathode metal is formed on the upper surface of the second doping region and is electrically connected to the fifth well region.

21. The method according to any one of claims 13 to 16, characterized in that: After simultaneously forming the first well region and / or the second well region in the substrate, and simultaneously forming the third well region and the fourth well region in the substrate, the method further includes: At the same time, an isolation region is formed between two adjacent well regions among the first well region and / or the second well region, the third well region and the fourth well region.

22. A method for manufacturing a bidirectional power device, characterized in that: The bidirectional power device comprises a driver chip as described in any one of claims 1 to 9, and a bidirectional power device; The method comprises: providing a first substrate and a second substrate respectively; The driving chip is prepared using the first substrate as a substrate, and the bidirectional power device is simultaneously prepared on the second substrate.

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