Second-order passive noise shaping successive approximation analog-to-digital converter and noise shaping method

Abstract

The invention provides a second-order passive noise shaping successive approximation analog-to-digital converter, a noise shaping method, equipment and a computer readable storage medium, and the method comprises the steps: controlling a capacitive digital-to-analog conversion circuit to carry out the voltage sampling of a current conversion period through a time sequence control circuit according to a conversion result of a previous conversion period in each conversion period; in the period, on one hand, the multi-input comparator carries out conversion and output according to the output voltage of the capacitive digital-to-analog conversion circuit and the integral voltage of the previous conversion period output by the passive loop filter circuit, and on the other hand, the output voltage of the passive loop filter circuit is converted and output according to the output voltage of the capacitive digital-to-analog conversion circuit. And on the other hand, the residual error sampling unit is controlled to collect residual error voltage of the current conversion period, and then the first integral unit and the second integral unit are respectively charged in sequence to obtain integral voltage of the current conversion period for conversion output of the next conversion period. Therefore, KT / C noise and gain loss during margin sampling can be eliminated, meanwhile, comparator noise is reduced, the signal-to-noise ratio of the analog-to-digital converter is increased, the spurious-free dynamic range of the analog-to-digital converter is widened, and in addition, due to the fact that passive filtering is adopted, power consumption and design complexity of the whole analog-to-digital converter are low.

Description

Technical Field

[0001] The present application relates to the technical field of successive approximation analog-to-digital converters, and in particular to a second-order passive noise shaping successive approximation analog-to-digital converter, a noise shaping method, a noise shaping device, and a readable storage medium. Background Art

[0002] Analog-to-digital converters are mainly divided into Nyquist rate analog-to-digital converters and oversampling analog-to-digital converters. One of the most representative types of Nyquist rate analog-to-digital converters is the successive approximation analog-to-digital converter (SAR DAC for short). The most widely used oversampling analog-to-digital converter is the Σ-Δ ADC. Due to the existence of comparator noise and DAC settling error, SAR ADC is widely used in medium speed and medium precision fields. Σ-Δ ADC has high precision, but its internal active loop filter requires an integrator, and the core unit in the integrator is an operational amplifier. The operational amplifier not only has a large power consumption, but also reduces the conversion rate of the system. Therefore, Σ-Δ ADC is widely used in low speed and high precision fields.

[0003] The noise shaping successive approximation analog-to-digital converter applies the oversampling technology and noise shaping technology in Σ-Δ to SAR DAC. It has the advantages of medium speed and high power efficiency of SARDAC and the advantages of high precision of Σ-Δ. Some of the existing noise shaping successive approximation analog-to-digital converters use active loop filters, which still have relatively high power consumption; while some use passive loop filter structures. Although they can effectively reduce the complexity of system design and power consumption, they usually only achieve first-order noise shaping. When using switched capacitors to sample the residual voltage, KT / C noise and gain loss will be introduced. At the same time, the passive loop filter of this structure requires a multi-input pair comparator, which increases the comparator noise, so the noise shaping effect is not very ideal. Summary of the invention

[0004] The present application provides a second-order passive noise shaping successive approximation analog-to-digital converter, a noise shaping method, a noise shaping device and a readable storage medium with low power consumption and good noise shaping effect.

[0005] A second-order passive noise shaping successive approximation analog-to-digital converter, comprising a capacitive digital-to-analog conversion circuit, a multi-input comparator, a SAR logic control circuit, two sets of passive loop filter circuits and a timing control circuit;

[0006] The input end of the capacitive digital-to-analog conversion circuit is connected to the SAR logic control circuit, the first differential output end of the capacitive digital-to-analog conversion circuit is connected to the first input end of the multi-input comparator, and the second differential output end of the capacitive digital-to-analog conversion circuit is connected to the second input end of the multi-input comparator;

[0007] Each of the passive loop filter circuits comprises a residual sampling unit, a first integration unit and a second integration unit; each of the residual sampling units is connected to the first differential output terminal and the second differential output terminal in a one-to-one correspondence; the first integration unit and the second integration unit are connected to the residual sampling units of the same group, and are connected to the multi-input comparator;

[0008] The timing control circuit is respectively connected to the SAR logic control circuit, the multi-input comparator and each of the passive loop filter circuits, and is used to drive the SAR logic control circuit according to the conversion result of the previous conversion cycle to control the capacitive digital-to-analog conversion circuit to perform voltage sampling of the current conversion cycle, and generate an output voltage that successively approximates the voltage to be measured based on the sampled voltage until the residual voltage of the current conversion cycle is generated;

[0009] The multi-input comparator is used to convert and output according to the output voltage of the capacitive digital-to-analog conversion circuit and the integrated voltage of the previous conversion cycle output by the passive loop filter circuit to obtain the conversion result of the current conversion cycle;

[0010] The timing control circuit is also used to control the residual sampling unit to collect the residual voltage of the current conversion cycle, and to charge the first integration unit and the second integration unit respectively based on the residual voltage of the current conversion cycle to obtain the integration voltage of the current conversion cycle for use in the conversion output of the next conversion cycle.

[0011] In one embodiment, the capacitance value of the residual sampling unit is equal to one third of the capacitance value of the capacitive digital-to-analog conversion circuit; the capacitance value of the first integration unit and the capacitance value of the second integration unit are respectively equal to the capacitance value of the capacitive digital-to-analog conversion circuit.

[0012] In one embodiment, each of the residual sampling units includes a sampling capacitor and a sampling switch; the first end of the sampling switch is connected to the target differential output end, and the second end of the sampling switch is respectively connected to the first end of the sampling capacitor, the first integration unit and the second integration unit; the second end of the sampling capacitor is connected to the ground end; wherein the target differential output end is the first differential output end or the second differential output end.

[0013] In one embodiment, the first integration unit includes a first switch and a first integration capacitor; the second integration unit includes a second switch and a second integration capacitor; the first end of the first switch and the first end of the second switch are respectively connected to the first end of the sampling capacitor; the second end of the first switch and the first end of the first integration capacitor are respectively connected to the multi-input comparator; the second end of the first integration capacitor is connected to the ground; the second end of the second switch and the first end of the second integration capacitor are respectively connected to the multi-input comparator; the second end of the second integration capacitor is connected to the ground.

[0014] In one embodiment, the analog-to-digital converter further includes a third switch; a first end of the third switch is connected to the residual sampling unit, and a second end of the third switch is connected to the ground, and the timing control circuit is further used to control the third switch to close before controlling the residual sampling unit to collect the residual voltage of the current conversion cycle, so that the residual sampling unit is discharged.

[0015] In one embodiment, the timing control circuit controls the capacitive digital-to-analog conversion circuit to perform voltage sampling in the current conversion cycle at the moment when charging of the first integration unit in the previous conversion cycle ends.

[0016] A noise shaping method is applied to a second-order passive noise shaping successive approximation analog-to-digital converter, wherein the second-order passive noise shaping successive approximation analog-to-digital converter comprises a capacitive digital-to-analog conversion circuit, a multi-input comparator, a SAR logic control circuit and two groups of passive loop filtering circuits; the capacitive digital-to-analog conversion circuit is connected to the SAR logic control circuit, the first differential output end of the capacitive digital-to-analog conversion circuit is connected to the first input end of the multi-input comparator, and the second differential output end of the capacitive digital-to-analog conversion circuit is connected to the second input end of the multi-input comparator; each of the passive loop filtering circuits comprises a residual sampling unit, a first integration unit and a second integration unit; each of the residual sampling units is connected to the first differential output end and the second differential output end in a one-to-one correspondence; the first integration unit and the second integration unit are respectively connected to the residual sampling unit of the same group and to the multi-input comparator;

[0017] The noise shaping method comprises: driving the SAR logic control circuit according to the conversion result of the previous conversion cycle to control the capacitive digital-to-analog conversion circuit to perform voltage sampling of the current conversion cycle, and generating an output voltage that successively approximates the voltage to be measured based on the sampled voltage until the residual voltage of the current conversion cycle is generated;

[0018] The multi-input comparator is used to convert and output according to the output voltage of the capacitive digital-to-analog conversion circuit and the integrated voltage of the previous conversion cycle output by the passive loop filter circuit to obtain the conversion result of the current conversion cycle;

[0019] The noise shaping method also includes: controlling the residual sampling unit to collect the residual voltage of the current conversion cycle, and charging the first integration unit and the second integration unit in sequence based on the residual voltage of the current conversion cycle, so as to obtain the integration voltage of the current conversion cycle for conversion output in the next conversion cycle.

[0020] In one embodiment, the capacitance value of the residual sampling unit is equal to one third of the capacitance value of the capacitive digital-to-analog conversion circuit; the capacitance value of the first integration unit and the capacitance value of the second integration unit are respectively equal to the capacitance value of the capacitive digital-to-analog conversion circuit.

[0021] In one embodiment, each of the residual sampling units includes a sampling capacitor and a sampling switch; the first end of the sampling switch is connected to the target differential output end, and the second end of the sampling switch is respectively connected to the first end of the sampling capacitor, the first integration unit and the second integration unit; the second end of the sampling capacitor is connected to the ground end; wherein the target differential output end is the first differential output end or the second differential output end; the controlling the residual sampling unit to collect the residual voltage of the current conversion cycle includes:

[0022] The sampling switch is controlled to be closed so that the sampling capacitor collects the residual voltage of the current conversion cycle.

[0023] In one embodiment, the first integration unit includes a first switch and a first integration capacitor; the second integration unit includes a second switch and a second integration capacitor; the first end of the first switch and the first end of the second switch are respectively connected to the first end of the sampling capacitor; the second end of the first switch and the first end of the first integration capacitor are respectively connected to the multi-input comparator; the second end of the first integration capacitor is connected to the ground; the second end of the second switch and the first end of the second integration capacitor are respectively connected to the multi-input comparator; the second end of the second integration capacitor is connected to the ground; the first integration unit and the second integration unit are respectively charged based on the residual voltage of the current conversion cycle, including:

[0024] Opening the sampling switch and closing the first switch so that the sampling capacitor charges the first integration capacitor;

[0025] The first switch is opened, and the second switch is closed, so that the discharged sampling capacitor charges the second integrating capacitor.

[0026] In one embodiment, the analog-to-digital converter further includes a third switch; a first end of the third switch is connected to the residual sampling unit, and a second end of the third switch is connected to the ground end, and the noise shaping method further includes:

[0027] Before controlling the residual sampling unit to collect the residual voltage of the current conversion cycle, the third switch is controlled to be closed so that the residual sampling unit is discharged.

[0028] In one embodiment, controlling the capacitive digital-to-analog conversion circuit to perform voltage sampling in the current conversion cycle includes: controlling the capacitive digital-to-analog conversion circuit to perform voltage sampling in the current conversion cycle at the moment when charging of the first integration unit in the previous conversion cycle ends.

[0029] A noise shaping device comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above methods when executing the computer program.

[0030] A computer-readable storage medium stores a computer program, which implements the steps of any of the above methods when executed by a processor.

[0031] In the above method, in each conversion cycle, the timing control circuit controls the capacitor type digital-to-analog conversion circuit to perform voltage sampling of the current conversion cycle according to the conversion result of the previous conversion cycle, and generates an output voltage that is close to the voltage to be measured based on the sampled voltage until the residual voltage of the current conversion cycle is generated. During this period, on the one hand, the multi-input comparator performs conversion and output according to the output voltage of the capacitor type digital-to-analog conversion circuit and the integral voltage of the previous conversion cycle output by the passive loop filter circuit to obtain the conversion result of the current conversion cycle, and on the other hand, the residual sampling unit is controlled to collect the residual voltage of the current conversion cycle, and then the first integral unit and the second integral unit are charged respectively, to obtain the integral voltage of the current conversion cycle for the conversion output of the next conversion cycle. In this way, the KT / C noise and gain loss during the residual sampling can be eliminated, and the comparator noise can be reduced at the same time, and the signal-to-noise ratio and spurious-free dynamic range of the analog-to-digital converter are improved. In addition, due to the use of passive filtering, the power consumption and design complexity of the entire analog-to-digital converter are also low. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the structure of a second-order passive noise shaping successive approximation analog-to-digital converter according to an embodiment of the present application;

[0033] Figure 2 A schematic diagram of sampling and integrating the residual voltage for this application;

[0034] Figure 3 A schematic structural diagram of a second-order passive noise shaping successive approximation analog-to-digital converter according to another embodiment of the present application;

[0035] Figure 4 This is a timing control diagram of the noise shaping process of this application;

[0036] Figure 5 A flowchart of a noise shaping process according to an embodiment of the present application;

[0037] Figure 6 A schematic diagram of the structure of a computer device for implementing a noise shaping method according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. The connection can be a direct connection or an indirect connection.

[0041] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0042] Figure 1 : is a structural block diagram of a second-order passive noise shaping successive approximation analog-to-digital converter according to an embodiment of the present application, such as Figure 1As shown, the analog-to-digital converter includes a capacitive digital-to-analog conversion circuit 110, a multi-input comparator 120, a SAR logic control circuit 130, two groups of passive loop filter circuits 140 and a timing control circuit 150; the capacitive digital-to-analog conversion circuit 110 is connected to the SAR logic control circuit, the first differential output end of the capacitive digital-to-analog conversion circuit 110 is connected to the first input end of the multi-input comparator 120, and the second differential output end of the capacitive digital-to-analog conversion circuit 110 is connected to the second input end of the multi-input comparator 120; each passive loop filter circuit 140 includes a residual sampling unit 141, a first integration unit 142 and a second integration unit 143; each residual sampling unit 141 is respectively connected to the first differential output end and the second differential output end in a one-to-one correspondence; the first integration unit 142 and the second integration unit 143 are respectively connected to the residual sampling unit 141 of the same group and to the multi-input comparator 120; the timing control circuit 150 is respectively connected to the S The AR logic control circuit 130, the multi-input comparator 120 and each passive loop filter circuit 140 are connected, and are used to drive the SAR logic control circuit 130 according to the conversion result of the previous conversion cycle, so as to control the capacitive digital-to-analog conversion circuit 110 to perform voltage sampling of the current conversion cycle, and generate an output voltage that successively approaches the voltage to be measured based on the sampled voltage until the residual voltage of the current conversion cycle is generated; the multi-input comparator is used to convert and output according to the output voltage of the capacitive digital-to-analog conversion circuit 110 and the integral voltage of the previous conversion cycle output by the passive loop filter circuit 140, so as to obtain the conversion result of the current conversion cycle; the timing control circuit 150 is also used to control the residual sampling unit 141 to collect the residual voltage of the current conversion cycle, and based on the residual voltage of the current conversion cycle, successively charge the first integral unit 142 and the second integral unit 143 respectively, so as to obtain the integral voltage of the current conversion cycle, so as to be used for the conversion output of the next conversion cycle.

[0043] Understandable, reference Figure 1 As shown, the capacitive digital-to-analog conversion circuit 110 is a differential structure, which includes a plurality of capacitors ( Figure 1 The input end of the capacitive digital-to-analog conversion circuit 110 includes the input end of the positive capacitor array and the input end of the negative capacitor array. In the sampling phase, the switch Φ s The voltage to be measured (V in / V ip In the conversion stage, the comparison result of the multi-input comparator 120 received by the SAR logic control circuit 130 can be used to measure the voltage V in / V ip Continue to search the binary interval and compare it with V ref / 2, V ref / 2±V ref / 4, Vref / 2±V ref / 4±V ref / 8……to compare, thus gradually approaching the voltage to be measured V in and V ip The interval where the equivalent voltage to be measured V is finally obtained in and V ip digital signal.

[0044] The analog-to-digital converter can be in a periodic working mode, wherein each conversion cycle may include two stages: a conversion stage and a residual integration stage; taking the current conversion cycle as an example, in the conversion stage, the passive loop filter circuit 140 is in a non-working state, that is, the residual sampling unit 141, the first integration unit 142 and the second integration unit 143 thereof are all non-working, and the timing control circuit 150 enters a new conversion cycle after receiving the conversion result of the previous conversion cycle, that is, starts to drive the SAR logic control circuit, and then the SAR logic control circuit first controls the capacitors in each capacitor array of the capacitive digital-to-analog conversion circuit 110 to receive the voltage to be measured at one end and the common-mode voltage at the other end to realize voltage sampling. After the sampling is completed, the switch Φ sDisconnect, and shift by adjusting each switch in the capacitor array to adjust the output voltage of the capacitor digital-to-analog conversion circuit 110, so that the output voltage approaches the voltage to be measured in each shift process, until the shift is completed to generate the residual voltage of the current conversion cycle. Assume that the output voltage of the first differential output terminal of the capacitor digital-to-analog conversion circuit 110 in the process of successive approximation is VCP, and the output voltage of the second differential output terminal is VCN, wherein during the shift period, the multi-input comparator converts and outputs according to the current output voltage and the integral voltage of the previous conversion cycle, and then drives the SAR logic control circuit to control the shift of the next bit through the timing control circuit 150, until the shift of the current conversion cycle is completed, the multi-input comparator 120 converts and outputs according to the output voltage of the capacitor digital-to-analog conversion circuit 110 after the last shift and the integral voltage of the previous conversion cycle output by the passive loop filter circuit 140, and finally the conversion result of the current conversion cycle can be obtained, and the timing control circuit 150 receives the conversion result of the current conversion cycle and then starts the next round of conversion cycle, and so on. The integral voltage of the previous conversion cycle is the integral voltage obtained by charging the first integral unit 142 and the second integral unit 143 respectively after the residual sampling unit 141 collects the residual voltage in the previous conversion cycle. Then, the residual integration stage is entered. After the residual voltage is obtained, the timing control circuit 150 controls the residual sampling unit 141 to collect the residual voltage of the current conversion cycle, and charges the first integral unit 142 and the second integral unit 143 respectively based on the residual voltage of the current conversion cycle, so as to obtain the integral voltage of the current conversion cycle for the conversion stage of the next conversion cycle. The output voltage of the first differential output terminal is VCP, and the output voltage of the second differential output terminal is VCN.

[0045] The following calculation proves that the analog-to-digital converter has a good noise shaping effect.

[0046] The integrated voltage includes a first integrated voltage after charging the first integration unit 142, and a second integrated voltage after charging the second integration unit 143. The multi-input comparator 120 can be a six-input comparator. The terminal connected to the first integration unit 142 of the comparator is set to GM_INT1, the terminal connected to the second integration unit 143 is set to GM_INT2, and the terminal connected to the capacitive digital-to-analog converter is set to GM_VIN. The output ratio between the terminals is set to GM_INT1 = 4GM_VIN; GM_INT2 = 16GM_VIN, then there is an output D out (z) is set to:

[0047] D out (z) = V in (z)+4V INT1 (z)+16V INT2 (z)+Q(z)

[0048] Among them, V in (z) is the voltage V to be measured converted to the complex frequency domain in , V INT1 (z) is the first integrated voltage converted to the complex frequency domain, V INT2 (z) is the second integrated voltage converted to the complex frequency domain, Q(z) includes the quantization error and the comparator equivalent input noise. Combining the above formula, the residual voltage V in the complex frequency domain res (z) can be expressed as:

[0049] V res (z) = V in (z)-D out (z)

[0050] =-4V INT1 (z)-16V INT2 (z)-Q(z)

[0051] refer to Figure 2 As shown, let the residual voltage be V res , the total capacitance of the positive and negative capacitor matrix is ​​C DAC For the convenience of calculation, let the capacitance value of the residual sampling unit 141 be The capacitance value of the first integration unit 142 and the capacitance value of the second integration unit 143 are both C DAC ; The opening and closing of switch S1 represents the control of charging the residual sampling unit 141, the opening and closing of switch S2 represents the control of charging the first integration unit 142, and the opening and closing of switch S3 represents the control of charging the second integration unit 143; when the residual sampling unit 141 collects the residual voltage (that is, only switch S1 is closed), the charge forming the residual voltage is redistributed between the capacitor matrix and the residual sampling unit 141, and the voltage sampled by the residual sampling unit 141 is represented by V res ', then the residual sampling unit 141 charges the first integration unit 142 (ie, only the switch s2 is closed), forming a voltage V res The charge of ' is redistributed between the residual sampling unit 141 and the first integration unit 142, and the voltage of the first integration unit 142 after charging is expressed as V INTI

[0052] Then the residual sampling unit 141 charges the second integration unit 143 (that is, only the switch s3 is closed), forming a voltage V res The charge of the residual sampling unit 141 is redistributed between the residual sampling unit 141 and the first integration unit 142, and the voltage of the second integration unit 143 after charging is expressed as V INT2 , assuming that the initial VINT1 and VINT2 are both 0, based on the charge conservation principle, the nth conversion cycle can be obtained as:

[0053]

[0054] After Z transformation, we can get:

[0055]

[0056] After sorting, we can get:

[0057]

[0058] Similarly, we can get:

[0059]

[0060] After Z transformation, we can get:

[0061]

[0062] After sorting, we can get:

[0063]

[0064] Also because

[0065] V res (z) = V in (z)-D out (z)=-4V INT1 (z)-16V INT2 (z)-Q(z)

[0066] Use V res (z) represents V INT1 (z) and V INT2 (z) can be obtained:

[0067] V res (z)=-4V INT1 (z)-16V INT2 (z)-Q(z)

[0068]

[0069] Solved

[0070]

[0071] Substitution

[0072] D out (z) = V in (z)-V res (z)

[0073] Available

[0074]

[0075] The noise transfer function (NTF) has two zeros located at Z=0.75. When Z=1, NTF=1 / 16. Therefore, based on the structure of the above analog-to-digital converter, by reasonably setting the residual sampling unit 141, the first integration unit 142 and the capacitance value of the first integration unit 142, theoretically, -24dB noise suppression can be achieved.

[0076] In the above method, in each conversion cycle, the timing control circuit 150 controls the capacitive digital-to-analog conversion circuit 110 to perform voltage sampling of the current conversion cycle according to the conversion result of the previous conversion cycle, and generates an output voltage that is close to the voltage to be measured based on the sampled voltage until the residual voltage of the current conversion cycle is generated. Then, on the one hand, the multi-input comparator performs conversion and output according to the output voltage of the capacitive digital-to-analog conversion circuit 110 and the integral voltage of the previous conversion cycle output by the passive loop filter circuit 140 to obtain the conversion result of the current conversion cycle. On the other hand, the timing control circuit 150 controls the residual sampling unit 141 to collect the current conversion cycle. The residual voltage of the current conversion cycle is obtained, and the first integration unit 142 and the second integration unit 143 are charged in sequence based on the residual voltage of the current conversion cycle to obtain the integration voltage of the current conversion cycle for use in the conversion output of the next conversion cycle. In this way, by performing a second-order integration of the residual voltage at the end of each conversion cycle and using it for the conversion output of the next conversion cycle, the KT / C noise and gain loss during residual sampling can be eliminated, while the comparator noise is reduced, and the signal-to-noise ratio and spurious-free dynamic range of the analog-to-digital converter are improved. In addition, since the passive loop filter circuit 140 is used, the power consumption and design complexity of the entire analog-to-digital converter are also low.

[0077] In one embodiment, the capacitance value of the residual sampling unit 141 is equal to one third of the capacitance value of the capacitive digital-to-analog conversion circuit 110 ; the capacitance value of the first integration unit 142 and the capacitance value of the second integration unit 143 are respectively equal to the capacitance value of the capacitive digital-to-analog conversion circuit 110 .

[0078] It can be understood that, assuming that the capacitance value of the capacitive digital-to-analog conversion circuit 110 is C DAC , then the capacitance value of the residual sampling unit 141 is The capacitance value of the first integration unit 142 and the capacitance value of the second integration unit 143 are both C DAC From the calculation process of the above embodiment, it can be obtained that the final noise suppression can reach -24dB. By setting the capacitance value in this way, the overall noise of the analog-to-digital converter can be greatly reduced.

[0079] In one embodiment, Figure 3As shown, each residual sampling unit 141 includes a sampling capacitor Cs and a sampling switch S0; the first end of the sampling switch S0 is connected to the target differential output end, and the second end of the sampling switch S0 is respectively connected to the first end of the sampling capacitor Cs, the first integration unit 142 and the second integration unit 143; the second end of the sampling capacitor Cs is connected to the ground end; wherein the target differential output end is the first differential output end or the second differential output end.

[0080] It can be understood that the number of the residual sampling units 141 is two. For the residual sampling unit 141 connected to the first differential output terminal, the first end of the sampling switch S0 therein is connected to the first differential output terminal, and for the residual sampling unit 141 connected to the second differential output terminal, the first end of the sampling switch S0 therein is connected to the second differential output terminal.

[0081] By controlling the sampling switch S0 to close, the sampling capacitor Cs can be charged, that is, the residual sampling unit 141 can be charged. The residual sampling unit 141 has a simple structure and is easy to control.

[0082] In one embodiment, the first integration unit 142 includes a first switch S1 and a first integration capacitor C1; the second integration unit 143 includes a second switch S2 and a second integration capacitor C2; the first end of the first switch S1 and the first end of the second switch S2 are respectively connected to the first end of the sampling capacitor Cs; the second end of the first switch S1 and the first end of the first integration capacitor C1 are respectively connected to the multi-input comparator 120; the second end of the first integration capacitor C1 is connected to the ground; the second end of the second switch S2 and the first end of the second integration capacitor C2 are respectively connected to the multi-input comparator 120; the second end of the second integration capacitor C2 is connected to the ground.

[0083] It can be understood that the first integrating unit 142 and the second integrating unit 143 may include a switch and a capacitor respectively, and the charging of the capacitor is controlled by opening and closing the switch, which has a simple structure and is easy to control.

[0084] In one embodiment, the analog-to-digital converter further includes a third switch S3; a first end of the third switch S3 is connected to the residual sampling unit 141, and a second end of the third switch S3 is connected to the ground. The timing control circuit 150 is also used to control the third switch S3 to close before controlling the residual sampling unit 141 to collect the residual voltage of the current conversion cycle, so that the residual sampling unit 141 is discharged.

[0085] Specifically, when the residual sampling unit 141 includes a sampling capacitor Cs and a sampling switch S0, a first end of the third switch S3 is connected to a first end of the sampling capacitor Cs, and a second end of the third switch S3 is connected to a ground end. The timing control circuit 150 is further configured to close the third switch S3 before controlling the residual sampling unit 141 to collect the residual voltage of the current conversion cycle, so as to discharge the sampling capacitor Cs. This can prevent the sampling capacitor Cs from having a residual voltage of the previous conversion cycle, thereby affecting the integral voltage of the current conversion cycle.

[0086] In one embodiment, the timing control circuit 150 controls the capacitive digital-to-analog conversion circuit 110 to perform voltage sampling in the current conversion cycle at the moment when the charging of the first integration unit in the previous conversion cycle ends.

[0087] It can be understood that since the capacitive digital-to-analog conversion circuit 110 performs voltage sampling at the beginning of each conversion cycle, and since the voltage sampling process and the integration process of the residual voltage do not interfere with each other, in order to shorten the overall conversion time, the timing control circuit 150 can control the charging of the first integration unit 142 using the residual voltage to end, and then start the voltage sampling of the next conversion cycle.

[0088] Specifically, the first switch S1 is used to control the charging of the first integration unit 142, the second switch S2 is used to control the charging of the second integration unit 143, and the switch Φ s The capacitor type digital-to-analog conversion circuit 110 is controlled to realize voltage acquisition, and the switch Φ s The closing time can be referred to Figure 4 The time t1 shown is the charging end time of the first integration unit 142. In this way, the capacitive digital-to-analog conversion circuit 110 has completed the voltage acquisition of the next conversion cycle when the charging of the second integration unit 143 ends, thus saving the overall conversion time of the analog-to-digital converter.

[0089] The embodiment of the present invention also provides a noise shaping method, which is applied to a second-order passive noise shaping successive approximation analog-to-digital converter. The second-order passive noise shaping successive approximation analog-to-digital converter includes a capacitive digital-to-analog conversion circuit 110, a multi-input comparator 120, a SAR logic control circuit 130 and two groups of passive loop filter circuits 140; the capacitive digital-to-analog conversion circuit 110 is connected to the SAR logic control circuit, the first differential output end of the capacitive digital-to-analog conversion circuit 110 is connected to the first input end of the multi-input comparator 120, and the second differential output end of the capacitive digital-to-analog conversion circuit 110 is connected to the second input end of the multi-input comparator 120; each passive loop filter circuit 140 includes a residual sampling unit 141, a first integration unit 142 and a second integration unit 143; each residual sampling unit 141 is connected to the first differential output end and the second differential output end in a one-to-one correspondence; the first integration unit 142 and the second integration unit 143 are connected to the first differential output end and the second differential output end in a one-to-one correspondence; 43 are respectively connected to the residual sampling unit 141 of the same group, and are connected to the multi-input comparator 120; the SAR logic control circuit is driven according to the conversion result of the previous conversion cycle to control the capacitive digital-to-analog conversion circuit 110 to perform voltage sampling of the current conversion cycle, and based on the sampled voltage, an output voltage that successively approximates the voltage to be measured is generated until the residual voltage of the current conversion cycle is generated; the multi-input comparator is used to convert and output according to the output voltage of the capacitive digital-to-analog conversion circuit 110 and the integral voltage of the previous conversion cycle output by the passive loop filter circuit 140, so as to obtain the conversion result of the current conversion cycle; the noise shaping method also includes: controlling the residual sampling unit 141 to collect the residual voltage of the current conversion cycle, and charging the first integral unit 142 and the second integral unit 143 respectively based on the residual voltage of the current conversion cycle, so as to obtain the integral voltage of the current conversion cycle for the conversion output of the next conversion cycle.

[0090] It can be understood that the noise shaping method can be implemented by the timing control circuit 150, and the timing control circuit 150 can be provided inside the second-order passive noise shaping successive approximation analog-to-digital converter or provided by an external device.

[0091] The capacitive digital-to-analog conversion circuit 110 is a differential structure, which includes a plurality of capacitors ( Figure 1 The input end of the capacitive digital-to-analog conversion circuit 110 includes the input end of the positive capacitor array and the input end of the negative capacitor array. One end of each capacitor in the positive capacitor array is connected in common as the input end of the positive capacitor array, which can be switched between the switch Φ s The voltage to be measured (V ip / V in ); through the control of each switch, with the comparison result of the multi-input comparator 120 received by the SAR logic control circuit 130, the voltage to be measured V inContinue to search the binary interval and compare it with V ref / 2, V ref / 2±V ref / 4, V ref / 2±V ref / 4±V ref / 8……to compare, thus gradually approaching the voltage to be measured V in and V ip The interval where the equivalent voltage to be measured V is finally obtained in and V ip digital signal.

[0092] The analog-to-digital converter may be in a periodic working mode, wherein each conversion cycle may include two stages: a conversion stage and a residual integration stage; taking the current conversion cycle as an example, in the conversion stage, the passive loop filter circuit 140 is in a non-working state, that is, the residual sampling unit 141, the first integration unit 142 and the second integration unit 143 thereof are all non-working, and after receiving the conversion result of the previous conversion cycle, a new conversion cycle is entered, that is, the SAR logic control circuit is started to be driven, and then the SAR logic control circuit first controls one end of the capacitor in each capacitor array of the capacitive digital-to-analog conversion circuit 110 to receive the voltage to be measured and the other end to receive the common-mode voltage to realize voltage sampling, and after the sampling is completed, the switch Φ sDisconnect, shift by adjusting each switch in the capacitor array to adjust the output voltage of the capacitive digital-to-analog conversion circuit 110, so that the output voltage gradually approaches the voltage to be measured during each shift process, until the shift is completed to generate the residual voltage of the current conversion cycle, assuming that the output voltage of the first differential output terminal of the capacitive digital-to-analog conversion circuit 110 during the successive approximation process is VCP, and the output voltage of the second differential output terminal is VCN. During the shift, the multi-input comparator performs conversion and output according to the current output voltage and the integral voltage of the previous conversion cycle, and then drives the SAR logic control circuit to control the shift of the next bit, until the shift of the current conversion cycle is completed, the conversion result of the current conversion cycle can be obtained, and the next round of conversion cycle is started after the conversion result of the current conversion cycle is received, and so on. The multi-input comparator 120 converts and outputs the output voltage of the capacitive digital-to-analog conversion circuit 110 and the integrated voltage of the previous conversion cycle output by the passive loop filter circuit 140 to obtain the conversion result of the current conversion cycle; wherein, the integrated voltage of the previous conversion cycle is the integrated voltage obtained by the residual sampling unit 141 after the residual voltage is collected in the previous conversion cycle, and the first integration unit 142 and the second integration unit 143 are respectively charged. Then, the residual integration stage is entered. After the residual voltage is obtained, the residual sampling unit 141 is controlled to collect the residual voltage of the current conversion cycle, and the first integration unit 142 and the second integration unit 143 are respectively charged based on the residual voltage of the current conversion cycle to obtain the integrated voltage of the current conversion cycle, which is used for the conversion stage of the next conversion cycle.

[0093] The noise shaping results achieved by the above method can be referred to Figure 1 The analysis of the embodiments will not be repeated here.

[0094] In the above method, in each conversion cycle, the capacitive digital-to-analog conversion circuit 110 is controlled to perform voltage sampling of the current conversion cycle according to the conversion result of the previous conversion cycle, and an output voltage that is close to the voltage to be measured is generated based on the sampled voltage until the residual voltage of the current conversion cycle is generated. Then, on the one hand, the multi-input comparator performs conversion and output according to the output voltage of the capacitive digital-to-analog conversion circuit 110 and the integral voltage of the previous conversion cycle output by the passive loop filter circuit 140 to obtain the conversion result of the current conversion cycle. On the other hand, the residual sampling unit 141 is controlled to collect the residual voltage of the current conversion cycle, and based on The residual voltage of the current conversion cycle charges the first integration unit 142 and the second integration unit 143 respectively to obtain the integration voltage of the current conversion cycle for use in the conversion output of the next conversion cycle. In this way, by performing a second-order integration of the residual voltage at the end of each conversion cycle and using it for the conversion output of the next conversion cycle, the KT / C noise and gain loss during residual sampling can be eliminated, while the comparator noise is reduced, and the signal-to-noise ratio and spurious-free dynamic range of the analog-to-digital converter are improved. In addition, since a passive loop filter circuit 140 is used, the power consumption and design complexity of the entire analog-to-digital converter are also low.

[0095] In one embodiment, the capacitance value of the residual sampling unit 141 is equal to one third of the capacitance value of the capacitive digital-to-analog conversion circuit 110 ; the capacitance value of the first integration unit 142 and the capacitance value of the second integration unit 143 are respectively equal to the capacitance value of the capacitive digital-to-analog conversion circuit 110 .

[0096] According to Figure 1 It can be seen from the analysis results of the embodiment that the overall noise of the analog-to-digital converter can be greatly reduced by setting the numerical value of the capacitance.

[0097] In one embodiment, each residual sampling unit 141 includes a sampling capacitor Cs and a sampling switch S0; the first end of the sampling switch S0 is connected to the target differential output end, and the second end of the sampling switch S0 is respectively connected to the first end of the sampling capacitor Cs, the first integration unit 142 and the second integration unit 143; the second end of the sampling capacitor Cs is connected to the ground end; wherein the target differential output end is the first differential output end or the second differential output end; controlling the residual sampling unit 141 to collect the residual voltage of the current conversion cycle includes: controlling the sampling switch S0 to be closed so that the sampling capacitor Cs collects the residual voltage of the current conversion cycle.

[0098] It can be understood that the number of the residual sampling units 141 is two. For the residual sampling unit 141 connected to the first differential output terminal, the first end of the sampling switch S0 therein is connected to the first differential output terminal, and for the residual sampling unit 141 connected to the second differential output terminal, the first end of the sampling switch S0 therein is connected to the second differential output terminal.

[0099] Among them, the timing control of the sampling switch S0 can refer to Figure 4 , which can be closed after the next clock cycle after the multi-input comparator 120 completes the comparison of each bit data of the capacitive digital-to-analog conversion circuit 110 (taking 6 bits as an example in the figure) and generates the residual voltage of the current conversion cycle. In addition, Figure 4 EN is an enable signal for starting the timing control, CLK is a reference clock signal, and CLK_COMP is a clock signal for driving the multi-input comparator 120 to perform comparison.

[0100] By controlling the sampling switch S0 to close, the sampling capacitor Cs can be charged, that is, the residual sampling unit 141 can be charged. The residual sampling unit 141 has a simple structure and is easy to control.

[0101] In one embodiment, the first integration unit 142 includes a first switch S1 and a first integration capacitor C1; the second integration unit 143 includes a second switch S2 and a second integration capacitor C2; the first end of the first switch S1 and the first end of the second switch S2 are respectively connected to the first end of the sampling capacitor Cs; the second end of the first switch S1 and the first end of the first integration capacitor C1 are respectively connected to the multi-input comparator 120; the second end of the first integration capacitor C1 is connected to the ground; the second end of the second switch S2 and the first end of the second integration capacitor C2 are respectively connected to the multi-input comparator 120; the second end of the second integration capacitor C2 is connected to the ground; the first integration unit 142 and the second integration unit 143 are respectively charged based on the residual voltage of the current conversion cycle, including: disconnecting the sampling switch S0 and closing the first switch S1, so that the sampling capacitor Cs charges the first integration capacitor C1; disconnecting the first switch S1 and closing the second switch S2, so that the discharged sampling capacitor Cs charges the second integration capacitor C2.

[0102] It can be understood that after the residual voltage is collected by closing the sampling switch S0, the sampling switch S0 is first opened, and the first switch S1 is closed, so that the sampling capacitor Cs charges the first integration capacitor C1. The control timing of the first switch S1 can refer to Figure 4 As shown, it can be located in the next clock cycle after the sampling switch S0 is turned off; when the first integral capacitor C1 is fully charged, the first switch S1 is turned off, and the second switch S2 is closed, so that the sampling capacitor Cs discharged to the first integral capacitor C1 charges the second integral capacitor C2. The control timing of the second switch S2 can refer to Figure 4 As shown, it may be located in the next clock cycle after the first switch S1 is turned off.

[0103] In one embodiment, the analog-to-digital converter further includes a third switch S3; a first end of the third switch S3 is connected to the residual sampling unit 141, and a second end of the third switch S3 is connected to the ground. The noise shaping method further includes: before controlling the residual sampling unit 141 to collect the residual voltage of the current conversion cycle, controlling the third switch S3 to close so that the residual sampling unit 141 is discharged.

[0104] It can be understood that before controlling the residual sampling unit 141 to collect the residual voltage of the current conversion cycle, the third switch S3 is closed to discharge the sampling capacitor Cs, so as to avoid the residual voltage of the previous conversion cycle remaining in the sampling capacitor Cs, thereby preventing the sampling capacitor Cs from affecting the integrated voltage of the current conversion cycle.

[0105] In one embodiment, controlling the capacitive digital-to-analog conversion circuit 110 to perform voltage sampling in the current conversion cycle includes: controlling the capacitive digital-to-analog conversion circuit 110 to perform voltage sampling in the current conversion cycle at the charging end time of the first integration unit in the previous conversion cycle.

[0106] It can be understood that since the capacitive digital-to-analog conversion circuit 110 performs voltage sampling at the beginning of each conversion cycle, and since the voltage sampling process and the integration process of the residual voltage do not interfere with each other, in order to shorten the overall conversion time, the voltage sampling of the next conversion cycle can be started at the end of the charging of the first integration unit 142 using the residual voltage.

[0107] Specifically, the first switch S1 is used to control the charging of the first integration unit 142, the second switch S2 is used to control the charging of the second integration unit 143, and the switch Φ s The capacitor type digital-to-analog conversion circuit 110 is controlled to realize voltage acquisition, and the switch Φ s The closing time can be referred to Figure 4 The time t1 shown is the charging end time of the first integration unit 142. In this way, the capacitive digital-to-analog conversion circuit 110 has completed the voltage acquisition of the next conversion cycle when the charging of the second integration unit 143 ends, thus saving the overall conversion time of the analog-to-digital converter.

[0108] An embodiment of the present invention further provides a noise shaping device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method of any of the above embodiments when executing the computer program.

[0109] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above embodiments are implemented.

[0110] The whole process of the noise shaping method is briefly described below.

[0111] like Figure 5 As shown, at the beginning of the conversion cycle, the SAR logic control circuit is first driven according to the conversion result of the previous conversion cycle to control the capacitive digital-to-analog conversion circuit 110 to collect voltage, and the common mode voltage and the voltage to be measured V are combined to realize in and V ip The capacitor matrix is ​​charged, and then the switch Φ is switched after the sampling is completed. s Disconnect, and shift by adjusting each switch in the capacitor array to adjust the output voltage of the capacitive digital-to-analog conversion circuit 110, so that the output voltage gradually approaches the voltage to be measured during each shift process, until the shift is completed to generate the residual voltage of the current conversion cycle, wherein during the shift period, the multi-input comparator converts and outputs according to the current output voltage and the integral voltage of the previous conversion cycle, and then drives the SAR logic control circuit to control the shift of the next bit, until the shift of the current conversion cycle is completed, the multi-input comparator 120 converts and outputs according to the output voltage of the capacitive digital-to-analog conversion circuit 110 and the integral voltage of the previous conversion cycle output by the passive loop filter circuit 140, and the conversion result of the current conversion cycle can be obtained. After receiving the conversion result of the current conversion cycle, the next round of conversion cycle starts, and so on. Then, the residual integration stage is entered. After the residual voltage is obtained, the sampling switch S0 is controlled to be closed, so that the sampling capacitor Cs samples the residual voltage. Then, the sampling switch S0 is disconnected, and the first switch S1 is closed, so that the sampling capacitor Cs discharges to the first integral capacitor C1 to charge the first integral capacitor C1. After the charging is completed, the first switch S1 is disconnected and the second switch S2 is closed, so that the discharged sampling capacitor Cs charges the second integral capacitor C2. In this way, the integral voltage of the current conversion cycle, that is, the charging voltage on the first integral capacitor C1 and the second integral capacitor C2, can be obtained.

[0112] It should be understood that, unless otherwise specified herein, the execution of the above method steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0113] In one embodiment, a computer device is provided. The computer device may be a terminal device, and its internal structure diagram may be as follows: Figure 6As shown. The computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, an operator network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a computer method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a button, a trackball or a touch pad set on the computer device housing, or an external keyboard, touch pad or mouse, etc.

[0114] Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of the present application, and does not constitute a limitation on the noise shaping device to which the scheme of the present application is applied. The specific noise shaping device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0115] In one embodiment, a noise shaping device is provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps of the above method embodiments when executing the computer program.

[0116] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned method embodiments are implemented.

[0117] In one embodiment, a computer program product or computer program is provided, the computer program product or computer program includes computer instructions, the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in the above-mentioned method embodiments.

[0118] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes in the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0119] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A second-order passive noise shaping successive approximation analog-to-digital converter, characterized in that: It includes a capacitive digital-to-analog conversion circuit, a multi-input comparator, a SAR logic control circuit, two sets of passive loop filter circuits and a timing control circuit; The capacitive digital-to-analog conversion circuit is connected to the SAR logic control circuit, the first differential output terminal of the capacitive digital-to-analog conversion circuit is connected to the first input terminal of the multi-input comparator, and the second differential output terminal of the capacitive digital-to-analog conversion circuit is connected to the second input terminal of the multi-input comparator; Each of the passive loop filter circuits comprises a residual sampling unit, a first integration unit and a second integration unit; each of the residual sampling units is connected to the first differential output terminal and the second differential output terminal in a one-to-one correspondence; the first integration unit and the second integration unit are connected to the residual sampling units of the same group, and are connected to the multi-input comparator; The timing control circuit is respectively connected to the SAR logic control circuit, the multi-input comparator and each of the passive loop filter circuits, and is used to drive the SAR logic control circuit according to the conversion result of the previous conversion cycle to control the capacitive digital-to-analog conversion circuit to perform voltage sampling of the current conversion cycle, and generate an output voltage that successively approximates the voltage to be measured based on the sampled voltage until a residual voltage of the current conversion cycle is generated; The multi-input comparator is used to convert and output according to the output voltage of the capacitive digital-to-analog conversion circuit and the integrated voltage of the previous conversion cycle output by the passive loop filter circuit to obtain the conversion result of the current conversion cycle; The timing control circuit is also used to control the residual sampling unit to collect the residual voltage of the current conversion cycle, and to charge the first integration unit and the second integration unit respectively based on the residual voltage of the current conversion cycle to obtain the integration voltage of the current conversion cycle for use in the conversion output of the next conversion cycle.

2. The second-order passive noise shaping successive approximation analog-to-digital converter according to claim 1, characterized in that: The capacitance value of the residual sampling unit is equal to one third of the capacitance value of the capacitive digital-to-analog conversion circuit; the capacitance value of the first integration unit and the capacitance value of the second integration unit are respectively equal to the capacitance value of the capacitive digital-to-analog conversion circuit.

3. The second-order passive noise shaping successive approximation analog-to-digital converter according to claim 1, characterized in that: Each of the residual sampling units includes a sampling capacitor and a sampling switch; the first end of the sampling switch is connected to the target differential output end, and the second end of the sampling switch is respectively connected to the first end of the sampling capacitor, the first integration unit and the second integration unit; the second end of the sampling capacitor is connected to the ground end; wherein the target differential output end is the first differential output end or the second differential output end.

4. The second-order passive noise shaping successive approximation analog-to-digital converter according to claim 3, characterized in that: The first integration unit includes a first switch and a first integration capacitor; the second integration unit includes a second switch and a second integration capacitor; the first end of the first switch and the first end of the second switch are respectively connected to the first end of the sampling capacitor; the second end of the first switch and the first end of the first integration capacitor are respectively connected to the multi-input comparator; the second end of the first integration capacitor is connected to the ground; the second end of the second switch and the first end of the second integration capacitor are respectively connected to the multi-input comparator; the second end of the second integration capacitor is connected to the ground.

5. The second-order passive noise shaping successive approximation analog-to-digital converter according to claim 1, characterized in that: The analog-to-digital converter also includes a third switch; a first end of the third switch is connected to the residual sampling unit, and a second end of the third switch is connected to the ground. The timing control circuit is also used to control the third switch to close before controlling the residual sampling unit to collect the residual voltage of the current conversion cycle, so that the residual sampling unit is discharged.

6. The second-order passive noise shaping successive approximation analog-to-digital converter according to claim 1, characterized in that: The timing control circuit controls the capacitive digital-to-analog conversion circuit to perform voltage sampling in the current conversion cycle at the charging end time of the first integration unit in the previous conversion cycle.

7. A noise shaping method, characterized in that: Applied to a second-order passive noise shaping successive approximation analog-to-digital converter, the second-order passive noise shaping successive approximation analog-to-digital converter includes a capacitive digital-to-analog conversion circuit, a multi-input comparator, a SAR logic control circuit and two groups of passive loop filtering circuits; the capacitive digital-to-analog conversion circuit is connected to the SAR logic control circuit, the first differential output end of the capacitive digital-to-analog conversion circuit is connected to the first input end of the multi-input comparator, and the second differential output end of the capacitive digital-to-analog conversion circuit is connected to the second input end of the multi-input comparator; each of the passive loop filtering circuits includes a residual sampling unit, a first integration unit and a second integration unit; each of the residual sampling units is connected to the first differential output end and the second differential output end in a one-to-one correspondence; the first integration unit and the second integration unit are respectively connected to the residual sampling unit of the same group, and are connected to the multi-input comparator; The noise shaping method comprises: driving the SAR logic control circuit according to the conversion result of the previous conversion cycle to control the capacitive digital-to-analog conversion circuit to perform voltage sampling of the current conversion cycle, and generating an output voltage that successively approximates the voltage to be measured based on the sampled voltage until the residual voltage of the current conversion cycle is generated; The multi-input comparator is used to convert and output according to the output voltage of the capacitive digital-to-analog conversion circuit and the integrated voltage of the previous conversion cycle output by the passive loop filter circuit to obtain a conversion result of the current conversion cycle; The noise shaping method also includes: controlling the residual sampling unit to collect the residual voltage of the current conversion cycle, and charging the first integration unit and the second integration unit in sequence based on the residual voltage of the current conversion cycle, so as to obtain the integration voltage of the current conversion cycle for conversion output in the next conversion cycle.

8. The noise shaping method according to claim 7, characterized in that: The capacitance value of the residual sampling unit is equal to one third of the capacitance value of the capacitive digital-to-analog conversion circuit; the capacitance value of the first integration unit and the capacitance value of the second integration unit are respectively equal to the capacitance value of the capacitive digital-to-analog conversion circuit.

9. The noise shaping method according to claim 7, characterized in that: Each of the residual sampling units includes a sampling capacitor and a sampling switch; the first end of the sampling switch is connected to the target differential output end, and the second end of the sampling switch is respectively connected to the first end of the sampling capacitor, the first integration unit and the second integration unit; the second end of the sampling capacitor is connected to the ground end; wherein the target differential output end is the first differential output end or the second differential output end; the controlling the residual sampling unit to collect the residual voltage of the current conversion cycle includes: The sampling switch is controlled to be closed so that the sampling capacitor collects the residual voltage of the current conversion cycle.

10. The noise shaping method according to claim 9, characterized in that: The first integration unit includes a first switch and a first integration capacitor; the second integration unit includes a second switch and a second integration capacitor; the first end of the first switch and the first end of the second switch are respectively connected to the first end of the sampling capacitor; the second end of the first switch and the first end of the first integration capacitor are respectively connected to the multi-input comparator; the second end of the first integration capacitor is connected to the ground; the second end of the second switch and the first end of the second integration capacitor are respectively connected to the multi-input comparator; the second end of the second integration capacitor is connected to the ground; The step of sequentially charging the first integration unit and the second integration unit based on the residual voltage of the current conversion cycle comprises: Opening the sampling switch and closing the first switch so that the sampling capacitor charges the first integration capacitor; The first switch is opened, and the second switch is closed, so that the discharged sampling capacitor charges the second integrating capacitor.

11. The noise shaping method according to claim 7, characterized in that: The analog-to-digital converter further includes a third switch; a first end of the third switch is connected to the residual sampling unit, and a second end of the third switch is connected to the ground. The noise shaping method further includes: Before controlling the residual sampling unit to collect the residual voltage of the current conversion cycle, the third switch is controlled to be closed so that the residual sampling unit is discharged.

12. The noise shaping method according to claim 7, characterized in that: The controlling the capacitive digital-to-analog conversion circuit to perform voltage sampling in the current conversion cycle includes: controlling the capacitive digital-to-analog conversion circuit to perform voltage sampling in the current conversion cycle at the charging end moment of the first integration unit in the previous conversion cycle.

13. A noise shaping device, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 7 to 12 are implemented.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 7 to 12 are implemented.

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