Comparator calibration method and device, computer equipment, medium and program product

Abstract

The invention relates to the technical field of integrated circuits, and discloses a comparator calibration method and device, computer equipment, a medium and a program product. According to the calibration module applied to the comparator calibration system, the calibration module is electrically connected with a multiplication digital-to-analog converter, the multiplication digital-to-analog converter comprises a plurality of comparators, the in-phase input end of each comparator is connected with the output end of a multiplexer, the in-phase input end and the anti-phase input end of each comparator are connected with an auxiliary differential pair, and the auxiliary differential pair is connected with the output end of the multiplexer. The input circuit inputs compensation voltage. When it is detected that the control end of the multiplexer receives a high level, the input end of the multiplication digital-to-analog converter is short-circuited, and then the voltage value of the compensation voltage corresponding to the target comparator is gradually changed until the output jump of the target comparator is detected; and finally, taking the compensation voltage when the output of the target comparator jumps as the target compensation voltage of the target comparator so as to complete the calibration of the target comparator. According to the scheme, the comparator calibration function is simple, convenient and efficient.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a comparator calibration method, device, computer equipment, medium and program product. Background Art

[0002] As the process nodes continue to shrink, the offset of the comparator in the high-precision Pipeline ADC (Pipeline Analog-to-Digital Converter) continues to increase, gradually approaching or exceeding the offset correction range, resulting in poor performance of the Pipeline ADC or even missing codes. Therefore, if you want to achieve high precision, you must introduce automatic calibration to eliminate the impact of comparator offset.

[0003] In the related art, the comparator calibration is performed through foreground automatic calibration or background automatic calibration. Foreground automatic calibration requires the injection of a calibration signal, usually a ramp signal generator or a digital-to-analog converter, to generate a level near the comparator threshold voltage and input it into the comparator, and then adjust the comparator so that the output of the comparator reaches the expected value, thereby achieving calibration. The disadvantage of this method is that it is necessary to add a switch to the analog signal input path to switch the calibration signal and the real analog signal, which will affect the high-frequency linearity of the final ADC, and it is necessary to design additional analog circuits for calibration. Background automatic calibration avoids the use of a switching switch, and the calibration signal is directly output from the signal path. The offset voltage of the comparator is calculated by statistical averaging, but this method requires the collection of a large amount of data (usually on the order of 1M), which occupies too many system resources.

[0004] Therefore, a simple and efficient comparator calibration method is urgently needed. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a comparator calibration method, apparatus, computer equipment, medium and program product to solve the problem that comparator calibration is not simple and efficient enough.

[0006] In a first aspect, the present invention provides a comparator calibration method, which is applied to a calibration module in a comparator calibration system; the comparator calibration system also includes a multiplication digital-to-analog converter, and the calibration module is electrically connected to the multiplication digital-to-analog converter; the multiplication digital-to-analog converter includes a plurality of comparators; wherein the in-phase input terminal of each comparator is respectively connected to the output terminal of a multiplexer, and the inverting input terminal of each comparator is connected to the input terminal of the multiplication digital-to-analog converter; the in-phase input terminal and the inverting input terminal of each comparator are also connected to an auxiliary differential pair for inputting a compensation voltage; the method includes:

[0007] When it is detected that the control terminal of the multiplexer receives a high level, short-circuiting the input terminal of the multiplication digital-to-analog converter;

[0008] For a target comparator among the multiple comparators, the voltage value of the compensation voltage corresponding to the target comparator is changed successively until an output jump of the target comparator is detected;

[0009] The compensation voltage when the output of the target comparator jumps is used as the target compensation voltage of the target comparator to complete the calibration of the target comparator.

[0010] In an optional implementation, the first input terminal of each multiplexer is connected to a threshold voltage corresponding to the comparator, and the second input terminal of each multiplexer is connected to a zero voltage; wherein the threshold voltage corresponding to the comparator is related to the number of the comparator.

[0011] In an optional implementation, the auxiliary differential pair is a first switch tube and a second switch tube, wherein the first switch tube is connected in parallel to the non-inverting input terminal of the comparator, and the second switch tube is connected in parallel to the inverting input terminal of the comparator.

[0012] In an optional implementation, the control end of the first switch tube is connected to an adjustable voltage source.

[0013] In an optional implementation, the number of the comparators is related to the number of bits of the multiplying digital-to-analog converter.

[0014] In a second aspect, the present invention provides a comparator calibration system, the system comprising:

[0015] A multiplication digital-to-analog converter, wherein the multiplication digital-to-analog converter includes a plurality of comparators; wherein the non-inverting input end of each comparator is respectively connected to the output end of a multiplexer, and the inverting input end of each comparator is connected to the input end of the multiplication digital-to-analog converter; the non-inverting input end and the inverting input end of each comparator are also connected to an auxiliary differential pair for inputting a compensation voltage;

[0016] A calibration module, electrically connected to the multiplication digital-to-analog converter, comprising:

[0017] A detection unit, configured to short-circuit the input terminal of the multiplication digital-to-analog converter when detecting that the control terminal of the multiplexer receives a high level;

[0018] A jump unit, for successively changing the voltage value of the compensation voltage corresponding to a target comparator among the multiple comparators until an output jump of the target comparator is detected;

[0019] The calibration unit is used to use the compensation voltage when the output of the target comparator jumps as the target compensation voltage of the target comparator to complete the calibration of the target comparator.

[0020] In an optional implementation, the system further includes a pipeline analog-to-digital converter; the pipeline analog-to-digital converter includes at least two of the multiplication digital-to-analog converters.

[0021] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the comparator calibration method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0022] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the comparator calibration method of the first aspect or any corresponding embodiment thereof.

[0023] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, wherein the computer instructions are used to enable a computer to execute the comparator calibration method of the first aspect or any corresponding embodiment thereof.

[0024] The technical solution provided by the present invention may include the following beneficial effects:

[0025] The comparator calibration method provided by the present invention is applied to a calibration module in a comparator calibration system, wherein the comparator calibration system further comprises a multiplication digital-to-analog converter, the calibration module is electrically connected to the multiplication digital-to-analog converter, and the multiplication digital-to-analog converter comprises a plurality of comparators, wherein the in-phase input end of each comparator is respectively connected to the output end of a multiplexer, the inverting input end of each comparator is connected to the input end of the multiplication digital-to-analog converter, and the in-phase input end and the inverting input end of each comparator are also connected to an auxiliary differential pair for inputting a compensation voltage. When calibrating the comparator, firstly, when it is detected that the control end of the multiplexer receives a high level, the input end of the multiplication digital-to-analog converter is short-circuited, and then, for a target comparator among the plurality of comparators, the voltage value of the compensation voltage corresponding to the target comparator is changed successively until the output jump of the target comparator is detected, and finally, the compensation voltage when the output jump of the target comparator is used as the target compensation voltage of the target comparator to complete the calibration of the target comparator. The above scheme inputs a high level to the control end of the multiplexer and short-circuits the input end of the multiplication digital-to-analog converter, so that the threshold voltage of each comparator is changed from different levels in the normal working state to a fixed level, so that the difference in threshold voltage cannot affect the calibration process of each comparator, so that the value of the corresponding compensation voltage can be directly adjusted according to the output of each comparator, and the target compensation voltage of the comparator can be determined by successively changing the compensation voltage. The comparator calibration is completed without the need to additionally design a calibration circuit and add switches, and without collecting a large amount of data. The comparator calibration function is simple and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 is a flow chart of a comparator calibration method according to an embodiment of the present invention;

[0028] Figure 2 is a structural diagram of a 2.5-bit multiplication digital-to-analog converter according to an embodiment of the present invention;

[0029] Figure 3 is a schematic diagram of comparator calibration according to an embodiment of the present invention;

[0030] Figure 4 is a structural block diagram of a comparator calibration system according to an embodiment of the present invention;

[0031] Figure 5 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0033] As the process nodes continue to shrink, the offset of the comparator in the high-precision Pipeline ADC (Pipeline Analog-to-Digital Converter) continues to increase, gradually approaching or exceeding the offset correction range, resulting in poor performance of the Pipeline ADC or even missing codes. Therefore, if you want to achieve high precision, you must introduce automatic calibration to eliminate the impact of comparator offset.

[0034] In the related art, the comparator calibration is performed through foreground automatic calibration or background automatic calibration. Foreground automatic calibration requires the injection of a calibration signal, usually a ramp signal generator or a digital-to-analog converter, to generate a level near the comparator threshold voltage and input it into the comparator, and then adjust the comparator so that the output of the comparator reaches the expected value, thereby achieving calibration. The disadvantage of this method is that it is necessary to add a switch to the analog signal input path to switch the calibration signal and the real analog signal, which will affect the high-frequency linearity of the final ADC, and it is necessary to design additional analog circuits for calibration. Background automatic calibration avoids the use of a switching switch, and the calibration signal is directly output from the signal path. The offset voltage of the comparator is calculated by statistical averaging, but this method requires the collection of a large amount of data (usually on the order of 1M), which occupies too many system resources.

[0035] According to an embodiment of the present invention, a comparator calibration method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0036] In the present embodiment, a comparator calibration method is provided, which is applied to a calibration module in a comparator calibration system. The comparator calibration system also includes a multiplication digital-to-analog converter, and the calibration module is electrically connected to the multiplication digital-to-analog converter. The multiplication digital-to-analog converter includes a plurality of comparators, wherein the in-phase input terminal of each comparator is respectively connected to the output terminal of a multiplexer, and the inverting input terminal of each comparator is connected to the input terminal of the multiplication digital-to-analog converter. The in-phase input terminal and the inverting input terminal of each comparator are also connected to an auxiliary differential pair for inputting a compensation voltage. The calibration module can be a desktop computer, a laptop computer, an industrial computer, a computer module, etc. Figure 1 is a flow chart of a comparator calibration method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0037] Step S101, when it is detected that the control terminal of the multiplexer receives a high level, the input terminal of the multiplication digital-to-analog converter is short-circuited.

[0038] The number of comparators is related to the number of bits of the multiplication DAC. Generally speaking, when x=n, an x-bit multiplication DAC has 2 n -1 comparator, when x=n-0.5, the x-bit multiplying DAC has 2 n-2 comparators, for example, a 2.5-bit multiplying DAC has 6 comparators. In practical applications, the number of comparators can be increased according to demand, for example, two more comparators are added to the 2.5-bit multiplying DAC, and a total of 8 comparators are used.

[0039] The multiplexer is used to provide a threshold voltage for the corresponding comparator. The first input terminal of each multiplexer is connected to the threshold voltage corresponding to the comparator, and the second input terminal of each multiplexer is connected to zero voltage. The threshold voltage corresponding to the comparator is related to the number of the comparator. Specifically, when x=n, 2 n -1 comparator corresponding to 2 n -1 threshold voltages are [(-2 n +2) / 2 n ]×V ref ,[(-2 n +4) / 2 n ]×V ref ,…,0,…,[(2 n -4) / 2 n ]×V ref ,[(2 n -2) / 2 n ]×V ref ; When x = n-0.5, 2 n -2 comparators corresponding to 2 n -2 threshold voltages are [(-2 n +3) / 2 n ]×V ref ,[(-2 n +5) / 2 n ]×V ref ,…,0,…,[(2 n -5) / 2 n ]×V ref ,[(2 n -3) / 2 n ]×V ref .

[0040] The control end of each multiplexer is electrically connected to an external circuit of the multiplication digital-to-analog converter, and the external circuit can send a signal to the control end of the multiplexer to pull up the control end level of the multiplexer. Exemplarily, the external circuit can send a signal to the control end of the multiplexer through a chip pin or an SPI command.

[0041] When the calibration module detects that the control end of the multiplexer receives a high level, the input end of the multiplication digital-to-analog converter is short-circuited, that is, the inverting input end of each comparator is also short-circuited. Since the control end of each multiplexer receives a high level and is set high, based on the principle of the multiplexer, the threshold voltage input to the first input end of each multiplexer cannot affect the output of the multiplexer at this time, and the second input end of each multiplexer inputs a zero voltage, that is, each multiplexer outputs 0V, and then the in-phase input end of each comparator receives a zero voltage, and since the inverting input end of each comparator is short-circuited, the threshold voltage of each comparator is 0V at this time. Ideally, the comparator should output 0V at this time, but due to the mismatch of the internal circuit of the comparator, the comparator will output a voltage near the 0 threshold at this time, that is, the output of the comparator can be made as close to the ideal state as possible by inputting a compensation voltage to perform mismatch calibration. That is to say, in the present invention, by adding a corresponding multiplexer to the in-phase input terminal of each comparator, and setting the control terminal voltage of each multiplexer high when the comparator calibration is required, the threshold voltage of each comparator is changed from different levels in the normal working state to a fixed level, so that the difference in threshold voltage cannot affect the calibration process of each comparator, so that the value of the corresponding compensation voltage can be directly adjusted according to the output of each comparator to complete the comparator calibration.

[0042] Step S102 , for a target comparator among the multiple comparators, the voltage value of the compensation voltage corresponding to the target comparator is changed successively until an output jump of the target comparator is detected.

[0043] Each comparator is calibrated separately in turn through the calibration module. Specifically, for the target comparator, the compensation voltage of the input target comparator is adjusted by successively inputting voltages to the auxiliary differential pair connected to the in-phase input terminal and the inverting input terminal of the target comparator. The voltage value of the input compensation voltage can be from small to large or from large to small, which is not limited here. When the output jump of the target comparator is detected, it means that the compensation voltage at this time makes the target comparator reach the desired state, and then the voltage value of the compensation voltage stops changing.

[0044] Optionally, the auxiliary differential pair is a first switch tube and a second switch tube, wherein the first switch tube is connected in parallel with the non-inverting input terminal of the comparator, and the second switch tube is connected in parallel with the inverting input terminal of the comparator. The compensation voltage input to the corresponding comparator can be adjusted by inputting a voltage to the first switch tube and the second switch tube. It should be noted that there is a power supply inside the comparator to power the comparator, and the auxiliary differential pair adjusts the relative value of the voltage at the non-inverting input terminal and the inverting input terminal of the comparator.

[0045] Optionally, the control end of the first switch tube is connected to an adjustable voltage source, and the control end of the second switch tube is grounded, and the voltage of the control end of the first switch tube is adjusted by adjusting the output voltage of the adjustable voltage source, thereby adjusting the compensation voltage of the corresponding comparator. The control end of the first switch tube can also be connected to different positions of the resistor string, so that the resistor string generates different compensation voltages through voltage division at different positions, or the control end of the first switch tube is connected to a charge pump, and different compensation voltages are generated by adjusting the charge pump.

[0046] Step S103 , using the compensation voltage when the output of the target comparator jumps as the target compensation voltage of the target comparator to complete the calibration of the target comparator.

[0047] The compensation voltage when the target comparator jumps is the target compensation voltage that can make the target comparator reach the desired state. Then, the mismatch calibration of the target comparator can be completed by inputting the target compensation voltage to the auxiliary differential pair.

[0048] After completing the calibration of all comparators, the voltage under normal working state is input to the control end of each multiplexer, so that the threshold voltage of each comparator is restored to normal working state, thereby restoring the multiplication digital-to-analog converter to normal working state.

[0049] In an optional embodiment, the system further comprises a pipeline analog-to-digital converter, wherein the pipeline analog-to-digital converter comprises at least two of the multiplication digital-to-analog converters. That is, the comparator calibration method of the present invention can be used to calibrate each stage of the multiplication digital-to-analog converter in the pipeline analog-to-digital converter in turn, thereby completing the comparator calibration of the pipeline analog-to-digital converter.

[0050] The comparator calibration method provided in this embodiment is applied to a calibration module in a comparator calibration system, wherein the comparator calibration system further includes a multiplication digital-to-analog converter, the calibration module is electrically connected to the multiplication digital-to-analog converter, and the multiplication digital-to-analog converter includes a plurality of comparators, wherein the in-phase input terminal of each comparator is respectively connected to the output terminal of a multiplexer, the inverting input terminal of each comparator is connected to the input terminal of the multiplication digital-to-analog converter, and the in-phase input terminal and the inverting input terminal of each comparator are also connected to an auxiliary differential pair for inputting a compensation voltage. When calibrating the comparator, first, when it is detected that the control terminal of the multiplexer receives a high level, the input terminal of the multiplication digital-to-analog converter is short-circuited, and then, for a target comparator among the multiple comparators, the voltage value of the compensation voltage corresponding to the target comparator is changed successively until the output jump of the target comparator is detected, and finally, the compensation voltage when the output jump of the target comparator is used as the target compensation voltage of the target comparator to complete the calibration of the target comparator. The above scheme enables the threshold voltage of each comparator to be changed from different levels in the normal working state to a fixed level, so that the difference in threshold voltage cannot affect the calibration process of each comparator, so that the value of the corresponding compensation voltage can be directly adjusted according to the output of each comparator, and the target compensation voltage of the comparator can be determined by successively changing the compensation voltage. The comparator calibration is completed without the need to design an additional calibration circuit and add switches, and without the need to collect a large amount of data. The comparator calibration function is simple and efficient.

[0051] As one or more specific application embodiments of the embodiments of the present invention, the optimal implementation scheme or the scheme that the inventor most wants to embody is described below in combination with specific application scenarios.

[0052] Figure 2 is a structural diagram of a 2.5-bit multiplication digital-to-analog converter according to an embodiment of the present invention, Figure 3 is a schematic diagram of comparator calibration according to an embodiment of the present invention.

[0053] like Figure 2 As shown, the Sub ADC of the 2.5-bit multiplication DAC contains 6 comparators, and the threshold levels are -5 / 8*VREF, -3 / 8*VREF, -1 / 8*VREF, +1 / 8*VREF, +3 / 8*VREF, and +5 / 8*VREF. s <0> To C s <7> is the sampling capacitor in the multiplying DAC, 2C is the feedback capacitor of the multiplying DAC, V IN is the input of the multiplying DAC, V OUT is the output of the multiplying DAC, ck s is a switch, V refp and V refnis the reference voltage connected to the top plate of the sampling capacitor, and OP is the residual amplifier of the multiplying digital-to-analog converter. Figure 3 As shown, in order to facilitate calibration, a TRIM signal is input to the control end of the multiplexer Mux corresponding to each comparator at the same time, the control end voltage of the multiplexer is pulled high, all comparator thresholds are changed to 0, and the input of the MDAC is short-circuited (VIN terminal is short-circuited), so that each comparator outputs a calibration signal near the 0 threshold, and then the comparator offset is calibrated one by one. After all comparators are calibrated, the threshold level of each comparator is switched to a normal working state, so that the multiplying digital-to-analog converter is restored to a normal working state.

[0054] In this embodiment, a comparator calibration system is also provided, in which a calibration module is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made are omitted. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the calibration module described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0055] This embodiment provides a comparator calibration system, such as Figure 4 As shown, including:

[0056] A multiplication digital-to-analog converter, wherein the multiplication digital-to-analog converter includes a plurality of comparators; wherein the non-inverting input terminal of each comparator is respectively connected to the output terminal of a multiplexer, and the inverting input terminal of each comparator is connected to the input terminal of the multiplication digital-to-analog converter; the non-inverting input terminal and the inverting input terminal of each comparator are also connected to an auxiliary differential pair for inputting a compensation voltage;

[0057] A calibration module, electrically connected to the multiplication digital-to-analog converter, comprises:

[0058] A detection unit, used for short-circuiting the input terminal of the multiplication digital-to-analog converter when detecting that the control terminal of the multiplexer receives a high level;

[0059] A jump unit, for successively changing the voltage value of the compensation voltage corresponding to a target comparator among the multiple comparators until an output jump of the target comparator is detected;

[0060] The calibration unit is used to use the compensation voltage when the output of the target comparator jumps as the target compensation voltage of the target comparator to complete the calibration of the target comparator.

[0061] In an optional embodiment, the system further includes a pipeline analog-to-digital converter; the pipeline analog-to-digital converter includes at least two of the multiplication digital-to-analog converters.

[0062] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0063] The comparator calibration device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0064] An embodiment of the present invention further provides a computer device having the calibration module in the above comparator calibration system.

[0065] See also Figure 5 , Figure 5 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 5 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 5 A processor 10 is taken as an example.

[0066] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0067] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0068] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0069] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0070] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0071] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0072] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0073] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0074] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations shall all fall within the scope of protection of the present invention.

Claims

1. A comparator calibration method, characterized in that: A calibration module applied to a comparator calibration system; the comparator calibration system further comprises a multiplication digital-to-analog converter, the calibration module is electrically connected to the multiplication digital-to-analog converter; the multiplication digital-to-analog converter comprises a plurality of comparators; wherein the in-phase input terminal of each comparator is respectively connected to the output terminal of a multiplexer, and the inverting input terminal of each comparator is connected to the input terminal of the multiplication digital-to-analog converter; the in-phase input terminal and the inverting input terminal of each comparator are also connected to an auxiliary differential pair for inputting a compensation voltage; the method comprises: When it is detected that the control terminal of the multiplexer receives a high level, short-circuiting the input terminal of the multiplication digital-to-analog converter; For a target comparator among the multiple comparators, the voltage value of the compensation voltage corresponding to the target comparator is changed successively until an output jump of the target comparator is detected; The compensation voltage when the output of the target comparator jumps is used as the target compensation voltage of the target comparator to complete the calibration of the target comparator.

2. The method according to claim 1, characterized in that The first input terminal of each multiplexer is connected to the threshold voltage corresponding to the comparator, and the second input terminal of each multiplexer is connected to zero voltage; wherein the threshold voltage corresponding to the comparator is related to the number of the comparator.

3. The method according to claim 1, characterized in that The auxiliary differential pair includes a first switch tube and a second switch tube, wherein the first switch tube is connected in parallel to the non-inverting input terminal of the comparator, and the second switch tube is connected in parallel to the inverting input terminal of the comparator.

4. The method according to claim 3, characterized in that The control end of the first switch tube is connected to an adjustable voltage source.

5. The method according to claim 1, characterized in that: The number of the comparators is related to the number of bits of the multiplying digital-to-analog converter.

6. A comparator calibration system, characterized in that: The system comprises: A multiplication digital-to-analog converter, wherein the multiplication digital-to-analog converter includes a plurality of comparators; wherein the non-inverting input end of each comparator is respectively connected to the output end of a multiplexer, and the inverting input end of each comparator is connected to the input end of the multiplication digital-to-analog converter; the non-inverting input end and the inverting input end of each comparator are also connected to an auxiliary differential pair for inputting a compensation voltage; A calibration module, electrically connected to the multiplication digital-to-analog converter, comprising: A detection unit, configured to short-circuit the input terminal of the multiplication digital-to-analog converter when detecting that the control terminal of the multiplexer receives a high level; A jump unit, for successively changing the voltage value of the compensation voltage corresponding to a target comparator among the multiple comparators until an output jump of the target comparator is detected; The calibration unit is used to use the compensation voltage when the output of the target comparator jumps as the target compensation voltage of the target comparator to complete the calibration of the target comparator.

7. The system according to claim 6, characterized in that The system further comprises a pipeline analog-to-digital converter; the pipeline analog-to-digital converter comprises at least two of the multiplication digital-to-analog converters.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the comparator calibration method according to any one of claims 1 to 5 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the comparator calibration method according to any one of claims 1 to 5.

10. A computer program product, characterized in that The invention comprises computer instructions, wherein the computer instructions are used to make a computer execute the comparator calibration method according to any one of claims 1 to 5.

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