Static random access memory array, memory and control method of memory array

Abstract

The invention provides a static random access memory array, a memory, electronic equipment, a control method and a preparation method. Relates to the technical field of data storage. A memory cell in the SRAM memory array comprises a first transistor, a second transistor, a third transistor and a fourth transistor, and further comprises a first capacitor and a second capacitor, the first transistor and the third transistor are connected in series, a series coupling point forms a first data storage node, the second transistor and the fourth transistor are connected in series, and a second data storage node is formed. The series coupling point forms a second data storage node, the first capacitor is electrically connected with the first data storage node, and the second capacitor is electrically connected with the second data storage node. By means of the two capacitors, the data storage capacitance value can be increased, the storage charge quantity can be increased, then the data retention time can be prolonged, and the influence of the capacitance coupling effect on the data storage state can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and in particular to a static random access memory array, a memory including the static random access memory array, an electronic device including the memory, a control method for the static random access memory array, and a preparation method for the static random access memory array. Background Art

[0002] The rapid development of technologies such as cloud computing, the metaverse, autonomous driving, and artificial intelligence has not only given rise to massive data processing needs, but also put forward higher requirements for the computing performance of chip systems. On the one hand, chip processors need to continuously improve data computing speed, and on the other hand, chip memories need to continuously improve data storage capacity. At present, the performance improvement of processors focuses on increasing computing frequency, while the performance improvement of memories focuses on increasing storage density. The speed difference between the two is increasing, resulting in the data throughput speed of memories not keeping up with the data processing speed of processors, resulting in a "storage wall" effect.

[0003] Static random-access memory (SRAM) has the highest data storage speed among all types of memories and is therefore widely used.

[0004] However, since some storage cells of the SRAM memory rely on the parasitic capacitance of transistors to store data, the data retention time is short and is easily disturbed by the capacitive coupling effect when the word line is turned off, which reduces the reliability of the SRAM. Summary of the invention

[0005] The present application provides a static random access memory array, a memory including the static random access memory array, an electronic device including the memory, a control method of the static random access memory array, and a preparation method of the static random access memory array. The purpose is to provide an SRAM memory array that can extend the data retention time and reduce the influence of the capacitive coupling effect on the data storage state.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, the present application provides a SRAM storage array.

[0008] The SRAM storage array includes a word line WL, a first bit line BL and a second bit line BLB, and a storage unit; the storage unit includes a first transistor, a second transistor, a third transistor and a fourth transistor, and a first capacitor and a second capacitor; the first transistor and the third transistor are coupled in series between the first bit line and the voltage end; the second transistor and the fourth transistor are coupled in series between the second bit line and the voltage end; the control end of the first transistor and the control end of the second transistor are both electrically connected to the word line; the series coupling point of the first transistor and the third transistor is electrically connected to the control end of the fourth transistor; the series coupling point of the first transistor and the third transistor is electrically connected to the first capacitor; the series coupling point of the second transistor and the fourth transistor is electrically connected to the control end of the third transistor; the series coupling point of the second transistor and the fourth transistor is electrically connected to the second capacitor.

[0009] The memory cell of the memory array provided by the present application belongs to a 4T2C memory cell, the serial coupling point of the first transistor and the third transistor forms a first data storage node, the serial coupling point of the second transistor and the fourth transistor forms a second data storage node, because the serial coupling point of the first transistor and the third transistor is also electrically connected to the first capacitor, and the serial coupling point of the second transistor and the fourth transistor is also electrically connected to the second capacitor. In this way, the capacitance value used to store data can be increased, thereby increasing the amount of stored charge. The data storage time depends on the amount of stored charge. When the amount of stored charge increases, the data retention time will be correspondingly extended, and the refresh frequency of the memory array will be reduced.

[0010] In addition, since the first capacitor and the second capacitor are added to the storage array circuit, the parasitic capacitance between the word line and the first data storage node and the parasitic capacitance between the word line and the second data storage node have less impact on the capacitor with larger storage data, thereby reducing the impact of the capacitive coupling effect on the data storage state and improving the data storage performance.

[0011] In one implementation, the first transistor, the second transistor, the third transistor, and the fourth transistor are N-type field effect transistors, and a channel material of the N-type field effect transistor includes an oxide semiconductor material.

[0012] When the transistor channel is made of oxide semiconductor material, the leakage current can be reduced, further extending the data retention time and improving the storage performance; and, since the growth temperature of semiconductor oxide is low, a three-dimensional stacked storage array can be produced by a back-end process to improve the storage density.

[0013] In one achievable manner, the first transistor, the second transistor, the third transistor, the fourth transistor, the first capacitor, and the second capacitor are all manufactured using a back-end process.

[0014] This can form a three-dimensional stacked storage array, improving storage density and storage capacity.

[0015] In one achievable manner, the first transistor and the second transistor are located in a first back-end device layer; the third transistor and the fourth transistor are located in a second back-end device layer; and the first back-end device layer and the second back-end device layer are stacked in a direction perpendicular to the memory array substrate.

[0016] In this implementation structure, the first transistor and the third transistor coupled in series are stacked in different back-end device layers and can be electrically connected through silicon vias. Similarly, the second transistor and the fourth transistor coupled in series are stacked in different back-end device layers and can also be electrically connected through silicon vias.

[0017] In one implementation, the word line is located in a first back-end device layer or a second back-end device layer.

[0018] In one achievable manner, the orthographic projection of the first transistor on the storage array substrate at least partially overlaps with the orthographic projection of the third transistor on the storage array substrate; the orthographic projection of the second transistor on the storage array substrate at least partially overlaps with the orthographic projection of the fourth transistor on the storage array substrate.

[0019] By adopting this process structure, the vertical projection area of ​​a storage unit can be reduced, and the storage density can be significantly improved.

[0020] In one possible implementation, the first transistor and the second transistor are arranged along a first direction parallel to the memory array substrate; and the third transistor and the fourth transistor are arranged along the first direction.

[0021] In one achievable manner, a voltage connection metal layer for electrically connecting to a voltage terminal is formed between a first back-end device layer and a second back-end device layer, and a first electrode of a first transistor is electrically connected to a first electrode of a third transistor by coupling via a first conductive via penetrating the voltage connection metal layer; a first capacitor layer is formed between an interface between the first conductive via and the voltage connection metal layer, and a structure including at least a portion of the first conductive via, at least a portion of the voltage connection metal layer, and the first capacitor layer forms a first capacitor.

[0022] In the example of the present application, a metal layer electrically connected to the voltage terminal is arranged between the first back-end metal layer and the second back-end metal layer, and a capacitor layer is arranged between the conductive through hole and the voltage connection metal layer, thereby forming a capacitor device that can increase the storage capacitance. The process structure is simple, does not occupy additional area, and can improve the storage density.

[0023] In one achievable manner, the second electrode of the third transistor in the second back-end device layer may be electrically connected to the voltage connection metal layer via a conductive via, and the second electrode of the fourth transistor in the second back-end device layer may be electrically connected to the voltage connection metal layer via a conductive via.

[0024] In one achievable method, the first electrode of the second transistor is electrically coupled to the first electrode of the fourth transistor via a second conductive via penetrating the voltage-connecting metal layer; a second capacitor layer is formed between the interface between the second conductive via and the voltage-connecting metal layer, and a structure including at least a portion of the second conductive via, at least a portion of the voltage-connecting metal layer, and the second capacitor layer forms a second capacitor.

[0025] In one achievable manner, the static random access memory array further includes: a first interconnect routing layer and a second interconnect routing layer; the first interconnect routing layer is arranged on a side of the first back-end device layer away from the memory array substrate; the second interconnect routing layer is arranged on a side of the second back-end device layer away from the memory array substrate; the first electrode of the first transistor is electrically connected to the control end of the fourth transistor through the first interconnect routing layer and the second interconnect routing layer; the first electrode of the second transistor is electrically connected to the control end of the third transistor through the first interconnect routing layer and the second interconnect routing layer.

[0026] In one achievable manner, the static random access memory array further includes a third interconnect routing layer; the third interconnect routing layer is arranged on a side of the first back-end device layer and the second back-end device layer away from the memory array substrate; the first bit line and the second bit line are formed in the third interconnect routing layer.

[0027] The first bit line and the second bit line in the third interconnection wiring layer may be electrically connected to the first transistor and the second transistor in the first back-end device layer through silicon vias.

[0028] In one achievable manner, the first transistor, the second transistor, the third transistor, and the fourth transistor are located in the same back-end device layer.

[0029] In this implementation structure, four transistors of a storage unit are integrated in the same back-end device layer.

[0030] In one possible implementation, the first transistor and the third transistor are arranged along a second direction parallel to the memory array substrate; the second transistor and the fourth transistor are arranged along the second direction; the first transistor and the second transistor are arranged along a third direction parallel to the memory array substrate, and the third transistor and the fourth transistor are arranged along the third direction, and the third direction intersects with the second direction, for example, is orthogonal.

[0031] In one achievable method, a voltage connection metal layer electrically connected to the voltage end is also provided in the back-end device layer where the first transistor, the second transistor, the third transistor, and the fourth transistor are located; the voltage connection metal layer surrounds the periphery of the gate of the third transistor, and a first capacitor layer is provided between the voltage connection metal layer and the gate interface of the third transistor, and a second capacitor is formed by a structure including at least a portion of the voltage connection metal layer, the first capacitor layer, and the gate of the third transistor.

[0032] In this process structure, a voltage connection metal layer for electrically connecting to a voltage terminal is arranged in a back-end device layer, and the voltage connection metal layer and a gate of a transistor are used as electrode plates of a capacitor, respectively.

[0033] In one achievable method, a voltage connection metal layer surrounds the periphery of the gate of the fourth transistor, a second capacitor layer is provided between the voltage connection metal layer and the gate interface of the fourth transistor, and a structure including at least a portion of the voltage connection metal layer, the second capacitor layer and the gate of the fourth transistor forms a first capacitor.

[0034] In one achievable manner, a first transistor, a second transistor, a third transistor, and a fourth transistor are located in a first back-end device layer; the static random access memory array further comprises a first interconnect routing layer, and the first interconnect routing layer is located on a side of the first back-end device layer away from the memory array substrate; a first electrode of the first transistor is electrically connected to a control terminal of the fourth transistor through the first interconnect routing layer; and a first electrode of the second transistor is electrically connected to a control terminal of the third transistor through the first interconnect routing layer.

[0035] Different transistors are electrically connected using an interconnection wiring layer disposed on one side of the back-end device layer.

[0036] In one achievable manner, the static random access memory array further includes a second interconnect routing layer, which is located on a side of the first interconnect routing layer away from the memory array substrate; the first bit line and the second bit line are formed in the second interconnect routing layer.

[0037] In one implementation, the word line is formed in a back-end device layer where the first transistor, the second transistor, the third transistor, and the fourth transistor are located.

[0038] In a second aspect, the present application provides a memory, which may include a controller and an SRAM storage array in any of the above-mentioned implementations, wherein the controller is electrically connected to the static random access storage array, and the controller is used to control the reading and writing of the static random access storage array.

[0039] In the SRAM storage array of the memory provided in the present application, since 4T2C storage units are included, the storage capacitance value can be increased by adding capacitance at the storage node, thereby increasing the amount of stored charge, thereby extending the storage time and reducing the refresh frequency; and the influence of the capacitive coupling effect on the data storage state can also be reduced.

[0040] In one implementable manner, in a write phase, a word line is used to receive a first word line control signal, a first bit line is used to receive a first bit line control signal, and a second bit line is used to receive a second bit line control signal; the first word line control signal is used to turn on a first transistor electrically connected to the first bit line, and to turn on a second transistor electrically connected to the second bit line, the first bit line control signal causes the first capacitor to be charged to a first potential, and the second bit line control signal causes the second capacitor to be charged to a second potential less than the first potential.

[0041] Compared with storing data in a data storage node that relies solely on the serial coupling point of the first transistor and the third transistor, the capacitance can be increased and the data retention time can be extended by increasing the capacitance.

[0042] In one achievable method, after the first bit line control signal causes the first capacitor to be charged to a first potential and the second bit line control signal causes the second capacitor to be charged to a second potential, the word line is also used to receive a second word line control signal, the second word line control signal is used to turn off the first transistor electrically connected to the first bit line, and is used to turn off the second transistor electrically connected to the second bit line; the first bit line control signal turns on the fourth transistor, and the second bit line control signal turns off the third transistor, thereby realizing data storage.

[0043] In a third aspect, the present application provides an electronic device, comprising a processor and a memory in any of the above-mentioned implementations, wherein the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

[0044] Since the electronic device includes the above-mentioned memory, the electronic device and the memory solve the same technical problem and achieve the same technical effect.

[0045] In a fourth aspect, the present application provides a control method for a static random access memory array, wherein the static random access memory array includes: a word line WL, a first bit line BL and a second bit line BLB, and a memory cell; the memory cell includes a first transistor, a second transistor, a third transistor and a fourth transistor, and a first capacitor and a second capacitor; the first transistor and the third transistor are coupled in series between the first bit line and a voltage terminal; the second transistor and the fourth transistor are coupled in series between the second bit line and the voltage terminal; the control terminal of the first transistor and the control terminal of the second transistor are both electrically connected to the word line; the series coupling point of the first transistor and the third transistor is electrically connected to the control terminal of the fourth transistor; the series coupling point of the first transistor and the third transistor is electrically connected to the first capacitor; the series coupling point of the second transistor and the fourth transistor is electrically connected to the control terminal of the third transistor; the series coupling point of the second transistor and the fourth transistor is electrically connected to the second capacitor; the control method may include:

[0046] In the write phase, a first word line control signal is input to the word line, a first bit line control signal is input to the first bit line, and a second bit line control signal is input to the second bit line;

[0047] The first word line control signal is used to turn on a first transistor electrically connected to the first bit line, and to turn on a second transistor electrically connected to the second bit line. The first bit line control signal causes the first capacitor to be charged to a first potential, and the second bit line control signal causes the second capacitor to be charged to a second potential less than the first potential.

[0048] In one achievable method, a first bit line control signal causes the first capacitor to be charged to a first potential, and a second bit line control signal causes the second capacitor to be charged to a second potential, and then a second word line control signal is input to the word line, and the second word line control signal is used to turn off the first transistor electrically connected to the first bit line, and to turn off the second transistor electrically connected to the second bit line; the first bit line control signal turns on the fourth transistor, and the second bit line control signal turns off the third transistor, thereby realizing data storage.

[0049] Since the capacitance is added at the data storage node in the storage unit, the data storage charge amount can be increased, the data retention time can be extended, and the refresh frequency can be reduced.

[0050] In a fifth aspect, the present application provides a method for preparing a static random access memory array, the method comprising:

[0051] A memory cell is manufactured on a substrate, wherein the memory cell comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor;

[0052] Fabricating a word line, a first bit line, and a second bit line on a substrate;

[0053] Among them, the first transistor and the third transistor are coupled in series between the first bit line and the voltage terminal; the second transistor and the fourth transistor are coupled in series between the second bit line and the voltage terminal; the control terminal of the first transistor and the control terminal of the second transistor are both electrically connected to the word line; the series coupling point of the first transistor and the third transistor is electrically connected to the control terminal of the fourth transistor; the series coupling point of the first transistor and the third transistor is electrically connected to the first capacitor; the series coupling point of the second transistor and the fourth transistor is electrically connected to the control terminal of the third transistor; the series coupling point of the second transistor and the fourth transistor is electrically connected to the second capacitor.

[0054] The storage unit manufactured by the method is a 4T2C storage unit, which includes four transistors and two capacitors. The added capacitor is connected to the data storage node, thereby increasing the storage capacitance value, storing the charge value, and extending the data retention time.

[0055] In one achievable manner, the channel materials of the first transistor, the second transistor, the third transistor, and the fourth transistor are all made of oxide semiconductor materials, which can reduce the leakage current of the memory cell.

[0056] In one achievable manner, when preparing the first transistor, the second transistor, the third transistor, the fourth transistor, the first capacitor, and the second capacitor, a back-end process is used.

[0057] The 4T2C storage unit is prepared using a back-end process to achieve three-dimensional stacking, thereby improving storage density and storage capacity.

[0058] In one achievable method, when preparing the first transistor and the second transistor, it includes: setting the first transistor and the second transistor in a first back-end device layer located in the same back-end device layer; when preparing the third transistor and the fourth transistor, it includes: setting the third transistor and the fourth transistor in a second back-end device layer located in the same back-end device layer.

[0059] The 4T2C memory cell is implemented using a double-layer back-end device layer.

[0060] In one achievable manner, after preparing the first back-end device layer and before preparing the second back-end device layer, the preparation method further includes: preparing a voltage connection metal layer for electrically connecting to the voltage end, preparing a conductive via penetrating the voltage connection metal layer, the conductive via connecting a first transistor located in the first back-end device layer and a third transistor located in the second back-end device layer, and preparing a capacitor layer between the conductive via and the voltage connection metal layer, the structure comprising at least a portion of the conductive via, at least a portion of the voltage connection metal layer, and the capacitor layer forming a first capacitor.

[0061] In one achievable manner, when preparing the first transistor, the second transistor, the third transistor and the fourth transistor, the process includes: arranging the first transistor, the second transistor, the third transistor and the fourth transistor in the same back-end device layer.

[0062] The 4T2C memory cell is implemented using a back-end device layer.

[0063] In one possible implementation, when preparing the first transistor, the second transistor, the third transistor and the fourth transistor, the method further includes:

[0064] A voltage connection metal layer electrically connected to the voltage end is prepared, the voltage connection metal layer surrounds the periphery of the gate of the third transistor, a capacitor layer is provided between the voltage connection metal layer and the gate of the third transistor, and a structure including at least a portion of the voltage connection metal layer, the capacitor layer and the gate of the third transistor forms a second capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 A circuit diagram of an electronic device;

[0066] Figure 2 A circuit diagram of a memory;

[0067] Figure 3A A packaging structure diagram of a storage array and a controller;

[0068] Figure 3B A packaging structure diagram of a storage array and a controller;

[0069] Figure 3C A packaging structure diagram of a storage array and a controller;

[0070] Figure 4 A simple circuit diagram of a memory;

[0071] Figure 5 A circuit diagram of a 4T2C storage unit provided in an embodiment of the present application;

[0072] Figure 6 The circuit diagram of a 4T2C storage unit;

[0073] Figure 7 A three-dimensional process structure diagram of a storage array provided in an embodiment of the present application;

[0074] Figure 8 A two-dimensional process structure diagram of a storage array provided in an embodiment of the present application;

[0075] Fig. 9 A three-dimensional process structure diagram of a storage array provided in an embodiment of the present application;

[0076] Fig.10 A portion of a three-dimensional process structure diagram of a storage array provided in an embodiment of the present application;

[0077] Fig.11 A two-dimensional process structure diagram of a capacitor provided in an embodiment of the present application;

[0078] Fig.12 A three-dimensional process structure diagram of a storage array provided in an embodiment of the present application;

[0079] Fig.13 A three-dimensional process structure diagram of a storage array provided in an embodiment of the present application;

[0080] Fig.14 A process structure diagram of a capacitor provided in an embodiment of the present application;

[0081] Fig.15 A flowchart of a method for preparing a storage array provided in an embodiment of the present application. DETAILED DESCRIPTION

[0082] The following embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0083] The technical solution of the present application can be applied to various electronic devices using memory, such as: Figure 1 This is a circuit block diagram of an electronic device 100 provided in an embodiment of the present application. The electronic device 100 can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc.

[0084] like Figure 1, the electronic device 100 may include a bus 205, and a system on chip (SOC) 210 connected to the bus 205. The SOC 210 may be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a first random access memory (RAM) 213 for caching high-speed data. The first RAM 213 may be a static random access memory (SRAM) or an embedded flash (EFlash), etc. The above-mentioned AP 211, GPU 212 and first RAM 213 may be integrated into a die, or may be separately set in multiple dies.

[0085] For example Figure 1 As shown, the electronic device 100 may further include a second RAM 220 connected to the SOC 210 via the bus 205. The second RAM 220 may be a dynamic random access memory (DRAM). The second RAM 220 may be used to store volatile data, such as temporary data generated by the SOC 210. The storage capacity of the second RAM 220 is generally greater than that of the first RAM 213, but the reading speed is generally slower than that of the first RAM 213.

[0086] In addition, the electronic device 100 may also include a communication chip 230 and a power management chip 240 connected to the SOC 210 via the bus 205. The communication chip 230 can be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for realizing the above functions at the same time. The power management chip 240 can be used to power other chips. In one embodiment, the SOC 210 and the second RAM 220 can be packaged in a packaging structure, such as using 2.5D (dimension) or 3D packaging, etc., to obtain a faster data transmission rate between chips and reduce the chip footprint.

[0087] like Figure 2 As shown, the memory 300 includes a storage array 31 and a controller 32 for accessing the storage array 31 , wherein the controller 32 is used to control the read and write operations of the storage array 31 .

[0088] in, Figure 2The storage array 31 and the controller 32 shown have a variety of achievable packaging structures. For example, several achievable packaging structures are given below.

[0089] Figure 3A It is one of the packaging structures of the storage array 31 and the controller 32 given in the embodiment of the present application, that is, the storage array 31 and the controller 32 are two independent chips, and the storage array 31 and the controller 32 are respectively integrated on the substrate 33. For example, the storage array 31 and the controller 32 can be electrically connected through metal traces arranged on the substrate 33. In this structure, since the storage array 31 and the controller 32 are two independent chips, the storage array 31 can be called a stand-alone memory.

[0090] Figure 3B This is another packaging structure of the storage array 31 and the controller 32 provided in the embodiment of the present application. Figure 3A Similarly, the storage array 31 and the controller 32 are two independent chips, so the storage array 31 can also be called an independent memory. Figure 3A The difference is that in Figure 3B In the embodiment, the memory array 31 and the controller 32 are stacked. For example, the memory array 31 and the controller 32 may be connected to each other through a through silicon via (TSV) or a redistribution layer (RDL).

[0091] Figure 3C This is another packaging structure of the storage array 31 and the controller 32 provided in the embodiment of the present application. In this exemplary structure, the storage array 31 and the controller 32 are integrated into the same chip 3, and the chip 3 is integrated on the substrate 33. Therefore, the storage array 31 can be called an embedded memory.

[0092] In one embodiment, the storage array 31 in the memory may include Figure 4 The memory cells 400 shown are arranged in a plurality of arrays, wherein each memory cell 400 can be used to store 1 bit (bit) or multiple bits of data. The memory array 31 can also include electrode lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to the corresponding word line WL and bit line BL. Different memory cells 400 can be electrically connected through word lines WL and bit lines BL. One or more of the above-mentioned word lines WL and bit lines BL are used to select the memory cell 400 to be read or written in the memory array by receiving the control level output by the control circuit, thereby realizing the read and write operation of the data.

[0093] The controller 32 in the memory may include Figure 4 One or more circuit structures of the decoder 320, driver 330, timing controller 340, buffer 350 or input / output driver 360 are shown.

[0094] exist Figure 4 In the memory 300 structure shown, the decoder 320 is used to decode according to the received address to determine the storage unit 400 that needs to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, so as to achieve access to the specified storage unit 400. The buffer 350 is used to cache the read data, for example, it can be cached using a first-in first-out (FIFO). The timing controller 340 is used to control the timing of the buffer 350, and control the driver 330 to drive the signal lines in the storage array 310. The input and output driver 360 is used to drive the transmission signal, such as driving the received data signal and driving the data signal to be sent, so that the data signal can be transmitted over a long distance.

[0095] The storage array 310 , decoder 320 , driver 330 , timing controller 340 , buffer 350 and input / output driver 360 may be integrated into one chip or may be integrated into multiple chips.

[0096] In some examples, the memory 300 may be electrically connected to the processor, and the memory is used to store data generated by the processor.

[0097] The memory involved in the embodiment of the present application may be a static random access memory array, and the static random access memory array may include Figure 5 The storage unit shown. Figure 5 A memory cell of the static random access memory array shown in , the memory cell may include 4 transistors and 2 capacitors, and may be referred to as a 4T2C memory cell.

[0098] for example, Figure 5 The memory cell shown includes a first transistor PG1, a second transistor PG2, a third transistor PD1 and a fourth transistor PD2, and a first capacitor C1 and a second capacitor C2.

[0099] In the storage unit circuit, the first transistor PG1 and the third transistor PD1 are coupled in series between the first bit line BL and a voltage terminal (such as a ground terminal); the second transistor PG2 and the fourth transistor PD2 are coupled in series between the second bit line BLB and a voltage terminal (such as a ground terminal); the control terminal of the first transistor PG1 and the control terminal of the second transistor PG2 are both electrically connected to the word line WL; the series coupling point of the first transistor PG1 and the third transistor PD1 is electrically connected to the control terminal of the fourth transistor PD1; the series coupling point of the first transistor PG1 and the third transistor PD1 is electrically connected to the first capacitor C1; the series coupling point of the second transistor PG2 and the fourth transistor PD2 is electrically connected to the control terminal of the third transistor PD1; the series coupling point of the second transistor PG2 and the fourth transistor PD2 is electrically connected to the second capacitor C2.

[0100] A serial coupling point of the first transistor PG1 and the third transistor PD1 forms a first data storage node Q of the memory array, and a serial coupling point of the second transistor PG2 and the fourth transistor PD2 forms a second data storage node QB of the memory array.

[0101] It can be understood that: one electrode plate of the first capacitor C1 is electrically connected to the first data storage node Q, and the other electrode plate can be grounded; one electrode plate of the second capacitor C2 is electrically connected to the second data storage node QB, and the other electrode plate can be grounded.

[0102] according to Figure 5 The circuit shown in the figure is described below. The data writing process of the storage unit is as follows:

[0103] A high potential is applied to the word line WL. When the high potential exceeds the threshold value of the first transistor PG1 and the second transistor PG2, the first transistor PG1 and the second transistor PG2 are turned on, so that the first data storage node Q is connected to the first bit line BL, and the second data storage node QB is connected to the second bit line BLB. When a high potential is applied to the first bit line BL and a low potential is applied to the second bit line BLB, the first capacitor C1 can be charged to a high potential and the second capacitor C2 can be charged to a low potential, corresponding to the writing of data "1"; when a low potential is applied to the first bit line BL and a high potential is applied to the second bit line BLB, the first capacitor C1 can be charged to a low potential and the second capacitor C2 can be charged to a high potential, corresponding to the writing of data "0".

[0104] After the first capacitor C1 and the second capacitor C2 are charged, the word line WL is placed at a low potential, and the first transistor PG1 and the second transistor PG2 can be turned off, thereby disconnecting the first data storage node Q from the first bit line BL, and disconnecting the second data storage node QB from the second bit line BLB. When storing data "1", the first data storage node Q is at a high potential, and the second data storage node QB is at a low potential, then the fourth transistor PD2 is turned on, so that the second data storage node QB is grounded, so that the second data storage node QB is maintained at a low potential, and the third transistor PD1 is turned off, so that the first data storage node Q is maintained at a high potential, thereby realizing the storage of data "1". When storing data "0", the second data storage node QB is at a high potential, and the first data storage node Q is at a low potential, then the third transistor PD1 is turned on, so that the first data storage node Q is grounded, and the first data storage node Q is maintained at a low potential, and the fourth transistor PD2 is turned off, so that the second data storage node QB is maintained at a high potential, thereby realizing the storage of data "0".

[0105] It can be understood as: Figure 5 In the storage unit shown, in the write phase, the word line WL is used to receive a first word line control signal, the first word line control signal is used to turn on the first transistor PG1 electrically connected to the first bit line BL, and is used to turn on the second transistor PG2 electrically connected to the second bit line BLB; the first bit line BL is used to receive a first bit line control signal, and the second bit line BLB is used to receive a second bit line control signal, the first bit line control signal causes the first capacitor C1 to be charged to a first potential, and the second bit line control signal causes the second capacitor C2 to be charged to a second potential less than the first potential.

[0106] After the first bit line control signal charges the first capacitor C1 to the first potential and the second bit line control signal charges the second capacitor C2 to the second potential, the word line WL is also used to receive the second word line control signal, and the second word line control signal is used to turn off the first transistor PG1 electrically connected to the first bit line BL, and to turn off the second transistor PG2 electrically connected to the second bit line BLB; the first bit line control signal turns on the fourth transistor PD2, and the second bit line control signal turns off the third transistor PD1 to achieve data storage.

[0107] Figure 6 It is another 4T storage unit. Data is stored at a first data storage node Q coupled in series with a first transistor PG1 and a third transistor PD1, and data is stored at a second data storage node QB coupled in series with a second transistor PG2 and a fourth transistor PD2. That is, data is stored using the parasitic capacitance of the transistor. The parasitic capacitance is small, the data retention time is short, and the refresh frequency is high.

[0108] Figure 6The storage unit shown in the example of this application Figure 5 The 4T2C storage unit shown in the figure has a first capacitor C1 and a second capacitor C2, which can increase the capacitance value of the stored data. According to the charge Q=UC, U is the voltage value, and C is the capacitance value. By increasing the capacitance value C, the charge Q can be increased, because the data retention time depends on the stored charge. According to Q / I=t, I is the leakage current, and t is the data retention time, when the charge Q increases, if the leakage current I remains unchanged, the data retention time t can be increased. In this way, the storage unit of the example of this application can reduce the data refresh frequency and improve the storage performance.

[0109] Compare again Figure 6 and this application Figure 5 ,exist Figure 6 In the case of a word line WL, when the voltage of the word line WL suddenly decreases, the parasitic capacitor voltage will be quickly pulled down because the parasitic capacitor used to store data is small, which will have a great impact on the data state stored on the small parasitic capacitor. Figure 5 In the present application shown in FIG. 1 , by adding a first capacitor and a second capacitor having a larger capacitance value, compared to FIG. Figure 6 With a smaller parasitic capacitance, a sudden drop in the voltage of the word line WL will not quickly pull down the storage capacitor voltage, thereby reducing the impact of the capacitive coupling effect on the data state when the word line WL is turned off. Thus, the present application can improve data storage reliability.

[0110] Figure 5 In the 4T2C memory cell shown, the first transistor PG1, the second transistor PG2, the third transistor PD1 and the fourth transistor PD2 can all be N-type field effect transistors, and the channel material of the transistor can be an oxide semiconductor material. In this way, the leakage current can be reduced. According to Q / I=t, when the charge amount Q increases and the leakage current I decreases, the data retention time t can be further increased, and the data refresh frequency can be further reduced. That is, the low leakage current characteristics of the oxide semiconductor and the increased capacitance can reduce the refresh frequency.

[0111] Among some materials that can be selected, the oxide semiconductor material may include at least one of IGZO, InGaO, ZnO, WO3, SnO2, TiO2, MoO3, and Ga2O3.

[0112] The field-effect transistor (OS-FET) process based on oxide semiconductor as the channel material is compatible with the back-end process, that is, the active device N-type field-effect transistor can be placed in the back-end device layer without complicating the process.

[0113] In order to improve storage density, storage capacity, and achieve high-capacity storage, Figure 5 The first transistor PG1, the second transistor PG2, the third transistor PD1 and the fourth transistor PD2, as well as the first capacitor C1 and the second capacitor C2 can be manufactured using a back-end process to achieve three-dimensional stacking and improve storage capacity.

[0114] against Figure 5 The storage unit shown in the embodiment of the present application provides two different process structures, which are described in detail below.

[0115] Figure 7 This is one of the process structure diagrams of the SRAM storage array given in the embodiment of the present application, and the process structure diagram embodies three 4T2C storage units.

[0116] In the memory array process structure, the first transistor PG1 and the second transistor PG2 are located in the first back-end device layer, and the third transistor PD1 and the fourth transistor PD2 are located in the second back-end device layer; the first back-end device layer and the second back-end device layer are stacked in a direction perpendicular to the memory array substrate.

[0117] In some examples, a controller electrically connected to the memory array and used to control the reading and writing of the SRAM memory array may be disposed in a front-end device layer.

[0118] The “front-end device layer” and “back-end device layer” involved in the embodiments of the present application can be understood as: Figure 8 As shown, in the chip manufacturing process, a front-end device layer can be first manufactured in a semiconductor substrate by a front-end process. The electronic devices in the front-end device layer can include transistors in a controller circuit, such as field effect transistors. The source and drain of the field effect transistor can be formed by doping in the semiconductor substrate. After the front-end device layer is manufactured, a back-end device layer can be manufactured by a back-end process, such as Figure 7 The four transistors in the exemplary memory cell may be formed in a back-end device layer using a back-end process.

[0119] like Figure 7 An example transistor can be integrated in Figure 8 In the back-end device layer shown, the interconnect routing layer is used to form metal routing to electrically connect the electronic devices in the back-end device layer. The back-end device layer and the interconnect routing layer are separated by a dielectric layer, and the back-end device layer and the interconnect routing layer can be electrically connected through conductive through holes (e.g., silicon through vias) that penetrate the dielectric layer.

[0120] exist Figure 7In the example, the first back-end device layer in which the first transistor PG1 and the second transistor PG2 are integrated can be further away from the memory array substrate than the second back-end device layer in which the third transistor PD1 and the fourth transistor PD2 are integrated. Alternatively, in some other examples, the first back-end device layer is closer to the memory array substrate than the second back-end device layer.

[0121] In the first back-end device layer, the first transistor PG1 and the second transistor PG2 are connected along a first direction (eg, Figure 7 The X direction in the figure is arranged.

[0122] In the second back-end device layer, the third transistor PD1 and the fourth transistor PD2 are also arranged along the first direction (eg Figure 7 The X direction in the figure is arranged.

[0123] The first transistor PG1 and the third transistor PD1 are arranged one above the other, and the second transistor PG2 and the fourth transistor PD2 are arranged one above the other.

[0124] In order to further improve the storage density, such as Figure 7 , the orthographic projection of the first transistor PG1 on the storage array substrate overlaps at least partially with the orthographic projection of the third transistor PD1 on the storage array substrate. The orthographic projection of the second transistor PG2 on the storage array substrate overlaps at least partially with the orthographic projection of the fourth transistor PD2 on the storage array substrate. In this way, the orthographic projection area of ​​each storage unit on the storage array substrate can be reduced, thereby improving storage density and storage capacity.

[0125] Continue reading Figure 7 and Fig. 9 , Fig. 9 yes Figure 7 Another perspective view of the process structure diagram shown. The memory array also includes: a first interconnect routing layer and a second interconnect routing layer. For example, the first interconnect routing layer is arranged on a side of the first back-end device layer away from the memory array substrate, and the second interconnect routing layer is arranged on a side of the second back-end device layer away from the memory array substrate.

[0126] Metal wiring is arranged in both the first interconnect wiring layer and the second interconnect wiring layer to electrically connect different transistors.

[0127] For example, in the second interconnect routing layer, metal routing 1 and metal routing 2 are included. Metal routing 1 is electrically connected to the first electrode of the third transistor PD1 and the gate of the fourth transistor PD2 through a conductive via. Metal routing 2 is electrically connected to the first electrode of the fourth transistor PD2 and the gate of the third transistor PD1 through a conductive via.

[0128] The first interconnection wiring layer includes metal wiring 3 and metal wiring 4. Metal wiring 3 is electrically connected to the first electrode of the first transistor PG1 through a conductive via, and metal wiring 4 is electrically connected to the first electrode of the second transistor PG2 through a conductive via.

[0129] Metal trace 3 is then electrically connected to metal trace 1 through a conductive via, so that the first transistor PG1 and the third transistor PD1 are coupled in series, and the series coupling point between the first transistor PG1 and the third transistor PD1 is electrically coupled to the gate of the fourth transistor PD2.

[0130] The metal trace 4 is then electrically connected to the metal trace 2 through a conductive via, so that the second transistor PG2 and the fourth transistor PD2 are coupled in series, and the series coupling point of the second transistor PG2 and the fourth transistor PD2 is electrically coupled to the gate of the third transistor PD1.

[0131] This application Figure 7 In the example, metal routing 1 and metal routing 2, as well as metal routing 3 and metal routing 4, are only one of the routing methods, and the present application may also adopt other routing methods.

[0132] See you next time Figure 7 and Fig. 9 The word line WL electrically connected to the gate of the first transistor PG1 and the gate of the second transistor PG2 may be disposed in the first back-end device layer, such as Figure 7 and Fig. 9 The word line WL in the substrate extends along the X direction parallel to the substrate to electrically connect the first transistor PG1 and the second transistor PG2 arranged along the X direction.

[0133] like Figure 7 and Fig. 9 The memory array may further include a third interconnect routing layer, and the third interconnect routing layer may be arranged on a side of the first interconnect routing layer away from the memory array substrate.

[0134] The first bit line BL and the second bit line BLB can be set in the third interconnect routing layer, the first bit line BL is electrically connected to the second electrode of the first transistor PG1 in the first back-end device layer through a conductive via, and the second bit line BLB is electrically connected to the second electrode of the second transistor PG2 in the first back-end device layer through a conductive via.

[0135] The first bit line BL and the second bit line BLB may be parallel to each other and may both extend along the Y direction parallel to the substrate. The first bit line BL is electrically connected to the second electrodes of the plurality of first transistors PG1 located in the Y direction, and the second bit line BLB is electrically connected to the second electrodes of the plurality of second transistors PG2 located in the Y direction.

[0136] In the example of the present application, the first electrode of the transistor is one of the source or the drain, the second electrode of the transistor is the other of the source or the drain, and the gate of the transistor can also be called a control terminal.

[0137] See Figure 7 and Fig. 9 As shown, the memory array also includes a voltage connection metal layer for electrically connecting to the voltage terminal, for example, Figure 5 As shown, the source of the third transistor PD1 and the source of the fourth transistor PD2 are both electrically connected to the voltage terminal.

[0138] The voltage connection metal layer is arranged between the first back-end device layer and the second back-end device layer. Figure 7 and Fig. 9 In the embodiment, the voltage connection metal layer is arranged between the first back-end device layer and the second interconnection wiring layer.

[0139] The source of the third transistor PD1 in the second back-end device layer may be electrically connected to the voltage connection metal layer through a conductive via 1 , and the source of the fourth transistor PD2 may be electrically connected to the voltage connection metal layer through a conductive via 2 .

[0140] like Figure 7 As shown, the first transistor PG1 located in the first back-end device layer can be coupled in series with the third transistor PD1 located in the second back-end device layer through the conductive via 3. The conductive via 3 can penetrate the voltage connection metal layer to form Figure 5 The first capacitor C1 in the circuit diagram is as follows: Fig.10 and Fig.11 A capacitor layer can be set at the interface between the conductive through hole 3 and the voltage connection metal layer. The conductive through hole 3 can serve as an electrode plate of the first capacitor C1, and the voltage connection metal layer can serve as another electrode plate of the first capacitor C1. That is, the capacitor layer, at least part of the conductive through hole 3, and at least part of the voltage connection metal layer form the first capacitor C1 structure.

[0141] Similarly, the second transistor PG2 in the first back-end device layer can be coupled in series with the fourth transistor PD2 in the second back-end device layer through the conductive via 4. The conductive via 4 can penetrate the voltage connection metal layer to form Figure 5 The second capacitor C2 in the circuit diagram can be provided with a capacitor layer at the interface between the conductive through hole 4 and the voltage-connected metal layer. The conductive through hole 4 can serve as an electrode plate of the second capacitor C2, and the voltage-connected metal layer can serve as another electrode plate of the second capacitor C2. That is, the second capacitor C2 structure is formed by at least a portion of the capacitor layer, the conductive through hole 4, and the voltage-connected metal layer.

[0142] use Fig.10 and Fig.11 The capacitor made by the structure shown has a simple process structure, does not occupy much space, and can improve storage density and storage capacity.

[0143] The capacitor layer located between the conductive via and the voltage connection metal layer may be made of a material with a high dielectric constant, for example, at least one of HfO2 and ZrO2 insulating materials may be selected.

[0144] The capacitor layer in the example of the present application may be a single-layer structure or a stacked multi-layer structure.

[0145] In some examples, the voltage connection metal layer can be as Figure 7 The plate-shaped metal layer structure is shown. In some other examples, the voltage connection metal layer may include multiple metal layers in strip-shaped structures, and the multiple strip-shaped metal layers are arranged in the same layer structure.

[0146] Prepared by back-end process Figure 7 When the storage array is shown, the first back-end device layer, dielectric layer, first interconnection routing layer, dielectric layer, voltage connection metal layer, dielectric layer, second back-end device layer, dielectric layer, second interconnection routing layer, dielectric layer and third interconnection routing layer can be sequentially manufactured along the direction perpendicular to the substrate. Conductive vias electrically connecting different layers penetrate the dielectric layer.

[0147] Fig.12 This is another process structure diagram of the SRAM storage array given in the embodiment of the present application, which embodies three 4T2C storage units.

[0148] Fig.12 In the example, the first transistor PG1, the second transistor PG2, the third transistor PD1 and the fourth transistor PD2 are arranged in the same back-end device layer. The first capacitor C1 and the second capacitor C2 may also be arranged in the back-end device layer.

[0149] In some examples, a controller electrically connected to the memory array and used to control the reading and writing of the SRAM memory array may be disposed in the front-end device layer. The memory array is disposed in the back-end device layer.

[0150] See Fig.12 and Fig.13 As shown, Fig.13 yes Fig.12 Another perspective view of the first transistor PG1 and the third transistor PD1 are arranged in a direction parallel to the memory array substrate, for example, in the Y direction, and the second transistor PG2 and the fourth transistor PD2 are also arranged in the Y direction. The first transistor PG1 and the second transistor PG2 can be arranged in the X direction, and the third transistor PD1 and the fourth transistor PD2 can be arranged in the X direction.

[0151] Since the first electrode of the first transistor PG1 is electrically connected to the first electrode of the third transistor PD1, Fig.12 The first electrode of the first transistor PG1 and the first electrode of the third transistor PD1 can be processed with the same electrode structure, that is, the first electrode of the first transistor PG1 can be the first electrode of the third transistor PD1, thereby realizing the series coupling of the first transistor PG1 and the third transistor PD1.

[0152] In some examples, since the first electrode of the second transistor PG2 is electrically connected to the first electrode of the fourth transistor PD2, as shown in FIG. Fig.12 The first electrode of the second transistor PG2 and the first electrode of the fourth transistor PD2 can be processed with the same electrode structure, that is, the first electrode of the second transistor PG2 can be the first electrode of the fourth transistor PD2, so as to realize the series coupling of the second transistor PG2 and the fourth transistor PD2.

[0153] The word line WL electrically connected to the gate of the first transistor PG1 and the gate of the second transistor PG2 may be disposed in the back-end device layer, such as Fig.12 and Fig.13 The word line WL in the substrate extends along the X direction parallel to the substrate to electrically connect the first transistor PG1 and the second transistor PG2 arranged along the X direction.

[0154] The memory array also includes a first interconnect routing layer, which can be arranged on a side of the first back-end device layer away from the memory array substrate. The back-end device layer where the first transistor PG1, the second transistor PG2, the third transistor PD1 and the fourth transistor PD2 are located can be called the first back-end device layer.

[0155] In the first interconnection wiring layer, metal wiring is arranged to electrically connect different transistors.

[0156] For example, in the first interconnect routing layer, metal routing 1 and metal routing 2 are included, metal routing 1 is electrically connected to the first electrode of the first transistor PG1 and the gate of the fourth transistor PD2 through a conductive via, and metal routing 2 is electrically connected to the first electrode of the second transistor PG2 and the gate of the third transistor PD1 through a conductive via.

[0157] This application Fig.12 and Fig.13 In the example, metal routing 1 and metal routing 2 are only one of the routing methods, and the present application may also adopt other routing methods.

[0158] See you next time Fig.12 and Fig.13, further comprising a second interconnect routing layer, which is arranged on a side of the first interconnect routing layer away from the memory array substrate, the first bit line BL and the second bit line BLB can be arranged in the second interconnect routing layer, the first bit line BL is electrically connected to the second electrode of the first transistor PG1 through a conductive via, and the second bit line BLB can be electrically connected to the second electrode of the second transistor PG2 through a conductive via.

[0159] The first bit line BL and the second bit line BLB may be parallel to each other and may both extend along the Y direction parallel to the substrate. The first bit line BL is electrically connected to the second electrodes of the plurality of first transistors PG1 located in the Y direction, and the second bit line BLB is electrically connected to the second electrodes of the plurality of second transistors PG2 located in the Y direction.

[0160] In the 4T2C memory cell of the present application example, the source of the third transistor PD1 and the source of the fourth transistor PD2 are both electrically connected to the voltage terminal (ground terminal). Fig.12 and Fig.13 In the process structure diagram shown, a voltage connection metal layer for electrically connecting to the voltage terminal may be provided.

[0161] like Fig.14 The voltage-connected metal layer surrounds the periphery of the gate of the third transistor PD1, and there is a capacitor layer between the voltage-connected metal layer and the gate interface of the third transistor PD1. The gate of the third transistor PD1 serves as one electrode plate of the capacitor, and the voltage-connected metal layer serves as another electrode plate of the capacitor. The structure including at least part of the voltage-connected metal layer, the capacitor layer and the gate of the third transistor PD1 forms a second capacitor C2.

[0162] The voltage-connected metal layer also surrounds the periphery of the gate of the fourth transistor PD2, and there is a capacitor layer between the voltage-connected metal layer and the gate interface of the fourth transistor PD2. The gate of the fourth transistor PD2 serves as one electrode plate of the capacitor, and the voltage-connected metal layer serves as another electrode plate of the capacitor. The structure including at least part of the voltage-connected metal layer, the capacitor layer and the gate of the fourth transistor PD2 forms a first capacitor C1.

[0163] The voltage connection metal layer is arranged in the back-end device layer where the four transistors are located. The voltage connection metal layer can be in a strip structure. The extension direction of the voltage connection metal layer can be consistent with the arrangement direction of the third transistor PD1 and the fourth transistor PD2, for example, extending along the X direction.

[0164] The voltage connection metal layer needs to be electrically connected to the peripheral power supply, for example, Fig.12 and Fig.13In the embodiment, a metal wiring 3 may be provided in the second interconnect wiring layer, and the metal wiring 3 is electrically connected to the voltage connection metal layer through a conductive via. The metal wiring 3 in the example may be parallel to the first bit line BL and the second bit line BLB.

[0165] Prepared by back-end process Fig.12 and Fig.13 When the storage array is shown, the back-end device layer, dielectric layer, first interconnection wiring layer, dielectric layer, and second interconnection wiring layer can be sequentially manufactured along a direction perpendicular to the substrate, and conductive vias electrically connecting different layers penetrate the dielectric layer.

[0166] The above two process structures exemplarily show the process structure of the 4T2C memory cell of the present application. In some other examples, the transistor may be a ring-gate structure, or a ring-channel structure.

[0167] The present application also provides a method for preparing a static random access memory array, such as Fig.15 , Fig.15 The flowchart of the method for preparing a static random access memory array is exemplarily shown, and the method for preparing the static random access memory array comprises:

[0168] Step S1: manufacturing a memory cell on a substrate, wherein the memory cell comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor.

[0169] In some feasible processes, the first transistor, the second transistor, the third transistor, the fourth transistor, the first capacitor and the second capacitor may be manufactured by a back-end process.

[0170] Step S2: fabricating a word line, a first bit line and a second bit line on a substrate.

[0171] Step S1 and step S2 of the examples of the present application can be interchanged with each other, or, in some examples, the preparation order of the first transistor, the second transistor, the third transistor, the fourth transistor, the first capacitor and the second capacitor, and the word line, the first bit line and the second bit line in the storage unit is not specifically limited.

[0172] In the storage array manufactured by the manufacturing method of the present application, the first transistor and the third transistor are coupled in series between the first bit line and the voltage terminal; the second transistor and the fourth transistor are coupled in series between the second bit line and the voltage terminal; the control terminal of the first transistor and the control terminal of the second transistor are both electrically connected to the word line; the series coupling point of the first transistor and the third transistor is electrically connected to the control terminal of the fourth transistor; the series coupling point of the first transistor and the third transistor is electrically connected to the first capacitor; the series coupling point of the second transistor and the fourth transistor is electrically connected to the control terminal of the third transistor; and the series coupling point of the second transistor and the fourth transistor is electrically connected to the second capacitor.

[0173] The storage unit prepared in the present application includes four transistors and two capacitors, and the two capacitors are coupled and electrically connected to the data storage node. In this way, the capacitance value used to store data can be increased, thereby increasing the amount of stored charge and extending the data storage time. In addition, the parasitic capacitance between the word line and the data storage node will also weaken the influence on the larger storage capacitance, thereby reducing the influence of the capacitive coupling effect on the data storage state and improving the reliability of the storage array.

[0174] The first transistor, the second transistor, the third transistor, and the fourth transistor in the example of the present application can be integrated in different back-end device layers. For example, the first transistor and the second transistor in the above example are located in the same back-end device layer, and the third transistor and the fourth transistor are located in the same device layer.

[0175] Alternatively, the first transistor, the second transistor, the third transistor, and the fourth transistor may be integrated in a back-end device layer.

[0176] The two capacitors can also be formed by the above method. Figure 7 and Fig.12 Example shown.

[0177] In the memory cell provided in the above embodiment, there are many materials that can be selected for the first transistor, the second transistor, the third transistor, the fourth transistor, the word line, the first bit line, and the second bit line. Some of the materials that can be selected are given below.

[0178] The source, drain and electrode lines of the transistor are all made of conductive materials, such as metal materials. In an optional embodiment, the material can be one or more of TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver) and other conductive materials.

[0179] The material of the gate dielectric layer can be one or more insulating materials such as SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide), Y2O3 (yttrium oxide) and Si3N4 (silicon nitride).

[0180] The material of the insulating dielectric layer can be one or more insulating materials such as SiO2 (silicon dioxide), Al2O3 (aluminum oxide), Si3N4 (silicon nitride), etc.

[0181] The four transistors in a memory cell in the example of the present application may all be N-type field effect transistors, which may be manufactured using a back-end process. In some examples, the N-type field effect transistor may be manufactured using an oxide semiconductor material compatible with the back-end process. The oxide semiconductor material may include at least one of IGZO, InGaO, ZnO, WO3, SnO2, TiO2, MoO3, and Ga2O3.

[0182] In this way, leakage current can be reduced. When the leakage current is reduced and the amount of stored data charge is increased, the data storage time can be further extended and the refresh frequency of the storage array can be reduced.

[0183] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0184] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A static random access memory array, characterized in that: include: A word line, a first bit line and a second bit line, and a memory cell; The storage unit comprises: A first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor; The first transistor and the third transistor are coupled in series between the first bit line and a voltage terminal; The second transistor and the fourth transistor are coupled in series between the second bit line and the voltage terminal; The control end of the first transistor and the control end of the second transistor are both electrically connected to the word line; A serial coupling point between the first transistor and the third transistor is electrically connected to a control terminal of the fourth transistor; A serial coupling point between the first transistor and the third transistor is electrically connected to the first capacitor; A serial coupling point of the second transistor and the fourth transistor is electrically connected to a control terminal of the third transistor; A series coupling point between the second transistor and the fourth transistor is electrically connected to the second capacitor.

2. The static random access memory array according to claim 1, characterized in that: The first transistor, the second transistor, the third transistor and the fourth transistor are N-type field effect transistors, and a channel material of the N-type field effect transistor includes an oxide semiconductor material.

3. The static random access memory array according to claim 1 or 2, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor, the first capacitor and the second capacitor are all manufactured by a back-end process.

4. The static random access memory array according to any one of claims 1 to 3, characterized in that: The first transistor and the second transistor are located in a first back-end device layer; The third transistor and the fourth transistor are located in a second back-end device layer; The first back-end device layer and the second back-end device layer are stacked along a direction perpendicular to the memory array substrate.

5. The static random access memory array according to claim 4, characterized in that: An orthographic projection of the first transistor on the memory array substrate at least partially overlaps with an orthographic projection of the third transistor on the memory array substrate.

6. The static random access memory array according to claim 4 or 5, characterized in that: The first transistor and the second transistor are arranged along a first direction parallel to the memory array substrate; The third transistor and the fourth transistor are arranged along the first direction.

7. The static random access memory array according to any one of claims 4 to 6, characterized in that: A voltage connection metal layer for electrically connecting to the voltage terminal is formed between the first back-end device layer and the second back-end device layer; The first electrode of the first transistor is coupled and electrically connected to the first electrode of the third transistor through a conductive via penetrating the voltage connection metal layer; A capacitor layer is formed between the conductive via and the interface of the voltage connection metal layer, and a structure including at least a portion of the conductive via, at least a portion of the voltage connection metal layer and the capacitor layer forms the first capacitor.

8. The static random access memory array according to any one of claims 4 to 7, characterized in that: The static random access memory array further comprises: a first interconnect routing layer and a second interconnect routing layer; The first interconnection wiring layer is arranged on a side of the first back-end device layer away from the memory array substrate; The second interconnection wiring layer is arranged on a side of the second back-end device layer away from the memory array substrate; The first electrode of the first transistor is electrically connected to the control terminal of the fourth transistor through the first interconnection wiring layer and the second interconnection wiring layer; The first electrode of the second transistor is electrically connected to the control terminal of the third transistor through the first interconnection wiring layer and the second interconnection wiring layer.

9. The static random access memory array according to any one of claims 4 to 8, characterized in that: The static random access memory array further comprises a third interconnect routing layer; The third interconnection wiring layer is arranged on a side of the first back-end device layer and the second back-end device layer away from the memory array substrate; The first bit line and the second bit line are formed in the third interconnect routing layer.

10. The static random access memory array according to any one of claims 1 to 3, characterized in that: The first transistor, the second transistor, the third transistor, and the fourth transistor are located in the same back-end device layer.

11. The static random access memory array according to claim 10, characterized in that: The first transistor and the third transistor are arranged along a second direction parallel to the memory array substrate; The second transistor and the fourth transistor are arranged along the second direction; The first transistor and the second transistor are arranged along a third direction parallel to the memory array substrate; The third transistor and the fourth transistor are arranged along the third direction; The third direction intersects with the second direction.

12. The static random access memory array according to claim 10 or 11, characterized in that: A voltage connection metal layer electrically connected to the voltage terminal is further provided in the back-end device layer where the first transistor, the second transistor, the third transistor and the fourth transistor are located; The voltage connection metal layer surrounds the periphery of the gate of the third transistor, and a capacitor layer is provided between the voltage connection metal layer and the gate interface of the third transistor. The structure including at least part of the voltage connection metal layer, the capacitor layer and the gate of the third transistor forms the second capacitor.

13. The static random access memory array according to any one of claims 10 to 12, characterized in that: The first transistor, the second transistor, the third transistor, and the fourth transistor are located in a first back-end device layer; The static random access memory array further comprises a first interconnection routing layer, wherein the first interconnection routing layer is located on a side of the first back-end device layer away from the memory array substrate; The first electrode of the first transistor is electrically connected to the control terminal of the fourth transistor through the first interconnection wiring layer; The first electrode of the second transistor is electrically connected to the control terminal of the third transistor through the first interconnection wiring layer.

14. The static random access memory array according to claim 13, characterized in that: The static random access memory array further comprises a second interconnection routing layer, wherein the second interconnection routing layer is located on a side of the first interconnection routing layer away from the memory array substrate; The first bit line and the second bit line are formed in the second interconnect routing layer.

15. A memory, characterized in that: include: The static random access memory array as claimed in any one of claims 1 to 14; A controller is electrically connected to the static random access memory array, and is used to control the reading and writing of the static random access memory array.

16. The memory according to claim 15, characterized in that: In the writing phase, the word line is used to receive a first word line control signal, the first bit line is used to receive a first bit line control signal, and the second bit line is used to receive a second bit line control signal; The first word line control signal is used to turn on the first transistor electrically connected to the first bit line, and to turn on the second transistor electrically connected to the second bit line. The first bit line control signal causes the first capacitor to be charged to a first potential, and the second bit line control signal causes the second capacitor to be charged to a second potential less than the first potential.

17. The memory according to claim 16, characterized in that: After the first bit line control signal causes the first capacitor to be charged to a first potential and the second bit line control signal causes the second capacitor to be charged to a second potential, the word line is further used to receive a second word line control signal, the second word line control signal is used to turn off the first transistor electrically connected to the first bit line, and is used to turn off the second transistor electrically connected to the second bit line; The first bit line control signal turns on the fourth transistor, and the second bit line control signal turns off the third transistor, thereby achieving data storage.

18. An electronic device, characterized in that: include: processor; The memory according to any one of claims 15 to 17, wherein the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

19. A control method for a static random access memory array, characterized in that: The static random access memory array comprises: A word line, a first bit line and a second bit line, and a memory cell; The storage unit comprises: A first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor; The first transistor and the third transistor are coupled in series between the first bit line and a voltage terminal; The second transistor and the fourth transistor are coupled in series between the second bit line and the voltage terminal; The control end of the first transistor and the control end of the second transistor are both electrically connected to the word line; A serial coupling point between the first transistor and the third transistor is electrically connected to a control terminal of the fourth transistor; A serial coupling point between the first transistor and the third transistor is electrically connected to the first capacitor; A serial coupling point of the second transistor and the fourth transistor is electrically connected to a control terminal of the third transistor; A serial coupling point between the second transistor and the fourth transistor is electrically connected to the second capacitor; The control method comprises: In a write phase, a first word line control signal is input to the word line, a first bit line control signal is input to the first bit line, and a second bit line control signal is input to the second bit line; The first word line control signal is used to turn on the first transistor electrically connected to the first bit line, and to turn on the second transistor electrically connected to the second bit line. The first bit line control signal causes the first capacitor to be charged to a first potential, and the second bit line control signal causes the second capacitor to be charged to a second potential less than the first potential.

20. The control method of the static random access memory array according to claim 19, characterized in that: The first bit line control signal causes the first capacitor to be charged to a first potential, and the second bit line control signal causes the second capacitor to be charged to a second potential, and then a second word line control signal is input to the word line, wherein the second word line control signal is used to turn off the first transistor electrically connected to the first bit line, and to turn off the second transistor electrically connected to the second bit line; The first bit line control signal turns on the fourth transistor, and the second bit line control signal turns off the third transistor, thereby achieving data storage.

21. A method for preparing a static random access memory array, characterized in that: The preparation method comprises: A memory cell is manufactured on a substrate, wherein the memory cell comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor; Fabricating a word line, a first bit line, and a second bit line on a substrate; wherein the first transistor and the third transistor are coupled in series between the first bit line and a voltage terminal; The second transistor and the fourth transistor are coupled in series between the second bit line and the voltage terminal; The control end of the first transistor and the control end of the second transistor are both electrically connected to the word line; A serial coupling point between the first transistor and the third transistor is electrically connected to a control terminal of the fourth transistor; A serial coupling point between the first transistor and the third transistor is electrically connected to the first capacitor; A serial coupling point of the second transistor and the fourth transistor is electrically connected to a control terminal of the third transistor; A series coupling point between the second transistor and the fourth transistor is electrically connected to the second capacitor.

22. The method for preparing a static random access memory array according to claim 21, characterized in that: When preparing the first transistor, the second transistor, the third transistor, the fourth transistor, the first capacitor and the second capacitor, a back-end process is adopted.

23. The method for preparing a static random access memory array according to claim 21 or 22, characterized in that: When preparing the first transistor and the second transistor, the method includes: disposing the first transistor and the second transistor in a first back-end device layer located in the same back-end device layer; When preparing the third transistor and the fourth transistor, the method includes: arranging the third transistor and the fourth transistor in a second back-end device layer located in the same back-end device layer.

24. The method for preparing a static random access memory array according to claim 23, characterized in that: After the first back-end device layer is prepared and before the second back-end device layer is prepared, the preparation method further includes: A voltage connection metal layer for electrically connecting to a voltage terminal is prepared, a conductive via penetrating the voltage connection metal layer is prepared, the conductive via connects the first transistor located in the first back-end device layer and the third transistor located in the second back-end device layer, and a capacitor layer is prepared between the conductive via and the voltage connection metal layer, and a structure including at least a portion of the conductive via, at least a portion of the voltage connection metal layer and the capacitor layer forms the first capacitor.

25. The method for preparing a static random access memory array according to claim 21 or 22, characterized in that: When preparing the first transistor, the second transistor, the third transistor and the fourth transistor, it includes: arranging the first transistor, the second transistor, the third transistor and the fourth transistor in the same back-end device layer.

26. The method for preparing a static random access memory array according to claim 25, characterized in that: When preparing the first transistor, the second transistor, the third transistor and the fourth transistor, the method further includes: A voltage connection metal layer electrically connected to the voltage terminal is prepared, the voltage connection metal layer surrounds the periphery of the gate of the third transistor, a capacitor layer is provided between the voltage connection metal layer and the gate of the third transistor, and a structure including at least a portion of the voltage connection metal layer, the capacitor layer and the gate of the third transistor forms the second capacitor.

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