Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device manufacturing method includes depositing a first thin polysilicon layer on an active region using a first atomic layer deposition, where the active region includes a trench; depositing a second thin polysilicon layer on the active region using a second atomic layer deposition; and depositing a polycrystalline silicon layer on the active region using chemical vapor deposition to form a polycrystalline silicon structure wherein the gas used for chemical vapor deposition comprises disilane, the thickness of the polycrystalline silicon layer in the bottom of the trench being substantially zero. The manufacturing method of the semiconductor device comprises first atomic layer deposition, second atomic layer deposition and chemical vapor deposition, and the thickness of a polycrystalline silicon layer grown through the chemical vapor deposition is gradually reduced from the top part of the side wall of the polycrystalline silicon layer to the bottom part of the side wall of the polycrystalline silicon layer, which means that no polycrystalline silicon is grown at the bottom of a groove; therefore, while the area of the array is enlarged, the possibility of short circuit at the bottom of the groove is eliminated.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced successive generations of ICs, each with smaller and more complex circuits than the previous generation. In DRAM cell manufacturing, after etching the active area, a thin layer of polysilicon is applied to the array to expand the area of ​​the array. However, the processes used in the growth of the thin polysilicon layer often cause polysilicon to grow at the bottom of the trench, where the polysilicon layer does not need to be grown and there is a risk of short circuits. Summary of the invention

[0003] One aspect of the present invention provides a method for manufacturing a semiconductor device.

[0004] According to one embodiment of the present invention, a method for manufacturing a semiconductor device includes: using a first atomic layer deposition to deposit a first thin polysilicon layer on an active region, wherein the active region includes a trench; using a second atomic layer deposition to deposit a second thin polysilicon layer on the active region; and using chemical vapor deposition to deposit a polysilicon layer on the active region to form a polysilicon structure, wherein the gas used for the chemical vapor deposition includes disilane, and the thickness of the polysilicon layer in the bottom of the trench is substantially zero.

[0005] In some embodiments of the present invention, the semiconductor device manufacturing method further includes etching a substrate to form the active region.

[0006] In some embodiments of the present invention, the semiconductor device manufacturing method further includes filling the trench with a dielectric material to form a shallow trench isolation.

[0007] In some embodiments of the present invention, a ratio of a thickness of a top portion of a sidewall of the polysilicon structure to a thickness of a top plane of the polysilicon structure is in a range of 0.6 to 0.7.

[0008] In some embodiments of the present invention, a ratio of a thickness of a middle portion of a sidewall of the polysilicon structure to a thickness of a top plane of the polysilicon structure is in a range of 0.6 to 0.7.

[0009] In some embodiments of the present invention, a ratio of a thickness of a bottom portion of a sidewall of the polysilicon structure to a thickness of a top plane of the polysilicon structure is in a range of 0.35 to 0.45.

[0010] In some embodiments of the present invention, the gas used in the first atomic layer deposition comprises dichlorosilane.

[0011] Another aspect of the present invention provides a method for manufacturing a semiconductor device.

[0012] According to one embodiment of the present invention, a method for manufacturing a semiconductor device includes: using first atomic layer deposition to deposit a first thin polysilicon layer on an active region, wherein the active region includes a trench, and the gas used in the first atomic layer deposition includes dichlorosilane; using second atomic layer deposition to deposit a second thin polysilicon layer on the active region; and using chemical vapor deposition to deposit a polysilicon layer on the active region to form a polysilicon structure, wherein the gas used for the chemical vapor deposition includes disilane.

[0013] In some embodiments of the present invention, the semiconductor device manufacturing method further includes etching a substrate to form the active region.

[0014] In some embodiments of the present invention, the semiconductor device manufacturing method further includes filling the trench with a dielectric material to form a shallow trench isolation.

[0015] In some embodiments of the present invention, a ratio of a thickness of a top portion of a sidewall of the polysilicon structure to a thickness of a top plane of the polysilicon structure is in a range of 0.6 to 0.7.

[0016] In some embodiments of the present invention, a ratio of a thickness of a middle portion of a sidewall of the polysilicon structure to a thickness of a top plane of the polysilicon structure is in a range of 0.6 to 0.7.

[0017] In some embodiments of the present invention, a ratio of a thickness of a bottom portion of a sidewall of the polysilicon structure to a thickness of a top plane of the polysilicon structure is in a range of 0.35 to 0.45.

[0018] In some embodiments of the present invention, the gas used in the second atomic layer deposition includes disilane.

[0019] Another aspect of the present invention provides a semiconductor device.

[0020] According to one embodiment of the present invention, a semiconductor device includes a substrate and a polysilicon layer. The substrate includes an active region. The active region includes a trench. The polysilicon layer is located on the active region, wherein the thickness of the polysilicon layer gradually decreases from the top portion of the sidewall of the polysilicon layer to the bottom portion of the sidewall of the polysilicon layer.

[0021] In some embodiments of the present invention, the thickness of the polysilicon layer on the bottom of the trench is substantially zero.

[0022] In some embodiments of the present invention, a ratio of a thickness of the top portion of the sidewall of the polysilicon layer to a thickness of a top plane of the polysilicon layer is in a range of 0.6 to 0.7.

[0023] In some embodiments of the present invention, a ratio of a thickness of a middle portion of the sidewall of the polysilicon layer to a thickness of a top plane of the polysilicon layer is in a range of 0.6 to 0.7.

[0024] In some embodiments of the present invention, a ratio of a thickness of the bottom portion of the sidewall of the polysilicon layer to a thickness of a top plane of the polysilicon layer is in a range of 0.35 to 0.45.

[0025] In some embodiments of the present invention, the polysilicon layer is formed by first atomic layer deposition, second atomic layer deposition and chemical vapor deposition.

[0026] In the above-mentioned embodiment of the present invention, since the semiconductor device manufacturing method includes a first atomic layer deposition, a second atomic layer deposition and a chemical vapor deposition, the thickness of the polysilicon layer grown by the chemical vapor deposition gradually decreases from the top portion of the side wall of the polysilicon layer to the bottom portion of the side wall of the polysilicon layer, which means that no polysilicon is grown at the bottom of the trench, thereby expanding the area of ​​the array while eliminating the possibility of causing a short circuit at the bottom of the trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0028] Figures 2 to 6 2 is a cross-sectional view showing an intermediate step of a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] Embodiments of the present invention can be best understood from the following detailed description and the appended claims. It is emphasized that, according to standard practice in the industry, various features are not necessarily drawn to scale. In fact, the size of various features may be arbitrarily enlarged or reduced for clarity of discussion.

[0030] The following disclosure provides many different embodiments or examples for implementing the different features of the provided theme. The specific examples of the components and configurations are described below to simplify the present invention. Of course, these components and configurations are merely examples and are not intended to be limiting. In addition, the present invention can repeat reference numerals and / or letters in various examples. This repetition is for simple and clear purposes, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0031] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0032] The terms "about," "approximately," or "substantially" as used herein include values ​​and averages within an acceptable tolerance range for a particular value determined by one of skill in the art taking into account the particular measurement quantity at issue and the measurement-related errors (i.e., the limitations of the measurement system). For example, "about" may indicate within one or more standard deviations of a value, or within ±30%, ±20%, ±10%, or ±5% of a value. In addition, for the terms "about," "approximately," or "substantially" as used herein, a relative acceptable tolerance range or standard deviation may be selected based on the optical properties, etching properties, or other properties, rather than applying one standard to all properties.

[0033] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 A method for manufacturing a semiconductor device comprises the following steps. First, in step S1, a first thin polysilicon layer is deposited on an active region using a first atomic layer deposition, wherein the active region includes a trench. Then, in step S2, a second thin polysilicon layer is deposited on the active region using a second atomic layer deposition. Finally, in step S3, a polysilicon layer is deposited on the active region using chemical vapor deposition, wherein the gas used for chemical vapor deposition includes disilane, and the thickness of the polysilicon layer at the bottom of the trench is zero.

[0034] In some embodiments, the semiconductor device manufacturing method is not limited to the steps S1 to S3 mentioned above. For example, in some embodiments, other steps may be further included between two steps of steps S1 to S3, before step S1, or after step S3. In the following description, at least the above steps are described in detail.

[0035] Figures 2 to 6 1 is a cross-sectional view of an intermediate step of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 First, the substrate 110 is etched to form the active region 112. The etching of the active region 112 may be dry etching, wet etching, or a combination thereof. Figure 2In the embodiment, two arrays 114 are shown, but the present invention is not limited thereto. In fact, more arrays 114 can be formed in this step. The array 114 formed in this step has the property of a large aspect ratio. In other words, the groove 115 between the two arrays 114 is both narrow and deep. In some embodiments, the depth of the groove 115 is in the range of 270 nanometers to 300 nanometers, and the width of the groove 115 is in the range of 2.5 nanometers to 3.5 nanometers. In some embodiments, the width of the array 114 is in the range of 7 nanometers to 13 nanometers.

[0036] Afterwards, refer to Figure 3 , using the first atomic layer deposition, a first thin polysilicon layer 122 is deposited on the active region 112. The gas used in the first atomic layer deposition includes dichlorosilane (Si2Cl2H2, DCS). During this process, a thin polysilicon layer will grow on the active region 112. That is, polysilicon will grow on the array 114 and at the bottom of the trench 115. However, in Figure 3 In the embodiment of the present invention, the polysilicon at the bottom of the trench 115 is ignored. The first thin polysilicon layer 122 functions as a seed layer for polysilicon, which will grow in the subsequent process. In some embodiments, after the first atomic layer deposition, a purge process is performed to remove excess gas. The gas used for purge may include nitrogen (N2), argon (Ar), a combination thereof, or other suitable gases.

[0037] Afterwards, refer to Figure 4 , a second thin polysilicon layer 124 is deposited on the active region 112 using a second atomic layer deposition. The gas used in the second atomic layer deposition includes dichlorosilane (Si2Cl2H2, DCS). During this process, a thin polysilicon layer will grow on the active region 112. That is, polysilicon will grow on the array 114 and at the bottom of the trench 115. However, in Figure 4 In the embodiment of the present invention, the polysilicon at the bottom of the trench 115 is ignored. The function of the second thin polysilicon layer 124 is a seed layer for polysilicon, which will grow in the subsequent process. In some embodiments, after the first atomic layer deposition, a purge process is performed to remove excess gas. The gas used for purge may include nitrogen (N2), argon (Ar), a combination thereof, or other suitable gases.

[0038] Afterwards, refer to Figure 5, using chemical vapor deposition, a polysilicon layer 126 is deposited on the active region 112 to form a polysilicon structure 120, wherein the gas used for chemical vapor deposition includes disilane (Si2H6), and the thickness of the polysilicon layer in the bottom of the trench 115 is substantially zero. The chemical vapor deposition process uses the first thin polysilicon layer 122 and the second thin polysilicon layer 124 as seed layers for growth, so that the film grown on the array 114 is dense. Since the step coverage of the chemical vapor deposition process using disilane gas is uneven compared to the previous atomic layer deposition, the thickness of the top portion of the sidewall of the polysilicon structure 120 is greater than the thickness of the bottom portion of the sidewall of the polysilicon structure 120. In some embodiments, the ratio of the thickness T1 of the top portion of the sidewall of the polysilicon structure 120 to the thickness T4 of the top plane of the polysilicon structure 120 is in the range of 0.6 to 0.7. In some embodiments, a ratio of a thickness T2 of a middle portion of the sidewall of the polysilicon structure 120 to a thickness T4 of a top plane of the polysilicon structure 120 is in a range of 0.6 to 0.7. In some embodiments, a ratio of a thickness T3 of a bottom portion of the sidewall of the polysilicon structure 120 to a thickness T4 of a top plane of the polysilicon structure is in a range of 0.35 to 0.45. The thickness of the polysilicon layer on the bottom of the trench 115 is substantially zero.

[0039] Afterwards, refer to Figure 6 The trench is filled with a dielectric material to form a shallow trench isolation (STI) 130. The function of the shallow trench isolation 130 is to electrically isolate the array 114. Figure 5 ) is substantially zero, so there is no risk of short circuit at the bottom of the trench 115, so that the shallow trench isolation 130 can properly isolate the array. The dielectric material of the shallow trench isolation 130 can include silicon oxide (SiO2) or other suitable dielectric materials. After this step, the semiconductor device 100 is manufactured.

[0040] In summary, since the manufacturing method of the semiconductor device 100 includes a first atomic layer deposition, a second atomic layer deposition and a chemical vapor deposition, the thickness of the polysilicon structure 120 grown by chemical vapor deposition gradually decreases from the top portion of the side wall of the polysilicon structure 120 to the bottom portion of the side wall of the polysilicon structure 120, which means that no polysilicon is grown at the bottom of the trench 115, thereby expanding the area of ​​the array 114 while eliminating the possibility of causing a short circuit at the bottom of the trench 115.

[0041] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that this equivalent construction does not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and changes may be made herein without departing from the spirit and scope of the present invention.

[0042]

Explanation of symbols

[0043] 100:Semiconductor device

[0044] 110:Substrate

[0045] 112: Active area

[0046] 114: Array

[0047] 115: Groove

[0048] 120: Polysilicon structure

[0049] 122: first thin polysilicon layer

[0050] 124: Second thin polysilicon layer

[0051] 126: Polysilicon layer

[0052] 130: Shallow Trench Isolation

[0053] S1: Steps

[0054] S2: Steps

[0055] S3: Steps

[0056] T1: Thickness

[0057] T2: Thickness

[0058] T3:Thickness

[0059] T4: Thickness.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: depositing a first thin polysilicon layer on an active region using a first atomic layer deposition, wherein the active region includes a trench; depositing a second thin polysilicon layer on the active region using a second atomic layer deposition; as well as A polysilicon layer is deposited on the active region to form a polysilicon structure using chemical vapor deposition, wherein a gas used for the chemical vapor deposition includes disilane, and a thickness of the polysilicon layer in the bottom of the trench is zero.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Further comprising the steps of: The substrate is etched to form the active region.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: Further comprising the steps of: The trench is filled with a dielectric material to form a shallow trench isolation.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: Wherein a ratio of a thickness of a top portion of a sidewall of the polysilicon structure to a thickness of a top plane of the polysilicon structure is in a range of 0.6 to 0.

7.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: A ratio of a thickness of a middle portion of a sidewall of the polysilicon structure to a thickness of a top plane of the polysilicon structure is in a range of 0.6 to 0.

7.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: A ratio of a thickness of a bottom portion of a sidewall of the polysilicon structure to a thickness of a top plane of the polysilicon structure is in a range of 0.35 to 0.

45.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The gas used in the first atomic layer deposition includes dichlorosilane.

8. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Depositing a first thin polysilicon layer on an active region using a first atomic layer deposition, wherein the active region includes a trench, wherein a gas used in the first atomic layer deposition includes dichlorosilane; depositing a second thin polysilicon layer on the active region using a second atomic layer deposition; and A polysilicon layer is deposited on the active region to form a polysilicon structure using chemical vapor deposition, wherein a gas used for the chemical vapor deposition includes disilane.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: Further comprising the steps of: The substrate is etched to form the active region.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: Further comprising the steps of: The trench is filled with a dielectric material to form a shallow trench isolation.

11. The method for manufacturing a semiconductor device according to claim 8, wherein: Wherein a ratio of a thickness of a top portion of a sidewall of the polysilicon structure to a thickness of a top plane of the polysilicon structure is in a range of 0.6 to 0.

7.

12. The method for manufacturing a semiconductor device according to claim 8, wherein: A ratio of a thickness of a middle portion of a sidewall of the polysilicon structure to a thickness of a top plane of the polysilicon structure is in a range of 0.6 to 0.

7.

13. The method for manufacturing a semiconductor device according to claim 8, wherein: A ratio of a thickness of a bottom portion of a sidewall of the polysilicon structure to a thickness of a top plane of the polysilicon structure is in a range of 0.35 to 0.

45.

14. The method for manufacturing a semiconductor device according to claim 8, wherein: The gas used in the second atomic layer deposition includes disilane.

15. A semiconductor device, characterized in that: include: a substrate, wherein the substrate includes an active region, the active region including a trench; as well as The polysilicon layer is located on the active region, wherein the thickness of the polysilicon layer gradually decreases from the top portion of the sidewall of the polysilicon layer to the bottom portion of the sidewall of the polysilicon layer.

16. The semiconductor device according to claim 15, wherein: The thickness of the polysilicon layer on the bottom of the trench is zero.

17. The semiconductor device according to claim 15, wherein: Wherein a ratio of a thickness of the top portion of the sidewall of the polysilicon layer to a thickness of a top plane of the polysilicon layer is in a range of 0.6 to 0.

7.

18. The semiconductor device according to claim 15, wherein: A ratio of a thickness of a middle portion of the sidewall of the polysilicon layer to a thickness of a top plane of the polysilicon layer is in a range of 0.6 to 0.

7.

19. The semiconductor device according to claim 15, wherein: A ratio of a thickness of the bottom portion of the sidewall of the polysilicon layer to a thickness of a top plane of the polysilicon layer is in a range of 0.35 to 0.

45.

20. The semiconductor device according to claim 15, wherein: The polysilicon layer is formed by first atomic layer deposition, second atomic layer deposition and chemical vapor deposition.

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