In-situ plasma processing prior to Al2O3 deposition for improved Ron
By inactive the Mg of the AlGaN layer before Al2O3 deposition, the problem of increasing block resistance of the AlGaN layer in GaN HEMT is solved, and the on-resistance performance of the HEMT is improved, power consumption is reduced and process flow is simplified.
Patent Information
- Application Number
- CN202411442157.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-30
- Filing Date
- 2024-10-16
- Publication Date
- 2025-05-02
AI Technical Summary
During the manufacturing process, the block resistance of the existing GaN HEMT increases due to the etching of the p-GaN layer, which in turn affects the on-resistance (Ron) performance of the HEMT.
The in-situ plasma treatment before Al2O3 deposition is used, and the Mg of the AlGaN layer is deactivated by hydrogen plasma treatment, thereby reducing the block resistance of 2DEG and thus improving the Ron performance of HEMT.
By reducing the block resistance of 2DEG, the power required for the normally off power device to transition to the on state is reduced and the process flow is simplified, avoiding additional cleaning and passivation operations.
Smart Images
Figure CN119922930A_ABST
Abstract
Description
Technical Field
[0001] Example embodiments of the present disclosure generally relate to high electron mobility transistors (HEMTs), including fabrication utilizing in-situ hydrogen-based plasma treatment prior to Al 2 O 3 deposition to improve Ron (on-resistance) during fabrication. Background Art
[0002] GaN HEMTs are typically depletion mode transistors, which may be referred to as normally-off HEMTs. These normally-off HEMTs may use GaN with p-doping to form a p-GaN gate of the normally-off HEMT. However, the fabrication of p-GaN may result in an increase in the sheet resistance of the AlGaN layer in the HEMT.
[0003] The inventors have identified numerous areas of improvement in the prior art and technology, which are the subject of the embodiments described herein. Through applied effort, ingenuity and innovation, many of these deficiencies, challenges and problems have been addressed by developing solutions included in the embodiments of the present disclosure, some examples of which are described in detail herein. Summary of the invention
[0004] Various embodiments described herein relate to high electron mobility transistors (HEMTs), including fabrication using in-situ plasma processing.
[0005] According to some embodiments of the present disclosure, an example method for manufacturing an integrated circuit is provided. The method for manufacturing an integrated circuit may include: providing a wafer including an AlGaN layer having a first surface and a p-GaN layer on a first of the AlGaN layers; etching the p-GaN layer to form at least a first p-GaN gate; depositing a first aluminum oxide layer over the first p-GaN gate; depositing a first silicon dioxide layer over the first aluminum oxide layer; etching the first silicon dioxide layer and the first aluminum oxide layer to expose a first portion of the AlGaN layer, the first portion starting at a first distance from the first p-GaN gate; treating the first portion of the AlGaN layer with an in-situ plasma-based hydrogen treatment, wherein the in-situ plasma treatment containing hydrogen deactivates magnesium in the first portion of the AlGaN layer; and forming at least a first normally-off HEMT, wherein the gate of the normally-off HEMT is the first p-GaN gate.
[0006] In some embodiments, forming the first normally-off HEMT includes depositing at least a second aluminum oxide layer and a second silicon dioxide layer.
[0007] In some embodiments, treating the first portion of the AlGaN layer with the in-situ plasma treatment does not deactivate Mg in another portion of the AlGaN layer associated below the first p-GaN gate.
[0008] In some embodiments, the in-situ plasma treatment includes diffusing hydrogen into the first portion of the AlGaN layer.
[0009] In some embodiments, the first distance is at least 200 nm.
[0010] In some embodiments, forming the first normally-off HEMT further includes depositing metallization layers associated with the first normally-off HEMT gate, the first normally-off HEMT source, and the first normally-off HEMT drain.
[0011] In some embodiments, forming the first normally-off HEMT further includes depositing at least a first metal shielding layer.
[0012] In some embodiments, the p-GaN gate includes a TiN layer.
[0013] In some embodiments, the method further includes depositing a third aluminum oxide layer over the p-GaN gate after etching the first silicon dioxide layer and the first aluminum oxide layer but before the in-situ plasma treatment.
[0014] In some embodiments, etching the first silicon dioxide layer and the first aluminum oxide layer further exposes a second portion of the AlGaN layer, the second portion being a second distance from a second side of the p-GaN gate; and treating the first portion of the AlGaN layer with the in-situ plasma hydrogen-based treatment further comprises treating the second portion of the AlGaN layer with the in-situ plasma hydrogen-based treatment.
[0015] According to some embodiments of the present disclosure, an example normally-off HEMT is provided. The normally-off HEMT includes a p-GaN gate on an AlGaN layer; wherein the p-GaN gate is covered by a first aluminum oxide layer and a first silicon dioxide layer; wherein the AlGaN layer includes a first portion of the AlGaN layer, the first portion starting at a first distance from the first p-GaN gate, and wherein the first portion of the AlGaN layer is not covered by the first aluminum oxide layer and the first silicon dioxide layer; and wherein the first portion of the AlGaN layer has deactivated Mg from an in-situ plasma treatment.
[0016] In some embodiments, the normally-off HEMT further includes at least a second aluminum oxide layer and a second silicon dioxide layer.
[0017] In some embodiments, the AlGaN layer includes non-deactivated Mg in another portion associated below the first p-GaN gate.
[0018] In some embodiments, the deactivated Mg includes Mg—H complexes from hydrogen diffused from the in-situ plasma treatment.
[0019] In some embodiments, the first distance is at least 200 nm.
[0020] In some embodiments, the normally-off HEMT further comprises a plurality of metallization layers, the plurality of metallization layers comprising a first metallization layer associated with the first normally-off HEMT gate, a second metallization layer associated with the first normally-off HEMT source, and a third metallization layer associated with the first normally-off HEMT drain.
[0021] In some embodiments, the normally-off HEMT further includes at least one metal shielding layer.
[0022] In some embodiments, the p-GaN gate includes a TiN layer.
[0023] In some embodiments, the normally-off HEMT further includes a third aluminum oxide layer of the p-GaN gate.
[0024] In some embodiments, the AlGaN layer further includes a second portion of the AlGaN layer that starts at a second distance from the first p-GaN gate on a side of the p-GaN gate opposite the first portion of the AlGaN layer, and wherein the second portion of the AlGaN layer is not covered by the first aluminum oxide layer and the first silicon dioxide layer; and the second portion of the AlGaN layer has deactivated Mg from the in-situ plasma hydrogen-based treatment.
[0025] The above summary of the invention is provided only for the purpose of summarizing some example embodiments to provide a basic understanding of some aspects of the present disclosure. Therefore, it will be understood that the above embodiments are merely examples and should not be interpreted as narrowing the scope or spirit of the present disclosure in any way. It will also be understood that the scope of the present disclosure also covers many possible embodiments in addition to those summarized here, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Having thus generally described certain example embodiments of the present disclosure, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:
[0027] Figure 1 illustrates a first cross-sectional view of a block diagram of a first exemplary power device according to one or more embodiments of the present disclosure;
[0028] Figure 2 illustrates a first example flow chart of operations for manufacturing a power device according to one or more embodiments of the present disclosure;
[0029] Figure 3A-3H illustrates an example block diagram associated with operations for manufacturing a power device according to one or more embodiments of the present disclosure;
[0030] Figure 4illustrates a second example flow chart of operations for manufacturing a power device according to one or more embodiments of the present disclosure;
[0031] Figure 5A-Figure 5C illustrates an example block diagram associated with operations for manufacturing a power device according to one or more embodiments of the present disclosure;
[0032] Figure 6 A third example flow chart illustrating operations for manufacturing a power device according to one or more embodiments of the present disclosure; and
[0033] Figure 7A-7C An example block diagram associated with operations for fabricating a power device according to one or more embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION
[0034] Some embodiments of the present disclosure will now be described more fully herein with reference to the accompanying drawings, in which some but not all embodiments of the present disclosure are shown. Indeed, the various embodiments of the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.
[0035] As used herein, the term "comprising" means including, but not limited to, and should be interpreted in the manner in which it is commonly used in a patent context. The use of broader terms such as including, comprising, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and consisting substantially of.
[0036] The phrases "in various embodiments," "in one embodiment," "according to one embodiment," "in some embodiments," etc. generally mean that the specific feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).
[0037] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.
[0038] If the specification states that a component or feature "may", "could", "should", "would", "preferably", "perhaps", "usually", "optionally", "for example", "often" or "might" (or other such language) be included or have a feature, then no particular component or feature is required to be included or have that feature. Such a component or feature may optionally be included in some embodiments or it may be excluded.
[0039] As used herein, the use of the term "circuitry" with respect to components of a system or device should be understood to include specific hardware configured to perform functions associated with a specific circuitry as described herein. The term "circuitry" should be broadly understood to include hardware and, in some embodiments, software for configuring the hardware. For example, in some embodiments, "circuitry" may include processing circuitry, communication circuitry, input / output circuitry, etc. In some embodiments, other elements may provide or supplement the functionality of a specific circuitry.
[0040] Overview
[0041] Various embodiments of the present disclosure are directed to improved HEMTs, including fabricating normally-on HEMTs with in-situ plasma treatment prior to Al2O3 deposition to improve Ron during fabrication.
[0042] A normally-off GaN HEMT may include a p-GaN gate doped with Mg. The p-doped gate allows depletion of electrons to result in a normally-off device. A normally-off HEMT power device requires a voltage to be applied to the gate to transition or switch the HEMT power device to an on state and conduct current.
[0043] To form a p-doped GaN gate, a wafer having a silicon dioxide layer below a GaN layer below an AlGaN layer may have a GaN layer grown or formed on top. This top GaN layer may be doped with Mg to obtain a p-type doped GaN layer. Thus, during the growth of p-type GaN, the AlGaN may be affected by the diffusion of Mg into the AlGaN layer. The p-GaN layer may be etched to form a p-GaN gate. However, the 2DEG block resistance of the finished power device is significantly affected by the growth and etching of p-GaN, including increasing the resistance of Ron. This is because the p-GaN etching damages the surface of the AlGaN layer. Because the p-GaN layer etched on the AlGaN layer is not perfectly selective to only etch the p-GaN layer without affecting the AlGaN layer, the surface is damaged.
[0044] According to the present disclosure, improving the Ron of a power device can be accomplished by reducing the 2DEG Rsh, particularly in one or more regions where p-GaN etching has been performed. An aluminum oxide layer can also be deposited over the region receiving a plasma treatment containing hydrogen, such as H2 and NH3, diluted in Ar and N2. Post-pGaN etch deactivation of Mg diffused into the second portion of the AlGaN layer can reduce the 2DEG sheet resistance. In hydrogen-rich ambient temperatures, hydrogen atoms form Mg-H complexes, thereby preventing Mg from acting as an acceptor. The aluminum oxide layer can also improve Ron. Successful surface passivation by aluminum oxide prevents surface states from being neutralized by trapped electrons and results in improved 2DEG sheet resistance.
[0045] In various embodiments, an in-situ plasma treatment is used to deactivate Mg in the AlGaN layer. During the in-situ plasma treatment, the region including the p-GaN gate is covered with a dielectric (e.g., a silicon dioxide layer and aluminum oxide) to protect the region from the plasma treatment and, therefore, not deactivate Mg in this region. Additionally or alternatively, various embodiments include multiple aluminum oxide layers, including an aluminum oxide layer contacted by the AlGaN layer that reduces the 2DEG sheet resistance (Rsh), which improves Ron. By reducing the 2DEG Rsh, the power required to transition a normally-off power device to an on state can be reduced. Additionally or alternatively, area consumption can be reduced by reducing the amount of distance required for plasma treatment.
[0046] Additionally or alternatively, another advantage of the present disclosure is that the plasma treatment of the present disclosure can be applied in situ prior to the deposition of the passivation layer. Such in situ plasma treatment simplifies the process flow and avoids the additional manufacturing time associated with ex situ cleaning processes and passivation operations that may affect exposed surfaces.
[0047] The power devices of the present disclosure may be used in a wide variety of applications. For example, various embodiments of the present disclosure may be used in 100 V to 650 V p-GaN HEMTs used in DC-DC converter applications.
[0048] Exemplary methods, systems, and apparatus
[0049] Figure 1 A first cross-sectional view of a block diagram of a first exemplary power device according to one or more embodiments of the present disclosure is illustrated. Figure 1 The example power device illustrated in is after completion of fabrication operations of the example method, which operations are further described herein.
[0050] like Figure 1As shown in , the power device 100 may include a normally-off p-GaN HEMT. The power device 100 may be on top of a silicon dioxide layer 110, which is below a p-GaN layer 112, which is below an AlGaN layer 114. Above the AlGaN layer 114 is a p-GaN gate 120. The p-GaN gate 120 may initially be part of a p-GaN layer that is etched to leave a region for the p-GaN gate 120. For example, a wafer may be provided with a silicon dioxide layer 110, a p-GaN layer 112, and an AlGaN layer 114. This p-GaN layer including the region for the p-GaN gate 120 may be grown or formed as a GaN layer on the AlGaN layer 114 and then implanted with Mg to form this p-GaN layer. To form the p-GaN gate 120 , the p-GaN layer may be etched such that only a remnant of the p-GaN gate 120 of the power device 100 remains.
[0051] In various embodiments, the p-GaN gate 120 may have a TiN layer 124 on top of the p-GaN gate 120. A first aluminum oxide layer 130 is deposited on the sidewalls of and around the p-GaN gate 120. A first silicon dioxide layer 140 may be deposited over the first aluminum oxide layer 130, which are shown in cross-sectional views as 140A and 140B.
[0052] The normally-off p-GaN HEMT of the power device 100 may include a gate, a source, and a drain. The metal contact to the gate of the normally-off p-GaN HEMT is shown as metallization layer 150. The metal contact to the source of the normally-off p-GaN HEMT is shown as metallization layer 152. The metal contact to the drain of the normally-off p-GaN HEMT is shown as metallization layer 154. The normally-off p-GaN HEMT 102 may also include one or more other metal shields 156 (e.g., 156A, 156B) for controlling the electric field generated when the power device is operating.
[0053] The gate of the normally-off p-GaN HEMT is located at a separation distance 160 from the drain of the normally-off p-GaN HEMT. The separation distance includes a first distance 162 and a second distance 164. The first distance 162 is the distance from the p-GaN gate 120 to the end of the first aluminum oxide layer 130. The second distance 1644 is the distance from the end of the first aluminum oxide layer 130 to the metallization layer 154 associated with the drain. This second distance 164 is also the distance of the AlGaN layer 114 that is directly covered by the second aluminum oxide layer 132, which is deposited onto the AlGaN layer 114, among other things. This portion of the AlGaN layer 114 is exposed by the operations further described herein to allow for an in-situ plasma pre-treatment to be performed over this portion of the AlGaN layer 114.
[0054] By controlling the first distance 162 and the second distance 164 in conjunction with the first aluminum oxide layer 130 covering the first distance 162, the portion of the AlGaN layer 114 exposed to the in-situ plasma treatment can be controlled. This allows the two-dimensional electron gas (2DEG) to be customized by splitting the aluminum oxide layer 130 deposition distance. In addition, by having the aluminum oxide layer 130 on the sidewalls of the p-GaN gate 120, the 2DEG under and around the p-GaN gate 120 is controlled, which reduces the electric field at the corners of the p-GaN gate 120 of the power device 100. This also prevents the Mg in and around the p-GaN gate 120 from being deactivated by the plasma treatment and allows the 2DEG Rsh to be selectively reduced.
[0055] The first aluminum oxide layer 130 may be referred to as an aluminum oxide etch stop layer.
[0056] In various embodiments, the first distance 162 can be a distance of 200 nm or more (e.g., 200 nm to 300 nm). The distance can be related to thermal processes with hydrogen diffusion during plasma processing. Mg deactivation can depend on the conditions of the thermal process, which can cause both vertical deactivation and some horizontal deactivation. For example, the first distance 162 is far enough to avoid hydrogen diffusion reaching the p-GaN gate 120. The first distance 162 can also depend on the structure and / or power level (e.g., voltage rating) of the power device 100. For example, at a 650 V rating of the power device 100, the separation distance 160 between the gate and the drain can be 17-18 and the first distance 160 can be 1 micron and the second distance 162 to the gate is 16-17 microns. If the power device 100 has a lower rating, the distance may need to be adjusted.
[0057] Also like Figure 1As shown in FIG. 1 , there may be a second silicon dioxide layer 142 and a third silicon dioxide layer 144. These additional silicon dioxide layers may be deposited over the various layers of the illustrated power device 100, which are further described herein.
[0058] Figure 2 A first example flow chart of operations for fabricating a power device according to one or more embodiments of the present disclosure is illustrated. Fabrication of a normally-off p-GaN HEMT power device may be part of a method of fabricating an integrated circuit.
[0059] At operation 200, a wafer having overlying AlGaN layers, p-GaN layers, and TiN layers is provided. The wafer may also include a GaN layer 112 beneath the AlGaN 114, and a silicon dioxide layer 110 may be beneath the GaN layer 112. The p-GaN layer may be used to form a p-GaN gate 120. This p-GaN layer may also be covered by a TiN layer 124.
[0060] In various embodiments, a wafer may be provided with a silicon dioxide layer 110, a GaN layer 112, and an AlGaN layer 114. A top or second GaN layer may then be grown or formed on the AlGaN layer 114. This top or second GaN layer may then be doped with Mg to form a p-GaN layer to be etched. A TiN layer 124 may be deposited on the p-GaN layer.
[0061] At operation 202, the TiN layer and the p-GaN layer are etched to form a gate. The p-GaN gate 120 may be etched, which may include the p-GaN gate 120 and the TiN layer 124. The p-GaN layer may be etched in a Cl-based chemistry. The TiN layer 124 may be etched with BCl3. In various embodiments, performing the etching may include TiN lateral recessing by wet etching with SiN HM, resist stripping in O2 / N2 plasma, and polymer removal.
[0062] At operation 204, the exposed surfaces are cleaned. This cleaning operation will clean the exposed surfaces of the p-GaN gate 120 and the TiN layer 124 and the AlGaN layer 114. In various embodiments, the cleaning may use hot HCl and / or HF.
[0063] At operation 206, a first aluminum oxide layer is deposited. The first aluminum oxide layer 130 can be deposited over the AlGaN layer 114, the p-GaN gate 120, and the TiN layer 124. In various embodiments, the aluminum oxide layer can be Al2O3 deposited by an atomic layer deposition (ALD) thermal or plasma process to a thickness of several nanometers. The thickness can vary. Other examples can include 2.5 nm to 11 nm. The ALD layer can include aluminum oxide, hafnium oxide, silicon dioxide, silicon nitride, and aluminum nitride.
[0064] At operation 208, a first silicon dioxide layer is deposited. In various embodiments, the first silicon dioxide layer 140 may be PECVD SiO2 with a thickness of 300 nm. The first silicon dioxide may be PECVD silicon nitride, LPCVD SiO2, and LPCVD SiN.
[0065] The wafer after operation 208 is shown in FIG. Figure 3A Shown in.
[0066] At operation 210, the first silicon dioxide layer and the first aluminum oxide layer are etched to expose the AlGaN layer. The etching of the first silicon dioxide layer 140 and the first aluminum oxide layer 130 can remove these layers above the exposed portion 310 of the AlGaN layer 114. The exposed portion 310 will include at least a second distance 164. The exposed portion 310 of the AlGaN layer 114 will start at a first distance 162 away from the p-GaN gate 120. The first distance 162 can be based on a distance to avoid introducing hydrogen diffusion into the area around and at the p-GaN gate 120 during the in-situ plasma treatment operation. This etch can use CF4-based chemistry, resist stripping with O2 / N2 plasma, and / or polymer removal on the AlGaN layer 114.
[0067] At operation 212, an in-situ plasma treatment is performed. The in-situ plasma treatment may be applied to the exposed first portion 310 of the AlGaN layer 114. The in-situ plasma treatment may use a hydrogen-based plasma treatment. The in-situ plasma treatment accelerates Mg deactivation by introducing hydrogen (H) to form a Mg-H complex composition and this deactivates the Mg doping of the exposed portion 310 of the AlGaN layer 114, which may reduce the 2DEG sheet resistance (Rsh) of the AlGaN / GaN heterostructure.
[0068] In various embodiments, in-situ plasma processing is performed on the wafer in a direct plasma chamber with NH3 / N2 flow or H2 / N2 and with a power range between 150 and 300 W. Additionally or alternatively, temperatures in the range of 300° C. may accelerate Mg deactivation by the introduction of hydrogen. By modifying the conditions of operation 212 to diffuse additional hydrogen and / or deactivate a greater amount of Mg, Vth may be further reduced.
[0069] The p-GaN gate 120 is protected by the silicon dioxide layer 140 and the first aluminum oxide layer 130 during the in-situ plasma treatment.
[0070] The wafer after operation 212 is shown in FIG. Figure 3B Shown in.
[0071] At operation 214, a second aluminum oxide layer is deposited. The second aluminum oxide layer 132 is deposited. For the first portion 310 of the wafer, the second aluminum oxide layer 132 will cover the AlGaN layer 114. Outside of the first portion 310 of the wafer, the second aluminum oxide layer 132 is deposited on the first silicon dioxide layer 140.
[0072] In various embodiments, the second aluminum oxide layer 132 can have a different thickness than the first aluminum oxide layer 130. This can be a second aluminum oxide layer thickness of the second aluminum oxide layer 132 while the first aluminum oxide layer 130 has a first aluminum oxide layer thickness. The second aluminum oxide layer thickness can be, for example, 3 nm, 5 nm, 7 nm, etc. Variations in the thickness of the second aluminum oxide layer 132 can be associated with different gate leakages. Although the gate leakage will also depend on other aspects of the power device, including the profile of the p-GaN gate 120. In various embodiments, the second aluminum oxide layer 132 can be an ALD Al2O3 deposition.
[0073] At operation 216, a second silicon dioxide layer is deposited. A second silicon dioxide layer 142 may be deposited. In various embodiments, the second silicon dioxide layer may be PECVD SiO2 with a thickness of 300 nm. The first silicon dioxide may be PECVD silicon nitride, LPCVD SiO2, and LPCVD SiN.
[0074] A diagram of the wafer after operation 216 is shown in FIG. Figure 3C Shown in.
[0075] At operation 218, the first portion of the second silicon dioxide layer and the second aluminum oxide layer is etched. The etching may be at a second portion 320 of the wafer, which is etched to remove the second silicon dioxide layer 142 and the second aluminum oxide layer 132, thereby exposing the first silicon dioxide layer 140 above and around the p-GaN gate 120, while leaving the second silicon dioxide layer 142 and the second aluminum oxide layer 132 covering the AlGaN layer 114 at portion 310. The removal of the second silicon dioxide layer 142 and the second aluminum oxide layer 132 is to prevent the presence of a double silicon dioxide layer above the p-GaN gate 120, which would affect electrical performance. This etching may use CF4-based chemistry, resist stripping with O2 / N2 plasma, and / or polymer removal on the aluminum oxide layer 132.
[0076] In various embodiments, etching may also leave an overlap of the second silicon dioxide layer 142 and the second aluminum oxide layer 132 over the first silicon dioxide layer 140 and the first aluminum oxide layer 130 at an overlap portion 322 of the wafer. This overlap portion 322 may also be etched to include tapering associated with a metallization layer (e.g., 156A) to be used for shielding.
[0077] The wafer after operation 218 is shown in FIG. Figure 3D Shown in.
[0078] At operation 220, the silicon dioxide layer(s) and the aluminum oxide layer(s) are etched to expose the first gate. The etching may be at a third portion 330 of the wafer, which is etched to remove the first silicon dioxide layer 140 and the first aluminum oxide layer 130, thereby exposing the p-GaN gate 120 and the TiN layer 124. This etching may use CF4-based chemistry, resist stripping with O2 / N2 plasma, polymer removal, and / or pre-metal cleaning.
[0079] The wafer after operation 220 is shown in FIG. Figure 3E Shown in.
[0080] At operation 222, metallization layers are deposited to form gate contacts and one or more shields. One or more metallization layers may be deposited to form gate contacts 150 and metal shields 156A for p-GaN gate 120. This metallization layer deposition may use TiN / AlCu / TiN or W metallization and / or tapered etching. Gate contacts 150A, 150B may be self-aligned.
[0081] The wafer after operation 222 is shown in FIG. Figure 3F Shown in.
[0082] At operation 224, a third silicon dioxide layer is deposited. In various embodiments, a third silicon dioxide layer 144 may be deposited. In various embodiments, the third silicon dioxide layer may be PECVD SiO2. The first silicon dioxide may be PECVD silicon nitride, LPCVD SiO2, and LPCVD SiN.
[0083] At operation 226, etching is performed for ohmic contacts. The etching for ohmic contacts may include etching the silicon dioxide layer and / or the aluminum oxide layer to expose the AlGaN layer 114 for making the source contact 152 and the drain contact 154. This etching may use CF4-based chemistry on AlGaN, Cl-based chemistry for AlGaN recess, resist stripping with O2 / N2 plasma, polymer removal and / or pre-metal cleaning.
[0084] At operation 228, metallization layer(s) for ohmic contact (and shielding) is deposited. This metallization layer may be deposited to form source contact 152 and drain contact 154. In various embodiments, this metallization layer may also include one or more shield metal portions (e.g., 156B) deposited. This metallization layer deposition may use Ti, Ta, AlCu, TiN metallization.
[0085] At operation 230, annealing is performed. The annealing may be an ohmic annealing.
[0086] The wafer after operation 230 is shown in FIG. Figure 1 Shown in.
[0087] In various embodiments, the operations following the in-situ plasma treatment may be referred to as forming the gate, source, and drain of the HEMT, as each of these operations forms one or more structures that are required to form the HEMT power device 100 .
[0088] It will be appreciated that the above operations may be iterated, omitted or varied. For example, various embodiments may omit the deposition of one or more aluminum oxide layers.
[0089] Figure 3A-3H An example block diagram associated with operations for fabricating a power device according to one or more embodiments of the present disclosure is illustrated.
[0090] Figure 3A The wafer is illustrated after performance of operation 208 .
[0091] Figure 3B The wafer is illustrated after performance of operation 212 .
[0092] Figure 3C The wafer is illustrated after performance of operation 216 .
[0093] Figure 3D The wafer is illustrated after performance of operation 218 .
[0094] Figure 3E The wafer is illustrated after performance of operation 220 .
[0095] Figure 3F The wafer is illustrated after performance of operation 222 .
[0096] Figure 3G The wafer is illustrated after performance of operation 224 .
[0097] Figure 3H The wafer is illustrated after performance of operation 228 .
[0098] Figure 4 A second example flow chart of operations for fabricating a power device according to one or more embodiments of the present disclosure is illustrated.
[0099] At operation 400 , a wafer having overlying AlGaN layer, p-GaN layer, and TiN layer is provided. Operation 400 may be the same as operation 200 .
[0100] At operation 402 , the TiN layer and the p-GaN layer are etched to form a gate. Operation 402 may be the same as operation 202 .
[0101] At operation 404 , the exposed surface is cleaned. Operation 404 may be the same as operation 204 .
[0102] At operation 406 , a first aluminum oxide layer is deposited. Operation 406 may be the same as operation 206 .
[0103] At operation 408 , a first silicon dioxide layer is deposited. Operation 408 may be the same as operation 208 .
[0104] At operation 410, the first silicon dioxide layer and the first aluminum oxide layer are etched to expose the AlGaN layer. Operation 410 may be the same or similar to operation 210, except that the exposed portion may be at portion 320A which is larger than portion 320. In this manner, the distance from the p-GaN gate 120 to the start of portion 320A is smaller.
[0105] At operation 412, in-situ plasma treatment is performed. Operation 412 may be the same as operation 212.
[0106] At operation 414, a second aluminum oxide layer is deposited. Operation 414 may be the same or similar to operation 214, except that the aluminum oxide layer 132 may be hafnium oxide, silicon dioxide, silicon nitride, and aluminum nitride. In various embodiments, this layer may be deposited with a thickness of a few nanometers.
[0107] At operation 416 , a second silicon dioxide layer is deposited. Operation 416 may be the same as operation 216 .
[0108] At operation 418, a third silicon dioxide layer is deposited on the third portion. Operation 418 may be different from Figure 2 In operation 418, a silicon dioxide layer 520 may be deposited on the third portion 530 of the wafer. The silicon dioxide layer 520 may be SiN having a thickness of 80 nm.
[0109] In various embodiments, additional operations for forming a gate, source, and drain of the HEMT may be performed after operation 418 .
[0110] Figure 5A-Figure 5C An example block diagram associated with operations for fabricating a power device according to one or more embodiments of the present disclosure is illustrated.
[0111] Figure 5A The wafer is illustrated after performance of operation 408 .
[0112] Figure 5B The wafer is illustrated after performance of operation 412 .
[0113] Figure 5C The wafer is illustrated after performance of operation 416 .
[0114] Figure 6 A third example flow chart of operations for fabricating a power device in accordance with one or more embodiments of the present disclosure is illustrated.
[0115] At operation 600 , a wafer having overlying AlGaN layer, p-GaN layer, and TiN layer is provided. Operation 600 may be the same as operation 200 .
[0116] At operation 602 , the TiN layer and the p-GaN layer are etched to form a gate. Operation 602 may be the same as operation 202 .
[0117] At operation 604 , the exposed surface is cleaned. Operation 604 may be the same as operation 204 .
[0118] At operation 606 , a first aluminum oxide layer is deposited. Operation 606 may be the same as operation 206 .
[0119] At operation 608 , a first silicon dioxide layer is deposited. Operation 608 may be the same as operation 208 .
[0120] At operation 610, the first silicon dioxide layer and the first aluminum oxide layer are etched to expose the first portion and the second portion of the AlGaN layer. Operation 610 may be the same or similar to operation 210, except that the first portion 710 and the second portion 720 of the AlGaN layer 114 are exposed on both sides of the p-GaN gate 120. In addition, the etching leaves spacers 142A, 142B around the p-GaN gate 120. The spacers 142A, 142B include portions of the first silicon dioxide layer 140 and the first aluminum oxide layer 130.
[0121] At operation 612, in-situ plasma treatment is performed. Operation 612 may be the same as operation 212.
[0122] At operation 614, a second aluminum oxide layer is deposited. Operation 614 may be the same or similar to operation 214, except that the aluminum oxide layer 732 may be an AlN layer, which may cover the spacers 140A, 140B along with the p-GaN gate 120 and the TiN layer 124. In various embodiments, the AlN layer may be deposited at a temperature of 370° C. with a thickness of 5 nm.
[0123] At operation 616 , a second silicon dioxide layer is deposited. Operation 616 may be the same as operation 216 .
[0124] At operation 618, a third silicon dioxide layer is deposited on the third portion. Operation 418 may be different from Figure 2 In operation 418, a silicon dioxide layer 520 may be deposited on the third portion 530 of the wafer. The silicon dioxide layer 520 may be SiN having a thickness of 80 nm.
[0125] In various embodiments, additional operations for forming a gate, source, and drain of the HEMT may be performed after operation 618 .
[0126] Figure 7A-7C An example block diagram associated with operations for fabricating a power device according to one or more embodiments of the present disclosure is illustrated.
[0127] Fig. 7A The wafer is illustrated after performance of operation 608 .
[0128] Figure 7B The wafer is illustrated after performance of operation 612 .
[0129] Figure 7C The wafer is illustrated after performance of operation 616 .
[0130] It should be readily appreciated that embodiments of the systems and devices described herein may be configured in a variety of additional and alternative ways besides those explicitly described herein.
[0131] in conclusion
[0132] The operations and / or functions of the present disclosure have been described herein, such as in flowcharts. The flowchart blocks support combinations of means for performing the specified operations and / or functions and combinations of operations and / or functions for performing the specified operations and / or functions.
[0133] Although this specification contains many specific embodiments and implementation details, these should not be interpreted as limitations on the scope of any disclosed or potentially claimed content, but rather as descriptions of features specific to specific disclosed embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually or in any appropriate sub-combination in multiple embodiments. In addition, although features may be described above as working in certain combinations, and even initially claimed as such, in some cases, one or more features from the claimed combination may be deleted from the combination, and the claimed combination may involve a sub-combination or a variation of a sub-combination.
[0134] Although operations and / or functions are illustrated in a particular order in the drawings, this should not be understood as requiring that such operations and / or functions be performed in the particular order shown or in a sequential order, or that all illustrated operations be performed, in order to achieve the desired results. In some cases, operations and / or functions in an alternative order may be advantageous. In some cases, the actions described in the claims may be performed in a different order and still achieve the desired results. Therefore, although specific embodiments of the subject matter have been described, other embodiments are within the scope of the following claims.
[0135] Although this detailed description has set forth some embodiments of the invention, the appended claims cover other embodiments of the invention that differ from the described embodiments according to various modifications and improvements.
[0136] In the following claims, unless the specific terms "means for" or "step for" are used within a given claim, it is not intended that the claim be interpreted under 35 USC §112, paragraph 6.
Claims
1. A method for manufacturing an integrated circuit, comprising: Providing a wafer, the wafer comprising an AlGaN layer having a first surface and a p-GaN layer on the first surface of the AlGaN layer; etching the p-GaN layer to form at least a first p-GaN gate; depositing a first aluminum oxide layer over the first p-GaN gate; depositing a first silicon dioxide layer over the first aluminum oxide layer; etching the first silicon dioxide layer and the first aluminum oxide layer to expose a first portion of the AlGaN layer, the first portion starting at a first distance from the first p-GaN gate; treating the first portion of the AlGaN layer with an in-situ plasma treatment, wherein the in-situ hydrogen-based plasma treatment deactivates magnesium in the first portion of the AlGaN layer; as well as At least a first normally-off HEMT is formed, wherein a gate of the first normally-off HEMT is the first p-GaN gate. 2 . The method of claim 1 , wherein forming the first normally-off HEMT comprises depositing at least a second aluminum oxide layer and a second silicon dioxide layer. 3 . The method of claim 1 , wherein treating the first portion of the AlGaN layer with the in-situ plasma treatment does not deactivate Mg in another portion of the AlGaN layer associated below the first p-GaN gate. 4 . The method of claim 1 , wherein the in-situ plasma treatment comprises diffusing hydrogen into the first portion of the AlGaN layer. The method of claim 1 , wherein the first distance is at least 200 nm.
6. The method of claim 1, wherein forming the first normally-off HEMT further comprises depositing metallization layers associated with a first normally-off HEMT gate, a first normally-off HEMT source, and a first normally-off HEMT drain. 7 . The method of claim 6 , wherein forming the first normally-off HEMT further comprises depositing at least a first metal shield layer. The method of claim 1 , wherein the p-GaN gate comprises a TiN layer.
9. The method according to claim 1, further comprising: After etching the first silicon dioxide layer and the first aluminum oxide layer but before the in-situ plasma treatment, a third aluminum oxide layer is deposited over the p-GaN gate.
10. The method of claim 1, wherein etching the first silicon dioxide layer and the first aluminum oxide layer further exposes a second portion of the AlGaN layer, the second portion being a second distance from a second side of the p-GaN gate; and Wherein treating the first portion of the AlGaN layer with the in-situ plasma treatment further comprises treating the second portion of the AlGaN layer with the in-situ plasma treatment.
11. A normally-off HEMT, comprising: A p-GaN gate, wherein the p-GaN gate is on the AlGaN layer; wherein the p-GaN gate is covered by a first aluminum oxide layer and a first silicon dioxide layer; wherein the AlGaN layer includes a first portion of the AlGaN layer, the first portion starting at a first distance from a first p-GaN gate, and wherein the first portion of the AlGaN layer is not covered by the first aluminum oxide layer and the first silicon dioxide layer; and Wherein the first portion of the AlGaN layer has deactivated Mg from an in-situ hydrogen-based plasma treatment.
12. The normally-off HEMT of claim 11 further comprising at least a second aluminum oxide layer and a second silicon dioxide layer.
13. The normally-off HEMT of claim 11, wherein the AlGaN layer includes non-deactivated Mg in another portion associated below the first p-GaN gate.
14. The normally-off HEMT of claim 11, wherein the deactivated Mg comprises Mg-H complexes from hydrogen diffused from an in-situ plasma treatment.
15. The normally-off HEMT of claim 11, wherein the first distance is at least 200 nm.
16. The normally-off HEMT of claim 11, further comprising a plurality of metallization layers, the plurality of metallization layers comprising a first metallization layer associated with a first normally-off HEMT gate, a second metallization layer associated with a first normally-off HEMT source, and a third metallization layer associated with a first normally-off HEMT drain.
17. The normally-off HEMT of claim 16, further comprising at least one metal shielding layer.
18. The normally-off HEMT of claim 11, wherein the p-GaN gate comprises a TiN layer.
19. The normally-off HEMT of claim 11, further comprising a third aluminum oxide layer of the p-GaN gate.
20. The normally-off HEMT of claim 11, wherein the AlGaN layer further comprises a second portion of the AlGaN layer, the second portion starting at a second distance from the first p-GaN gate on a side of the p-GaN gate opposite the first portion of the AlGaN layer, and wherein the second portion of the AlGaN layer is not covered by the first aluminum oxide layer and the first silicon dioxide layer; and Wherein the second portion of the AlGaN layer has deactivated Mg from the in-situ hydrogen-based plasma treatment.