Power FinFET with one-piece control electrode and method of manufacturing same
By alternately arranging the shielding area and a second trench of smaller width in the power FinFET, and combining a method of manufacturing a one-piece control electrode with a photolithography and etching process, the problems of high on-resistance and complex manufacturing processes caused by wide trench in the prior art are solved, and effective limiting of short-circuit current and reducing on-resistance are achieved.
Patent Information
- Application Number
- CN202411525424.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-30
- Filing Date
- 2024-10-30
- Publication Date
- 2025-05-02
AI Technical Summary
Existing power MOSFETs have problems with wide trenches in increasing breakdown voltages, and process fluctuations affect the limits of short circuit currents.
Using alternately arranged shielding areas and a second trench of smaller widths, a power FinFET with a one-piece control electrode is manufactured by a lithography and etching process, and a polysilicon layer is introduced into the fin region to fill the trench.
Effective limits on short circuit current are achieved, the impact of process fluctuations on current is reduced, and the on-resistance is reduced, while simplifying the manufacturing process.
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Figure CN119922932A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a method for producing a power FinFET (Fin Field Effect Transistor) having alternating shielding regions and a one-piece control electrode and a power FinFET having alternating shielding regions and a one-piece control electrode. Background Art
[0002] Semiconductors with a large band gap, such as SiC or GaN, are used in power electronic components. Typically, power MOSFETs with a vertical channel region are used.
[0003] In order to increase the breakdown voltage of such power MOSFETs, shielding regions are arranged below the trenches. These shielding regions can be connected to the source region via contacts in the trenches, thereby forming a bisected control electrode within the trenches, as shown, for example, in document DE 102 24 201 B4.
[0004] Here, for example, it may be disadvantageous that the trenches must be made very wide, so that for example the pitch dimensions and the on-resistance of the power MOSFET are large. The form factor may be large. In addition, the method for producing the control electrode divided in half may be complicated.
[0005] Between the usually p-doped shielding regions, between two adjacent trenches, a so-called JFET is formed, which serves to limit the current flow through the channel region in the event of a short circuit. To this end, the p-doped shielding regions are implanted by means of a photolithographically structured mask.
[0006] In this case, it can be disadvantageous, for example, that the distance between two p-doped shielding regions is therefore subject to process fluctuations which influence the limitation of the short-circuit current. Summary of the invention
[0007] The object of the present invention is to overcome these and other disadvantages.
[0008] The present invention provides a method for manufacturing a power FinFET having alternating shielding regions and a one-piece control electrode and a power FinFET having alternating shielding regions and a one-piece control electrode.
[0009] Preferred embodiments are described below.
[0010] According to a first aspect, the invention relates to a method for producing a power FinFET with a one-piece control electrode and a semiconductor body, the semiconductor body having a second connection region and a drift layer, wherein the second connection region forms the front side of the semiconductor body, the method comprising: generating a structured first mask on the front side of the semiconductor body by means of a photolithography step, wherein the first mask has an oxide region and an open first region, wherein the open first region exposes the front side of the semiconductor body; and generating a first trench below the open first region starting from the front side of the semiconductor body into the drift layer by means of a first etching process. Furthermore, the method comprises: generating a shielding region below the first trench by means of a first implantation process. The method comprises: applying an isotropic oxide layer to the front side of the semiconductor body; generating a structured second mask by means of a second etching process, so that the isotropic oxide layer has an open second region, wherein the open second region exposes the front side of the semiconductor body; and generating a second trench below the open second region by means of a third etching process starting from the front side into the drift layer, wherein the second trench is arranged substantially parallel to the first trench and the first trench and the second trench alternate, wherein the second trench has a smaller width than the first trench. In addition, the method comprises: oxidizing the front side, so that a further oxide layer is arranged on the front side; and widening the first trench and the second trench by means of a fourth etching process, so that a fin is generated between the first trench and the second trench, wherein the fin has a width of less than 500 nm. The method comprises: applying a polysilicon layer to the front side of the semiconductor body, so that the first trench and the second trench are completely filled; and activating the shielding region by means of annealing.
[0011] An advantage here may be that a short-circuit current limiting effect is produced between the shielding region and the side wall of the second trench. Process fluctuations can thus be tolerated. In addition, the spacing between the shielding regions can be reduced.
[0012] In one configuration, the structured first mask comprises a nitride region, wherein the oxide region is arranged on the nitride region.
[0013] Here, it may be advantageous to prevent oxidation of the upper side of the fin.
[0014] In a further configuration, the diffusion region is produced below the second trench by means of a second implantation process, wherein the second implantation energy has a value between 200 keV and 2500 keV.
[0015] Here, one advantage may be that the on-resistance may be reduced.
[0016] In a further development, the first etching process, the second etching process and the third etching process are anisotropic plasma etching processes.
[0017] In this case, it may be advantageous if the structured mask can be transferred to the underlying layer with minimal widening.
[0018] In one configuration, the first implant process has a first implant energy in a range of 30 keV to 2700 keV.
[0019] An advantage here may be that a shielding region is produced at the trench bottom below the gate oxide to be protected, so that a maximum shielding effect is achieved without pitch losses.
[0020] According to a second aspect, the invention relates to a power FinFET having a one-piece control electrode and a semiconductor body, the semiconductor body having a drift layer and a second connection region. The second connection region is arranged above the drift layer, and the first trench and the second trench extend from the second connection region into the drift layer. The first trench and the second trench are arranged alternately with each other, wherein the second trench has a smaller width than the first trench, and a shielding region is arranged below the first trench. The shielding region directly adjoins the first trench, wherein the shielding region is conductively connected to the source region, wherein the conductive connection is not arranged inside the first trench (206). A corresponding one-piece control electrode is arranged inside the first trench, wherein the corresponding one-piece control electrode is electrically insulated from the shielding region below the first trench. A fin is arranged between the first trench and the second trench, wherein the fin has a maximum width of 500 nm.
[0021] Here, an advantage may be that the short-circuit current may be limited by the space charge region of the shielding area and the opposing trench wall of the second trench. Furthermore, it may be advantageous that the influence of process variability on the short-circuit current and the on-resistance may be reduced.
[0022] In one development, the diffusion region is arranged below the second trench.
[0023] An advantage here may be that the current transfer can be increased and / or the on-resistance can be reduced.
[0024] In a further embodiment, the shielding region is p-doped and has a p-type doping ratio of at least 1E18 / cm 3 of dopant concentration.
[0025] Here, it may be advantageous if a high implantation dose can be introduced cost-effectively below the trench bottom.
[0026] In one configuration, the semiconductor body includes SiC.
[0027] An advantage here may be that aluminum can be used for the implantation, which can be easily activated.
[0028] In a further configuration, the semiconductor body includes GaN.
[0029] Here, it may be advantageous if the critical field strength and the electron mobility can be increased.
[0030] Further advantages result from the following description of exemplary embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The invention is then explained based on a preferred embodiment and the accompanying drawings. The drawings show:
[0032] Figure 1 A method for fabricating a power FinFET having alternating shielding regions and a one-piece control electrode is shown, and
[0033] Figure 2 A power FinFET with alternating shielding regions and a one-piece control electrode is shown. DETAILED DESCRIPTION
[0034] Figure 1 A method for manufacturing a power FinFET with alternating shielding regions without a control electrode divided in half is shown. The control electrode is constructed in one piece. In general, at least one control electrode can be constructed in one piece. The shielding region of the power FinFET is connected to the source region. The connection is not arranged inside the trench of the power FinFET. Instead, the source region can be conductively connected, for example, via a contact at the end of the cell region (Zellenfeldes) or via a deep connection region implanted, for example, at periodic intervals along the fin.
[0035] The power FinFET comprises a semiconductor body, which comprises, for example, SiC or GaN, a second connection region and a drift layer, wherein the second connection region forms a front side of the semiconductor body.
[0036] The method may include a step 105 in which a structured first mask is produced on the front side of the semiconductor body by means of a photolithography step. The structured first mask may have oxide regions and open first regions that expose the front side of the semiconductor body.
[0037] In step 110 , a first trench may be produced below the open first region starting from the front side of the semiconductor body into the drift layer by means of a first etching process.
[0038] In step 115, a shielding region may be generated under the first trench by means of a first implantation process with a first implantation energy. The first implantation energy is between 30 keV and 2700 keV. The shielding region may be p-doped.
[0039] In step 120 , an isotropic oxide layer may be applied to the front side of the semiconductor body.
[0040] In step 125 , a structured second mask can be produced by means of a second etching process, so that the isotropic oxide layer has open second regions, wherein the open second regions expose the front side of the semiconductor body.
[0041] In step 130, a second trench can be produced below the open second region by means of a third etching process starting from the front side of the semiconductor body into the drift layer. The second trench is preferably arranged parallel to the first trench and staggered with each other. The second trench can have a smaller width than the first trench.
[0042] In other words, in step 125, a self-aligning or self-adjusting mask can be produced. Thus, in step 130, the second trench can be produced sub-lithographically by means of a mask reversal process, and the width or pitch of the terrace between the first trench and the second trench can be determined by the thickness of the isotropic oxide layer. In addition, an accurate adjustment between the shielding area below the first trench and the opposite sidewalls of the second trench is possible, so that an optimal adjustment of the on-resistance, the short-circuit current and the field in the oxide at the trench bottom of the second trench can be achieved.
[0043] In step 135 , the front side of the semiconductor body can be oxidized so that a further oxide layer is arranged on the front side of the semiconductor body. The further oxide layer has a thickness of at least 10 nm.
[0044] In step 140, the first trench and the second trench may be widened by means of a fourth etching process, thereby producing a fin between the first trench and the second trench, the fin having a width of, for example, less than 500 nm, preferably a width in the range between 400 and 50 nm, and more preferably a width in the range between 200 and 50 nm. Here, the oxide from step 135 may be selectively wet-chemically etched.
[0045] Depending on the fin width to be achieved, steps 135 and 140 can be performed cyclically. In other words, the front side of the semiconductor body can be oxidized multiple times. Etching steps can be performed between oxidation steps. Thus, the widening of the trench can be performed without adjustment, because the lateral oxidation rate exceeds the vertical oxidation rate by approximately a factor of two.
[0046] In step 145, a polysilicon layer can be applied to the front side of the semiconductor body, so that the first trench and the second trench are completely filled. In the subsequent etching, this can result in not only spacers remaining on the trench sidewalls, but also all first and second trenches are still completely filled. Alternatively or in addition, the first trench and / or the second trench can be partially or completely filled in a separate step.
[0047] In a subsequent step 150, the shielding region can be activated by means of annealing. The annealing is usually carried out at 1700°C.
[0048] By means of the method according to the invention, the shielding regions below the first trench are located further from each other than from the opposing trench walls or side walls of the second trench. Therefore, the short-circuit current is not limited by the collision of the space charge regions of the two shielding regions, but by the space charge region of each p-doped shielding region, which squeezes or presses the current toward the opposing trench walls of the second trench. The low sensitivity with respect to process variability is achieved in that the trench walls of each second trench form an accumulation channel due to the positive gate voltage in the event of a short circuit, which accumulation channel is not eliminated by the space charge region of the p-doped shielding region.
[0049] The first etching process, the second etching process and / or the third etching process may be anisotropic etching processes. The fourth etching process may be isotropic. Here, in the case of a SiC semiconductor body, the first and / or third etching process may be selected between etched SiC and unetched SiO2, SiN and Si. In the case of a SiC semiconductor body, the second etching process and / or the fourth etching process may be selected between etched SiO2 and unetched SiC, SiN and Si.
[0050] In one embodiment, the structured first mask has a nitride region between the front side and the oxide region. The nitride region protects the front side or the surface of the fin, since oxidation of the upper side of the fin in step 140 is prevented in this way. The nitride region may be Figure 1 It is removed in an intermediate step between step 145 and step 150, not shown in FIG.
[0051] In a further embodiment, a diffusion region may be implanted below the second trench by means of a second implantation process. The diffusion region may be n-doped and may have a higher doping than the n-doped drift layer. Thereby, the current transport effect below the second trench may be enhanced. The second implantation process may have a second implantation energy having a value between 200 keV and 2500 keV.
[0052] Figure 2 A power FinFET 200 is shown with alternating shielding regions without a control electrode 209 divided in two. The control electrode 209 is in one piece. The power FinFET 200 has a semiconductor body 201 with a first connection region 202, a drift layer 203, a channel region 204 and a second connection region 205. The first connection region 202 functions as a drain connection and the second connection region 205 functions as a source connection. The drift layer 203 is arranged on the first connection region 202, the channel region 204 is arranged on the drift layer 203, and the second connection region 205 is arranged on the channel region 204. The second connection region 205 functions as the front side of the semiconductor body 201.
[0053] The first trench 206 and the second trench 207 extend from the front side of the semiconductor body 201 into the drift layer 203, wherein the second trench 207 has a smaller width than the first trench 206. In this case, the first trench 206 and the second trench 207 are arranged alternately with each other. A shielding region 211, preferably doped p-type, is arranged below the first trench 206 and directly adjoins the trench bottom of the first trench 206. The dopant concentration of the shielding region 211 is at least 1E18 / cm 3 The shielding region 211 is electrically conductively connected to the source region 210, which is not arranged inside the trench, but for example via a contact at the end of the cell region or as in Figure 2 The control electrode 209 is electrically conductively connected, for example, by deep connection areas implanted at periodic intervals along the fins, as partially described in the figure. The control electrode 209 can function as a gate contact. The bisection (Zweiteilung) of the control electrode 209 can be completely or at least partially omitted. That is, one, more than one or all control electrodes 209 can be one-piece. The control electrode 209 is electrically insulated from the shielding area 211 by means of an oxide layer 208. A fin 212 is arranged between the first trench 206 and the second trench 207, and the fin can have a width of, for example, less than 500nm, preferably a width in the range between 400 and 50nm, and more preferably a width in the range between 200 and 50nm.
[0054] The semiconductor body 201 may include SiC and / or GaN.
[0055] In one embodiment, a diffusion region 213 is arranged below the second trench 207. The diffusion regions 213 may be n-doped. They may have a higher doping than the drift layer 203, which may likewise be n-doped. The shielding regions 211 and the diffusion regions 213 may be arranged staggered, in particular alternately or in a periodic pattern. The spacing between directly adjacent shielding regions 211 may be in the range between 800 and 1000 nm, preferably in the range between 850 and 950 nm. Still more preferably, the spacing between directly adjacent shielding regions may be 900 nm.
[0056] Power FinFETs are used, for example, in DC / DC converters and inverters in the electric drive train of electric vehicles or hybrid vehicles and in on-board chargers.
Claims
1. A method (100) for manufacturing a power FinFET (200) having a one-piece control electrode, wherein: The power FinFET comprises a semiconductor body (201) having a second connection region (205) and a drift layer (203), wherein the second connection region (205) forms a front side of the semiconductor body (202), and the method comprises the following steps: generating (105) a structured first mask on the front side of the semiconductor body (201) by means of a photolithography step, wherein the structured first mask has oxide regions and open first regions, wherein the open first regions expose the front side of the semiconductor body (202), producing (110) a first trench (206) below the open first region starting from the front side of the semiconductor body (201) into the drift layer (203) by means of a first etching process, creating (115) a shielding region (211) below the first trench by means of a first implantation process, applying (120) an isotropic oxide layer onto the front side of the semiconductor body (201), generating (125) a structured second mask by means of a second etching process, so that the isotropic oxide layer has open second regions and the open second regions expose the front side of the semiconductor body (201), producing (130) a second trench (207) below the open second region starting from the front side into the drift layer (203) by means of a third etching process, wherein the second trench (207) is arranged substantially parallel to the first trench (206) and the first trench (206) and the second trench (207) alternate, wherein the second trench (207) has a smaller width than the first trench (206), oxidizing the front side (135) so that a further oxide layer is arranged on the front side, widening (140) the first trench (206) and the second trench (207) by means of a fourth etching process, thereby producing a fin (212) between the first trench (206) and the second trench (207), wherein the fin (212) has a width of less than 500 nm, applying (145) a polysilicon layer onto the front side of the semiconductor body so that the first trench (206) and the second trench (207) are completely filled, and Activating (150) the shielding region (211) by means of annealing.
2. The method (100) according to claim 1, wherein: The structured first mask comprises a nitride region, wherein the oxide region is arranged on the nitride region.
3. The method (100) according to claim 1 or 2, wherein: A diffusion region is produced below the second trench by means of a second implantation process, wherein the second implantation energy has a value between 200 keV and 2500 keV.
4. A method according to any one of the preceding claims, wherein: The first etching process, the second etching process, and the third etching process are anisotropic plasma etching processes.
5. A method according to any one of the preceding claims, wherein: The first implantation process has a first implantation energy in a range of 30 keV to 2700 keV.
6. A power FinFET (200) having a one-piece control electrode and a semiconductor body (201) having a drift layer (203) and a second connection region (205), in, The second connection region (205) is arranged above the drift layer (203), and the first trench (206) and the second trench (207) extend from the second connection region (205) into the drift layer (203), wherein the first grooves (206) and the second grooves (207) are arranged alternately with each other, wherein the second grooves (207) have a smaller width than the first grooves (206), wherein a shielding region (211) is arranged below the first trench (206), wherein the shielding region (211) directly adjoins the first trench (206), and the shielding region (221) is electrically conductively connected to the source region (210), wherein the electrically conductive connection is not arranged inside the first trench (206), A corresponding one-piece control electrode (201) is arranged inside the first trench (206), wherein the corresponding one-piece control electrode (201) is electrically insulated from a shielding region (211) below the first trench (204), and A fin (212) is arranged between the first trench (206) and the second trench (207), wherein the fin (212) has a maximum width of 500 nm.
7. The power FinFET (200) according to claim 6, wherein: The diffusion region (213) is arranged below the second trench (207).
8. The power FinFET (200) according to any one of claims 6 or 7, wherein: The shielding region is p-doped and has a 3 of dopant concentration.
9. The power FinFET (200) according to any one of claims 6 to 8, wherein: The semiconductor body (201) comprises SiC.
10. The power FinFET (200) according to any one of claims 6 to 8, wherein: The semiconductor body (201) includes GaN.
Citation Information
Patent Citations
Semiconductor device with breakdown current path and manufacturing process thereof
DE10224201B4