Terminal structure of IGBT (Insulated Gate Bipolar Translator) device, manufacturing method and IGBT device

Abstract

The invention provides a terminal structure of an IGBT (Insulated Gate Bipolar Translator) device, a manufacturing method and the IGBT device. According to the terminal structure, an opening is formed in a specific position of a polycrystalline silicon layer, and a gradient composite dielectric layer structure is formed by filling the opening with a bottom dielectric layer and superposing an intermediate dielectric layer. The structure can effectively guide an electric field to diffuse from a high-curvature region such as the edge of the first conductive type well region to a low-field-intensity region, and electric field peak concentration is effectively inhibited. And meanwhile, the thickening design of the dielectric layer in the opening area in the terminal structure can strengthen local pressure resistance and enhance the interface pressure resistance. Through the synergistic effect of the dual mechanisms, the overall voltage-resistant performance of the device is effectively improved. Besides, complex processes such as deep junction ion implantation and high-temperature junction pushing required by a traditional field limiting ring structure are avoided, the problems of wafer warping, lattice damage, leakage current degradation and the like possibly caused in the deep junction process and the high-temperature junction pushing process are solved while the manufacturing process is simplified and the cost is reduced, and the reliability and the overall performance of the device are remarkably improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices and relates to a terminal structure of an IGBT device, a manufacturing method and an IGBT device. Background Art

[0002] In the device design of high-voltage insulated gate bipolar transistors (IGBTs), the terminal structure has a decisive influence on the blocking voltage capability and reliability. Due to the significant curvature effect at the edge of the main junction depletion region in the IGBT blocking state, the electric field strength is locally concentrated in the terminal area. When high voltage is applied, this electric field distortion can easily cause avalanche breakdown, resulting in permanent device failure. To solve this key problem, the industry generally adopts two types of terminal technologies: field limiting ring (FLR) and field plate (FP), but the existing technical solutions still have the following technical bottlenecks:

[0003] (1) The field limiting ring sets several highly doped annular regions of the same type around the main junction of the device, and uses the carrier concentration gradient to adjust the distribution of the space charge region, thereby reducing the maximum electric field strength at the curvature peak. However, in order to achieve high-voltage tolerance, the field limiting ring needs to have a sufficient junction depth (usually more than 10 microns), which requires a long-term high-temperature junction push process (such as >1200℃ / several hours). This long-term hot junction push process is not only prone to wafer warping, leading to lithography alignment deviation and epitaxial layer defects, significantly reducing the yield and increasing manufacturing costs, but also causes the field limiting ring width to continue to increase. When the field limiting ring width exceeds the critical value, the field limiting ring cannot be completely exhausted in the blocking state, resulting in a significant decrease in the voltage withstand capability per unit length and a serious degradation of the terminal efficiency.

[0004] (2) Existing field plates include metal field plates and polysilicon field plates. Although metal field plates can effectively flatten the surface electric field through potential coupling, the dielectric constant mismatch at the metal-semiconductor interface causes edge electric field distortion, and the accumulation of interface trap charges under dynamic stress leads to increased parasitic capacitance, exacerbating the risk of premature breakdown of the dielectric layer. Although polysilicon field plates can avoid metal-semiconductor interface problems, their electric field regulation capabilities are insufficient, which can easily lead to uneven electric field distribution in the terminal area, affecting device reliability.

[0005] Therefore, how to provide a terminal structure, manufacturing method and IGBT device of an IGBT device to improve the device's voltage resistance, reduce manufacturing costs, optimize terminal efficiency and enhance device reliability while solving the bottleneck problems in the above-mentioned prior art has become an important technical problem that technical personnel in this field need to solve urgently.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide a terminal structure, a manufacturing method and an IGBT device of an IGBT device, which are used to solve the problems of wafer warping, reduced yield, increased manufacturing cost and terminal efficiency degradation caused by the high-temperature push-junction process when the IGBT device adopts a field limiting ring terminal design in the prior art, as well as the problems of edge electric field distortion, increased parasitic capacitance and reduced reliability caused by insufficient electric field control capability that are easily caused when a field plate terminal design is adopted.

[0008] To achieve the above-mentioned object and other related objects, the present invention provides a terminal structure of an IGBT device, comprising:

[0009] A base layer, comprising a substrate and an oxide layer located above the substrate, wherein the substrate comprises a main junction region and a terminal extension region located outside the main junction region, an upper surface layer of the substrate corresponding to the main junction region is provided with a first conductive type well region, and the first conductive type well region forms a PN junction with the substrate;

[0010] a polysilicon layer, located above the oxide layer, wherein an opening is provided in the polysilicon layer to expose the oxide layer, the opening is located in the terminal extension region, an end of the opening facing the main junction region is spaced from an outer edge of the main junction region by a first preset distance D1, and an end of the opening away from the main junction region is spaced from an outer edge of the terminal extension region by a second preset distance D2;

[0011] The dielectric layer comprises a bottom dielectric layer and an intermediate dielectric layer located above the bottom dielectric layer, wherein the bottom dielectric layer covers the polysilicon layer and fills the opening, and the intermediate dielectric layer is located in the area where the opening is located.

[0012] Optionally, the intermediate dielectric layer includes a first dielectric layer and a second dielectric layer stacked together, the material of the first dielectric layer includes nitride, and the material of the second dielectric layer includes at least one of BPSG, PSG, USG and BSG.

[0013] Optionally, the nitride includes Si3N4, and the thickness of the first dielectric layer is in the range of 5 to 300 nanometers, and the thickness of the second dielectric layer is in the range of 2 to 8 micrometers.

[0014] Optionally, the oxide layer includes a gate oxide layer and a field oxide layer that are continuously and adjacently arranged, the field oxide layer at least covers the substrate surface located in the terminal extension region, and the gate oxide layer is located on the substrate surface not covered by the field oxide layer.

[0015] Optionally, it further comprises a conductive metal layer and a passivation layer, wherein the conductive metal layer covers the surface of the dielectric layer, and a plurality of metal openings are provided in the conductive metal layer, and the passivation layer covers the conductive metal layer and fills the metal openings.

[0016] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a terminal structure of an IGBT device, comprising the following steps:

[0017] Providing a base layer, the base layer comprising a substrate and an oxide layer located above the substrate, the substrate comprising a main junction region and a terminal extension region located outside the main junction region, an upper surface layer of the substrate corresponding to the main junction region is provided with a first conductive type well region, and the first conductive type well region forms a PN junction with the substrate;

[0018] A polysilicon layer is formed above the oxide layer, wherein an opening is provided in the polysilicon layer to expose the oxide layer, the opening is located in the terminal extension region, an end of the opening facing the main junction region is spaced from an outer edge of the main junction region by a first preset distance D1, and an end of the opening away from the main junction region is spaced from an outer edge of the terminal extension region by a second preset distance D2;

[0019] A dielectric layer is formed above the polysilicon layer, the dielectric layer comprising a bottom dielectric layer and an intermediate dielectric layer located above the bottom dielectric layer, wherein the bottom dielectric layer covers the polysilicon layer and fills the opening, and the intermediate dielectric layer is located in the area where the opening is located.

[0020] Optionally, the intermediate dielectric layer includes a first dielectric layer and a second dielectric layer stacked together, the material of the first dielectric layer includes nitride, and the material of the second dielectric layer includes at least one of BPSG, PSG, USG and BSG.

[0021] Optionally, the formation of the base layer comprises the following steps:

[0022] Providing a substrate, forming an oxide material layer on the surface of the substrate, and patterning the oxide material layer to obtain a field oxide layer, wherein the field oxide layer at least covers the surface of the substrate located in the terminal extension region;

[0023] Performing ion implantation on the substrate based on the field oxide layer, and then performing a thermal junction treatment to form a well region of the first conductivity type;

[0024] A gate oxide layer is formed on the surface of the substrate to obtain the base layer, wherein the gate oxide layer is located in a region not covered by the field oxide layer, and the gate oxide layer and the field oxide layer are continuously and adjacently arranged to together constitute the oxide layer.

[0025] Optionally, the temperature range of the thermal push junction treatment is 900-1000° C., and the time range of the thermal push junction treatment is 20-70 minutes.

[0026] To achieve the above-mentioned object and other related objects, the present invention further provides an IGBT device, comprising at least one unit cell and a terminal structure as described in any one of the above items, wherein the terminal structure is located at the periphery of the unit cell.

[0027] As described above, the present invention provides a terminal structure, a manufacturing method and an IGBT device of an IGBT device, wherein the terminal structure includes a base layer, a polysilicon layer and a dielectric layer, wherein the base layer includes a substrate and an oxide layer located above the substrate, the substrate includes a main junction region and a terminal extension region located outside the main junction region, the upper surface layer of the substrate corresponding to the main junction region is provided with a first conductive type well region, the first conductive type well region forms a PN junction with the substrate, the polysilicon layer is located above the oxide layer, an opening is provided in the polysilicon layer to expose the oxide layer, the opening is located in the terminal extension region, one end of the opening facing the main junction region is spaced from the outer edge of the main junction region by a first preset distance D1, and one end of the opening away from the main junction region is spaced from the outer edge of the terminal extension region by a second preset distance D2, the dielectric layer includes a bottom dielectric layer and an intermediate dielectric layer located above the bottom dielectric layer, wherein the bottom dielectric layer covers the polysilicon layer and fills into the opening, and the intermediate dielectric layer is located in the region where the opening is located. The terminal structure of the present invention forms an opening at a specific position of the polysilicon layer, fills the opening with the bottom dielectric layer and superimposes the intermediate dielectric layer to form a gradient composite dielectric layer structure. The composite dielectric layer structure can guide the electric field to diffuse from the high curvature region such as the edge of the first conductive type well region to the low field strength region through the gradient potential buffering characteristics, effectively suppressing the concentration of the electric field peak, thereby solving the problems of electric field distortion and terminal efficiency degradation of the traditional field plate terminal. At the same time, the thickening design of the dielectric layer in the opening area of ​​the terminal structure can strengthen the local withstand voltage and significantly enhance the interface withstand voltage capability. The above dual mechanisms work together to effectively improve the overall withstand voltage performance of the device. In addition, the present invention avoids the complex processes such as deep junction ion implantation and high temperature push junction required by the traditional field limiting ring structure. While simplifying the manufacturing process and reducing costs, it eliminates the problems of wafer warping, lattice damage and leakage current degradation that may be caused by the deep junction process and high temperature push junction process, significantly improving the device yield and overall performance. At the same time, compared with the multi-field limiting ring structure, the terminal structure of the present invention further shortens the terminal length, reduces the chip area, and effectively improves the device integration. The formation of the terminal device of the present invention can not only significantly improve the performance of the IGBT device in a high temperature environment, but also effectively enhance the long-term stability of the IGBT device in high reliability applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic cross-sectional structure diagram of the terminal structure of the IGBT device in the first embodiment of the present invention.

[0029] Figure 2 It shows a process flow chart of a method for manufacturing a terminal structure of an IGBT device in the second embodiment of the present invention.

[0030] Figure 3 It is a schematic diagram showing the cross-sectional structure of the base layer provided in the method for manufacturing the terminal structure of the IGBT device in the second embodiment of the present invention.

[0031] Figure 4 It is a schematic diagram of a cross-sectional structure after a polysilicon layer is formed on an oxide layer in a method for manufacturing a terminal structure of an IGBT device in a second embodiment of the present invention.

[0032] Figure 5 It is a schematic diagram of the cross-sectional structure after the opening in the method for manufacturing the terminal structure of the IGBT device in the second embodiment of the present invention extends downward from the surface of the polysilicon layer, penetrates the polysilicon layer and terminates in the field oxide layer.

[0033] Figure 6 It is a schematic diagram of a cross-sectional structure after a dielectric layer is formed on a polysilicon layer in a method for manufacturing a terminal structure of an IGBT device in a second embodiment of the present invention.

[0034] Figure 7 It is a schematic diagram of the cross-sectional structure after forming a conductive metal layer covering the surface of the dielectric layer in the method for manufacturing the terminal structure of the IGBT device in the second embodiment of the present invention.

[0035] Figure 8 It is a schematic diagram of a cross-sectional structure after a passivation layer is formed on a conductive metal layer in a method for manufacturing a terminal structure of an IGBT device in a second embodiment of the present invention.

[0036] Fig. 9 It shows a schematic cross-sectional structure diagram of an IGBT device in the third embodiment of the present invention.

[0037] Component number description

[0038] 1 Terminal structure

[0039] 11. Basal layer

[0040] 111 Substrate

[0041] 1111 Main junction area

[0042] 11111 Well region of first conductivity type

[0043] 1112 Terminal Extension

[0044] 112 Oxide layer

[0045] 1121 Field Oxide Layer

[0046] 1122 Gate Oxide

[0047] 12 Polysilicon layer

[0048] 121 Opening

[0049] 13 Dielectric layer

[0050] 131 bottom dielectric layer

[0051] 132 Intermediate dielectric layer

[0052] 1321 First dielectric layer

[0053] 1322 Second dielectric layer

[0054] 14 Conductive metal layer

[0055] 141 Metal opening

[0056] 1411 First Opening

[0057] 1412 Second Opening

[0058] 1413 The Third Opening

[0059] 15 Top dielectric layer

[0060] 16 Passivation layer

[0061] 2 Cells

[0062] 21 Substrate

[0063] 211 Active Area

[0064] 2111 Second conductivity type well region

[0065] 2112 first conductivity type doping region

[0066] 22. Gate structure layer

[0067] 221 Gate opening

[0068] 222 Gate Oxide

[0069] 223 Polysilicon Gate Layer

[0070] 23 Bottom dielectric layer

[0071] 231 Through Hole

[0072] 24 Conductive metal layer

[0073] Steps S1 to S3 DETAILED DESCRIPTION

[0074] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0076] Embodiment 1

[0077] This embodiment provides a terminal structure 1 of an IGBT device, see Figure 1 , which is a schematic cross-sectional structure diagram of the terminal structure 1 of the IGBT device, including a base layer 11, a polysilicon layer 12 and a dielectric layer 13, wherein the base layer 11 includes a substrate 111 and an oxide layer 112 located above the substrate 111, the substrate 111 includes a main junction region 1111 and a terminal extension region 1112 located outside the main junction region 1111, the upper surface layer of the substrate 111 corresponding to the main junction region 1111 is provided with a first conductive type well region 11111, the first conductive type well region 11111 forms a PN junction with the substrate 111, the polysilicon layer 12 is located above the oxide layer 112, and the polysilicon layer 12 is provided with a first conductive type well region 11111 The oxide layer 112 has an opening 121, wherein the opening 121 is located in the terminal extension region 1112, wherein one end of the opening 121 facing the main junction region 1111 is spaced from the outer edge of the main junction region 1111 by a first preset distance D1, and one end of the opening 121 away from the main junction region 1111 is spaced from the outer edge of the terminal extension region 1112 by a second preset distance D2, wherein the dielectric layer 13 comprises a bottom dielectric layer 131 and an intermediate dielectric layer 132 located above the bottom dielectric layer 131, wherein the bottom dielectric layer 131 covers the polysilicon layer 12 and fills the opening 121, and the intermediate dielectric layer 132 is located in the region where the opening 121 is located.

[0078] Specifically, the substrate 111 may be a single-layer structure or a multi-layer structure, for example, a single substrate, or a stacked structure consisting of a single substrate and an epitaxial layer thereon, wherein the material, doping type and doping concentration of the substrate and / or the epitaxial layer may be selected as required, and are not excessively limited here. For example, the substrate material may be selected from silicon, silicon germanium, III-V compounds, silicon carbide or other suitable semiconductor materials, and its doping type may be N-type or P-type. In this embodiment, the substrate 111 takes an N-type silicon substrate as an example.

[0079] As an example, the conductivity type of the first conductivity type well region 11111 is P type, which can be formed by performing P type ion implantation at a preset position on the surface of the substrate 111, and then performing a thermal push junction treatment. Of course, in other embodiments, the conductivity type of the first conductivity type well region 11111 can also be N type, which can be specifically determined according to the conductivity type of the substrate.

[0080] As an example, the depth of the first conductive type well region 11111 is in the range of 1 to 5.5 micrometers. In this embodiment, the depth of the first conductive type well region 11111 is preferably in the range of 4.5 micrometers.

[0081] As an example, the oxide layer 112 includes a gate oxide layer 1122 and a field oxide layer 1121 that are continuously and adjacently arranged, the field oxide layer 1121 at least covers the surface of the substrate 111 located in the terminal extension region 1112 , and the gate oxide layer 1122 is located on the surface of the substrate 111 not covered by the field oxide layer 1121 .

[0082] Specifically, the material of the oxide layer 112 includes SiO2 or other suitable dielectric materials. In this embodiment, the oxide layer 112 is preferably a SiO2 layer.

[0083] As an example, the thickness of the field oxide layer 1121 is greater than the thickness of the gate oxide layer 1122 .

[0084] As an example, the thickness of the field oxide layer 1121 is in the range of 700 to 1500 nanometers, and the thickness of the gate oxide layer 1122 is in the range of 90 to 150 nanometers. In this embodiment, the thickness of the gate oxide layer 1122 is preferably 120 nanometers.

[0085] As an example, the opening 121 extends downward from the surface of the polysilicon layer 12 , penetrates the polysilicon layer 12 and terminates in the field oxide layer 1121 .

[0086] Specifically, the thickness of the field oxide layer 1121 corresponding to the opening 121 region is smaller than the thickness of the field oxide layer 1121 covered with the polysilicon layer 12 .

[0087] As an example, the thickness of the field oxide layer 1121 corresponding to the opening 121 region is in the range of 700 to 1050 nanometers, and the thickness of the field oxide layer 1121 covered with the polysilicon layer 12 is in the range of 1100 to 1500 nanometers. In this embodiment, the thickness of the field oxide layer 1121 corresponding to the opening 121 region is preferably 925 nanometers, and the thickness of the field oxide layer 1121 covered with the polysilicon layer 12 is preferably 1300 nanometers.

[0088] As an example, the thickness of the polysilicon layer 12 is in the range of 600 to 700 nanometers. In this embodiment, the thickness of the polysilicon layer 12 is preferably 650 nanometers.

[0089] As an example, the numerical range of the first preset distance D1 is 10 to 70 micrometers, and the numerical range of the second preset distance D2 is 5 to 30 micrometers.

[0090] As an example, the bottom dielectric layer 131 includes a USG (undoped silicate glass) layer and a BPSG (boron phospho-silicate glass) layer located above the USG layer, and the thickness of the bottom dielectric layer 131 ranges from 1.5 to 3.5 microns. In this embodiment, the thickness of the bottom dielectric layer 131 is preferably 2.5 microns.

[0091] As an example, the material of the intermediate dielectric layer 132 includes at least one of BPSG, PSG (phosphosilicate glass), USG, BSG (borosilicate glass) and Si 3 N 4 (silicon nitride).

[0092] Specifically, the intermediate dielectric layer 132 may be a single-layer structure or a multi-layer stacked structure, for example, a single dielectric layer or a stacked structure consisting of two or more dielectric layers. In this embodiment, the intermediate dielectric layer 132 is preferably illustrated as a double-layer stacked structure, which can also be expanded to a stacked structure consisting of three or more dielectric layers in practical applications.

[0093] As an example, the intermediate dielectric layer 132 includes a stacked first dielectric layer 1321 and a second dielectric layer 1322 , the material of the first dielectric layer 1321 includes nitride, and the material of the second dielectric layer 1322 includes at least one of BPSG, PSG, USG and BSG.

[0094] As an example, the nitride includes Si3N4.

[0095] As an example, the thickness of the first dielectric layer 1321 is in the range of 5 to 300 nanometers, and the thickness of the second dielectric layer 1322 is in the range of 2 to 8 micrometers. In this embodiment, the first dielectric layer 1321 is preferably a Si3N4 layer, and the second dielectric layer 1322 is preferably a PSG layer. The thickness of the Si3N4 layer is preferably 150 nanometers, and the thickness of the PSG layer is preferably 4.5 micrometers.

[0096] As an example, the top surface of the middle dielectric layer 132 is higher than the top surface of the bottom dielectric layer 131 .

[0097] Specifically, the top surface of the middle dielectric layer 132 located in the area where the opening 121 is located is higher than the top surface of the bottom dielectric layer 131 located above the polysilicon layer 12 .

[0098] As an example, the terminal structure 1 also includes a conductive metal layer 14 and a passivation layer 16 , wherein the conductive metal layer 14 covers the surface of the dielectric layer 13 , and a plurality of metal openings 141 are provided in the conductive metal layer 14 , and the passivation layer 16 covers the conductive metal layer 14 and fills the metal openings 141 .

[0099] As an example, the terminal structure 1 further includes a top dielectric layer 15 , which covers the conductive metal layer 14 and fills the metal opening 141 , and the passivation layer 16 is located on the top dielectric layer 15 .

[0100] Specifically, the conductive metal layer 14 includes an AlCu layer, an AlSiCu layer or other suitable conductive material layer.

[0101] As an example, the metal opening 141 includes a first opening 1411 and a second opening 1412, the first opening 1411 is located at the junction of the main junction area 1111 and the terminal extension area 1112, the bottom of the first opening 1411 exposes the underlying dielectric layer 131, the second opening 1412 is located in the terminal extension area 1112 and in the opening 121 area of ​​the polysilicon layer 12, and the bottom of the second opening 1412 exposes the intermediate dielectric layer 132.

[0102] As an example, the metal opening 141 further includes a third opening 1413 , which is located in the terminal extension region 1112 and outside the opening 121 of the polysilicon layer 12 , and the bottom of the third opening 1413 exposes the underlying dielectric layer 131 .

[0103] Specifically, the top dielectric layer 15 includes a Si3N4 layer, a SRN (silicon rich nitride) layer or other suitable dielectric material layer. In this embodiment, the top dielectric layer 15 is preferably a Si3N4 layer.

[0104] Specifically, the material of the passivation layer 16 includes polyimide. The thickness of the passivation layer 16 is in the range of 5 to 20 micrometers.

[0105] The terminal structure of the IGBT device of this embodiment forms a composite dielectric layer structure with three-dimensional gradient potential buffering characteristics by setting an opening at a specific position of the polysilicon layer, filling the opening with an underlying dielectric layer, and superimposing an intermediate dielectric layer on this basis. The gradient-distributed dielectric layer in this structure can effectively guide the electric field to expand from the high curvature area (such as the edge of the first conductive type well area) to the low electric field strength area, thereby significantly suppressing the peak concentration of the electric field. In addition, the thickening design of the intermediate dielectric layer in the opening area effectively improves the local withstand voltage strength, and the interaction between the two further improves the overall withstand voltage performance. Compared with the traditional multi-field limiting ring structure, this terminal structure avoids complex processes such as deep junction ion implantation and high-temperature push junction, which not only reduces the production cost, but also effectively reduces the lattice damage and leakage current problems caused by the deep junction process, thereby significantly improving the reliability of the device.

[0106] Embodiment 2

[0107] This embodiment provides a method for manufacturing a terminal structure of an IGBT device, which can be used to manufacture the terminal structure 1 of the IGBT device as described in the first embodiment. Figure 2 As shown, it is shown as a process flow chart of the method, comprising the following steps:

[0108] S1: providing a base layer, the base layer comprising a substrate and an oxide layer located above the substrate, the substrate comprising a main junction region and a terminal extension region located outside the main junction region, an upper surface layer of the substrate corresponding to the main junction region is provided with a first conductive type well region, and the first conductive type well region forms a PN junction with the substrate;

[0109] S2: forming a polysilicon layer above the oxide layer, wherein an opening is provided in the polysilicon layer to expose the oxide layer, the opening is located in the terminal extension region, an end of the opening facing the main junction region is spaced from an outer edge of the main junction region by a first preset distance D1, and an end of the opening away from the main junction region is spaced from an outer edge of the terminal extension region by a second preset distance D2;

[0110] S3: forming a dielectric layer above the polysilicon layer, the dielectric layer comprising a bottom dielectric layer and an intermediate dielectric layer located above the bottom dielectric layer, wherein the bottom dielectric layer covers the polysilicon layer and fills the opening, and the intermediate dielectric layer is located in the area where the opening is located.

[0111] First, see Figure 3 , perform the step S1: provide a base layer 11, the base layer 11 includes a substrate 111 and an oxide layer 112 located above the substrate 111, the substrate 111 includes a main junction area 1111 and a terminal extension area 1112 located outside the main junction area 1111, the upper surface layer of the substrate 111 corresponding to the main junction area 1111 is provided with a first conductive type well area 11111, and the first conductive type well area 11111 forms a PN junction with the substrate 111.

[0112] As an example, the formation of the base layer 11 includes the following steps:

[0113] (1) providing a substrate 111, forming an oxide material layer on the surface of the substrate 111, and patterning the oxide material layer to obtain a field oxide layer 1121, wherein the field oxide layer 1121 at least covers the surface of the substrate 111 located in the terminal extension region 1112 (not shown);

[0114] (2) performing ion implantation on the substrate 111 based on the field oxide layer 1121, and then performing a thermal push-in junction treatment to form a first conductive type well region 11111 (not shown);

[0115] (3) Figure 3 As shown, a gate oxide layer 1122 is formed on the surface of the substrate 111 to obtain the base layer 11, wherein the gate oxide layer 1122 is located in an area not covered by the field oxide layer 1121, and the gate oxide layer 1122 and the field oxide layer 1121 are continuously and adjacently arranged to together constitute the oxide layer 112.

[0116] Specifically, the substrate 111 may be a single-layer structure or a multi-layer structure, for example, a single substrate, or a stacked structure consisting of a single substrate and an epitaxial layer thereon, wherein the material, doping type and doping concentration of the substrate and / or the epitaxial layer may be selected as required, and are not excessively limited here. For example, the substrate material may be selected from silicon, silicon germanium, III-V compounds, silicon carbide or other suitable semiconductor materials, and its doping type may be N-type or P-type. In this embodiment, the substrate 111 takes an N-type silicon substrate as an example.

[0117] Specifically, thermal oxidation (such as wet oxidation, dry oxidation) or other suitable methods can be used to form the oxide material layer on the upper and lower surfaces of the substrate 111, and then the oxide material layer is patterned by conventional photolithography and etching processes to form the field oxide layer 1121. Finally, based on the field oxide layer 1121, P-type ion implantation (such as boron ion implantation) is performed on the substrate 111, and a thermal push junction treatment is performed after the implantation is completed, so as to form the first conductive type well region 11111. It should be noted that the conductivity type of the first conductive type well region 11111 is not limited to the P type. In other embodiments, according to the initial conductivity type of the substrate 111, N-type ion implantation can also be selected to form an N-type well region.

[0118] As an example, the thickness of the field oxide layer 1121 is in the range of 700 to 1500 nanometers.

[0119] As an example, the temperature range of the thermal push junction treatment is 900-1000° C., and the time range of the thermal push junction treatment is 20-70 minutes. In this embodiment, the temperature of the thermal push junction treatment is preferably 950° C., and the time of the thermal push junction treatment is preferably 60 minutes.

[0120] As an example, the depth of the first conductive type well region 11111 is in the range of 1 to 5.5 micrometers. In this embodiment, the depth of the first conductive type well region 11111 is preferably in the range of 4.5 micrometers.

[0121] Specifically, the gate oxide layer 1122 may be formed by thermal oxidation or other suitable methods, and the thickness of the field oxide layer 1121 is greater than the thickness of the gate oxide layer 1122 .

[0122] As an example, the thickness of the gate oxide layer 1122 ranges from 90 to 150 nanometers. In this embodiment, the thickness of the gate oxide layer 1122 is preferably 120 nanometers.

[0123] Please see again Figure 4 , perform the step S2: form a polysilicon layer 12 above the oxide layer 112, and an opening 121 is provided in the polysilicon layer 12 to expose the oxide layer 112, and the opening 121 is located in the terminal extension area 1112, and the opening 121 is spaced from the outer edge of the main junction area 1111 by a first preset distance D1 at one end facing the main junction area 1111, and the opening 121 is spaced from the outer edge of the terminal extension area 1112 by a second preset distance D2 at one end away from the main junction area 1111.

[0124] Specifically, chemical vapor deposition or other suitable methods may be used to form a polysilicon material layer covering the surface of the oxide layer 112. Then, the polysilicon material layer is patterned by dry etching and / or wet etching to form the polysilicon layer 12.

[0125] As an example, the thickness of the polysilicon layer 12 is in the range of 600 to 700 nanometers. In this embodiment, the thickness of the polysilicon layer 12 is preferably 650 nanometers.

[0126] As an example, the numerical range of the first preset distance D1 is 10 to 70 micrometers, and the numerical range of the second preset distance D2 is 5 to 30 micrometers.

[0127] As an example, Figure 5 As shown, the opening 121 extends downward from the surface of the polysilicon layer 12 , penetrates the polysilicon layer 12 and terminates in the field oxide layer 1121 .

[0128] Specifically, in the process of forming the opening 121, the polysilicon material layer is first etched until the polysilicon material layer is completely penetrated, and then the field oxide layer 1121 at the bottom of the polysilicon material layer is continuously etched until the opening 121 reaches a preset depth and ends in the field oxide layer 1121.

[0129] As an example, the thickness of the field oxide layer 1121 corresponding to the opening 121 region is smaller than the thickness of the field oxide layer 1121 covered with the polysilicon layer 12 .

[0130] As an example, the thickness of the field oxide layer 1121 corresponding to the opening 121 region is in the range of 700 to 1050 nanometers, and the thickness of the field oxide layer 1121 covered with the polysilicon layer 12 is in the range of 1100 to 1500 nanometers. In this embodiment, the thickness of the field oxide layer 1121 corresponding to the opening 121 region is preferably 925 nanometers, and the thickness of the field oxide layer 1121 covered with the polysilicon layer 12 is preferably 1300 nanometers.

[0131] Please see again Figure 6 , perform the step S3: form a dielectric layer 13 above the polysilicon layer 12, the dielectric layer 13 includes a bottom dielectric layer 131 and an intermediate dielectric layer 132 located above the bottom dielectric layer 131, wherein the bottom dielectric layer 131 covers the polysilicon layer 12 and fills the opening 121, and the intermediate dielectric layer 132 is located in the area where the opening 121 is located.

[0132] As an example, the bottom dielectric layer 131 includes a USG layer and a BPSG layer located above the USG layer, and the thickness of the bottom dielectric layer 131 is in the range of 1.5 to 3.5 microns.

[0133] Specifically, APCVD (atmospheric pressure chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition) or other suitable methods can be used to sequentially deposit a USG layer and a BPSG layer on the polysilicon layer 12 to form the bottom dielectric layer 131. In this embodiment, the bottom dielectric layer 131 is preferably formed by the APCVD method, and the thickness of the bottom dielectric layer 131 is preferably 2.5 microns.

[0134] As an example, the intermediate dielectric layer 132 includes a stacked first dielectric layer 1321 and a second dielectric layer 1322 , the material of the first dielectric layer 1321 includes nitride, and the material of the second dielectric layer 1322 includes at least one of BPSG, PSG, USG and BSG.

[0135] As an example, the nitride includes Si3N4.

[0136] As an example, the thickness of the first dielectric layer 1321 is in the range of 5 to 300 nanometers, and the thickness of the second dielectric layer 1322 is in the range of 2 to 8 micrometers. In this embodiment, the first dielectric layer 1321 is preferably a Si3N4 layer, and the second dielectric layer 1322 is preferably a PSG layer.

[0137] Specifically, a dielectric material layer may be deposited on the surface of the bottom dielectric layer 131 by LPCVD (low pressure chemical vapor deposition), PECVD or other suitable process methods. Afterwards, the dielectric material layer is patterned by photolithography and etching processes (dry etching and / or wet etching) to finally form the intermediate dielectric layer 132. In this embodiment, the intermediate dielectric layer 132 is preferably formed by a step-by-step deposition and patterning process, and the specific process is as follows: first, the first dielectric layer 1321 (Si3N4 layer) is deposited on the surface of the bottom dielectric layer 131 by LPCVD, and then the second dielectric layer 1322 (PSG layer) is formed on the surface of the first dielectric layer 1321 by PECVD to form a double-layer stacked structure; then, the stacked structure is patterned by photolithography and etching processes to obtain the intermediate dielectric layer 132. The thickness of the Si3N4 layer is preferably 150 nanometers, and the thickness of the PSG layer is preferably 4.5 micrometers.

[0138] As an example, the top surface of the middle dielectric layer 132 is higher than the top surface of the bottom dielectric layer 131 .

[0139] Specifically, the top surface of the middle dielectric layer 132 located in the area where the opening 121 is located is higher than the top surface of the bottom dielectric layer 131 located above the polysilicon layer 12 .

[0140] As an example, after forming the dielectric layer 13, the following steps are further included:

[0141] (1) Figure 7 As shown, a conductive metal layer 14 is formed to cover the surface of the dielectric layer 13, and a plurality of metal openings 141 are provided in the conductive metal layer 14;

[0142] (2) Figure 8 As shown, a passivation layer 16 is formed on the conductive metal layer 14 , and the passivation layer 16 covers the conductive metal layer 14 and fills the metal opening 141 .

[0143] As an example, before forming the passivation layer 16 , a step of forming a top dielectric layer 15 is also included, the top dielectric layer covers the conductive metal layer 14 and fills the metal opening 141 , and the passivation layer 16 is located on the top dielectric layer 15 .

[0144] Specifically, a conductive material layer may be deposited on the surface of the dielectric layer 13 by evaporation, sputtering or other suitable methods, and then the conductive material layer may be patterned by photolithography and etching processes, thereby obtaining the conductive metal layer 14 having a plurality of metal openings 141. The conductive metal layer 14 includes an AlCu layer, an AlSiCu layer or other suitable conductive material layer.

[0145] As an example, the metal opening 141 includes a first opening 1411 and a second opening 1412, the first opening 1411 is located at the junction of the main junction area 1111 and the terminal extension area 1112, the bottom of the first opening 1411 exposes the underlying dielectric layer 131, the second opening 1412 is located in the terminal extension area 1112 and in the opening 121 area of ​​the polysilicon layer 12, and the bottom of the second opening 1412 exposes the intermediate dielectric layer 132.

[0146] As an example, the metal opening 141 further includes a third opening 1413 , which is located in the terminal extension region 1112 and outside the opening 121 of the polysilicon layer 12 , and the bottom of the third opening 1413 exposes the underlying dielectric layer 131 .

[0147] Specifically, the top dielectric layer 15 may be formed on the conductive metal layer 14 by chemical vapor deposition, physical vapor deposition or other suitable methods. The top dielectric layer 15 includes a Si3N4 layer, a SRN (silicon rich nitride) layer or other suitable dielectric material layer. In this embodiment, the top dielectric layer 15 is preferably a Si3N4 layer.

[0148] Specifically, the passivation layer 16 can be formed on the top dielectric layer 15 by chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, spray coating, dip coating or other suitable methods. The material of the passivation layer 16 includes polyimide, and the thickness of the passivation layer 16 ranges from 5 to 20 microns.

[0149] The manufacturing method of the terminal structure of the IGBT device of this embodiment forms a composite dielectric layer structure with three-dimensional gradient potential buffering characteristics by forming a specific opening on the polysilicon layer, filling the opening with an underlying dielectric layer, and then superimposing an intermediate dielectric layer. The gradient-distributed dielectric layer in the structure can effectively guide the electric field to expand from the high curvature area (such as the edge of the first conductive type well area) to the low electric field strength area, thereby significantly suppressing the peak concentration of the electric field. In addition, the thickening design of the intermediate dielectric layer in the opening area greatly improves the local withstand voltage strength. Under the synergistic effect of the two, the overall withstand voltage performance is significantly improved. Compared with the traditional multi-field limiting ring structure, the formation of the terminal structure avoids deep junction ion implantation and high-temperature push-junction process, which not only effectively reduces the production cost, but also avoids the lattice damage and leakage current increase problems that may be caused by the deep junction process, thereby effectively improving the reliability of the device.

[0150] Embodiment 3

[0151] This embodiment provides an IGBT device. Fig. 9 , which is a schematic diagram of the cross-sectional structure of the IGBT device, wherein the IGBT device includes at least one cell 2 and the terminal structure 1 described in the first embodiment, wherein the terminal structure 1 is located at the periphery of the cell 2 and is used to achieve an optimized distribution of the electric field at the edge of the device.

[0152] As an example, the substrate 21 further includes an active region 211 .

[0153] Specifically, Fig. 9As shown, the area corresponding to the cell 2 is the left area (i.e., the active area 211), and the area corresponding to the terminal structure 1 is the right area (i.e., the main junction area 1111 and the terminal extension area 1112). It should be noted that the substrate 21 described in this embodiment is the same substrate structure as the substrate 111 in Embodiment 1 and Embodiment 2. In order to clearly distinguish different functional areas, this embodiment defines the functional partitions of the substrate: the substrate portion in the active area 211 is defined as substrate 21, and the substrate portion in the main junction area 1111 and the terminal extension area 1112 is defined as substrate 111. This definition is only used to distinguish functional areas, and does not mean that there are differences in the physical structure of the substrate. In fact, the substrate 21 and the substrate 111 are physically continuous and unified, and are only distinguished by the division of functional areas.

[0154] As an example, the cell 2 includes a trench gate or a planar gate structure. In this embodiment, the planar gate is taken as an example for description.

[0155] As an example, the cell 2 includes the substrate 21, the gate structure layer 22, the bottom dielectric layer 23 and the conductive metal layer 24 located in the active area 211, wherein the upper surface layer of the substrate 21 is provided with a second conductive type well region 2111, and the second conductive type well region 2111 is provided with a first conductive type doped region 2112, the gate structure layer 22 is located above the substrate 21, and the gate structure layer 22 is provided with a gate opening 221 exposing the second conductive type well region 2111, the bottom dielectric layer 23 covers the surface of the gate structure layer 22 and fills the gate opening 221, and the bottom dielectric layer 23 is provided with a through hole 231 exposing the first conductive type doped region 2112, and the conductive metal layer 24 is located above the bottom dielectric layer 23 and fills the through hole 231.

[0156] As an example, the conductivity type of the second conductivity type well region 2111 is P type, and the conductivity type of the first conductivity type doped region 2112 is N type.

[0157] As an example, the gate structure layer 22 includes a gate oxide layer 222 and a polysilicon gate layer 223 located above the gate oxide layer 222 .

[0158] It should be noted that the bottom dielectric layer 23 of this embodiment is consistent with the bottom dielectric layer 131 in Embodiment 1 and Embodiment 2 in terms of material, structure and function, the conductive metal layer 24 is consistent with the conductive metal layer 14 in Embodiment 1 and Embodiment 2 in terms of material, structure and function, and the gate oxide layer 222 is consistent with the gate oxide layer 1122 in Embodiment 1 and Embodiment 2 in terms of material, structure and function. Such differences in the naming of the layer structures between different embodiments only reflect the requirements for device area division, and do not represent any substantial differences in terms of material, structure or function.

[0159] The IGBT device of this embodiment includes a cell and a terminal structure located at the periphery of the cell. The terminal structure is designed based on a gradient dielectric layer, and suppresses peak electric field concentration and enhances local withstand voltage capability through electric field distribution optimization, while avoiding deep junction injection and high-temperature junction pushing processes. This embodiment achieves a synergistic improvement in the withstand voltage performance and electric field regulation capability of the IGBT device through the above-mentioned terminal structure, and has both cost advantages and reliability enhancement.

[0160] In summary, the present invention provides a terminal structure, a manufacturing method and an IGBT device of an IGBT device, wherein the terminal structure includes a base layer, a polysilicon layer and a dielectric layer, wherein the base layer includes a substrate and an oxide layer located above the substrate, the substrate includes a main junction region and a terminal extension region located outside the main junction region, the upper surface layer of the substrate corresponding to the main junction region is provided with a first conductive type well region, the first conductive type well region forms a PN junction with the substrate, the polysilicon layer is located above the oxide layer, an opening is provided in the polysilicon layer to expose the oxide layer, the opening is located in the terminal extension region, one end of the opening facing the main junction region is spaced from the outer edge of the main junction region by a first preset distance D1, and one end of the opening away from the main junction region is spaced from the outer edge of the terminal extension region by a second preset distance D2, the dielectric layer includes a bottom dielectric layer and an intermediate dielectric layer located above the bottom dielectric layer, wherein the bottom dielectric layer covers the polysilicon layer and fills into the opening, and the intermediate dielectric layer is located in the region where the opening is located. The terminal structure of the present invention forms an opening at a specific position of the polysilicon layer, fills the opening with the bottom dielectric layer and superimposes the intermediate dielectric layer to form a gradient composite dielectric layer structure. The composite dielectric layer structure can guide the electric field to diffuse from the high curvature region such as the edge of the first conductive type well region to the low field strength region through the gradient potential buffering characteristics, effectively suppressing the concentration of the electric field peak, thereby solving the problems of electric field distortion and terminal efficiency degradation of the traditional field plate terminal. At the same time, the thickening design of the dielectric layer in the opening area of ​​the terminal structure can strengthen the local withstand voltage and significantly enhance the interface withstand voltage capability. The above dual mechanisms work together to effectively improve the overall withstand voltage performance of the device. In addition, the present invention avoids the complex processes such as deep junction ion implantation and high temperature push junction required by the traditional field limiting ring structure. While simplifying the manufacturing process and reducing costs, it eliminates the problems of wafer warping, lattice damage and leakage current degradation that may be caused by the deep junction process and high temperature push junction process, significantly improving the device yield and overall performance. At the same time, compared with the multi-field limiting ring structure, the terminal structure of the present invention further shortens the terminal length, reduces the chip area, and effectively improves the device integration. The formation of the terminal device of the present invention can not only significantly improve the performance of the IGBT device in a high temperature environment, but also effectively enhance the long-term stability of the IGBT device in high reliability applications. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0161] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A terminal structure of an IGBT device, characterized in that: include: A base layer, comprising a substrate and an oxide layer located above the substrate, wherein the substrate comprises a main junction region and a terminal extension region located outside the main junction region, an upper surface layer of the substrate corresponding to the main junction region is provided with a first conductive type well region, and the first conductive type well region forms a PN junction with the substrate; a polysilicon layer, located above the oxide layer, wherein an opening is provided in the polysilicon layer to expose the oxide layer, the opening is located in the terminal extension region, an end of the opening facing the main junction region is spaced from an outer edge of the main junction region by a first preset distance D1, and an end of the opening away from the main junction region is spaced from an outer edge of the terminal extension region by a second preset distance D2; The dielectric layer comprises a bottom dielectric layer and an intermediate dielectric layer located above the bottom dielectric layer, wherein the bottom dielectric layer covers the polysilicon layer and fills the opening, and the intermediate dielectric layer is located in the area where the opening is located.

2. The terminal structure according to claim 1, characterized in that: The intermediate dielectric layer includes a first dielectric layer and a second dielectric layer stacked together. The material of the first dielectric layer includes nitride, and the material of the second dielectric layer includes at least one of BPSG, PSG, USG and BSG.

3. The terminal structure according to claim 2, characterized in that: The nitride includes Si3N4, the thickness of the first dielectric layer is in the range of 5 to 300 nanometers, and the thickness of the second dielectric layer is in the range of 2 to 8 micrometers.

4. The terminal structure according to claim 1, characterized in that: The oxide layer includes a gate oxide layer and a field oxide layer which are continuously and adjacently arranged. The field oxide layer at least covers the substrate surface located in the terminal extension region, and the gate oxide layer is located on the substrate surface not covered by the field oxide layer.

5. The terminal structure according to claim 1, characterized in that: It also includes a conductive metal layer and a passivation layer. The conductive metal layer covers the surface of the dielectric layer, and a plurality of metal openings are arranged in the conductive metal layer. The passivation layer covers the conductive metal layer and fills the metal openings.

6. A method for manufacturing a terminal structure of an IGBT device, characterized in that: The following steps are involved: Providing a base layer, the base layer comprising a substrate and an oxide layer located above the substrate, the substrate comprising a main junction region and a terminal extension region located outside the main junction region, an upper surface layer of the substrate corresponding to the main junction region is provided with a first conductive type well region, and the first conductive type well region forms a PN junction with the substrate; A polysilicon layer is formed above the oxide layer, wherein an opening is provided in the polysilicon layer to expose the oxide layer, the opening is located in the terminal extension region, an end of the opening facing the main junction region is spaced from an outer edge of the main junction region by a first preset distance D1, and an end of the opening away from the main junction region is spaced from an outer edge of the terminal extension region by a second preset distance D2; A dielectric layer is formed above the polysilicon layer, the dielectric layer comprising a bottom dielectric layer and an intermediate dielectric layer located above the bottom dielectric layer, wherein the bottom dielectric layer covers the polysilicon layer and fills the opening, and the intermediate dielectric layer is located in the area where the opening is located.

7. The method for manufacturing the terminal structure of the IGBT device according to claim 6, characterized in that: The intermediate dielectric layer includes a first dielectric layer and a second dielectric layer stacked together. The material of the first dielectric layer includes nitride, and the material of the second dielectric layer includes at least one of BPSG, PSG, USG and BSG.

8. The method for manufacturing the terminal structure of the IGBT device according to claim 6, characterized in that: The formation of the base layer comprises the following steps: Providing a substrate, forming an oxide material layer on the surface of the substrate, and patterning the oxide material layer to obtain a field oxide layer, wherein the field oxide layer at least covers the surface of the substrate located in the terminal extension region; Performing ion implantation on the substrate based on the field oxide layer, and then performing a thermal junction treatment to form a well region of the first conductivity type; A gate oxide layer is formed on the surface of the substrate to obtain the base layer, wherein the gate oxide layer is located in a region not covered by the field oxide layer, and the gate oxide layer and the field oxide layer are continuously and adjacently arranged to together constitute the oxide layer.

9. The method for manufacturing the terminal structure of the IGBT device according to claim 8, characterized in that: The temperature range of the heat push junction treatment is 900-1000° C., and the time range of the heat push junction treatment is 20-70 minutes.

10. An IGBT device, characterized in that: The method comprises at least one unit cell and a terminal structure as claimed in any one of claims 1 to 5, wherein the terminal structure is located at the periphery of the unit cell.

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