Physical non-replicable functional element and manufacturing method thereof

Abstract

The present invention discloses a method of fabricating a physical unclonable function (PUF) device and a method of fabricating the same, the method mainly providing a PUF cell array, the PUF cell array comprising a plurality of unit lattices, each of the unit lattices comprising a transistor and a first metal-oxide-semiconductor capacitor (MOSCAP), and a second MOSCAP coupled to the transistor, the first metal-oxide-semiconductor capacitor (MOSCAP) being coupled to the transistor, the second metal-oxide-semiconductor capacitor (MOSCAP) being coupled to the transistor, the first metal-oxide-semiconductor capacitor (MOSCAP) being coupled to the transistor, the second metal-oxide-semiconductor capacitor (MOSCAP) being coupled to the transistor, the second metal-oxide-semiconductor capacitor (MOSCAP) being coupled to the transistor, and the second metal-oxide-semiconductor capacitor (MOSCAP) being coupled to the transistor. The transistor transmits a voltage to the first MOSCAP and the second MOSCAP, and determines whether the first MOSCAP or the second MOSCAP reaches a breakdown state.

Description

Technical Field

[0001] The invention relates to a physically non-copyable functional element and a manufacturing method thereof. Background Art

[0002] Although integrated circuits are designed and manufactured with the same materials and fabrication processes, each integrated circuit may have inherent variations from one another that make each integrated circuit unique. In recent years, security researchers have proposed physically unclonable functions (PUFs), which use the inherent variations between integrated circuits as unique identifiers similar to human DNA. PUFs are physical objects that can be used to generate unique identifiers or unique keys for encryption, secure computing, or secure communications. Due to the random nature of the PUF output, the output of a PUF object is very difficult to predict and adds a layer of security. Summary of the invention

[0003] An embodiment of the present invention discloses a method for manufacturing a physically unclonable function (PUF) element, which mainly provides a PUF cell array, wherein the PUF cell array includes a plurality of unit cells, wherein each unit cell includes a transistor and a first metal-oxide-semiconductor capacitor (MOSCAP) and a second MOSCAP coupled to the transistor. Then, a voltage is transmitted to the first MOSCAP and the second MOSCAP through the transistor to determine whether the first MOSCAP or the second MOSCAP reaches a breakdown state.

[0004] Another embodiment of the present invention discloses a physically unclonable function (PUF) element, which mainly includes a PUF cell array, wherein the PUF cell array includes a plurality of unit cells, wherein each of the unit cells includes a transistor and a first MOSCAP and a second MOSCAP coupled to the transistor, wherein a voltage is transmitted to the first MOSCAP and the second MOSCAP via the transistor to determine whether the first MOSCAP or the second MOSCAP reaches a breakdown state. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A schematic diagram of manufacturing a PUF element under a circuit architecture according to an embodiment of the present invention;

[0006] Figure 2 A schematic diagram of a PUF element in a semiconductor device architecture according to an embodiment of the present invention;

[0007] Figures 3 to 8 FIG. 1 is a schematic diagram of a method for manufacturing MOS transistors and MOSCAPs in a PUF device in a semiconductor device architecture according to an embodiment of the present invention.

[0008] Explanation of symbols

[0009] 12: Base

[0010] 14: Non-MOSCAP area

[0011] 16: MOSCAP area

[0012] 18: Base

[0013] 20: Fin structure

[0014] 22: Shallow Trench Isolation

[0015] 30: Gate oxide layer

[0016] 32: Gate electrode

[0017] 34: Gate electrode

[0018] 36: Gate material layer

[0019] 38: Interlayer dielectric layer

[0020] 40: Source / drain region

[0021] 46: High dielectric constant dielectric layer

[0022] 48: Work function metal layer

[0023] 50: Low impedance metal layer

[0024] 52: Insulation layer

[0025] 54: Patterned Mask

[0026] 56: Ion implantation process

[0027] 58: Peak annealing process

[0028] 72:Metal gate

[0029] 74: Hard mask

[0030] 100:PUF cell array

[0031] 102: Unit Cell

[0032] 104: Transistor

[0033] 106: First MOSCAP

[0034] 108: Second MOSCAP

[0035] 110: Gate

[0036] 112: First End

[0037] 114: Second End

[0038] 132: Gate electrode

[0039] 134: Dielectric layer DETAILED DESCRIPTION

[0040] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of manufacturing a PUF element under a circuit architecture according to an embodiment of the present invention. Figure 1 As shown in the upper left corner, a PUF cell array 100 is first provided, wherein the PUF cell array 100 includes a plurality of unit cells 102 and each unit cell 102 is connected to a bit line (BL) and a word line (WL) according to a circuit design.

[0041] like Figure 1 As shown in the lower right corner, each unit cell 102 further includes a transistor 104 such as a metal oxide semiconductor (MOS) transistor and a first MOSCAP 106 and a second MOSCAP 108 coupled to the transistor 104. Figure 1 From the upper right corner, each transistor 104 includes a gate 110 or gate electrode, a first end 112 and a second end 114, wherein the gate 110 is coupled to a word line WL, the first end 112 is coupled to the first MOSCAP 106 and the second MOSCAP 108, the second end 114 is coupled to a source line (SL), and the first MOSCAP 106 coupled to the first end 112 of each transistor 104 is coupled to the first bit line BL-1 and the second MOSCAP 108 is coupled to the second bit line BL-2.

[0042] Please also refer to Figure 1 Bottom right corner, Figure 1 The lower right corner is a schematic diagram of the operation of programming and reading the PUF cell array according to an embodiment of the present invention. Figure 1 As shown in the lower right corner, only one programming operation is performed first, which mainly transmits a voltage to the first MOSCAP 106 and the second MOSCAP 108 through the transistor 104 and determines whether one of the first MOSCAP 106 or the second MOSCAP 108 reaches a breakdown state.

[0043] More specifically, the programming operation performed in this stage is mainly performed by the source line SL connected to the second terminal 114 of the transistor 104 transmitting a voltage to the first MOSCAP 106 and the second MOSCAP 108 through a compliance limiter, so that one of the two reaches a breakdown state, wherein the compliance limiter mainly limits the programming operation to a single action, that is, the action is stopped when one of the first MOSCAP 106 or the second MOSCAP 108 reaches a breakdown. In addition, in this embodiment, the breakdown state achieved is preferably a soft breakdown, that is, when the voltage is used to stress the first MOSCAP 106 and the second MOSCAP 108, the gate dielectric layer composed of, for example, silicon oxide in the MOSCAP element is mainly oxide ruptured, thereby achieving voltage breakdown.

[0044] It should be noted that the action of applying pressure to the first MOSCAP 106 and the second MOSCAP 108 by using voltage to make one of the two MOSCAPs reach the breakdown state is preferably completely random. In other words, when the source line SL of the second end 114 of the transistor 104 transmits voltage to the first MOSCAP 106 and the second MOSCAP 108 of the first end 112, only one of the two MOSCAPs will reach the breakdown state and the user cannot predict in advance which of the two MOSCAPs will reach the breakdown state first, that is, it is possible that the first MOSCAP 106 reaches the breakdown state or the second MOSCAP 108 reaches the breakdown state.

[0045] Then as Figure 1 As shown in the lower right corner, in the read phase, the first bit line BL-1 and the second bit line BL-2 can be used to detect which MOSCAP element is in the on state or which MOSCAP element is in the breakdown state. For example, if the first bit line BL-1 is in the breakdown state, the first MOSCAP 106 can be assigned a first state value such as state 1, and if the second bit line BL-2 is in the breakdown state, the second MOSCAP 108 can be assigned a second state value such as state 0.

[0046] From the overall programming operation, first, a voltage is transmitted to the first MOSCAP 106 and the second MOSCAP 108 via the transistor 104 and it is determined whether the first MOSCAP 106 or the second MOSCAP 108 reaches a breakdown state. When a voltage is transmitted to the first MOSCAP 106 to initiate a breakdown state, the first MOSCAP 106 may be assigned a first state value such as "1" and the second MOSCAP may be assigned a second state value such as "0". Similarly, when a voltage is transmitted to the second MOSCAP 108 to initiate a breakdown state, the second MOSCAP 108 may be assigned a first state value such as "1" and the first MOSCAP 106 may be assigned a second state value such as "0".

[0047] Please continue to refer to Figures 2 to 8 , Figure 2 FIG. 1 is a schematic diagram of a PUF device in a semiconductor device architecture according to an embodiment of the present invention. Figures 3 to 8 FIG. 1 is a schematic diagram of a method for manufacturing MOS transistors and MOSCAP in a PUF device in a semiconductor device architecture according to an embodiment of the present invention. Figure 2 As shown, the PUF element as a whole includes a transistor 104, such as a metal oxide semiconductor conductor (MOS) transistor, and a first MOSCAP 106 and a second MOSCAP 108 are coupled to the transistor 104 at the same time, wherein a first terminal 112 of the transistor 104 is coupled to the first MOSCAP 106 and the second MOSCAP 108 at the same time, and a second terminal 114 is coupled to a source line SL, the first MOSCAP 106 is coupled to the first bit line BL-1, and the second MOSCAP 108 is coupled to the second bit line BL-2.

[0048] like Figure 3 As shown, the preparation of MOS transistors and MOSCAP elements in the PUF element may first provide a substrate 12, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, on which at least two regions are defined, including a non-MOSCAP area 14 and a MOSCAP area 16, wherein the non-MOSCAP area 14 may be used in the subsequent manufacturing process to prepare input / output (I / O) elements or low-voltage elements such as MOS transistors in the PUF element, and the MOSCAP area 16 is preferably used to prepare the MOSCAP element in the PUF element. In order to highlight the detailed structure in the MOSCAP element, the subsequent manufacturing process only forms a single MOSCAP element in the MOSCAP area 16, such as one of the first MOSCAP 106 or the second MOSCAP 108.

[0049] Then, a base 18 and a fin structure 20 can be formed on the substrate 12 of the non-MOSCAP area 16, and a plurality of fin structures 20 can be formed on the substrate 12 of the MOSCAP area 18. According to a preferred embodiment of the present invention, the fin structure 20 is preferably obtained by sidewall image transfer (SIT) technology, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers or mandrels can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. Subsequently, the patterned sacrificial layer is removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then a fin structure cutting process (fin cut) is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0050] In addition, the formation method of the base 18 and the fin-shaped structure 20 may include first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the base 18 and the fin-shaped structure 20. In addition, the formation method of the base 18 and the fin-shaped structure 20 may also include first making a patterned hard mask layer (not shown) on the substrate 12, and using an epitaxial process to grow a semiconductor layer such as silicon germanium on the substrate 12 exposed to the patterned hard mask layer, and this semiconductor layer can serve as the corresponding base 18 and the fin-shaped structure 20. These embodiments of forming the base 18 and the fin-shaped structure 20 are all within the scope of the present invention.

[0051] Then, a flowable chemical vapor deposition (FCVD) process is performed to form an insulating layer 52 made of silicon oxide on the base 18 and the fin structure 20 and fill the groove between the base 18 and the fin structure 20. Then, a planarization process is performed, such as chemical mechanical polishing (CMP), to remove a portion of the insulating layer 52 so that the remaining insulating layer 52 is roughly aligned with the top surface of the fin structure 20.

[0052] Then as Figure 4As shown, a patterned mask 54 such as a patterned photoresist is first formed in the non-MOSCAP area 14 or even a portion of the MOSCAP area 16 to expose a portion of the insulating layer 52 in the MOSCAP area 16 and the top surface of the fin structure 20, and then an ion implantation process 56 is performed using the patterned mask 54 as a mask to implant dopants such as arsenic (As) or phosphorus (P) into the fin structure 20.

[0053] like Figure 5 As shown, a heat treatment process or more specifically a spike annealing process 58 is then performed to diffuse the implanted dopants into the fin structure 20 using high temperature. According to a preferred embodiment of the present invention, the temperature of the spike annealing process 58 is preferably between 950 and 1250 degrees Celsius and the time is preferably between 0 and 3 seconds. The patterned mask 54 of the MOSCAP region 16 can then be removed. It should be noted that although the patterned mask 54 is removed after the spike annealing process 58 is completed in this embodiment, it is not limited thereto. According to other embodiments of the present invention, the patterned mask 54 can be completely removed before the spike annealing process 58 is performed, and this sequence is also within the scope of the present invention.

[0054] like Figure 6 As shown, etching may then be used to remove a portion of the insulating layer 52 in the non-MOSCAP region 14 and the MOSCAP region 16, so that the top surface of the remaining insulating layer 52 is slightly lower than the top surface of the fin structure 20 to form a shallow trench isolation (STI) 22. Then, an oxide growth process such as a rapid thermal oxidation (RTO) process or an in-situ steam generation (ISSG) process is performed to form a gate oxide layer 30 composed of silicon oxide on the substrate 12 and the fin structure 20 in the non-MOSCAP region 14 and the MOSCAP region 16. It should be noted that since the fin structure 20 in the MOSCAP region 16 has been additionally processed in the aforementioned process, when etching is used in this stage to make the fin structure 20 protrude from the shallow trench isolation 22, the sidewall of the fin structure 20 in the MOSCAP region 16 preferably presents an irregular surface such as a curved or rough surface, whereas the sidewall of the fin structure 20 in the non-MOSCAP region 14 is still a flat surface.

[0055] Then Figure 7As shown, gate electrodes 32, 34, and 132 can be formed on the substrate 12 and the fin structure 20 of the non-MOSCAP area 14 and the MOSCAP area 16, respectively, wherein the gate electrode 32 of the non-MOSCAP area 14 can be used as the gate electrode of the medium voltage element, the gate electrode 132 can be used as the gate electrode of the transistor 104 in the PUF element, and the gate electrode 34 of the MOSCAP area 16 can be used as the upper electrode of the MOSCAP element in the PUF element. The gate electrodes 32, 34, and 132 can be manufactured in a gate first manufacturing process, a high-k first manufacturing process of a gate last manufacturing process, or a high-k last manufacturing process of a gate last manufacturing process according to the manufacturing process requirements.

[0056] Taking the post-high-k dielectric layer manufacturing process of the present embodiment as an example, a gate material layer 36 composed of polysilicon and a selective hard mask (not shown) can be sequentially formed on the substrate 12, and a patterned photoresist (not shown) is used as a mask to perform a pattern transfer manufacturing process, and a portion of the gate material layer 36 and a portion of the gate oxide layer 30 are removed by a single etching or successive etching steps, and then the patterned photoresist is stripped to form gate electrodes 32, 34, 132 composed of the patterned gate material layer 36 on the substrate 12 and the fin structure 20 in the non-MOSCAP area 14 and the MOSCAP area 16.

[0057] Then, at least one spacer (not shown) is formed on the sidewalls of the gate electrodes 32, 34, and 132, respectively, and a source / drain region 40 and / or an epitaxial layer is formed in the fin structure 20 and / or the substrate 12 on both sides of the spacer in the non-MOSCAP region 14, and a metal silicide (not shown) is selectively formed on the surface of the source / drain region 40 and / or the epitaxial layer. In the present embodiment, the spacer may be a single spacer or a composite spacer, for example, the details may include an offset spacer and a main spacer. The offset spacer and the main spacer may include the same or different materials, and both may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. The source / drain region 40 may include different dopants depending on the conductivity type of the transistor to be provided, for example, it may include P-type dopants or N-type dopants.

[0058] Next, an interlayer dielectric layer 38 is formed to cover the gate electrodes 32, 34, 132, and then a planarization process is performed, such as using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 38 and expose the gate electrodes 32, 34, 132 made of polysilicon material, so that the upper surface of the gate electrodes 32, 34, 132 is flush with the upper surface of the interlayer dielectric layer 38.

[0059] like Figure 8 As shown, a metal gate replacement process is then performed to convert the gate electrodes 32, 34, 132 formed of polysilicon material in the non-MOSCAP region 14 and the MOSCAP region 16 into metal gates. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 36 and even the gate oxide layer 30, so as to form a groove in the interlayer dielectric layer 38 (not shown).

[0060] Then, a patterned mask (not shown) such as a patterned photoresist is formed in the non-MOSCAP region 14, and the patterned mask is used as a mask to etch away the gate oxide layer 30 in the MOSCAP region 16 and expose the surface of the substrate 12 or the fin structure 20. Then, another dielectric layer 134 composed of silicon oxide is first formed on the surface of the fin structure 20 in the MOSCAP region 16, and then the patterned mask is removed to sequentially form a high-k dielectric layer 46, a work function metal layer 48, and a low-resistance metal layer 50 in the groove, and then a planarization process is performed, such as using CMP to remove part of the low-resistance metal layer 50, part of the work function metal layer 48, and part of the high-k dielectric layer 46 to form a metal gate 72. Taking the gate structure fabricated by the post-high-k dielectric layer fabrication process in the present embodiment as an example, each metal gate 72 formed preferably includes a dielectric layer 134 or a gate oxide layer 30, a U-shaped high-k dielectric layer 46, a U-shaped work function metal layer 48, and a low-resistance metal layer 50. It should be noted that, although the gate oxide layer 30 and the dielectric layer 134 formed in the non-MOSCAP region 14 and the MOSCAP region 16 at this stage are both composed of silicon oxide, the thickness of the dielectric layer 134 is preferably slightly lower than the thickness of the gate oxide layer 30, or more specifically, the thickness of the dielectric layer 134 is preferably lower than more than half of the thickness of the gate oxide layer 30.

[0061] In the present embodiment, the high-k dielectric layer 46 includes a dielectric material with a dielectric constant greater than 4, for example, selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (strontium bismuth tantalum oxide), and strontium tantalum oxide (strontium bismuth tantalum oxide). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x TiO3, BST), or a combination thereof.

[0062] The work function metal layer 48 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl) or TiAlC (titanium aluminum carbide), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 48 and the low resistance metal layer 50, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and other materials. The low resistance metal layer 50 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (cobalttungsten phosphide, CoWP) or a combination thereof. Since converting a dummy gate into a metal gate according to a metal gate replacement manufacturing process is a well-known technique in this field, it will not be further described here. Then, a portion of the high dielectric constant dielectric layer 46, a portion of the work function metal layer 48 and a portion of the low resistance metal layer 50 may be removed to form a groove (not shown), and then a hard mask 74 is filled in the groove and the hard mask 74 is flush with the surface of the interlayer dielectric layer 38, wherein the hard mask 74 may be selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon nitride carbide.

[0063] Afterwards, a pattern transfer process may be performed, for example, a patterned mask may be used to remove part of the interlayer dielectric layer 38 next to the gate electrodes 32 and 132 in the non-MOSCAP region to form a plurality of contact holes (not shown) and expose the source / drain regions. Then, the required metal material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (cobalt tungsten phosphide, CoWP), or a combination thereof. Afterwards, a planarization process is performed, for example, chemical mechanical polishing is used to remove part of the metal material to form contact plugs (not shown) in each contact hole to electrically connect the source / drain region 40. This is completed. Figure 2 Fabrication of MOS transistors and MOSCAPs for PUF components.

[0064] like Figure 8As shown, the PUF element mainly includes at least one transistor 114 such as a metal oxide semiconductor conductor transistor including a gate electrode 132 disposed in the non-MOSCAP area 14 and at least one MOSCAP element disposed in the MOSCAP area 16. In this embodiment, the MOSCAP element mainly includes at least one fin structure 20 disposed on the substrate 12, at least one insulating layer such as a combination of a dielectric layer 134 and / or a high dielectric constant dielectric layer 46 disposed on the fin structure 20, and a gate electrode 34 disposed on the dielectric layer 134, wherein the heavily doped fin structure 20 is preferably used as the lower electrode of the MOSCAP element, the dielectric material such as the dielectric layer 134 and / or the high dielectric constant dielectric layer 46 is preferably used as the capacitor dielectric layer of the MOSCAP element, and the gate electrode 34 is used as the upper electrode of the MOSCAP element. In addition, although the fin structures 20 in the non-MOSCAP region 14 and the MOSCAP region 16 are formed in the same manufacturing process, the overall concentration or the maximum concentration in the fin structure 20 in the non-MOSCAP region 14 is preferably smaller than the overall concentration or the maximum concentration in the fin structure 20 in the MOSCAP region 16 .

[0065] In summary, the present invention discloses a method for manufacturing a PUF element, which mainly provides a PUF cell array, wherein the PUF cell array includes a plurality of unit cells, and each unit cell includes a transistor and a first MOSCAP and a second MOSCAP coupled to the transistor. Then, a voltage is transmitted to the first MOSCAP and the second MOSCAP through the transistor to determine whether the first MOSCAP or the second MOSCAP reaches a breakdown state.

[0066] According to a preferred embodiment of the present invention, the action of applying pressure to the first MOSCAP 106 and the second MOSCAP 108 by using voltage to make one of the two MOSCAPs reach a breakdown state occurs completely randomly, and after one of the two MOSCAP elements reaches a breakdown, one of the MOSCAPs can be assigned a first state value and the other MOSCAP can be assigned a second state value. For example, if the first bit line BL-1 detects that the first MOSCAP 106 is in a breakdown state, the first MOSCAP 106 can be assigned a first state value such as state 1, and conversely, if the second bit line BL-2 detects that the connected second MOSCAP 108 is in a breakdown state, the second MOSCAP 108 can be assigned a second state value such as state 0. Through the random state exchange between the two MOSCAPs, the present invention can use this randomness as a unique or non-copyable feature of a PUF element or chip.

[0067] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for producing a physically non-copyable functional element, characterized in that: Include: A physically non-copyable functional unit array is provided, the physically non-copyable functional unit array comprising a plurality of unit cells, wherein each of the unit cells comprises: transistors; and A first metal-oxide-semiconductor capacitor and a second metal-oxide-semiconductor capacitor are coupled to the transistor; as well as A voltage is transmitted to the first MOS capacitor and the second MOS capacitor via the transistor to determine whether the first MOS capacitor or the second MOS capacitor reaches a breakdown state.

2. The method of claim 1, further comprising: The voltage is transmitted to the first MOS capacitor to initiate a breakdown state, wherein the first MOS capacitor is assigned a first state value and the second MOS capacitor is assigned a second state value.

3. The method of claim 1, further comprising: The voltage is transmitted to the second MOS capacitor to initiate a breakdown state, wherein the second MOS capacitor is assigned a first state value and the first MOS capacitor is assigned a second state value.

4. The method of claim 1, wherein the transistor comprises: Gate; a first end; and Second end. The method of claim 4 , wherein the gate is coupled to a word line. 6 . The method of claim 4 , wherein the first terminal is coupled to the first MOS capacitor and the second MOS capacitor. The method of claim 4 , wherein the second terminal is coupled to a source line.

8. A physically non-copyable functional element, characterized in that: Include: A physically non-copyable functional unit array, the physically non-copyable functional unit array comprising a plurality of unit cells, wherein each of the unit cells comprises: transistors; and The first MOS capacitor and the second MOS capacitor are coupled to the transistor, wherein a voltage is transmitted to the first MOS capacitor and the second MOS capacitor via the transistor to determine whether the first MOS capacitor or the second MOS capacitor reaches a breakdown state.

9. The physically non-copyable functional device of claim 8, wherein when the voltage is transmitted to the first MOS capacitor to initiate a breakdown state, the first MOS capacitor is assigned a first state value and the second MOS capacitor is assigned a second state value.

10. The physically non-copyable functional device of claim 8, wherein when the voltage is transmitted to the second MOS capacitor to initiate a breakdown state, the second MOS capacitor is assigned a first state value and the first MOS capacitor is assigned a second state value.

11. The physically non-copyable functional element as claimed in claim 8, wherein the transistor comprises: Gate; a first end; and Second end.

12. The physically non-copyable functional device as claimed in claim 11, wherein the gate is coupled to a word line. 13 . The physically non-copyable functional device as claimed in claim 11 , wherein the first terminal is coupled to the first metal-oxide-semiconductor capacitor and the second metal-oxide-semiconductor capacitor.

14. The physically non-copyable functional device as claimed in claim 11, wherein the second terminal is coupled to a source line.

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