Wafer level packaging thermopile infrared array chip and preparation method thereof

Abstract

The invention provides a wafer level packaging thermopile infrared array chip and a preparation method thereof. The method comprises the following steps: providing a device wafer, wherein the surface of the device wafer comprises at least one thermopile chip; covering a packaging layer on the front surface of the device wafer to form a packaging structure; and forming a light condensation structure at a position, corresponding to the thermopile of the thermopile chip, on the back surface of the device wafer. According to the technical scheme, the packaging process can be implemented under the wafer-level size, the packaging efficiency of the thermopile infrared array chip is improved, and the process cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of MEMS chip manufacturing, and in particular to a wafer-level packaged thermopile infrared array chip and a preparation method thereof. Background Art

[0002] Thermopile chips convert thermal energy into electrical energy by using thermocouples made of two different materials. When the temperature at one end is higher, a temperature difference is generated between the two ends of the couple, which stimulates the movement of charges and forms a voltage. This voltage can be used to power electronic devices, measure temperature, and sense heat sources. It can be widely used in micro devices, wireless sensors, satellite aerospace, and medical equipment.

[0003] With the widespread application of thermopile chips, how to reduce chip manufacturing costs and better meet the needs of large-scale applications is a problem that the existing technology needs to solve. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a wafer-level packaged thermopile infrared array chip and a preparation method thereof, which can improve the packaging efficiency of the thermopile infrared array chip and reduce the process cost.

[0005] In order to solve the above problems, the present invention provides a method for preparing a wafer-level packaged thermopile infrared array chip, comprising the following steps: providing a device single-piece wafer, the surface of the device wafer comprising at least one thermopile chip; covering the front side of the device wafer with a packaging layer to form a packaging structure; and forming a focusing structure at a position corresponding to the thermopile of the thermopile chip on the back side of the device wafer.

[0006] Optionally, the packaging layer is selected from one of a supporting wafer and a multiple wiring layer.

[0007] Optionally, the packaging layer includes an infrared reflector at a position corresponding to the thermopile of the thermopile chip.

[0008] Optionally, the focusing structure is selected from one of a convex lens and a Fresnel lens.

[0009] Optionally, after the step of forming a light-focusing structure at a position on the back side of the device wafer corresponding to the thermopile of the thermopile chip, an infrared anti-reflection film is formed on the surface of the back side of the device wafer.

[0010] Optionally, before the step of forming a light-focusing structure at a position on the back side of the device wafer corresponding to the thermopile of the thermopile chip, the back side of the device wafer is thinned.

[0011] Optionally, the device wafer surface also includes a driving circuit for signal readout and processing.

[0012] In order to solve the above problems, the present invention provides a wafer-level packaged thermopile infrared array chip, comprising: a device wafer, wherein the surface of the device wafer comprises at least one thermopile chip; a packaging layer covering the front side of the device wafer; and a focusing structure at a position corresponding to the thermopile of the thermopile chip on the back side of the device wafer.

[0013] Optionally, the packaging layer is selected from one of a supporting wafer and a multiple wiring layer.

[0014] Optionally, the packaging layer includes an infrared reflector at a position corresponding to the thermopile of the thermopile chip.

[0015] Optionally, the focusing structure is selected from a type of superstructure lens.

[0016] The above technical solution can implement the packaging process at the wafer level, improve the packaging efficiency of the thermopile infrared array chip, and reduce the process cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Attached Figure 1 Shown is a schematic diagram of the implementation steps of a method for preparing a wafer-level packaged thermopile infrared array chip according to a specific embodiment of the present invention.

[0018] Attached Figure 2A To Attachment Figure 2E Shown is a process flow chart of a method for preparing a wafer-level packaged thermopile infrared array chip according to a specific embodiment of the present invention.

[0019] Attached Figure 3 Shown is a schematic structural diagram of a wafer-level packaged thermopile infrared array chip according to a specific embodiment of the present invention.

[0020] Attached Figure 4 Shown is a schematic structural diagram of a wafer-level packaged thermopile infrared array chip according to a specific embodiment of the present invention.

[0021] Attached Figure 5 Shown is a schematic structural diagram of a wafer-level packaged thermopile infrared array chip according to a specific embodiment of the present invention.

[0022] Attached Figure 6 Shown is a schematic structural diagram of a wafer-level packaged thermopile infrared array chip according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0023] The specific implementation methods of the wafer-level packaged thermopile infrared array chip and the preparation method thereof provided by the present invention are described in detail below with reference to the accompanying drawings.

[0024] Attached Figure 1The figure is a schematic diagram of the implementation steps of the method for preparing the wafer-level packaged thermopile infrared array chip of the present invention, comprising the following steps: step S10, providing a device wafer, the surface of the device wafer comprising at least one thermopile chip; step S11, covering the front side of the device wafer with a packaging layer to form a packaging structure; step S12, thinning the back side of the device wafer; step S13, forming a focusing structure at a position on the back side of the device wafer corresponding to the thermopile of the thermopile chip; and step S14, forming an infrared anti-reflection film on the surface of the back side of the device wafer.

[0025] Attached Figure 2A As shown, referring to step S10, a device wafer 10 is provided, and the surface of the device wafer 10 includes at least one thermopile chip. FIG2 shows an example of a thermopile chip 11. In other specific embodiments, a plurality of parallel thermopile chips or an array composed of more thermopile chips may also be included. The surface of the device wafer 10 also includes a driving circuit 12, including but not limited to an integrated CMOS driving circuit, for reading and processing the output signal of the thermopile chip. The output signal of the thermopile chip can also be directly output, and the signal processing is performed through an external ASIC.

[0026] Attached Figure 2B As shown, referring to step S11, the front side of the device wafer 10 is covered with a packaging layer to form a packaging structure. The packaging layer is selected from one of a supporting wafer and a multiple wiring layer. Figure 2B The figure shows a specific implementation of using a support wafer 13 as a packaging structure. The support wafer 13 is mounted on the front of the device wafer 10 using a wafer-level packaging process to form a sealed packaging structure. Subsequently, electrical pins are formed by through-hole etching, and the entire structure is cut to complete the packaging.

[0027] Attached Figure 2C As shown, referring to step S12, the back side of the device wafer 10 is thinned. This step is an optional step. Since the thermopile chip mainly absorbs infrared light, and the wafer is usually made of materials such as silicon that are transparent to infrared light. Therefore, the thermopile chip 11 can also work without thinning the wafer 10, and thinning can reduce the absorption rate of the device wafer 10, which is more conducive to improving the sensitivity of the thermopile chip 11. Thinning can be performed by mechanical grinding or wet etching, or a combination of the two.

[0028] Attached Figure 2D As shown, referring to step S13, a focusing structure is formed on the back of the device wafer 10 at a position corresponding to the thermopile of the thermopile chip 11. The focusing structure is selected from one of the superstructure lenses. Figure 2DThe light focusing structure shown is a convex lens 14. The convex lens structure can be released on the back of the device wafer 10 by wet etching, or a convex lens made of transparent materials such as resin can be mounted on the surface by assembly.

[0029] Attached Figure 2E As shown, referring to step S14, an infrared anti-reflection film 15 is formed on the surface of the back side of the device wafer 10. This step is an optional step. The anti-reflection film 15 is conducive to better infrared light passing through the surface of the device wafer 10 and entering the thermopile of the thermopile chip 11, so as to improve the sensitivity of the thermopile chip 11. It is preferred to form the anti-reflection film 15 on the surface of the convex lens 14 as a focusing structure.

[0030] The wafer-level packaged thermopile infrared array chip obtained after the above steps are implemented includes: a device wafer, the surface of the device wafer includes at least one thermopile chip; a packaging layer covering the front of the device wafer; and a focusing structure at the back of the device wafer corresponding to the thermopile of the thermopile chip. The above method can implement the packaging process at the wafer level, improve the packaging efficiency of the thermopile infrared array chip, and reduce the process cost.

[0031] In a specific embodiment of the present invention, referring to the attached Figure 3 As shown, the packaging layer is a multiple wiring layer 30 .

[0032] In a specific embodiment of the present invention, referring to the attached Figure 4 As shown, the packaging layer further includes an infrared reflector 40 at a position corresponding to the thermopile of the thermopile chip, so as to improve the sensitivity of the thermopile chip 11 .

[0033] In a specific embodiment of the present invention, referring to the attached Figure 5 As shown, the light-focusing structure may also be a Fresnel lens 50 composed of a plurality of concentric rings, which can also play a role in focusing light.

[0034] In a specific embodiment of the present invention, referring to the attached Figure 6 As shown, it may also include a plurality of parallel thermopile chips, or an array composed of more thermopile chips, wherein the structure of each thermopile chip refers to the above content.

[0035] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for preparing a wafer-level packaged thermopile infrared array chip, characterized in that: The steps include: Providing a device single wafer, wherein the surface of the device wafer includes at least one thermopile chip; Covering the front side of the device wafer with a packaging layer to form a packaging structure; A light focusing structure is formed on the back side of the device wafer at a position corresponding to the thermopile of the thermopile chip.

2. The method according to claim 1, characterized in that The packaging layer is selected from one of a supporting wafer and a multiple wiring layer.

3. The method according to claim 1, characterized in that The packaging layer includes an infrared reflector at a position corresponding to the thermopile of the thermopile chip.

4. The method according to claim 1, characterized in that: The light-focusing structure is selected from one of the superstructure lenses.

5. The method according to claim 1, characterized in that After the step of forming a light-collecting structure at a position on the back side of the device wafer corresponding to the thermopile of the thermopile chip, an infrared anti-reflection film is formed on the surface of the back side of the device wafer.

6. The method according to claim 1, characterized in that Before the step of forming a light-focusing structure at a position on the back side of the device wafer corresponding to the thermopile of the thermopile chip, the back side of the device wafer is thinned.

7. The method according to claim 1, characterized in that The device wafer surface also integrates a CMOS driving circuit for signal reading and processing.

8. A wafer-level packaged thermopile infrared array chip, characterized in that: include: A device wafer, wherein the surface of the device wafer includes at least one thermopile chip; A packaging layer covering the front side of the device wafer; A light focusing structure is included at a position on the back side of the device wafer corresponding to the thermopile of the thermopile chip.

9. The chip according to claim 8, characterized in that: The packaging layer is selected from one of a supporting wafer and a multiple wiring layer.

10. The chip according to claim 8, characterized in that: The packaging layer includes an infrared reflector at a position corresponding to the thermopile of the thermopile chip.

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