Correction of global curvature during stress management

Abstract

Embodiments of the present disclosure relate to techniques and apparatus for reducing out-of-plane distortion (OPD) in a substrate, as well as controlling the effect of the OPD and modifying the substrate to correct for the effect of the OPD on subsequent substrate processing operations performed on the substrate. Embodiments of the present invention employ novel techniques to reduce OPD in a substrate without adding or modifying a portion of the substrate that will cause problems in a subsequent substrate manufacturing process.

Description

Technical Field

[0001] The present disclosure relates generally to stress control in substrates, and more particularly to stress compensation that reduces out-of-plane distortion in substrates. Background Art

[0002] Memory elements are essential components in digital electronic components being developed today. As today's technology advances, most electronic components require increased storage capacity. At the same time, smaller memory elements are also required to meet the market demand for manufacturing smaller electronic components in which the memory elements are located.

[0003] In recent years, conventional (2D) NAND memory elements have encountered many challenges, including issues related to voltage drop (e.g., depletion of electrons in the current-carrying element due to the continuous scaling of cell size), retention loss, and global reliability. To address these challenges encountered when scaling planar (2D) NAND memory elements to achieve higher density at a lower cost per bit, ultra-high density, three-dimensional (3D) stacked memory structures have been introduced. Such 3D memory structures are sometimes referred to as having a Bit Cost Scalable (BiCS) architecture and include vertically integrated strings of memory cells. Typically, the vertically aligned memory cells are formed from an array of alternating conductor and insulator layers, where the conductive layers correspond to the word lines of the memory structure.

[0004] As the number of vertically stacked memory cells in a 3D NAND device increases (e.g., as chip density increases), the stress generated within the stacked memory cells increases, which increases substrate bowing and brings many performance issues. Local variations in material composition in vertically stacked memory cells may induce stresses that deform or warp the semiconductor substrate on which the structure is formed. Substrate flatness or bowing has a very large impact on semiconductor device manufacturing because it affects the ability of the lithography system to effectively form device patterns on the substrate surface. Even moderate variations in surface topography within the lithography exposure area will change the device feature pattern and ultimately lead to potential chip (die) yield loss. In order to accurately form the device pattern, it is important to form the pattern on the substrate while the substrate remains relatively flat or flat. Substrate bowing is also important for other related manufacturing processes because deformation or warping of the substrate may also cause difficulties in subsequent processing steps, which may include chip bonding or packaging.

[0005] A common concern in fabricating such components and structures on substrates is the development of in-plane distortion (IPD), which affects the overlay of a layer relative to an underlying reference layer. IPD is a complex quantity that is affected by the out-of-plane distortion (OPD) of the substrate and the alignment scheme employed in lithography. OPD is a fundamental quantity of the substrate, and the characterization of the residual OPD formed in the substrate due to stress is critical to the achievable overlay. For example, a commonly encountered type of OPD is global substrate curvature, which can occur in many processing examples due to stress accumulation in the substrate caused by processing operations.

[0006] Therefore, there is a need for an improved memory element structure and a method of forming the structure to solve the above problems. Summary of the invention

[0007] An embodiment of the present disclosure provides a semiconductor element containing a substrate. The semiconductor element containing the substrate includes a plurality of semiconductor element layers formed on the front side surface of the substrate, wherein the semiconductor element layers include at least one layer, the at least one layer includes a compressive or tensile stress that causes out-of-plane distortion in the substrate; and a distortion correction structure formed on the back side surface of the substrate and including a distortion correction layer, the distortion correction layer including a first material having a compressive or tensile stress and having a thickness when just deposited on the back side surface, and implanted ions uniformly distributed across a back side surface of the first material, the first material being arranged across the back side surface of the substrate, wherein the thickness and compressive or tensile stress formed in the just deposited first material cannot compensate for all out-of-plane distortion formed in the substrate, the implanted ions include implanted ions of a uniform dose provided at a first ion energy, and the combination of the just deposited first material and the addition of the implanted ions within the first material is configured to correct the out-of-plane distortion formed in the substrate.

[0008] An embodiment of the present disclosure also provides a method for forming a three-dimensional storage element. The method includes: measuring out-of-plane distortion formed in a substrate, the substrate including a plurality of semiconductor element layers formed on the front side surface of the substrate; determining at least one distortion correction parameter for forming a distortion correction structure formed on the back side surface of the substrate; forming a distortion correction layer of the distortion correction structure on the back side surface of the substrate, wherein the distortion correction layer includes a first material having a compressive or tensile stress and having a thickness when just deposited on the back side surface; and performing an ion implantation process to uniformly implant ions across the back side surface of the first material deposited on the back side surface of the substrate, wherein the thickness and compressive or tensile stress formed in the just deposited first material cannot compensate for all out-of-plane distortion formed in the substrate, the implanted ions include implanted ions of a uniform dose provided at a first ion energy, and the combination of the just deposited first material and the addition of the implanted ions within the first material is configured to correct the out-of-plane distortion formed in the substrate.

[0009] Embodiments of the present disclosure also provide a method of forming a distortion correction structure. The method includes depositing a distortion correction layer on a backside surface of a substrate, the substrate including a plurality of semiconductor element layers on a front side of the substrate, wherein at least one of the plurality of semiconductor element layers has a compressive or tensile stress that causes out-of-plane distortion in the substrate; and performing an ion implantation process to expose the just-deposited distortion correction layer to a uniform dose of implanted ions. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description of the present disclosure briefly summarized above may be had by reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of the scope thereof, and may allow for other equally effective embodiments.

[0011] Figure 1 A substrate including out-of-plane distortion is shown.

[0012] Figure 2 shows that adding a conventional stress compensation layer to Figure 1 The rear surface of the substrate is shown after the substrate.

[0013] Figure 3 A method of forming a distortion correcting structure according to one or more embodiments described herein is shown.

[0014] Figure 4 and Figure 5 The present invention shows that according to one or more embodiments described herein, Figure 1 Portions of a distortion correction structure formation process performed on a substrate are shown.

[0015] Figure 6 is a graph illustrating the effect of providing increasing amounts of uniform implant dose to a distortion correction layer of a distortion correction structure according to one or more embodiments described herein.

[0016] Figure 7~Figure 9 The effect of different uniform implant dose levels on out-of-plane distortion is shown according to one or more embodiments described herein.

[0017] To facilitate understanding, identical reference numerals have been used, where possible, to designate elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0018] In the following description, details are described by way of example to facilitate understanding of the disclosed objectives. However, it will be appreciated by those skilled in the art that the disclosed embodiments are exemplary rather than exhaustive descriptions of all possible embodiments. Therefore, it should be understood that the examples described are not intended to limit the scope of the present disclosure by reference. As would be generally expected by a person skilled in the art to which the present disclosure pertains, any changes and further modifications to the described apparatus, instrument, method, and any further application of the principles of the present disclosure are fully conceivable. In particular, it is fully conceivable that the features, components, and / or steps described with respect to one embodiment may be combined with the features, components, and / or steps described with respect to other embodiments of the present disclosure. As used herein, the term "approximately" may refer to a variation of + / -10% of a nominal value. It should be understood that such variation may be included in any value provided herein.

[0019] Embodiments described herein relate to techniques and apparatus for reducing out-of-plane distortion (OPD) in substrates, as well as controlling the effects of OPD and modifying the substrate to correct for the effects of OPD on subsequent substrate processing operations performed on the substrate. The present embodiments employ new techniques to reduce OPD in substrates without adding or modifying portions of the substrate that will create problems in subsequent substrate manufacturing processes.

[0020] As described above, in one application example, as the number of vertically stacked memory cells in a 3D NAND element increases (e.g., as chip density increases), the stress generated within the stacked memory cells increases, which increases the OPD of the substrate and, therefore, increases a phenomenon commonly referred to as "wafer bow" or "substrate bow." In order to compensate for global substrate bow or bowing across the entire substrate surface, it is common practice to deposit a stress compensation layer on the substrate surface to a desired thickness so that the intrinsic and extrinsic stresses within the deposited stress compensation layer will tend to offset the global substrate bow generated by previous substrate processing steps. Therefore, as the global substrate bow increases, a thicker deposited stress compensation layer is required to offset the larger substrate bow. Due to metal contamination, the deposited stress compensation layer typically includes a dielectric film layer, such as silicon oxide (SiOx), silicon nitride (SiN), carbon, or a combination thereof.

[0021] However, during the manufacture of most semiconductor devices, when the device layers are formed on the substrate, one or more plasma processes are usually used to process the substrate many times, such as physical vapor deposition (PVD) process, plasma enhanced chemical vapor deposition (PECVD) process, reactive ion etching (RIE) process, plasma-enhanced atomic layer deposition (PEALD) process or other similar processing techniques. During most plasma processes, in order to ensure good temperature control, it is desirable to electrostatically clamp the substrate to the surface of the substrate support. During processing, the action of electrostatically clamping the substrate to the surface of the substrate support causes the charge to migrate to the lower surface of the substrate and accumulate in the lower surface. Before the substrate is removed from the surface of the substrate support, the accumulated charge needs to be discharged, a process often referred to as the process of releasing the substrate. However, as the thickness of the stress compensation layer deposited on the back side of the substrate increases, the ability to discharge all the accumulated charge on the back side of the substrate becomes more difficult to discharge completely or more difficult to discharge in a reasonable time. The inability to discharge the accumulated charge also greatly increases the chances of the substrate being damaged or broken when the substrate is separated from the substrate support surface using a substrate lifting mechanism, which often results in particle generation and chamber downtime to remove the damaged or broken substrate.

[0022] Stress compensation process

[0023] In order to eliminate or minimize complex distortion shapes formed in deformed substrates, a distortion correction structure and a process sequence for forming the structure have been developed and disclosed herein.

[0024] Figure 1 A side cross-sectional view of a substrate having significant global substrate curvature resulting from large OPD is shown. The amount of deflection resulting from OPD can be measured at the center or neutral axis of the substrate 101. In one example, the substrate 101 includes a semiconductor element layer formed on a front side surface 102 of the substrate 101, which is used to form a 3D memory element. At least one layer of the semiconductor element layer has a compressive or tensile stress that causes out-of-plane distortion (OPD) in the substrate 101.

[0025] Figure 2 FIG. 1 is a side cross-sectional view of the substrate 101 after a conventional stress compensation layer 201 is formed on the back surface 103 of the substrate 101. The conventional stress compensation layer 201 includes a thickness T CON , and is typically formed of a dielectric material. However, as described above, due to the large thickness required for the conventional stress compensating layer 201, the properties of the dielectric film can cause significant problems in many subsequent processes performed on the substrate. In one example, it has been found that when used in a typical process utilizing an electrostatic chuck, a conventional stress compensating layer of silicon nitride (SiN) deposited on the backside surface 103 of the substrate 101 having a thickness greater than 5,000 angstroms (Å) has an undesirably high breakage rate. In some cases, as discussed in U.S. Patent Application Publication No. 20170178891A1, the conventional stress compensating layer can have a thickness of about 1 µm for every about 5 µm to about 8 µm of warpage or bow.

[0026] Figure 3 A method 300 is shown for forming a distortion correction structure 502 for compensating for OPD found in a substrate 101 according to one or more embodiments described herein. Figure 4 and Figure 5 According to one or more embodiments described herein, Figure 3 Schematic side cross-sectional views of the substrate 101 during different stages of the distortion correction structure 502 formation process are shown. In general, the distortion correction structure 502 formation process includes depositing a 3D-type substrate having a thickness T DCL The distortion correction layer 501 formed on the backside surface 103 of the substrate 101 is then exposed to a uniform implantation dose to correct the OPD in the substrate 101.

[0027] Method 300 begins at activity 302 where the OPD of substrate 101 is measured using conventional substrate bow measurement techniques. Conventional measurement techniques may be performed using a WaferSight™ tool from KLA of Milpitas, California, a metrology system from MTI Instrument of Albany, New York, or other similar substrate bow measurement tools.

[0028] At activity 304, a system controller (not shown) within one or more distortion correction structure processing tools determines a desired distortion correction amount for one or more of the various portions of the distortion correction structure 502 to be formed on the backside surface of the substrate 101. The desired determined correction amount is based on the information collected during activity 302. The system controller includes a programmable central processing unit (CPU) and support circuits operable with storage (e.g., non-volatile storage). The support circuits are coupled to the CPU in a conventional manner and include caches, clock circuits, input / output subsystems, etc., coupled to various components within the one or more distortion correction structure processing tools, and combinations thereof, to facilitate control thereof. The CPU is one of any form of general-purpose computer processor used in an industrial environment to control various components and subprocessors of a processing system. Typically, the storage is in the form of a non-transitory computer-readable storage medium (e.g., non-volatile storage) containing instructions that, when executed by the CPU, facilitate the operation of the one or more distortion correction structure processing tools. The computer instructions in the storage are in the form of a program product, such as a program that implements one or more portions of the disclosed method.

[0029] In activity 306, a freshly deposited distortion correction layer 501 is formed on the backside surface of the substrate 101. The process of forming the freshly deposited distortion correction layer 501 may include depositing a dielectric-containing layer on the backside surface 103 using a chemical vapor deposition (CVD) process, a physical vapor deposition process (PVD), an atomic layer deposition (ALD) process, or other useful deposition processes. The thickness T of the freshly deposited distortion correction layer 501 is selected by using the previous activities. DCL , such that it is less than the thickness required to fully compensate for the OPD of the substrate 101, and also has a thickness that will ensure that the distortion correction layer 501 will not cause problems in any subsequent manufacturing process. In one example, the just-deposited distortion correction layer 501 may include a layer containing silicon nitride (Si3N4) formed by a PVD or CVD process. In some embodiments, the system controller determines the required thickness T of the just-deposited distortion correction layer 501 based on the data collected during activity 302. DCL .Thickness T DCL The thickness T of the as-deposited distortion correction layer 501 may be selected based on aspects of the implant dose to be provided during activity 308 and, therefore, adjusted based on the implant dose parameters used during activity 308. DCLIn some cases, it is desirable to set the thickness of the as-deposited distortion correction layer 501 to be thick enough to ensure that the implanted ions provided during the ion implantation process performed during activity 308 do not cause the implanted ions to implant into the back side of the substrate 101. In some non-limiting examples, the as-deposited distortion correction layer 501 is a silicon nitride (SixNy) film layer having a thickness T DCL Less than 4,000Å, such as less than 2,000Å, or between 1,000Å and 2,000Å.

[0030] At activity 308, an ion implantation process is performed in which the as-deposited distortion correction layer 501 is exposed to a dose of implanted ions (also referred to as "implantation dose") such that the modified as-deposited distortion correction layer 501 (herein referred to as distortion correction layer 503) will correct the OPD, such as Figure 5As shown. In some embodiments, the dose of implanted ions includes a spatially uniform ion dose. According to some non-limiting embodiments, suitable implanted ions provided from an ion beam may include any ion species capable of causing stress changes after implantation at a suitable ion energy, including ions such as argon (Ar), phosphorus (P), silicon (Si), carbon (C), boron (B), nitrogen (N2), krypton (Kr), indium (In) or boron difluoride (BF2), and the ion energy is customized according to the exact ion species used. The dose of implanted ions is applied to the just-deposited distortion correction layer 501 by using an ion implantation energy source to correct the OPD and thereby reduce or minimize the in-plane distortion (IPD) that affects component manufacturing and other component patterning procedures. Non-limiting examples of ion implantation energy sources include ion beams that can be scanned relative to the backside surface 103 of the substrate 101. In various embodiments, the ion implantation energy source can transfer the dose to the substrate involving a uniform, direct write process. In this case, a "direct write" process, including a direct write implantation process, can refer to a process that uses relative movement of an ion beam or other beam used to produce a uniform dose across the substrate surface. In some embodiments, a direct write process using an ion implantation energy source may involve exposure to electrons, such as an electron beam, or photons, such as a laser beam, which may be used to globally adjust the stress in the as-deposited distortion correction layer 501 to adjust the curvature of the substrate, thereby adjusting the OPD of the substrate. In some embodiments of activity 308, the system controller determines the desired ion implantation process parameters, such as ion energy (keV), dose (atoms / cm2), and / or even ion species, based on the data collected during activity 302 and the thickness of the as-deposited distortion correction layer 501. In some embodiments, method 300 is completed after performing activity 308, so that the substrate 101 can then be transferred to one or more subsequent processing steps, such as additional 3D memory element (e.g., 3D NAND element) processing steps. In one non-limiting example, the ion implantation process includes implanting argon (Ar) ions at a constant energy (e.g., 65 keV) into a as-deposited distortion correction layer of silicon nitride (SixNy), the layer having a thickness of approximately 1,300 Å and a thickness of 1 × 10 12 Up to 1 × 10 16 In another non-limiting example, the ion implantation process includes implanting argon (Ar) ions at a constant energy (eg, 70 keV) into a as-deposited distortion correction layer of silicon nitride (SixNy) having a thickness of about 2,000 Å to correct an OPD of about 300 µm.

[0031] However, in some embodiments of method 300, after performing activities 302-308, activities 310-314 are additionally performed to further adjust the OPD found in substrate 101. At activity 310, after performing activities 302-308, the OPD of substrate 101 is measured again to determine whether further OPD correction is needed. At activity 312, a system controller (not shown) determines a second desired distortion correction amount needed to correct the OPD found in substrate 101. The determined second distortion correction amount is based on the data collected during activity 310. At activity 314, an ion implantation process is performed, wherein a second uniform dose of implanted ions is calculated based on activities 310 and 312, and the distortion correction layer 503 formed during activity 308 is then exposed to the second uniform dose of implanted ions, so that the modified distortion correction layer 503 will correct the remaining OPD.

[0032] In some other embodiments of method 300, during activity 308, a dose of implanted ions is calculated, but an ion implantation process is not performed during activity 308. In this case, during activity 314, an ion implantation process is performed, wherein the ion implantation dose includes delivery of a combined implantation dose, the combined implantation dose including the ion implantation dose calculated during activity 308 and a second implantation dose determined during activity 314. Thus, at activity 314, the system controller determines the desired ion implantation process parameters, such as ion energy (keV), dose (atoms / cm2), and / or even ion species, for delivering the combined implantation dose based on the data collected during activities 302 and 310 and the thickness of the just-deposited distortion correction layer.

[0033] Example

[0034] Figure 6 is a graph showing the effect of providing increasing amounts of uniform implant dose to the distortion correction layer of the distortion correction structure. The graph was created using a fixed ion energy level applied across the entire backside surface of the substrate 101. It can be seen that as the implant ion dose increases, the global substrate bow 601 decreases.

[0035] Figures 7-9The figures show the effect of different uniform implant dose levels on out-of-plane distortion by using a distortion correction structure including a silicon nitride layer. FIG. 7 shows OPD profiles of an example substrate before and after ion implantation with a low uniform implant dose. FIG. 8 shows OPD profiles of an example substrate before and after ion implantation with a medium uniform implant dose. FIG. 9 shows an example of OPD profiles of a substrate before and after an ion implantation process with a high uniform implant dose. As shown in FIG. 7, at a low uniform implant dose, the substrate bow is slightly corrected (e.g., a global substrate bow of 40 µm is corrected to 36 µm). As shown in FIGs. 8 and 9, at a medium uniform implant dose and a high uniform implant dose, the substrate bow is overcorrected (e.g., a global substrate bow of 16 µm and 26 µm is corrected to -19 µm and -37 µm, respectively).

[0036] The applications of the disclosures provided herein can be used during the formation of 2D NAND, 3D NAND, 2D DRAM, 3D DRAM, and logic devices. The applications of the disclosures provided herein can also be used in various device packaging applications, such as hybrid wafer bonding and other similar packaging processes.

[0037] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the same is determined by the claims which follow.

Claims

1. A semiconductor device comprising a substrate, comprising: a plurality of semiconductor element layers formed on a front side surface of a substrate, wherein the semiconductor element layers include at least one layer including a compressive or tensile stress that causes out-of-plane distortion in the substrate; as well as A distortion correction structure is formed on the back side surface of the substrate and includes a distortion correction layer, the distortion correction layer including: a first material having a compressive or tensile stress when deposited on the backside surface and having a thickness; as well as implanting ions uniformly distributed across a backside surface of the first material, the first material being disposed across the backside surface of the substrate, wherein the thickness and compressive or tensile stresses formed in the as-deposited first material are unable to compensate for all of the out-of-plane distortions formed in the substrate, The implanted ions include a uniform dose of implanted ions provided at a first ion energy, and The combination of the as-deposited first material and the addition of the implanted ions within the first material is configured to correct the out-of-plane distortion formed in the substrate.

2. The substrate of claim 1, wherein the thickness of the as-deposited first material and parameters of an ion implantation process for implanting ions are selected such that the implanted ions are not implanted into the backside surface of the substrate. 3 . The substrate of claim 2 , wherein the implanted ions include argon (Ar), phosphorus (P), silicon (Si), or carbon (C). 4 . The substrate of claim 1 , wherein the plurality of semiconductor device layers are configured to form at least a portion of a 3D memory device.

5. A method for forming a three-dimensional memory element, comprising the following steps: measuring out-of-plane distortion formed in a substrate including a plurality of semiconductor element layers formed on a front side surface of the substrate; determining at least one distortion correction parameter for forming a distortion correction structure formed on a backside surface of the substrate; forming a distortion correction layer of the distortion correction structure on the backside surface of the substrate, wherein the distortion correction layer comprises a first material having a compressive or tensile stress and having a thickness just deposited on the backside surface; as well as performing an ion implantation process to uniformly implant ions across a backside surface of the first material deposited on the backside surface of the substrate, wherein the thickness and compressive or tensile stresses formed in the as-deposited first material are not able to compensate for all of the out-of-plane distortions formed in the substrate, The implanted ions include a uniform dose of implanted ions provided at a first ion energy, and The combination of the as-deposited first material and the addition of the implanted ions within the first material is configured to correct the out-of-plane distortion formed in the substrate.

6. The method of claim 5, wherein the thickness of the as-deposited first material and parameters of the ion implantation process for implanting the implant ions are selected such that the implant ions are not implanted into the backside surface of the substrate. 7 . The method of claim 6 , wherein the implanted ions include argon (Ar), phosphorus (P), silicon (Si), or carbon (C). 8 . The method of claim 7 , wherein the plurality of semiconductor device layers are configured to form at least a portion of a 3D memory device.

9. The method of claim 5, wherein the at least one distortion correction parameter comprises at least one of the thickness of the as-deposited first material, ion energy, dose, and ion species desired during the ion implantation process.

10. The method of claim 5, wherein the step of determining the at least one distortion correction parameter is performed by a system controller after receiving information related to the measurement of the out-of-plane distortion formed in the substrate.

11. The method of claim 10, wherein the system controller is further configured to control the thickness, ion energy, dose, and ion species of the as-deposited first material during the ion implantation process after the step of determining the at least one distortion correction parameter.

12. A method for forming a distortion correction structure, comprising the following steps: depositing a distortion correction layer on a backside surface of a substrate, the substrate comprising a plurality of semiconductor element layers on a frontside surface of the substrate, wherein at least one of the plurality of semiconductor element layers has a compressive or tensile stress that causes out-of-plane distortion in the substrate; as well as An ion implantation process is performed to expose the as-deposited distortion correction layer to a uniform dose of implanted ions.

13. The method of claim 12, wherein the distortion correction layer comprises a layer containing silicon nitride (Si3N4).

14. The method of claim 12, wherein the thickness of the distortion correction layer is between 1,000 Å and 2,00 Å.

15. The method of claim 12, wherein the implanted ions include phosphorus, boron, argon, nitrogen, krypton, indium, or boron fluoride.

16. The method of claim 12, wherein the ion implantation process comprises implanting ions at a constant energy between 65 keV and 70 keV and 1 × 10 12 and 1 × 10 16 Argon (Ar) ions are implanted into the as-deposited distortion-correcting layer at a dose of between 1000 and 2000 Å / cm2.

17. The method according to claim 12, further comprising the steps of: Before the step of depositing the distortion correction layer, measuring the out-of-plane distortion in the substrate; and At least one distortion correction parameter for forming the distortion correction layer is determined.

18. The method of claim 17, wherein the at least one distortion correction parameter comprises at least one of a thickness of the distortion correction layer, ion energy, dose, and ion species desired during an ion implantation process.

19. The method according to claim 12, further comprising the steps of: After the ion implantation process, measuring out-of-plane distortion found in the substrate; and At least one distortion correction parameter for forming an additional distortion correction layer is determined.

20. The method according to claim 19, further comprising the steps of: depositing the additional distortion correction layer on the backside surface of the substrate; as well as An ion implantation process is performed to expose the as-deposited additional distortion correction layer to a uniform dose of implanted ions.

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