Gate all-around transistor with heterogeneous channel

Abstract

A semiconductor device, such as an integrated circuit, a microprocessor, a wafer, and the like, includes a first gate all-around field effect transistor (GAA FET) (303) and a second GAA FET (313, 323, 333) within the same region type (such as a p-type region or an n-type region, and the like) with relatively heterogeneous channels within the same region. The first GAA FET includes a plurality of first channels (e.g., SiGex-coated channels) (482, 486, 490) of a first channel material. The second GAA FET includes a plurality of second channels of a second channel material (e.g., a SiGey-coated channel, a Si channel, etc.) (382, 386, 390). The GAA FETs may have different channel structures, such as relatively different channel lengths. The heterogeneous channel may provide improved GAA FET device performance by allowing for the ability to adjust or adjust the channel mobility of the GAA FET at different locations in similar region types or when used in different applications.

Description

Background Art

[0001] Various embodiments of the present application generally relate to semiconductor device manufacturing operations and the resulting devices. More specifically, various embodiments relate to gate-all-around transistors including relatively heterogeneous channels.

[0002] Conventional semiconductor devices, such as integrated circuits (ICs), include planar field effect transistors (FETs) in which current flows through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate. The semiconductor industry strives to adhere to Moore's Law, which states that each successive generation of integrated circuit devices shrinks to half their size and operates at twice the speed. However, as device size shrinks, the geometry and materials of conventional silicon devices have problems maintaining switching speeds without causing failures, such as leakage current from the device into the semiconductor substrate. Several new technologies have emerged that allow chip designers to continue to shrink transistor size.

[0003] One particularly radical technology change required redesigning the structure of the FET from a planar device to a three-dimensional device, in which the semiconductor channel is replaced by a fin extending from the plane of the substrate. In such a device, commonly referred to as a FinFET, the control gate surrounds three sides of the fin to affect current flow from three surfaces instead of one. The improved control achieved with the 3D design results in faster switching performance and reduced current leakage. Building taller devices also allows for increased device density within the same footprint previously occupied by planar FETs.

[0004] The FinFET concept has been further extended by developing gate-all-around FETs or GAA FETs, where the gate completely surrounds one or more channels for maximum control of current flow therein. In a GAA FET, the channel can take the form of a nanowire, sheet, isolated from the substrate. In a GAA FET, the respective channel surfaces that are not in contact with the source and drain are in contact with and surrounded by the gate.

[0005] In the pFET region of the GAA FET, channel mobility can be improved by incorporating a strained or unstrained silicon germanium (SiGe) channel. However, in some embodiments, not all pFETs GAA FETs within a semiconductor device benefit from the SiGe channel. Therefore, embodiments of the present disclosure provide a manufacturing technique for forming a semiconductor device including a heterogeneous channel within a similar region (e.g., a pFET region, etc.). Summary of the invention

[0006] In an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first gate all around field effect transistor (GAA FET) in a first region of a first type and a second GAA FET in a second region of the first type. The first GAA FET includes a plurality of first nanostructure channels of a first channel material, and the second GAA FET includes a plurality of second nanostructure channels of a second channel material.

[0007] The first region may be a p-type region, and the second region may also be a p-type region. The first channel material may be silicon germanium (SiGe x ), wherein the second channel material is silicon germanium (SiGe y ). The plurality of second nanostructure channels may each have a longer channel length relative to the plurality of first nanostructure channels.

[0008] The first GAA FET may further include a first portion of the nanolayer channel between each of the plurality of first nanostructure channels and the first source and drain. Similarly, the second GAA FET may further include a second portion of the nanolayer channel between each of the plurality of second nanostructure channels and the second source and drain.

[0009] In an embodiment of the present disclosure, another semiconductor device is provided. The semiconductor device includes a first gate all-around field effect transistor (GAA FET) in a first p-type region and a second GAA FET in a second p-type region. The first GAA FET includes a plurality of silicon germanium (SiGe) nanostructure channels, and the second GAA FET includes a plurality of silicon (Si) nanostructure channels.

[0010] The plurality of silicon nanostructure channels may each have a channel length that is the same or longer than the plurality of SiGe nanostructure channels. The first GAA FET may also include a Si portion of the nanolayer channel between each of the plurality of SiGe nanostructure channels and the first source and drain. Each of the plurality of Si nanostructure channels may directly contact the second source and drain.

[0011] The semiconductor device may also include a third GAA FET having one or more silicon nanostructure channels in the n-type region. The one or more silicon nanostructure channels may each have the same or different channel lengths relative to the plurality of SiGe nanostructure channels.

[0012] In another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes forming a first gate all-around field effect transistor (GAA FET) in a first region of a first type and forming a second GAA FET in a second region of the first type. The first GAA FET includes a plurality of first nanostructure channels of a first channel material, and the second GAA FET includes a plurality of second nanostructure channels of a second channel material.

[0013] When GAA FETs are used in different applications, and / or when GAA FETs have relatively different geometries, such as channel lengths, relatively different or heterogeneous nanostructure channels within GAA FETs within similar region types can provide improved GAA FET device performance by allowing the ability to tune or adjust the channel mobility of GAA FETs in similar region types but in different locations.

[0014] Relatively different or heterogeneous nanostructure channels within GAA FETs within similar region types can further provide techniques for changing or adjusting the threshold voltage of the GAA FET based on the material selection of the nanostructure channel therein. In addition, when the first GAA FET and the second GAA FET have relatively different geometries or are used for different performance requirements, such as the second GAA FET has a relatively long nanostructure channel, the second GAA FET is a relatively high voltage GAA FET, is a lower performance or non-critical GAA FET, etc., it may be desirable for the first GAA FET and the second GAA FET to have relatively different channel materials therein. For example, a silicon nanostructure channel may be desirable for the second GAA FET in the p-type region due to lower risk of defects and reduced integration complexity, while a SiGe nanostructure channel may be desirable for the first GAA FET in the p-type region due to relatively improved electron mobility therein.

[0015]

[0011] These and other embodiments, features, aspects and advantages will become better understood with reference to the following description, appended claims and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1 to 8 Depicted are respective cross-sectional views of a semiconductor device including a gate-all-around transistor shown after sequential fabrication operations in accordance with one or more embodiments of the present disclosure.

[0017] Figures 9 to 14 Depicted are respective cross-sectional views of a semiconductor device including a gate-all-around transistor with a heterogeneous channel shown after sequential fabrication operations in accordance with one or more embodiments of the present disclosure.

[0018] Fig.15is a flowchart illustrating a method for manufacturing a semiconductor device according to one or more embodiments of the present disclosure.

[0019] Figure 16 to Figure 23 Depicted are respective cross-sectional views of a semiconductor device including a gate-all-around transistor with a heterogeneous channel shown after sequential fabrication operations in accordance with one or more embodiments of the present disclosure.

[0020] Fig.24 is a flowchart illustrating a method for manufacturing a semiconductor device according to one or more embodiments of the present disclosure.

[0021] Figure 25 to Figure 27 Depicted are respective cross-sectional views of a semiconductor device including a gate-all-around transistor with a heterogeneous channel shown after sequential fabrication operations in accordance with one or more embodiments of the present disclosure.

[0022] Fig.28 is a flowchart illustrating a method for manufacturing a semiconductor device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0023] Embodiments of the present disclosure recognize that not all GAA FETs or other devices within a similar region of a semiconductor device or across a semiconductor device benefit from the same homogeneous channel type or material. Therefore, the present disclosure provides a manufacturing method for forming multiple GAA FETs or other devices that include heterogeneous channels within similar regions or across a semiconductor device. The method includes forming a first GAA FET including multiple first channels of a first channel material. The method also includes forming a second GAA FET including multiple second channels of a second channel material. The method may also include forming a third GAA FET including multiple third channels of a third channel material. For example, forming a third GAA FET including SiGe x The first p-type GAA FET of the channel is formed by including SiGe y A second p-type GAA FET including a Si channel is formed, and / or a third p-type GAA FET including a Si channel is formed.

[0024] Similar region GAA FETs with heterogeneous channels may have different structures, such as relatively different channel lengths. For example, a first p-type GAA FET may include a SiGe short channel, while a second p-type GAA FET may include a Si long channel, wherein the length of the long channel is greater than the length of the short channel.

[0025] Embodiments of the present disclosure may provide improved GAA FET device performance by improving p-type GAA FET channel mobility, by reducing channel trimming defects and process complexity on long channel GAA FETs, and / or by providing GAA FET design flexibility that allows the GAA FET to have different channels depending on the design or semiconductor device requirements.

[0026] Although this detailed description contains examples of how embodiments of the present disclosure may be implemented to form exemplary semiconductor devices having various GAA FETs, implementation of the teachings set forth herein is not limited to the particular types of GAA FET structures or material combinations depicted or described. Rather, embodiments of the present disclosure can be implemented in conjunction with other transistor types or materials now known or later developed where it is desired to provide transistors having heterogeneous gates in either p-type or n-type regions.

[0027] For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. In addition, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. The various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps will only be briefly mentioned herein or will be omitted entirely without providing well-known process details.

[0028] In general, the various processes used to form semiconductor devices to be packaged into ICs are divided into four general categories, namely, film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD), among others. Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization (CMP), among others. Semiconductor doping is the process of changing electrical properties by doping, for example, transistor source and drain, usually by diffusion and / or by ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate the implanted dopants. Films of conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various areas of a semiconductor substrate allows the conductivity of the substrate to be changed as a voltage is applied. By forming structures of these various components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate so that the pattern can be subsequently transferred to the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called a photoresist. The lithography and etching pattern transfer steps are repeated many times in order to build the complex structures that make up the transistors and the many wires that connect the millions of transistors of the circuit. Each pattern printed on the wafer is aligned with the previously formed pattern, and conductors, insulators, and selectively doped regions are slowly built up to form the final device.

[0029] Turning now to a description of the technology more specifically related to the present disclosure, transistors are semiconductor devices commonly found in various ICs. Typical semiconductor devices are formed using active regions of a wafer. The active region is defined by an isolation region for separating and electrically isolating adjacent semiconductor devices. For example, in an IC having multiple GAA FETs, each GAA FET has a source and a drain formed in an active region of a semiconductor layer by injecting n-type or p-type impurities into the corresponding source and drain materials. Disposed between the source and drain is a channel (or body) region. A gate is disposed around the channel. The gate and the channel are separated by a dielectric layer.

[0030] GAA FETs can be manufactured using so-called complementary metal oxide semiconductor (CMOS) manufacturing technology. Generally, CMOS is a technology that uses complementary and symmetrical pairs of p-type and n-type MOSFETs to implement logic functions. A channel region connects the source and drain, and current flows through the channel region from the source to the drain. Current is induced in the channel region by a voltage applied to the gate electrode.

[0031] The wafer footprint of a GAA FET is related to the conductivity of the channel material. If the channel material has a relatively high conductivity, a GAA FET can be manufactured with a correspondingly smaller wafer footprint. A known method to increase channel conductivity and reduce the size of a GAA FET is to form the channel into nanostructures, such as nanowires or nanosheets. These GAA FETs provide a relatively small FET footprint by forming the channel into a series of vertical nanostructures.

[0032] In a known GAA configuration, a nanostructure-based FET includes a source region, a drain region, and a stacked nanostructure channel between the source and drain regions. The gate surrounds the stacked nanostructure channel and regulates the flow of electrons through the nanostructure channel between the source and drain regions. A GAA FET can be manufactured by forming alternating layers of channel nanostructure layers and sacrificial nanostructure layers. Before completing the GAA FET device, the sacrificial nanostructure layer is released from the channel nanostructure. For an n-type GAA FET, the channel nanostructure layer can be silicon (Si), and the sacrificial nanostructure layer can be silicon germanium (SiGe). For a p-type GAA FET, in some embodiments, the channel nanostructure layer can be SiGe, and the sacrificial nanostructure layer can be Si, and in other embodiments, the channel nanostructure can be Si, and the sacrificial nanostructure can be SiGe.

[0033] In some embodiments, the channel nanostructure layer may initially be Si, and may be converted to SiGe or other materials after removal of the sacrificial nanostructure layer.

[0034] Forming a GAA nanostructure with alternating layers of channel nanostructure layers formed of a first type of semiconductor material (e.g., Si for n-type FETs and SiGe for p-type FETs) and sacrificial nanostructure layers formed of a second type of semiconductor material (e.g., SiGe for n-type FETs and Si for p-type FETs) can provide excellent channel electrostatic control, which is beneficial to the continued scaling of CMOS technology. The use of different channel materials for p-type GAA FETs relative to n-type GAA FETs is generally intended to improve channel mobility and the resulting overall device performance. In addition, the use of different channel materials for GAA FETs in a first p-type or n-type region and GAA FETs in a second identical p-type or n-type region can further improve channel mobility and structural integrity (where desired), and therefore can also improve the resulting overall device performance.

[0035] Turning now to a more detailed description of fabrication operations and resulting structures according to embodiments of the present disclosure, Figure 1-8The semiconductor device 100 is depicted after various manufacturing operations. For ease of illustration, the semiconductor device 100 will be described in the context of forming one or more GAA FETs. Figure 1-8 The fabrication operations described herein are equally applicable to fabricating any number and / or logic location of various FET types.

[0036] Although the cross-sectional structural diagrams shown in the figures are two-dimensional, it should be understood that the figures shown represent three-dimensional devices. Figure 1 The top view reference diagram shown provides Figure 1-8 Reference points for the various cross-sectional views (X view, Y view) shown, the X view is a side cross-sectional view taken along the channel stack 125 across three gates 135, and the Y view is another side cross-sectional view taken along the gate 135 across two channel stacks 125. For clarity, the gate 135 is depicted as a general gate or gate structure, and can be, for example, a sacrificial gate or sacrificial gate structure, a replacement gate conductor or replacement gate structure, etc.

[0037] Figure 9-14 The semiconductor device 300 is depicted after various manufacturing operations. For ease of illustration, the semiconductor device 300 will be described in the context of a first GAA FET including a short channel of a first channel material formed in a p-type region, a second GAA FET including a short channel of a second channel material formed in an n-type region, a third GAA FET including a long channel of the second channel material formed in the p-type region, and a fourth GAA FET including a long channel of the second channel material formed in the n-type region. Figure 10-14 The fabrication operations described herein are equally applicable to fabricating any number and / or logic location of various FET types. Figure 9-14 A cross section of the structure is similar to the X-view cross section diagram above.

[0038] Figure 16-23 The semiconductor device 600 is depicted after various manufacturing operations. For ease of illustration, the semiconductor device 600 will be described in the context of a first GAA FET formed in a particular region type (e.g., a p-type region) including a channel of a first channel material, a second GAA FET formed in the same particular region type including a channel of a second channel material, and / or a third GAA FET formed in the same particular region type including a channel of a third channel material. Figure 16-23 The fabrication operations described herein are equally applicable to fabricating any number and / or logic location of various FET types. Figure 16-23 A cross section of the structure is similar to the X-view cross section diagram above.

[0039] Figure 25 to Figure 27The semiconductor device 900 is depicted after various manufacturing operations. For ease of illustration, the semiconductor device 900 will be described in the context of a first GAA FET formed in a particular region type (e.g., a p-type region) including a channel of a first channel material, a second GAA FET formed in the same particular region type including a channel of a second channel material, and / or a third GAA FET formed in the same particular region type including a channel of a third channel material. Figure 25 to Figure 27 The fabrication operations described herein are equally applicable to fabricating any number and / or logic location of various FET types. Figure 25 to Figure 27 The cross section of the structure is similar to the above X-view cross section diagram. For clarity, Fig.26 The semiconductor device 900 depicted in includes a first GAA FET having a short channel of a first channel material, a second GAA FET having a short channel of a second channel material, and / or a third GAA FET having a short channel of a third channel material, all of which are located in the same region type, but not necessarily in the same region location.

[0040] For clarity, the term "same region type" and the like are defined herein as regions of a semiconductor device that share the same semiconductor impurities within transistors formed therein to form transistors of the same type (e.g., p-type regions share the same or similar trivalent impurities in appropriate transistor structures to form p-type transistors, and n-type regions share the same or similar pentavalent impurities in appropriate transistor structures to form n-type transistors), but need not be in the same region location. For example, three GAA FETs in the same region type may all be p-type GAA FETs and may be located in the same p-type region location and / or different p-type region locations.

[0041] Similarly, Fig. 27 The semiconductor device 900 shown in includes a first GAA FET having a long channel of a first channel material, a second GAA FET having a long channel of a second channel material, and / or a third GAA FET having a long channel of a third channel material, all of which are located in the same region type, but not necessarily in the same region location.

[0042] For the sake of clarity, embodiments of the present disclosure describe various techniques for forming a GAA FET with a heterogeneous channel. Figures 9 to 23 The associated GAA FET depicts a second material last process, where the second material is formed after the initial channel of the first material is formed, and Figure 23 to Figure 27The associated GAA FET 23 depicts a second material first process, where a channel of a first material and a different channel of a second material are formed simultaneously, etc. Other technologies developed now or later may be incorporated into at least some of the embodiments of the present disclosure to form a GAA FET with a heterogeneous channel, as at least structurally contemplated herein.

[0043] Figure 1 A cross-sectional view of a semiconductor device 100 is depicted after initial manufacturing operations according to an embodiment of the present disclosure. In this manufacturing stage, one or more nanolayer stacks 125 are formed on a substrate 102. Additionally, in this manufacturing stage, shallow trench isolation (STI) regions 130 may be formed on the substrate 102 adjacent to the nanolayer stacks 125.

[0044] Non-limiting examples of suitable materials for the substrate 102 include Si (silicon), strained Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon germanium), SiGe:C (silicon-germanium-carbon), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof. Other non-limiting examples of semiconductor materials include III-V materials, such as indium phosphide (InP), gallium arsenide (GaAs), aluminum arsenide (AlAs), or any combination thereof. The III-V group material may include at least one "Group III element", such as aluminum (Al), boron (B), gallium (Ga), indium (In), and at least one "Group V element", such as nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb). The substrate 102 may be a bulk semiconductor material including Si.

[0045] A bottom sacrificial layer 108 may be formed on the substrate 102. Subsequently, an alternating nanostructure layer may be formed on the bottom sacrificial layer 108. The bottom sacrificial layer 108 may be initially formed on the substrate 102. The bottom sacrificial layer 108 may include an epitaxial SiGe layer with a high Ge% ranging from 50% to 70%. In some embodiments of the present invention, the bottom sacrificial layer 108 is SiGe with a Ge percentage that is sufficiently different from the Ge percentage in the sacrificial nanolayer, so that the bottom sacrificial layer 108 can be selectively removed without also removing the SiGe sacrificial nanolayer. The bottom sacrificial layer 108 may have a thickness of, for example, from about 4 to about 15 nm.

[0046] The nanolayer stack 125 may include a portion formed by a series of alternating sacrificial nanolayers (e.g., SiGe sacrificial nanolayers) and portions of nanolayers (e.g., Si nanolayers). The sacrificial SiGe nanolayers may have a lower Ge% ranging from 20% to 45%. The sacrificial portions 110, 114, 118, and 122 of each nanolayer stack 125 may be formed by an associated sacrificial nanolayer, and the nanostructure portions 112, 116, and 120 of each nanolayer stack 125 may be formed by an associated nanolayer.

[0047] According to an embodiment of the present disclosure, the bottom sacrificial layer can be epitaxially grown from the substrate 102, and the alternating nanolayers can be formed by epitaxially growing one layer and then the next layer until the desired number of layers and the desired thickness are achieved. Any number of alternating layers can be provided. The epitaxial material can be grown from a gaseous or liquid precursor. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. Depending on the type of transistor, epitaxial silicon, silicon germanium, and / or carbon-doped silicon (Si:C) silicon can be doped (in situ doped) during deposition by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium).

[0048] The terms "epitaxial growth and / or deposition" and "epitaxial formation and / or growth" refer to the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), wherein the grown semiconductor material (crystalline capping layer) has substantially the same crystal properties as the semiconductor material (seed material) of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gas are controlled, and the system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move back and forth on the surface so that the deposited atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, the epitaxially grown semiconductor material has substantially the same crystal properties as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100} crystalline surface will exhibit a {100} crystalline orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for formation on semiconductor surfaces, and generally does not deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0049] In some embodiments of the present disclosure, the nanolayer is formed of silicon (Si) and may include, for example, single crystal silicon. The nanolayer may have, for example, a thickness of about 4 to about 12 nm. In embodiments where the sacrificial nanolayer includes SiGe, the sacrificial nanolayer may have, for example, a thickness from about 4 to about 12 nm. Subsequently, a mask layer (not shown) may be formed on top of the uppermost sacrificial nanolayer.

[0050] At this stage of fabrication, each nanolayer stack 125 may include a bottom sacrificial portion 108, a sacrificial nanolayer portion 110, a nanostructure channel 112, a sacrificial nanolayer portion 114, a nanostructure channel 116, a sacrificial nanolayer portion 118, a nanostructure channel 120, and a sacrificial nanolayer portion 122. The nanolayer stacks 125 may be formed by patterning associated layers or portions thereof. Subsequently, STI regions 130 may be formed over the substrate 102 and adjacent to the one or more nanolayer stacks 125. In the depicted embodiment, the top surface of the one or more STI regions 130 may be coplanar with the bottom surface of the bottom sacrificial portion 108 of the one or more nanolayer stacks 125.

[0051] One or more nanolayer stacks 125 may be patterned by removing corresponding undesirable portions or sections of the above layers while retaining corresponding desired portions. Removal of the bottom sacrificial layer and the alternating sacrificial nanolayers and undesirable portions of the nanolayers may be achieved using, for example, conventional photolithography and etching processes. As depicted, such removal of undesirable portions may further remove undesirable portions of the substrate 102. The bottom sacrificial layer and the alternating sacrificial nanolayers and desired portions of the nanolayers may be retained, thereby forming one or more nanolayer stacks 125.

[0052] STI regions 130 may be formed by depositing an STI dielectric material on substrate 102 and adjacent to nanolayer stack 125, followed by etching back, recessing, etc. the STI dielectric material. STI regions 130 may electrically isolate components or features of adjacent GAA FETs, etc.

[0053] Figure 2 A cross-sectional view of semiconductor device 100 is depicted after exemplary manufacturing operations according to one or more embodiments. In the depicted manufacturing stage, one or more sacrificial gate structures 144 are formed on and around one or more nanolayer stacks 125 and on STI regions 130. Sacrificial gate structures 144 may include a sacrificial gate liner (not shown), a sacrificial gate 140, and a sacrificial gate cap 142.

[0054] Sacrificial gate structure 144 may be formed by forming a sacrificial gate liner layer (e.g., dielectric, oxide, etc.) on STI region 130 and on and around nanolayer stack 125. For example, the sacrificial gate liner layer may be deposited on the upper surface of STI region 130, the sidewalls of bottom sacrificial portion 108, the sidewalls of sacrificial nanolayer portion 110, the sidewalls of nanostructure channel 112, the sidewalls of sacrificial nanolayer portion 114, the sidewalls of nanostructure channel 116, the sidewalls of sacrificial nanolayer portion 118, the sidewalls of nanostructure channel 120, and the sidewalls and upper surface of sacrificial nanolayer portion 122.

[0055] The sacrificial gate structure 144 may be further formed by subsequently forming a sacrificial gate layer (eg, amorphous silicon, etc.) on the sacrificial gate pad. The thickness of the sacrificial gate layer may be greater than the height of the one or more nanolayer stacks 125.

[0056] The sacrificial gate structure 144 may be further formed by subsequently forming a gate capping layer on the sacrificial gate layer. The gate capping layer may be formed by depositing a mask material such as a hard mask material. The gate capping layer may be composed of one or more layers of masking material to protect the sacrificial gate layer and / or other underlying materials during subsequent processing of the device 100. The gate capping layer may be formed of known gate masking materials, such as silicon nitride, silicon oxide, combinations thereof, and the like.

[0057] Conventional photolithography and etching processes can be used to pattern the gate cap layer, the sacrificial gate layer, and the sacrificial gate liner to remove undesirable portions and retain desired portions, respectively. The retained desired portions of the gate cap layer, the sacrificial gate layer, and the sacrificial gate liner can form a sacrificial gate liner (not shown), a sacrificial gate 140, and a sacrificial gate cap layer 142 of each of the one or more sacrificial gate structures 144, respectively.

[0058] Each sacrificial gate structure 144 can be formed on a target region or area of ​​the semiconductor device 100 to define the length of one or more GAA FETs, one or more GAA FET channels, etc., and provide sacrificial material to produce a target GAA FET structure in subsequent processing. According to an example, each sacrificial gate structure 144 can have a height between about 50nm and about 200nm, and a length between about 10nm and about 200nm.

[0059] Figure 3 Depicted is a cross-sectional view of a semiconductor device 100 shown after exemplary fabrication operations according to one or more embodiments. In the depicted fabrication stage, the bottom sacrificial portion 108 may be selectively removed, a BDI region 152 may be formed in its place, and one or more gate spacers 154 may be formed.

[0060] The bottom sacrificial portions 108 can be selectively removed and can form associated BDI cavities between the substrate 102 and the sacrificial nanolayer portions 110, respectively. In lieu of the bottom sacrificial portions 108 being removed, a bottom dielectric isolation (BDI) region 152 can be formed between the substrate 102 and the sacrificial nanolayer portions 110 within each nanolayer stack 125.

[0061] Additionally, in the depicted manufacturing stage, gate spacers 154 may be formed around each of the one or more sacrificial gate structures 144. Each gate spacer 154 may also be formed on at least a portion of a sidewall of the one or more nanolayer stacks 125 and on a top surface of a portion of the STI regions 130.

[0062] The BDI region 152 and the gate spacer 154 can be formed simultaneously by conformally depositing a dielectric material (such as silicon nitride, SiBCN, SiNC, SiN, SiCO, SiNOC, or a combination thereof) within the BDI cavity and on the STI region 130 and around each of the one or more sacrificial gate structures 144. Undesirable portions of the dielectric material can be removed by etching or other subtractive material removal processes. Desired portions of the dielectric material can remain within the BDI cavity, and the BDI region 152 can be formed. Additional desired portions of the dielectric material can be retained on the top surface of the STI region 130, adjacent to and on the sidewalls of the sacrificial gate structure 144, and around the one or more nanolayer stacks 125.

[0063] Figure 4 Depicted is a cross-sectional view of a semiconductor device 100 shown after exemplary fabrication operations according to one or more embodiments. In the depicted fabrication stage, one or more source / drain (S / D) recesses 160 and one or more nanostructure stacks 170 are formed.

[0064] One or more S / D recesses 160 and one or more nanostructure stacks 170 may be formed by recessing or otherwise removing at least one corresponding portion of one or more nanolayer stacks 125 that is not protected by sacrificial gate structure 144 and / or gate spacer 154. For example, unprotected and / or undesired portions of each nanolayer stack 125 may be etched or otherwise removed. The etching may utilize the top surface of BDI 152 as an etch stop. The one or more portions of the nanolayer stacks 125 that are retained may effectively form a nanostructure stack 170.

[0065] At this manufacturing stage, the nanostructure stack 170 may include a sacrificial nanolayer portion 180 formed by the sacrificial nanolayer portion 110, a nanostructure channel 182 formed by the nanostructure channel 112, a sacrificial nanolayer portion 184 formed by the sacrificial nanolayer portion 114, a nanostructure channel 186 formed by the nanostructure channel 116, a sacrificial nanolayer portion 188 formed by the sacrificial nanolayer portion 118, a nanostructure channel 190 formed by the nanostructure channel 120, and a sacrificial nanolayer portion 192 formed by the sacrificial nanolayer portion 122.

[0066] One or more nanostructure stacks 170 may be further modified or fabricated by selectively recessing the length or otherwise laterally recessing the sacrificial nanolayer portions 180, 184, 188, 192, etc. Such lateral recessing of the sacrificial nanolayer portions 180, 184, 188, 192 may be provided, for example, by a vapor phase process that leaves other structures (e.g., substrate 102, BDI 152, gate spacers 154, nanostructure channels 182, 186, 190, etc.) substantially intact.

[0067] The inner spacers 196 can be formed within the grooves or lateral depressions of the sacrificial nanolayer portions 180, 184, 188, 192. The inner spacers 196 can be formed by depositing an electrically insulating material (e.g., a dielectric) to pinch off the previously formed depressions, thereby creating the inner spacers 196 located therein (e.g., above and below each nanostructure channel 182, 186, 190 within the nanosheet stack 170). For example, inner spacer 196 may be formed on the sidewalls of sacrificial nanolayer portion 180 and between BDI 152 and nanostructure channel 182, inner spacer 196 may be formed on the sidewalls of sacrificial nanolayer portion 184 and between nanostructure channel 182 and nanostructure channel 186, inner spacer 196 may be formed on the sidewalls of sacrificial nanolayer portion 188 and between nanostructure channel 186 and nanostructure channel 190, and inner spacer 196 may be formed on the sidewalls of sacrificial nanolayer portion 192 and between nanostructure channel 190 and gate spacer 154. At this stage of manufacturing, nanostructure stack 170 may also include spacer 196.

[0068] Figure 5 A cross-sectional view of a semiconductor device 100 is depicted after exemplary manufacturing operations according to one or more embodiments. In the depicted manufacturing stage, S / D regions 240 are formed in one or more S / D recesses 160, respectively, and S / D caps 252 are formed on one or more S / D regions 240, respectively.

[0069] The S / D region 240 may be formed by epitaxially growing a source / drain epitaxial region in the S / D recess 160, for example, from an exposed inner sidewall within the S / D recess 160. In some embodiments, the S / D region 240 is formed by in-situ doping epitaxial growth. In some embodiments, the epitaxial growth and / or deposition process may be selectively formed on a semiconductor surface and may not deposit material on a dielectric surface, such as a silicon dioxide or silicon nitride surface. In some embodiments, the epitaxial growth of the S / D region 240 may be overgrown above the upper surface of the semiconductor device 100.

[0070] Suitable n-type dopants include, but are not limited to, phosphorus (P), and suitable p-type dopants include, but are not limited to, boron (B). The use of an in-situ doping process is merely an example. For example, a non-in-situ process may be used instead to introduce dopants into the source and drain. Other doping techniques may be used to incorporate dopants into the bottom source / drain region. Doping techniques include, but are not limited to, ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implant doping, liquid phase doping, solid phase doping, in-situ epitaxial growth, or any suitable combination of these techniques. In a preferred embodiment, the conditions for S / D epitaxial growth are to promote in-situ boron doped SiGe for p-type transistors and phosphorus or arsenic doped silicon or Si:C for n-type transistors. The doping concentration of the S / D region 240 may be between 1×10 19 cm -3 Up to 2×10 21 cm -3 or preferably between 2×10 20 cm -3 Up to 7×10 20 cm -3 between.

[0071] In some embodiments, the S / D region 240 can be partially recessed to remove an upper portion of the S / D region 240. For example, the upper portion of one or more S / D regions 240 can be etched or otherwise removed. The etching can be timed or otherwise controlled to stop removing one or more S / D regions 240 so that the top surface of the remaining one or more S / D regions 240 is located above the upper surface of the nanostructure channel 190. Partially removing the upper portion of the S / D region 240 can at least partially reform the S / D recess 160.

[0072] The S / D cap 252 may be formed on one or more S / D regions 240 within the partially reformed S / D recess 160, respectively. The S / D cap 252 may be formed by depositing a dielectric material, such as silicon oxide, silicon nitride, SiBCN, SiNC, SiN, SiCO, SiNOC, or a combination thereof, within the partially reformed S / D recess 160 and on the S / D region 240. In one embodiment, the S / D cap 252 may be formed to a certain thickness above the top surface of the semiconductor device 100, and then planarized or etched by chemical mechanical polishing (CMP) so that the top surface of the S / D cap 252 is coplanar with the top surface of the sacrificial gate structure 144 and / or the top surface of the gate spacer 152. The S / D cap 252 may also be referred to herein as an S / D insulator.

[0073] Figure 6 Depicted is a cross-sectional view of a semiconductor device 100 shown after exemplary fabrication operations in accordance with one or more embodiments. In the depicted fabrication stage, a gate opening 250 is formed.

[0074] The gate opening 250 may be formed by removing the sacrificial gate structure 144, and as shown in the Y-sectional view, at least corresponding portions of the upper surface of the STI region 130, corresponding sidewall surface portions of the BDI 152, corresponding sidewall surface portions of the sacrificial nanolayer portions 180, 184, 188, and 192, and corresponding sidewall surface portions of the nanolayer channels 182, 186, and 190 may be exposed.

[0075] Figure 7 Depicted is a cross-sectional view of a semiconductor device 100 shown after exemplary fabrication operations in accordance with one or more embodiments. In the depicted fabrication stage, the nanostructure stack 170 is modified by selectively removing sacrificial nanolayer portions 180 , 184 , 188 , and 192 .

[0076] Various techniques may be used to process the nanostructure stack 170. For example, the gate opening 250 may laterally or otherwise expose the nanostructure stack 170. Subsequently, the exposed sacrificial nanolayer portions 180, 184, 188, and 192 may be removed to expose the nanolayer channels 182, 186, and 190 within the nanostructure stack 170. As depicted in the X-section, the upper and lower surfaces of the nanolayer channels 182, 186, and 190 may be exposed inside or within adjacent inner spacers 196 associated with adjacent nanostructure stacks 170. As depicted in the Y-section, the perimeters of the nanolayer channels 182, 186, and 190 may be exposed inside or within adjacent inner spacers 196 associated with adjacent nanostructure stacks 170.

[0077] Figure 8 Depicted is a cross-sectional view of semiconductor device 100 shown after exemplary fabrication operations in accordance with one or more embodiments. In the depicted fabrication stage, a replacement gate structure 289 is formed within gate opening 250 around nanolayer channels 182 , 186 , and 190 .

[0078] The replacement gate structure 289 may include a gate dielectric 290 and a gate conductor 292. The gate dielectric 290 may include any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or any combination of these materials. The gate dielectric 290 may be formed by any suitable deposition process, etc. In some embodiments, the gate dielectric 290 has a thickness ranging from 1 nm to 5 nm, although lesser thicknesses and greater thicknesses are also contemplated.

[0079] The gate conductor 292 may include any suitable conductive material, including but not limited to doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au), conductive metal compound materials (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide (CoSi), nickel silicide (NiSi)), transition metal aluminides (e.g., Ti3Al, ZrAl), TaC, TaMgC, carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials.

[0080] The gate conductor 292 may also include dopants introduced during or after deposition. In some embodiments, the gate conductor 292 may further include a work function setting layer (not shown) between the gate dielectric 290 and the gate conductor 292. The work function setting layer may be a work function metal (WFM). The gate conductor 292 and the WFM may be formed by any suitable process or any suitable combination of processes, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, etc.

[0081] The replacement gate structure 289 may be formed by initially forming a gate dielectric layer within the gate opening 250 around the channels 182, 186, and 190, on the sidewalls of the inner spacer 196, on the gate spacer 154, and on the top surface of the BDI 152. The replacement gate structure 289 may be further formed by subsequently forming a gate conductor layer on the gate dielectric layer. For clarity, the replacement gate structure 289 may be a wrap-around gate structure, a gate-all-around structure, because the gate conductor 292 wraps around the channels 182, 186, and 190, as depicted in the Y cross section.

[0082] Conventional photolithography and etching processes can be used to pattern the gate conductor layer and the gate dielectric layer to remove undesirable portions and retain desired portions, respectively. The remaining desired portions of the gate conductor layer and the gate dielectric layer can form the gate dielectric layer 290 and the gate conductor 292 of the replacement gate structure 292. The etching process or another subtractive removal technique can remove the undesirable portions of the replacement gate structure 289 so that the top surface of the replacement gate structure 289 is coplanar with the top surface of the semiconductor device 100.

[0083] In some embodiments, the gate conductor 292 can be recessed below the top surface of the semiconductor device 100 , and a dielectric gate cap (not shown) can be formed on the recessed gate conductor 292 .

[0084] Figure 9-14 Semiconductor device 300 is depicted after various manufacturing operations. For example, Fig. 9 The semiconductor device 300 depicted in FIG. 3 may have previously undergone Figure 1-5 Manufacturing operations similar to those depicted in FIG. Fig. 9 As shown, semiconductor device 300 may include substrate 302, BDI 352, nanostructure stack 370, S / D 340, S / D cap 452, sacrificial gate structure and / or gate spacer 354. Nanostructure stack 370 may include sacrificial nanolayer portions 380, 384, 388, and 392. Nanostructure stack 370 may also include nanolayer channels 382, ​​386, and 390. Nanostructure stack 370 may also include inner spacer 396.

[0085] For clarity, substrate 302 , BDI 352 , nanostructure stack 370 , S / D 340 , S / D cap 452 , sacrificial gate structure and / or gate spacer 354 may be formed from similar materials and by similar fabrication techniques as described with reference to related features of semiconductor device 100 .

[0086] The semiconductor device 300 may include a p-type GAA FET 303, an n-type GAA FET 313, a p-type GAA FET 323, and an n-type GAA FET 333. In general, a long channel GAA FET includes a channel having a greater channel length relative to a related channel length in a short channel GAA FET. The p-type GAA FET 303, the n-type GAA FET 313, the p-type GAA FET 323, and the n-type GAA FET 333 may be formed on the same substrate 302 and / or BDI 352. For clarity, the p-type GAA FET 303 and the p-type GAA FET 323 are formed in the same region type (i.e., p-type region), but may be formed in the same p-type region or different p-type regions of the semiconductor device 300, as depicted. Likewise, n-type GAA FET 313 and n-type GAA FET 333 are formed in the same region type (i.e., n-type region), but may be formed in the same n-type region or different n-type regions of semiconductor device 300, as depicted. P-type GAA FET 303 and n-type GAA FET 313 may include a short channel, while p-type GAA FET 323 and n-type GAA FET 333 may include a long channel, wherein the length of the long channel is greater than the length of the short channel, as depicted.

[0087] P-type GAA FET 303 and p-type GAA FET 323 include respective S / D 340 including appropriate materials, dopants, etc. Similarly, n-type GAA FET 313 and n-type GAA FET 333 include respective S / D 340 including appropriate materials, dopants, etc.

[0088] Fig. 9 Depicted is a cross-sectional view of a semiconductor device 300 shown after exemplary fabrication operations in accordance with one or more embodiments. In the depicted fabrication stage, a gate opening 450 is formed.

[0089] The gate opening 450 may be formed by removing the sacrificial gate structure, and may expose at least a corresponding portion of the upper surface of the STI region, a corresponding sidewall surface portion of the BDI 352, a corresponding sidewall surface portion of the sacrificial nanolayer portions 380, 384, 388, and 392, and a corresponding sidewall surface portion of the nanolayer channels 382, ​​386, and 390. In other words, the gate opening 450 may expose the side surfaces of the BDI 352, the sacrificial nanolayer portions 380, 384, 388, and 392, and the nanolayer channels 382, ​​386, and 390. The gate opening 450 may further expose the top surface of the sacrificial nanolayer portion 392. The gate opening 450 may further expose at least an inner portion or an inner-facing portion of the gate spacer 354.

[0090] Fig.10 Depicted is a cross-sectional view of a semiconductor device 300 shown after exemplary manufacturing operations according to one or more embodiments. In the depicted manufacturing stage, a mask 460 is formed over the p-type GAA FET 323 , the n-type GAA FET 313 , and / or the n-type GAA FET 333 .

[0091] The mask 460 may be a dielectric material, an organic planarization material, or a mask material, and may be formed by depositing a blanket mask material on the p-type GAA FET 303, the p-type GAA FET 323, the n-type GAA FET 313, and / or the n-type GAA FET 333. The mask material may be deposited on the corresponding S / D cap 452, on the corresponding gate spacer 354, on and around the corresponding nanostructure stack 370, on the corresponding BDI 352, and / or on the corresponding STI region. A portion of the mask material on the p-type GAA FET 303 may then be removed, thereby re-exposing at least the gate opening 450 and / or its nanostructure stack 370.

[0092] The mask 460 may protect the p-type GAA FET 323 , the n-type GAA FET 313 , and / or the n-type GAA FET 333 from subsequent channel processing of the p-type GAA FET 303 .

[0093] Fig.11 A cross-sectional view of a semiconductor device 300 is depicted, shown after exemplary fabrication operations, in accordance with one or more embodiments. In the depicted fabrication stage, the nanostructure stack 370 of the p-type GAA FET 303 is processed by selectively removing sacrificial nanolayer portions 380, 384, 388, and 392 and by trimming the nanolayer channels 382, ​​386, and 390 therein.

[0094] Various techniques may be utilized to process the nanostructure stack 370 of the p-type GAA FET 303 to selectively remove the sacrificial nanolayer portions 380, 384, 388, and 392. For example, the gate opening 450 may laterally or otherwise expose the nanostructure stack 370 of the p-type GAA FET 303, while the mask 460 protects the underlying corresponding p-type GAA FET 323, n-type GAA FET 313, and / or n-type GAA FET 333. Subsequently, the exposed sacrificial nanolayer portions 380, 384, 388, and 392 may be removed to expose the associated nanolayer channels 382, ​​386, and 390. As depicted in the X cross-section, the upper, lower, and side surfaces of the nanolayer channels 382, ​​386, and 390 may be exposed inside or within the adjacent inner spacer 396.

[0095] Nanolayer channels 382, ​​386, and 390 may be trimmed, for example, by etching or other selective removal processes. Nanolayer channels 382, ​​386, and 390 may be trimmed to form nanolayers that are coated, grown, deposited, or otherwise formed. Fig.12 The vertical space between adjacent nanolayer channels 382, ​​386, and 390 is increased before the capping channels 482, 486, and 490 depicted in FIG. 4 to prevent undesired merging of adjacent nanolayer channels. The trimming of nanolayer channels 382, ​​386, and 390 can be accomplished using a vapor phase etching process, controlled etching cycles, and the like.

[0096] Fig.12 Depicted is a cross-sectional view of a semiconductor device 300 shown after exemplary manufacturing operations according to one or more embodiments. In the depicted manufacturing stage, the mask 460 may be removed and the nanostructure stack 370 of the p-type GAA FET 303 may be further processed by forming a channel material on the trimmed nanolayer channels 382, ​​386, and 390 to form cladding channels 482, 486, and 490, respectively.

[0097] Mask 460 may be removed from n-type GAA FET 313, p-type GAA FET 323, and / or n-type GAA FET 333 using conventional photolithography and etching processes. Removal of mask 460 may reform gate openings 450 of n-type GAA FET 313, p-type GAA FET 323, and n-type GAA FET 333.

[0098] The cladding channels 482, 486, and 490 may be formed by epitaxially growing material from applicable surfaces of the trimmed nanolayer channels 382, ​​386, and 390 until a desired growth thickness or shape has been achieved. In a particular embodiment, as exemplarily depicted, the cladding channels 482, 486, and 490 may be formed by epitaxially growing SiGe from associated one or more surfaces of the trimmed nanolayer channels 382, ​​386, and 390. Alternatively, the cladding channels 482, 486, and 490 may be formed by depositing a second material on the trimmed nanolayer channels 382, ​​386, and 390 material.

[0099] In certain embodiments, the cladding channels 482, 486, and 490 may include a peripheral portion of a second or different channel material relative to an inner core of a first channel material of the trimmed nanolayer channels 382, ​​386, and 390. For example, the cladding channels 482, 486, and 490 may each include a SiGe outer portion surrounding a Si inner core of the trimmed nanolayer channels 382, ​​386, and 390. In other embodiments, as depicted, after forming the cladding channels 482, 486, and 490, a thermal mixing process may react the second or different channel material with the first material of the inner core, which causes the second material to diffuse and the first material to be consumed. The thermal mixing process may produce channels 482, 486, and 490 clad with a continuous material (e.g., SiGe) such that a particular second material percentage at one location of the cladding channels 482, 486, and 490 is the same or substantially the same as the second material percentage at any different location of the cladding channels 482, 486, and 490, respectively.

[0100] After forming the cladding channel 482, the associated channel of the p-type GAA FET 303 may include a first portion of the nanolayer channel 382 vertically between vertically adjacent inner spacers 396 and in contact with the S / D 340, a second portion of the nanolayer channel 382 vertically between vertically adjacent inner spacers 396 and in contact with another S / D 340, and the cladding channel 482 in contact with the first and second portions of the nanolayer channel 382. Similarly, after forming the cladding channel 486, the associated channel of the p-type GAA FET 303 may include a first portion of the nanolayer channel 386 vertically between vertically adjacent inner spacers 396 and in contact with the S / D 340, a second portion of the nanolayer channel 386 vertically between vertically adjacent inner spacers 396 and in contact with another S / D 340, and the cladding channel 490 in contact with the first and second portions of the nanolayer channel 386. Similarly, after forming the cladding channel 490, the associated channel of the p-type GAA FET 303 may include a first portion of the nanolayer channel 390 vertically between vertically adjacent inner spacers 396 and in contact with the S / D 340, a second portion of the nanolayer channel 390 vertically between vertically adjacent inner spacers 396 and in contact with another S / D 340, and the cladding channel 490 in contact with the first and second portions of the nanolayer channel 390.

[0101] In some embodiments (eg, without thermal mixing, etc.), cladding channels 482 , 486 , and 490 may include an inner portion extending and contacting each associated S / D 340 and a cladding portion of a second material surrounding or encircling the inner portion at least within gate opening 450 .

[0102] In a particular embodiment, cladding channels 482, 486, and 490 may be formed of SiGe having a Ge% illustratively ranging from 50% to 70%, and may generally be formed of SiGe having a Ge percentage sufficient to achieve a desired channel mobility for p-type GAA FET 303. In this embodiment, respective first and second portions of nanolayer channels 382, ​​386, and 390 may be formed of different materials, such as Si.

[0103] Fig.13Depicted is a cross-sectional view of a semiconductor device 300 shown after exemplary manufacturing operations according to one or more embodiments. In the depicted manufacturing stage, a mask 461 is formed over the p-type GAA FET 303, the mask 460 is removed from the n-type GAA FET 313, from the p-type GAA FET 323, and / or from the n-type GAA FET 333, and / or the respective nanostructure stacks 370 of the n-type GAA FET 313, the p-type GAA FET 323, and the n-type GAA FET 333 are processed by selectively removing the sacrificial nanolayer portions 380, 384, 388, and 392 therein.

[0104] The mask 461 may be a dielectric material, an organic planarization material, or a mask material, and may be formed by depositing a mask material over the p-type GAA FET 303. The mask 461 material may be deposited on the p-type GAA FET 303 S / D cap 452, the gate spacer 354, on and around the nanostructure stack 370, on the BDI 352, and / or on the corresponding STI region. The material of the mask 461 may be selectively etched relative to the material of the mask 460 to remove the mask 460 while at least temporarily retaining the mask 461. The mask 461 may be formed within the gate opening 450 of the p-type GAA FET 303.

[0105] The respective nanostructure stacks 370 of the n-type GAA FET 313, the p-type GAA FET 323, and the n-type GAA FET 333 can be processed by selectively removing the sacrificial nanolayer portions 380, 384, 388, and 392 therein. For example, the gate opening 450 can be reformed by removing the mask 460 and exposing the nanostructure stack 370. Subsequently, the exposed sacrificial nanolayer portions 380, 384, 388, and 392 can be removed to expose the nanolayer channels 382, ​​386, and 390 within the nanostructure stack 370. As depicted, the respective upper and lower surfaces of the nanolayer channels 382, ​​386, and 390, along with the side surfaces, can be exposed inside or within the adjacent inner spacers 396 associated with the opposite sides of the respective nanostructure stacks 370.

[0106] Fig.14 Depicted is a cross-sectional view of semiconductor device 300 shown after exemplary fabrication operations in accordance with one or more embodiments. In the depicted fabrication stage, a replacement gate structure 489 is formed within gate opening 450 around nanolayer channels 382 , 386 , and 390 .

[0107] The replacement gate structure 489 may include a gate dielectric 488 and a gate conductor 492. The gate dielectric 488 may include any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or any combination of these materials. The gate dielectric 488 may be formed by any suitable deposition process, etc. In some embodiments, the gate dielectric 488 has a thickness ranging from 1 nm to 5 nm, although lesser thicknesses and greater thicknesses are also contemplated.

[0108] The gate conductor 492 may include any suitable conductive material, including but not limited to doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au), conductive metal compound materials (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide (CoSi), nickel silicide (NiSi)), transition metal aluminides (e.g., Ti3Al, ZrAl), TaC, TaMgC, carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials.

[0109] The gate conductor 492 may further include dopants introduced during or after deposition to be suitable for inclusion in the p-type GAA FET 303, the n-type GAA FET 313, the p-type GAA FET 323, and the n-type GAA FET 333, respectively. In some embodiments, the gate conductor 492 may further include a work function setting layer (not shown) between the gate dielectric 488 and the gate conductor 492. The work function setting layer may be a work function metal (WFM). The gate conductor 492 and the WFM may be formed by any suitable process or any suitable combination of multiple processes, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, etc.

[0110] The replacement gate structure 489 may be formed by initially forming a gate dielectric layer within the gate opening 450 around the channels 382, ​​386, and 390, on the sidewalls of the inner spacer 396, on the gate spacer 354, and on the top surface of the BDI 352. The replacement gate structure 489 may be further formed by subsequently forming a gate conductor layer on the gate dielectric layer. For clarity, the replacement gate structure 489 may be a wrap-around gate structure, a gate-all-around structure, because the gate conductor 392 wraps around and envelops the channels 482, 486, and 490 and the channels 382, ​​386, and 390, respectively.

[0111] The gate conductor layer and the gate dielectric layer may be patterned using conventional photolithography and etching processes to remove undesirable portions and retain desired portions, respectively. The retained desired portions of the gate conductor layer and the gate dielectric layer may form the gate dielectric layer 390 and the gate conductor 392 of the replacement gate structure 392. The etching process or another subtractive removal technique may remove the undesirable portions of the replacement gate structure 489 so that the top surface of the replacement gate structure 489 is coplanar with the top surface of the semiconductor device 300.

[0112] In some embodiments, the gate conductor 392 can be recessed below the top surface of the semiconductor device 300 , and a dielectric gate cap (not shown) can be formed on the recessed gate conductor 392 .

[0113] For clarity, the semiconductor device 300 includes heterogeneous channels in the same region, for example, in the p-type region. The first GAA FET includes a plurality of first channels of a first channel material (e.g., SiGe-clad channels 482, 486, and 490). The second GAAFET includes a plurality of second channels of a second channel material (e.g., Si channels 382, ​​386, and 390). Similar region GAA FETs with heterogeneous channels may have different channel structures, such as relatively different channel lengths. For example, the first GAA FET may include a short channel, and the second GAA FET may include a long channel, wherein the length of the long channel is greater than the length of the short channel. Embodiments of the present disclosure may provide improved p-type GAA FET device performance by improving p-type GAA FET channel mobility and by reducing channel trimming defects within long channel GAA FETs.

[0114] Fig.15 1 is a flowchart of a method 500 for manufacturing a semiconductor device 300 according to one or more embodiments of the present disclosure. Figures 1 to 14One or more of the diagrams and descriptions of the depicted manufacturing operations of method 500. The method 500 depicted herein is exemplary. Many variations of the drawings or operations described therein may exist without departing from the spirit of the embodiments. For example, the operations may be performed in a different order, or operations may be added, deleted, or modified.

[0115] At block 502 , method 500 may include removing a sacrificial gate of a first p-type GAA FET (e.g., p-type GAA FET 303 ), removing a sacrificial gate of a second p-type GAA FET (e.g., p-type GAA FET 323 ), removing a sacrificial gate of a first n-type GAA FET (e.g., n-type GAA FET 313 ), and removing a sacrificial gate of a second n-type GAA FET (e.g., n-type GAA FET 333 ).

[0116] At block 504, method 500 may include masking the second p-type GAA FET, masking the first n-type GAA FET, and masking the second n-type GAA FET. At block 506, method 500 may include exposing channels 382, ​​386, and 390 of the first material within the first p-type GAA FET by removing sacrificial nanolayer portions 380, 384, 388, and 392, thereby forming a gate trench 450.

[0117] At block 508, method 500 may include thinning the thickness of channels 382, ​​386, and 390 within the first p-type GAA FET. At block 510, method 500 may include forming cladding channels 482, 486, and 490 by depositing a second material on channels 382, ​​386, and 390 within the first p-type GAA FET.

[0118] At block 512, method 500 may include masking the first p-type GAA FET. At block 514, method 500 may include exposing channels 382, ​​386, and 390 of the first material within the second p-type GAA FET, within the first n-type GAA FET, and within the second n-type GAA FET by removing the mask and by removing the corresponding sacrificial nanolayer portions 380, 384, 388, and 392.

[0119] At block 516, the method 500 may include exposing the cladding channels 482, 486, and 490 in the first p-type GAA FET by removing the mask. At block 518, the method 500 may include forming a replacement gate structure 489 around the cladding channels 482, 486, and 490 in the first p-type GAA FET, forming a replacement gate structure 489 around the channels 382, ​​386, and 390 in the second p-type GAA FET, forming a replacement gate structure 489 around the channels 382, ​​386, and 390 in the first n-type GAA FET, and forming a replacement gate structure 489 around the channels 382, ​​386, and 390 in the second n-type GAA FET.

[0120] Figure 16-23 Semiconductor device 600 is depicted after various manufacturing operations. For example, Fig.16 The semiconductor device 600 depicted in FIG. 6 may have previously undergone Figure 1-5 Manufacturing operations similar to those depicted in FIG. Fig.16 As shown, semiconductor device 600 may include substrate 602, BDI 652, nanostructure stack 670, S / D 640, S / D cap 652, sacrificial gate structure and / or gate spacer 654. Nanostructure stack 670 may include sacrificial nanolayer portions 680, 684 and 688, and 692. Nanostructure stack 670 may also include nanolayer channels 682, 686, and 690. Nanostructure stack 670 may also include inner spacer 696.

[0121] For clarity, substrate 602 , BDI 652 , nanostructure stack 670 , S / D 640 , S / D cap 752 , sacrificial gate structure and / or gate spacer 654 may be formed from similar materials and by similar fabrication techniques as described with reference to related features of semiconductor device 100 .

[0122] The semiconductor device 600 may include GAA FET 603, GAA FET 605, and GAA FET 607. GAA FET 603, GAA FET 605, and GAA FET 607 may be formed on the same substrate 602 and / or BDI 652. For clarity, GAA FET 603, GAA FET 605, and GAA FET 607 are formed in the same region type (e.g., p-type region, n-type region, etc.), but may be formed in the same region or location, or different regions or locations, of the semiconductor device 600, as depicted.

[0123] Fig.16Depicted is a cross-sectional view of a semiconductor device 600 shown after exemplary fabrication operations in accordance with one or more embodiments. In the depicted fabrication stage, a gate opening 750 is formed.

[0124] The gate opening 750 may be formed by removing the sacrificial gate structure, and may expose at least a corresponding portion of the upper surface of the STI region, a corresponding sidewall surface portion of the BDI 652, a corresponding sidewall surface portion of the sacrificial nanolayer portions 680, 684, 688, and 692, and a corresponding sidewall surface portion of the nanolayer channels 682, 686, and 690. In other words, the gate opening 750 may expose the side surfaces of the BDI 652, the sacrificial nanolayer portions 680, 684, 688, and 392, and the nanolayer channels 682, 686, and 690. The gate opening 450 may further expose the top surface of the sacrificial nanolayer portion 692. The gate opening 750 may further expose at least an inner portion or an inner-facing portion of the gate spacer 654.

[0125] Fig.17 Depicted is a cross-sectional view of a semiconductor device 600 shown after exemplary fabrication operations in accordance with one or more embodiments. In the depicted fabrication stage, a mask 460 is formed over GAA FET 605 and GAA FET 607 .

[0126] The mask 760 may be a dielectric material, an organic planarization material, or other mask material, and may be formed by depositing a blanket mask material on the GAA FET 603, the GAA FET 605, and the GAA FET 607. The mask material may be deposited on the respective S / D caps 752, on the respective gate spacers 654, on and around the respective nanostructure stacks 670, on the respective BDI 652, and / or on the respective STI regions. A portion of the mask material on the GAA FET 603 may then be removed to reform its gate opening 750.

[0127] The mask 760 may protect the GAA FET 605 and the GAA FET 607 from subsequent channel processing of the GAA FET 603 .

[0128] Fig.18 Depicted is a cross-sectional view of a semiconductor device 600 shown after exemplary fabrication operations according to one or more embodiments. In the depicted fabrication stage, the nanostructure stack 670 of the GAA FET 603 is processed by selectively removing sacrificial nanolayer portions 680, 684, 688, and 692 and by trimming the nanolayer channels 682, 686, and 690 therein.

[0129] The nanostructure stack 670 of the GAA FET 603 may be processed using various techniques to selectively remove the sacrificial nanolayer portions 680, 684, 688, and 692. For example, the gate opening 750 may laterally or otherwise expose the nanostructure stack 670 of the GAA FET 603, while the mask 760 protects the corresponding GAA FET 605 and GAA FET 607 below. Subsequently, the exposed sacrificial nanolayer portions 680, 684, 688, and 692 may be removed to expose the associated nanolayer channels 682, 686, and 690. As depicted, the upper, lower, and side surfaces of the nanolayer channels 682, 686, and 690 may be exposed inside or within the adjacent inner spacer 696.

[0130] Nanolayer channels 682, 686, and 690 may be trimmed, for example, by etching or other selective removal processes. Nanolayer channels 682, 686, and 690 may be trimmed so that they are coated, grown, deposited, or otherwise formed. Fig.19 Before encapsulating channels 782, 786, and 790 as depicted in FIG. 1 , vertical space above / below nanolayer channels 682, 686, and 690 is increased to prevent undesired merging of adjacent nanolayer channels. Trimming of nanolayer channels 682, 686, and 690 can be accomplished using a vapor phase etching process, controlled etching cycles, and the like.

[0131] Fig.19 A cross-sectional view of semiconductor device 600 is depicted after exemplary fabrication operations according to one or more embodiments. In the depicted fabrication stage, nanostructure stack 670 of GAA FET 603 is further processed by removing mask 760 and forming channel material on trimmed nanolayer channels 682, 686, and 690 to form capping channels 782, 786, and 790, respectively.

[0132] Conventional photolithography and etching processes may be used to remove mask 760 from n-type GAA FET 313, from GAA FET 603, and / or from GAA FET 607. Removal of mask 760 may reform gate opening 750 of GAA FET 603 and / or reform gate opening of GAA FET 607.

[0133] The cladding channels 782, 786, and 790 may be formed by epitaxially growing material from applicable surfaces of the trimmed nanolayer channels 682, 686, and 690 until a desired growth thickness or shape has been achieved. In a particular embodiment, as exemplarily depicted, the cladding channels 782, 786, and 790 may be formed by epitaxially growing SiGe from associated one or more surfaces of the trimmed nanolayer channels 682, 686, and 690. Alternatively, the cladding channels 782, 786, and 790 may be formed by depositing a second material on the trimmed nanolayer channels 682, 686, and 690 material.

[0134] In certain embodiments, the cladding channels 782, 786, and 790 may include peripheral portions of a second or different channel material relative to the inner core of the first channel material of the trimmed nanolayer channels 682, 686, and 690. For example, the cladding channels 782, 786, and 790 may each include SiGe surrounding the Si inner core of the trimmed nanolayer channels 682, 686, and 690. x In other embodiments, as depicted, after forming the cladding channels 782, 786, and 790, a thermal mixing process can react a second or different channel material with the first material of the inner core, which causes the second material to diffuse and the first material to be consumed. The thermal mixing process can produce a continuous material (e.g., SiGe x ) coated channels 782, 786 and 790, so that a specific second material percentage at one location of the coated channels 782, 786 and 790 is the same or substantially the same as the second material percentage at any different location of the coated channels 782, 786 and 790, respectively.

[0135] After forming the cladding channel 782, the associated channel of the GAA FET 603 may include a first portion of the nanolayer channel 782 vertically between vertically adjacent inner spacers 696 and in contact with the S / D 640, a second portion of the nanolayer channel 682 vertically between vertically adjacent inner spacers 696 and in contact with another S / D 640, and a cladding channel 482 in contact with the first and second portions of the nanolayer channel 382.

[0136] Similarly, after forming the cladding channel 786, the associated channel of the GAA FET 603 may include a first portion of the nanolayer channel 686 vertically between vertically adjacent inner spacers 696 and in contact with the S / D 640, a second portion of the nanolayer channel 686 vertically between vertically adjacent inner spacers 696 and in contact with another S / D 640, and the cladding channel 786 in contact with the first and second portions of the nanolayer channel 686.

[0137] Similarly, after forming the cladding channel 790, the associated channel of the GAA FET 603 may include a first portion of the nanolayer channel 690 vertically between vertically adjacent inner spacers 696 and in contact with the S / D 640, a second portion of the nanolayer channel 690 vertically between vertically adjacent inner spacers 696 and in contact with another S / D 640, and the cladding channel 790 in contact with the first and second portions of the nanolayer channel 690.

[0138] In some embodiments (eg, without thermal mixing, etc.), cladding channels 782 , 786 , and 790 may each include an inner portion extending and contacting each associated S / D 640 and a cladding portion of a second material surrounding or encircling the inner portion at least within gate opening 750 .

[0139] In a specific embodiment, the cladding channels 782, 786, and 790 of the GAA FET 603 may be made of SiGe having a first Ge% x The first Ge% may be a first Ge percentage sufficient to achieve a desired channel mobility of the GAA FET 603. In this embodiment, within the GAA FET 603, respective first and second portions of the nanolayer channels 682, 686, and 690 may be formed of different materials, such as Si.

[0140] Fig. 20 Depicted is a cross-sectional view of a semiconductor device 600 shown after exemplary fabrication operations in accordance with one or more embodiments. In the depicted fabrication stage, a mask 762 is formed over the GAA FET 603 and / or the GAA FET 607 .

[0141] The mask 762 may be a dielectric material, an organic planarization material, or a mask material, and may be formed by depositing a mask material over the GAA FET 603. The mask 762 material may be deposited on the GAA FET 603 S / D cap 752, the gate spacer 654, on and around the nanostructure stack 670, on the BDI 652, and / or on corresponding STI regions within the GAA FET 603. The mask 762 may be formed within the gate opening 750 of the GAA FET 603 and / or within the gate opening 750 of the GAA FET 607.

[0142] Fig.21Depicted is a cross-sectional view of a semiconductor device 600 shown after exemplary fabrication operations according to one or more embodiments. In the depicted fabrication stage, the nanostructure stack 670 of the GAA FET 605 is processed by selectively removing sacrificial nanolayer portions 680, 684, 688, and 692 and by trimming the nanolayer channels 682, 686, and 690 therein.

[0143] Various techniques may be utilized to process the nanostructure stack 670 of the GAA FET 605 to selectively remove the sacrificial nanolayer portions 680, 684, 688, and 692. For example, the gate opening 750 may laterally or otherwise expose the nanostructure stack 670 of the GAA FET 605 while the mask 762 protects the underlying corresponding GAA FET 603 and / or GAA FET 607. Subsequently, the exposed sacrificial nanolayer portions 680, 684, 688, and 692 may be removed to expose the associated nanolayer channels 682, 686, and 690 within the GAA FET 605. As depicted, the upper, lower, and side surfaces of the nanolayer channels 682, 686, and 690 may be exposed inside or within the adjacent inner spacer 696.

[0144] Nanolayer channels 682, 686, and 690 may be trimmed, for example, by etching or other selective removal processes. Nanolayer channels 682, 686, and 690 may be trimmed to form nanolayers such as nanoparticles that are coated, grown, deposited, or otherwise formed. Fig. 22 Before encapsulating channels 783, 787, and 791 as depicted in FIG. 1 , vertical space above / below nanolayer channels 682, 686, and 690 is increased to prevent undesired merging of adjacent nanolayer channels. Trimming of nanolayer channels 682, 686, and 690 can be accomplished using a vapor phase etching process, controlled etching cycles, and the like.

[0145] Fig. 22 A cross-sectional view of semiconductor device 600 is depicted after exemplary manufacturing operations according to one or more embodiments. In the depicted manufacturing stage, mask 762 is removed and nanostructure stack 670 of GAA FET 605 is further processed by forming channel material on trimmed nanolayer channels 682, 686, and 690 to form capping channels 783, 787, and 791, respectively.

[0146] Conventional photolithography and etching processes may be used to remove the mask 762 from the GAA FET 602 and / or the GAA FET 607. Removal of the mask 762 may reform the gate opening 750 of the GAA FET 603 and / or reform the gate opening of the GAA FET 607.

[0147] The cladding channels 783, 787, and 791 may be formed by epitaxially growing material from applicable surfaces of the trimmed nanolayer channels 682, 686, and 690 until a desired growth thickness or shape has been achieved. In a particular embodiment, as exemplarily depicted, the cladding channels 783, 787, and 791 may be formed by epitaxially growing SiGe from associated one or more surfaces of the trimmed nanolayer channels 682, 686, and 690. Alternatively, the cladding channels 783, 787, and 791 may be formed by depositing a second material on the trimmed nanolayer channels 682, 686, and 690 material.

[0148] In certain embodiments, the cladding channels 783, 787, and 791 may include peripheral portions of a second or different channel material relative to the inner core of the first channel material of the trimmed nanolayer channels 682, 686, and 690. For example, the cladding channels 783, 787, and 791 may each include SiGe surrounding the Si inner core of the trimmed nanolayer channels 682, 686, and 690. y In other embodiments, as depicted, after forming the cladding channels 783, 787, and 791, a thermal mixing process can react a second or different channel material with the first material of the inner core, which causes the second material to diffuse and the first material to be consumed. The thermal mixing process can produce a continuous material (e.g., SiGe y ) coated channels 783, 787 and 791, so that a specific second material percentage at one position of the coated channels 783, 787 and 791 is the same or substantially the same as the second material percentage at any different position of the coated channels 783, 787 and 791, respectively.

[0149] After forming the cladding channel 783, the associated channel of the GAA FET 605 may include a first portion of the nanolayer channel 682 vertically between vertically adjacent inner spacers 696 and in contact with the S / D 640, a second portion of the nanolayer channel 682 vertically between vertically adjacent inner spacers 696 and in contact with another S / D 640, and the cladding channel 783 in contact with the first and second portions of the nanolayer channel 682.

[0150] Similarly, after forming the cladding channel 787, the associated channel of the GAA FET 605 may include a first portion of the nanolayer channel 686 vertically between vertically adjacent inner spacers 696 and in contact with the S / D 640, a second portion of the nanolayer channel 686 vertically between vertically adjacent inner spacers 696 and in contact with another S / D 640, and the cladding channel 787 in contact with the first and second portions of the nanolayer channel 686.

[0151] Similarly, after forming the cladding channel 791, the associated channel of the GAA FET 605 may include a first portion of the nanolayer channel 690 vertically between vertically adjacent inner spacers 696 and in contact with the S / D 640, a second portion of the nanolayer channel 690 vertically between vertically adjacent inner spacers 696 and in contact with another S / D 640, and the cladding channel 791 in contact with the first and second portions of the nanolayer channel 690.

[0152] In some embodiments (eg, without thermal mixing, etc.), cladding channels 783 , 787 , and 791 can each include an inner portion extending and contacting each associated S / D 640 and a cladding portion of a second material surrounding or encircling the inner portion at least within gate opening 750 .

[0153] In a particular embodiment, the cladding channels 783, 787, and 791 of the GAA FET 605 may be made of SiGe having a second Ge% y The second Ge% is sufficient to achieve the desired channel mobility of the GAA FET 605 and is relatively high relative to the SiGe having the first Ge% of the encapsulating channels 782, 786 and 790 of the GAA FET 603. x In this embodiment, in the GAAFET 605, the respective first and second portions of the nanolayer channels 682, 686, and 690 may be formed of different materials, such as Si.

[0154] In some embodiments, a liner such as an oxide liner can be formed around the cladding channels 782, 786 and 790 of the GAA FET 603 and / or around the nanolayer channels 682, 686 and 690 of the GAAFET 607 to protect these channels from epitaxial growth therefrom before forming the cladding channels 783, 787 and 791 of the GAAFET 605.

[0155] Fig.23 Depicted is a cross-sectional view of a semiconductor device 600 shown after exemplary fabrication operations according to one or more embodiments. In the depicted fabrication stage, a replacement gate structure 489 is formed within the gate opening 450 around the respective nanolayer channels of the GAA FETs 603 , 605 , and / or 607 .

[0156] The respective nanostructure stack 370 of the GAA FET 607 can be processed by selectively removing the sacrificial nanolayer portions 680, 684, 688, and 692 therein. As depicted, respective upper and lower surfaces and side surfaces of the nanolayer channels 682, 686, and 690 can be exposed inside or within adjacent inner spacers 696 associated with opposite sides of the respective nanostructure stack 670 of the GAA FET 607.

[0157] The replacement gate structure 789 may include a gate dielectric 788 and a gate conductor 792. The gate dielectric 788 may include any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, high-k material, or any combination of these materials. The gate dielectric 788 may be formed by any suitable deposition process, etc. In some embodiments, the gate dielectric 788 has a thickness ranging from 1 nm to 5 nm, but lesser thicknesses and greater thicknesses are also contemplated.

[0158] The gate conductor 792 may include any suitable conductive material, including but not limited to doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au), conductive metal compound materials (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide (CoSi), nickel silicide (NiSi)), transition metal aluminides (e.g., Ti3Al, ZrAl), TaC, TaMgC, carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials.

[0159] The gate conductor 792 may also include dopants introduced during or after deposition to be suitable for inclusion in the GAAFETs 603, 605, and / or 607, respectively. In some embodiments, the gate conductor 792 may further include a work function setting layer (not shown) between the gate dielectric 788 and the gate conductor 792. The work function setting layer may be a work function metal (WFM). The gate conductor 792 and the WFM may be formed by any suitable process or any suitable combination of processes, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, etc.

[0160] In the GAA FET 603, a replacement gate structure 689 may be formed by initially forming a gate dielectric layer within the gate opening 750 around the cladding channels 782, 786, and 790, on the sidewalls of the inner spacer 696, on the gate spacer 654, on the top surface of the BDI 652, and on the STI regions. In the GAA FET 605, a gate dielectric layer may be formed within the gate opening 750 around the cladding channels 783, 787, and 791, on the sidewalls of the inner spacer 696, on the gate spacer 654, on the top surface of the BDI 652, and on the STI regions. Similarly, within the GAA FET 607 , a gate dielectric layer may be formed within the gate opening 750 around the channels 682 , 686 , and 690 , on the sidewalls of the inner spacer 696 , on the gate spacer 654 , on the top surface of the BDI 652 , and on the STI regions.

[0161] The replacement gate structure 489 within the GAA FETs 603, 605, and / or 607 may also be formed by subsequently forming a gate conductor layer on the gate dielectric layer. For clarity, the replacement gate structure 489 may be a wraparound gate structure, a gate-all-around structure, because the gate conductor wraps around the enclosing channels 782, 786, and 790, wraps around the enclosing channels 783, 787, and 791, and / or wraps around the channels 682, 686, and 690, respectively.

[0162] Conventional photolithography and etching processes can be used to pattern the gate conductor layer and the gate dielectric layer to remove undesirable portions and retain desired portions, respectively. The remaining desired portions of the gate conductor layer and the gate dielectric layer can form the gate dielectric layer 790 and the gate conductor 792 of the replacement gate structure 689. The etching process or another subtractive removal technique can remove the undesirable portions of the replacement gate structure 689 so that the top surface of the replacement gate structure 689 is coplanar with the top surface of the semiconductor device 600.

[0163] In some embodiments, the gate conductor 792 can be recessed below the top surface of the semiconductor device 600 , and a dielectric gate cap (not shown) can be formed on the recessed gate conductor 792 .

[0164] For clarity, the semiconductor device 600 includes heterogeneous channels in the same region, for example, a p-type region. The first GAA FET includes a plurality of first channels of a first channel material (eg, SiGe x The second GAA FET includes a plurality of second channels of a second channel material (eg, SiGe yThe third GAA FET includes multiple third channels of a third channel material (e.g., Si channels 682, 686, and 690). Similar region GAAFETs with heterogeneous channels can have different channel structures, such as relatively different channel lengths. For example, GAA FET 603 can be a short channel GAA FET, GAA FET 603 can have an intermediate channel length channel or an intermediate channel GAA FET, and GAA FET 607 can be a long channel GAA FET.

[0165] Fig.24 800 of a method for manufacturing a semiconductor device 600 according to one or more embodiments of the present disclosure is shown. Figures 1 to 8 and / or Figures 16 to 23 One or more of the diagrams and descriptions of the depicted manufacturing operations of method 800. The method 800 described herein is exemplary. Many variations of the drawings or operations described therein may exist without departing from the spirit of the embodiments. For example, the operations may be performed in a different order, or operations may be added, deleted, or modified.

[0166] At block 802, method 800 may include removing a sacrificial gate of GAA FET 603, GAA FET 605, and / or GAA FET 607. At block 804, method 800 may include masking GAA FET 605 and / or GAA FET 607. At block 806, method 800 may include exposing channels 682, 686, and 690 of a first material (e.g., Si, etc.) within GAA FET 603 by removing sacrificial nanolayer portions 680, 684, 688, and 692, thereby forming a gate trench 450 therein.

[0167] At block 808, method 800 may include thinning the thickness of channels 682, 686, and 690 within GAA FET 603. At block 810, method 800 may include removing the mask of GAA FET 605 and / or GAA FET 607 and depositing a second material (e.g., SiGe) at a first concentration on channels 682, 686, and 690 within GAA FET 603. x ) to form encapsulating channels 782, 786 and 790.

[0168] At block 812, method 800 may include masking GAA FET 603 and / or GAA FET 607. At block 814, method 800 may include exposing channels 682, 686, and 690 of the first material within GAA FET 605 by removing sacrificial nanolayer portions 680, 684, 688, and 692 therefrom.

[0169] At block 816, method 800 may include thinning the thickness of channels 682, 686, and 690 within GAA FET 605. At block 818, method 800 may include removing the mask of GAA FET 603 and / or GAA FET 607 and depositing a second material (e.g., SiGe) at a second concentration on channels 682, 686, and 690 within GAA FET 605. y ) to form the cladding channels 783, 787 and 791.

[0170] At block 822 , method 800 may include forming a replacement gate structure 689 around cladding channels 782 , 786 , and 790 within GAA FET 603 , forming a replacement gate structure 689 around cladding channels 783 , 787 , and 791 within GAA FET 605 , and / or forming a replacement gate structure 689 around channels 682 , 686 , and 690 within GAA FET 607 .

[0171] Figure 25 to Figure 27 The semiconductor device 900 is depicted after various manufacturing operations. Fig.26 The semiconductor device 900 depicted in the drawings includes a GAA FET 903 including nanolayer channels 1082, 1086 and 1090 of a first channel material in a specific region type (e.g., a p-type region), a GAA FET 905 including nanolayer channels 1081, 1085 and 1089 of a second channel material in the same specific region type, and / or a GAA FET 907 including nanolayer channels 1083, 1087 and 1091 of a third channel material in the same specific region type. Fig. 27 A semiconductor device 900 having a long channel is depicted in FIG.

[0172] Semiconductor device 900 may further include substrate 902, BDI 952, S / D 940, S / D cap 1052, replacement gate structure 989, gate spacer 954, and / or interspacer 996. Replacement gate structure 989 may include gate dielectric 1088 and gate conductor 1092.

[0173] For clarity, the corresponding end surface of each nanolayer channel 1082, 1086, and 1090 can contact S / D 940. For example, as depicted, the corresponding left end surface of each nanolayer channel 1082, 1086, and 1090 can contact the source, and the corresponding right end surface of each nanolayer channel 1082, 1086, and 1090 can contact the drain. Similarly, the corresponding left end surface of each nanolayer channel 1081, 1085, and 1089 can contact the source, and the corresponding right end surface of each nanolayer channel 1081, 1085, and 1089 can contact the drain. Likewise, the corresponding left end surface of each nanolayer channel 1083, 1087, and 1091 can contact the source, and the corresponding right end surface of each nanolayer channel 1083, 1087, and 1091 can contact the drain.

[0174] For the sake of clarity, Fig.26 The semiconductor device 900 shown in FIG. 1 may be formed by Fig.25 The substrate 902 and nanolayer stack 925 structures exemplarily shown in FIG. 1 are formed, and may also be formed using similar manufacturing techniques described with reference to the semiconductor device 100 .

[0175] Fig.25 Depicted is a cross-sectional view of a semiconductor device 100 after initial manufacturing operations according to an embodiment of the present disclosure. In this manufacturing stage, one or more nanolayer stacks 925 are formed on a substrate 902. Additionally, in this manufacturing stage, shallow trench isolation (STI) regions may be formed on the substrate 902 adjacent to the nanolayer stacks 925.

[0176] Non-limiting examples of suitable materials for the substrate 902 include Si (silicon), strained Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon germanium), SiGe:C (silicon-germanium-carbon), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof. Other non-limiting examples of semiconductor materials include III-V materials, such as indium phosphide (InP), gallium arsenide (GaAs), aluminum arsenide (AlAs), or any combination thereof. The III-V group material may include at least one "Group III element", such as aluminum (Al), boron (B), gallium (Ga), indium (In), and at least one "Group V element", such as nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb). The substrate 102 may be a bulk semiconductor material including Si.

[0177] A bottom sacrificial layer 908 may be formed on the substrate 902. Subsequently, alternating nanostructure layers may be formed on the bottom sacrificial layer 908. The bottom sacrificial layer 908 may be initially formed on the substrate 902. The bottom sacrificial layer 908 may include an epitaxial SiGe layer having a high Ge% ranging from 90% to 99%. In some embodiments of the present disclosure, the bottom sacrificial layer 908 is SiGe having a Ge percentage that is sufficiently different from the Ge percentage in other layers in the nanolayer stack 925 so that the bottom sacrificial layer 908 may be selectively removed without also removing other, e.g., SiGe layers in the nanolayer stack 925. The bottom sacrificial layer 908 may have a thickness, e.g., from about 4 to about 15 nm.

[0178] Nanolayer stack 925 may include a portion formed by a series of alternating sacrificial nanolayers (e.g., SiGe sacrificial nanolayers) and heterogeneous nanolayers (e.g., SiGe and Si heterogeneous nanolayers). The sacrificial SiGe nanolayer may have a lower Ge% ranging from 70% to 80% relative to the Ge% of the bottom sacrificial layer 908.

[0179] The sacrificial portions 910, 914, 918, and 922 of each nanolayer stack 125 may be formed by an associated sacrificial nanolayer, and the heterogeneous nanostructure portions 930, 932, and 934 of each nanolayer stack 925 may be formed by an associated heterogeneous nanolayer.

[0180] Semiconductor device 900 may include GAA FET region 903, GAA FET region 905, and / or GAA FET region 907. GAA FET region 903, GAA FET region 905, and / or GAA FET region 907 are generally the same region type (e.g., all are p-type regions), but may be at different, the same, or similar locations within semiconductor device 900.

[0181] The heterogeneous nanostructure portions 930, 932, and 934 generally include different or heterogeneous materials within different GAA FET regions 903, GAA FET regions 905, and / or GAA FET regions 907. For example, the heterogeneous nanostructure portion 930 includes a first nanostructure portion 912 (e.g., SiGe with a Ge% concentration of 40% to 60%) within the GAA FET region 903, a second nanostructure portion 911 (e.g., SiGe with a Ge% concentration of 10% to 30%) within the GAA FET region 905, and / or a third nanostructure portion 913 (e.g., Si) within the GAA FET region 907. Similarly, the heterogeneous nanostructure portion 932 includes a first nanostructure portion 916 (e.g., SiGe with a Ge% concentration of 40% to 60%) within the GAA FET region 903, a second nanostructure portion 915 (e.g., SiGe with a Ge% concentration of 10% to 30%) within the GAA FET region 905, and / or a third nanostructure portion 917 (e.g., Si) within the GAA FET region 907. Likewise, the heterogeneous nanostructure portion 934 includes a first nanostructure portion 920 (e.g., SiGe with a Ge% concentration of 40% to 60%) within the GAA FET region 903, a second nanostructure portion 919 (e.g., SiGe with a Ge% concentration of 10% to 30%) within the GAA FET region 905, and / or a third nanostructure portion 921 (e.g., Si) within the GAA FET region 907.

[0182] According to an embodiment of the present disclosure, the bottom sacrificial layer 908 may be epitaxially grown from the substrate 902, the sacrificial nanolayer forming the sacrificial portion 910 may be epitaxially grown therefrom, and one or more GAA FET regions 903, GAA FET regions 905, and / or GAA FET regions 907 may be appropriately masked and sequentially exposed to form a heterogeneous nanolayer in which the heterogeneous nanostructure portion 930 is formed. Subsequently, the sacrificial nanolayer in which the sacrificial portion 914 may be formed, the one or more GAA FET regions 903, GAA FET regions 905, and / or GAA FET regions 907 may be appropriately masked and sequentially exposed to form a heterogeneous nanolayer in which the heterogeneous nanostructure portion 932 is formed. Subsequently, the sacrificial nanolayer in which the sacrificial portion 918 may be formed, the one or more GAA FET regions 903, GAA FET regions 905, and / or GAA FET regions 907 may be appropriately masked and sequentially exposed to form a heterogeneous nanolayer in which the heterogeneous nanostructure portion 934 is formed. Subsequently, a sacrificial nanolayer in which the sacrificial portion 934 is formed may be formed.

[0183] Then, the various layers can be patterned by removing various undesirable portions or sections of the above layers while retaining various desired portions. The removal of the undesirable portions of the bottom sacrificial layer and the alternating sacrificial nanolayers and heterogeneous nanolayers can be achieved using, for example, conventional photolithography and etching processes. Such removal of undesirable portions can further remove undesirable portions of the substrate 902. The bottom sacrificial layer 908 and the desired portions of the alternating sacrificial nanolayers and heterogeneous nanolayers can be retained to form one or more nanolayer stacks 925.

[0184] Subsequently, STI regions may be formed over the substrate 902 and adjacent to the one or more nanolayer stacks 925. The top surface of the one or more STI regions may be coplanar with the bottom surface of the bottom sacrificial portion 908 of the one or more nanolayer stacks 925. The STI regions may be formed by depositing an STI dielectric material on the substrate 902 and adjacent to the nanolayer stacks 925, followed by etching back, recessing, etc. the STI dielectric material. The STI regions may electrically isolate components or features of adjacent GAA FETs, etc.

[0185] For the sake of clarity, Fig.26 and Fig. 27 The semiconductor device 900 shown in FIG. 1 may be formed by a substrate 902 and a nanolayer stack 925 structure, such as Fig.25 exemplarily shown in FIG. 1 , and by further utilizing reference semiconductor device 100 and Figure 2-8 Thus, it is possible to manufacture Fig.26 As shown in Fig. 27 The semiconductor device 900 shown in FIG. 1 generally includes heterogeneous channels in the same region (e.g., a p-type region), which may or may not be at the same location in the semiconductor device 900. The semiconductor device 900 includes a plurality of first channels having a first channel material (e.g., SiGe x Nanolayer channels 1082, 1086, and 1090 each have a first GAA FET having a first Ge% or concentration. Semiconductor device 900 may include a plurality of second channels having a second channel material (eg, SiGe y A second GAA FET may include channels 1081, 1085, and 1089, each having a second Ge% or concentration different from the first Ge% or concentration, or may include a third GAA FET having multiple third channels of a third channel material (e.g., Si channels 1083, 1087, and 1091). Similar region GAA FETs with heterogeneous channels may have different channel structures, such as relatively different channel lengths.

[0186] For clarity, in one embodiment, the semiconductor device 900 may include a SiGe x or SiGe y The short channel GAA FET 903 covering the channels 1082, 1086, 1090 and / or having SiGe x or SiGe y The short channel GAA FET 905 with wrap channels 1081, 1085, 1089 and the long channel GAA FET 907 with SE nanolayer channels 1083, 1087, 1091 are all in the same p-type region, but not necessarily in the same p-type region location.

[0187] Fig.28 A flow chart of a method 1100 for manufacturing a semiconductor device according to one or more embodiments of the present disclosure is shown. The illustrated manufacturing operations of the method 1100 are shown and described above with reference to one or more block diagrams of the accompanying drawings. The method 1100 described herein is exemplary. Many variations of the diagrams or operations described therein may exist without departing from the spirit of the embodiments. For example, the operations may be performed in a different order, or operations may be added, deleted, or modified.

[0188] At block 1102, the method 1100 includes forming a first GAA FET having a plurality of first channels of a first channel material. At block 1104, the method 1100 also includes forming a second GAA FET having a plurality of second channels of a second channel material and / or forming a third GAA FET having a plurality of third channels of a third channel material (block 1106). For example, forming a SiGe x The first p-type GAA FET with SiGe y The second p-type GAA FET (i.e., SiGe x Relative to SiGe y Intentionally or predetermined different concentrations or %Ge), and / or forming a third p-type GAA FET with a Si channel.

[0189] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but it is not intended to be exhaustive or limited to the described embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to existing technologies on the market, or to enable other persons of ordinary skill in the art to understand the embodiments described herein.

Claims

1. A semiconductor device, comprising: a first gate-all-around field effect transistor (GAA FET) in the first region of the first type, the first GAAFET comprising a plurality of first nanostructure channels of a first channel material; as well as A second GAA FET in a second region of the first type, the second GAA FET comprising a plurality of second nanostructure channels of a second channel material, the second channel material being different from the first channel material.

2. The semiconductor device according to claim 1, further comprising: A third GAA FET within a third region of the first type, the third GAA FET comprising a plurality of third nanostructure channels of a third channel material, the third channel material being different from the first channel material and different from the second channel material. 3 . The semiconductor device according to claim 2 , wherein the first region is a p-type region, and wherein the second region is a p-type region. The semiconductor device according to claim 3 , wherein the third region is a p-type region.

5. The semiconductor device according to claim 3, wherein the first channel material is silicon germanium (SiGe) having a first Ge percentage. x ), and wherein the second channel material is silicon germanium (SiGe y ).

6. The semiconductor device according to claim 4, wherein the first channel material is silicon germanium (SiGe) having a first Ge percentage. x ), wherein the second channel material is silicon germanium (SiGe y ), and wherein the third channel material is silicon (Si).

7. The semiconductor device of any one of the preceding claims, wherein the plurality of second nanostructure channels each have a longer channel length relative to the plurality of first nanostructure channels. 8 . The semiconductor device of claim 2 , wherein each of the plurality of third nanostructure channels has a longer channel length relative to the plurality of first nanostructure channels. 9 . The semiconductor device of claim 6 , wherein the first GAA FET further comprises a first portion of a nanolayer channel between each of the plurality of first nanostructure channels and the first source and drain. 10 . The semiconductor device of claim 9 , wherein the second GAA FET further comprises a second portion of the nanolayer channel between each of the plurality of second nanostructure channels and the second source and drain.

11. The semiconductor device according to claim 10, wherein: Each of the plurality of third nanostructure channels directly contacts the third source and drain.

12. A semiconductor device comprising: a first gate-all-around field effect transistor (GAA FET) in the first p-type region, the first GAA FET comprising a plurality of silicon germanium (SiGe) nanostructure channels; as well as A second GAA FET in the second p-type region includes a plurality of silicon nanostructure channels. 13 . The semiconductor device of claim 12 , wherein each of the plurality of silicon nanostructure channels has a same channel length relative to the plurality of SiGe nanostructure channels. 14 . The semiconductor device according to claim 12 , wherein each of the plurality of silicon nanostructure channels has a longer channel length relative to the plurality of SiGe nanostructure channels.

15. The semiconductor device according to any one of claims 12 to 14, wherein: The first GAA FET also includes a Si portion of a nanolayer channel between each of the plurality of SiGe nanostructure channels and the first source and drain. 16 . The semiconductor device according to claim 13 , wherein each of the plurality of Si nanostructure channels directly contacts the second source and drain. 17 . The semiconductor device according to claim 12 , further comprising a third GAA FET in the n-type region, the third GAA FET comprising one or more silicon nanostructure channels. 18 . The semiconductor device of claim 17 , wherein the one or more silicon nanostructure channels each have the same channel length relative to the plurality of SiGe nanostructure channels.

19. The semiconductor device of claim 17, wherein the one or more silicon nanostructure channels each have a longer channel length relative to the plurality of SiGe nanostructure channels.

20. A method for manufacturing a semiconductor device, comprising: forming a first gate all-around field effect transistor (GAA FET) in a first region of the first type, the first GAA FET comprising a plurality of first nanostructure channels of a first channel material; as well as A second GAA FET is formed within the second region of the first type, the second GAA FET comprising a plurality of second nanostructure channels of a second channel material.

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