Ultra-low power consumption band-gap reference circuit with starting circuit suitable for high-temperature condition

Abstract

The invention discloses an ultra-low-power-consumption band-gap reference circuit with a starting circuit suitable for a high-temperature condition. The ultra-low-power-consumption band-gap reference circuit comprises a control circuit module, a starting core circuit unit, an electric leakage compensation circuit unit and a band-gap reference circuit module. The control circuit module is used for establishing a starting identification signal based on the enable signal; the starting core circuit unit is used for providing starting temporary current for the band-gap reference circuit module according to the starting identification signal, so that the band-gap reference circuit module gets rid of a degenerate electricity state of zero current; the electric leakage compensation circuit unit is used for generating corresponding mirror leakage current and keeping the balance state of the band-gap reference circuit module when the starting core circuit unit has an electric leakage condition; the band-gap reference circuit module is used for generating and outputting a reference voltage based on an input power supply and a starting identification signal. According to the ultra-low power consumption band-gap reference circuit, the core circuit unit and the electric leakage compensation circuit unit are started to ensure that the ultra-low power consumption band-gap reference can be normally started at high temperature and keep good working performance.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an ultra-low power consumption bandgap reference circuit with a startup circuit suitable for high temperature conditions. Background Art

[0002] The bandgap reference source is a reference voltage source inside the chip. It can generate a stable voltage that is independent of temperature changes and voltage fluctuations. It is widely used in circuits such as ADC, DAC, and LDO to provide them with a reference voltage for reference comparison, thereby ensuring the high accuracy and stability of the overall circuit. In recent years, with the rise of wearable electronic devices, the static power consumption requirements of electronic systems have become increasingly higher. As a core component of electronic systems, the bandgap reference is also expected to ensure stability while consuming as little energy as possible, thereby extending the battery life of the device.

[0003] In a bandgap reference circuit, the circuit usually has two working states, the first is a normal working state, and the second is a state where the circuit has no current at all. For the second case, a startup circuit needs to be added to help the circuit get rid of the abnormal working state. The most common startup circuit is to get the circuit out of the no-current working state when the circuit is just started, and after the circuit has current and works normally, the startup circuit is usually turned off to reduce the power consumption of the circuit. In the prior art, the startup circuit usually forms a current sink through a MOS transistor and is connected to the output of the bandgap reference operational amplifier. The circuit is started by pulling down the output of the operational amplifier, injecting temporary current, and turning off the transistor after the operational amplifier is started. Ideally, the transistor will not affect the core circuit of the bandgap reference after being turned off, and the output voltage of the bandgap reference operational amplifier is determined by the core circuit of the bandgap itself. But in fact, MOS transistors will have picoampere-level leakage at high temperatures. This leakage current will hardly affect the performance of circuits with power consumption of microamperes or above at high temperatures. However, for circuits with power consumption of nanoamperes, it will cause serious mismatch of the operational amplifier and gain reduction, thereby affecting the output voltage or current of the bandgap reference, and further affecting the accuracy and stability of the bandgap reference source.

[0004] Therefore, it is urgent to design a startup circuit that can ensure that the ultra-low power bandgap reference starts normally and maintains performance under high temperature conditions to meet the working requirements of the bandgap reference circuit. Summary of the invention

[0005] The present invention provides an ultra-low power bandgap reference circuit with a startup circuit suitable for high temperature conditions, which is used to solve the technical problem that the startup circuit designed based on the existing bandgap reference circuit is difficult to ensure that the ultra-low power bandgap reference starts normally under high temperature conditions and maintains good working performance of the bandgap reference.

[0006] The present invention provides an ultra-low power consumption bandgap reference circuit with a startup circuit suitable for high temperature conditions, comprising: a control circuit module, a startup circuit module and a bandgap reference circuit module; the startup circuit module is composed of a startup core circuit unit and a leakage compensation circuit unit;

[0007] The control circuit module is connected to the startup circuit module, and is used to establish a startup identification signal for starting the core circuit unit based on the enable signal, and send the startup identification signal to the startup core circuit unit;

[0008] The startup core circuit unit is connected to the bandgap reference circuit module and is used to provide a startup temporary current to the bandgap reference circuit module according to the startup identification signal, so that the bandgap reference circuit module can get rid of the degenerate electrical state of zero current;

[0009] The leakage compensation circuit unit is connected to the startup circuit module and the bandgap reference circuit module respectively, and is used to generate a corresponding mirror leakage current when leakage occurs in the startup core circuit unit, thereby maintaining a balanced state of the bandgap reference circuit module;

[0010] The bandgap reference circuit module is used to generate and output a reference voltage based on an input power supply and the start-up identification signal.

[0011] Further, the startup core circuit unit is composed of a PMOS tube Mp2, an NMOS tube Mn1 and an NMOS tube Mn2;

[0012] The gate of the PMOS tube Mp2 is respectively connected to the gate of the NMOS tube Mn1 and the first end of the bandgap reference circuit module, the drain of the PMOS tube Mp2 is connected to the first end of the control circuit module, and the source of the PMOS tube Mp2 is respectively connected to the second end of the control circuit module, the drain of the NMOS tube Mn1 and the gate of the NMOS tube Mn2;

[0013] The gate of the NMOS tube Mn1 is connected to the first end of the bandgap reference circuit module, the drain of the NMOS tube Mn1 is respectively connected to the gate of the NMOS tube Mn2 and the second end of the control circuit module, and the source of the NMOS tube Mn1 is grounded;

[0014] The gate of the NMOS tube Mn2 is respectively connected to the second end of the control circuit module and the first end of the leakage compensation circuit unit, the drain of the NMOS tube Mn2 is connected to the second end of the bandgap reference circuit module, and the source of the NMOS tube Mn2 is grounded.

[0015] Furthermore, the leakage compensation circuit unit includes an NMOS tube Mn3 and a resistor Res2;

[0016] The drain of the NMOS tube Mn3 is connected to one end of the resistor Res2, and the source of the NMOS tube Mn3 is grounded;

[0017] The other end of the resistor Res2 is connected to the third end of the bandgap reference circuit module.

[0018] Furthermore, the first end of the leakage compensation circuit unit is specifically the gate of the NMOS tube Mn3.

[0019] Furthermore, the control circuit module is composed of an inverter INV1, an inverter INV2, a PMOS tube Mp1 and an NMOS tube Mn4;

[0020] The input end of the inverter INV1 is connected to the enable signal, and the output end of the inverter INV1 is connected to the input end of the inverter INV2;

[0021] The gate of the PMOS tube Mp1 is connected to the output end of the inverter INV1, and the drain of the PMOS tube Mp1 is connected to the input power supply;

[0022] The gate of the NMOS transistor Mn4 is connected to the output end of the inverter INV2, and the source of the NMOS transistor Mn4 is grounded.

[0023] Furthermore, the first end of the control circuit module is specifically the source of the PMOS transistor Mp1, and the second end of the control circuit module is specifically the drain of the NMOS transistor Mn4.

[0024] Furthermore, the bandgap reference circuit module is composed of a PMOS tube Mp3, a PMOS tube Mp4, a PMOS tube Mp5, a PMOS tube Mp6, a resistor Res1, a transistor Bipolar1, a transistor Bipolar2 and an amplifier AMP;

[0025] The gate of the PMOS tube Mp3 is respectively connected to the gate of the PMOS tube Mp4 and the first output terminal of the amplifier AMP, the drain of the PMOS tube Mp3 is connected to the input power supply, and the source of the PMOS tube Mp3 is connected to the drain of the PMOS tube Mp5;

[0026] The gate of the PMOS tube Mp4 is connected to the first output terminal of the amplifier AMP, the drain of the PMOS tube Mp4 is connected to the input power supply, and the source of the PMOS tube Mp4 is connected to the drain of the PMOS tube Mp6;

[0027] The gate of the PMOS tube Mp5 is connected to the gate of the PMOS tube Mp6, and the source of the PMOS tube Mp5 is connected to the positive input terminal of the amplifier AMP and one end of the resistor Res1 respectively;

[0028] The source of the PMOS tube Mp6 is respectively connected to the reverse input terminal of the amplifier AMP, the base and the collector of the transistor Bipolar2;

[0029] One end of the resistor Res1 is connected to the positive input end of the amplifier AMP, and the other end of the resistor Res1 is connected to the base and collector of the transistor Bipolar1 respectively;

[0030] The emitter of the transistor Bipolar1 is grounded;

[0031] The base of the transistor Bipolar2 is connected to its collector and the reverse input terminal of the amplifier AMP respectively, and the emitter of the transistor Bipolar2 is grounded.

[0032] Furthermore, the first end of the bandgap reference circuit module is specifically the inverting input end of the amplifier AMP, the second end of the bandgap reference circuit module is specifically the first output end of the amplifier AMP, and the third end of the bandgap reference circuit module is specifically the second output end of the amplifier AMP.

[0033] Further, the amplifier AMP is composed of NMOS tube Man1, NMOS tube Man2, NMOS tube Man3, NMOS tube Man4, NMOS tube Man5, NMOS tube Man6, NMOS tube Man7, PMOS tube Map1, PMOS tube Map2, PMOS tube Map3, PMOS tube Map4 and PMOS tube Map5;

[0034] Among them, the NMOS tube Man1 and the NMOS tube Man2 form an input pair of tubes of the amplifier AMP, the PMOS tube Map1 and the PMOS tube Map2 form a current mirror load of the amplifier AMP, and the NMOS tube Man4 and the PMOS tube Map5 form a mirror current branch of the current mirror load of the amplifier AMP.

[0035] Furthermore, the first output end of the amplifier AMP is specifically the output end of the mirror current branch of the current mirror load; the second output end of the amplifier AMP is specifically the output end of the current mirror load.

[0036] It can be seen from the above technical solutions that the present invention has the following advantages:

[0037] The present invention provides an ultra-low power consumption bandgap reference circuit with a startup circuit suitable for high temperature conditions, comprising: a control circuit module, a startup circuit module and a bandgap reference circuit module; the startup circuit module is composed of a startup core circuit unit and a leakage compensation circuit unit;

[0038] The control circuit module is connected to the startup circuit module, and is used to establish a startup identification signal of the startup core circuit unit based on the enable signal, and send the startup identification signal to the startup core circuit unit; the startup core circuit unit is connected to the bandgap reference circuit module, and is used to provide a startup temporary current to the bandgap reference circuit module according to the startup identification signal, so that the bandgap reference circuit module can get rid of the degenerate electrical state of zero current; the leakage compensation circuit unit is respectively connected to the startup circuit module and the bandgap reference circuit module, and is used to generate a corresponding mirror leakage current when there is leakage in the startup core circuit unit, so as to maintain the balanced state of the bandgap reference circuit module; the bandgap reference circuit module is used to generate and output a reference voltage based on an input power supply and a startup identification signal.

[0039] In the present invention, a temporary current is provided to the bandgap reference circuit by starting the core circuit unit to avoid the bandgap reference circuit from falling into a deadlock state. At the same time, when leakage occurs in the starting core circuit unit, the leakage compensation circuit unit provides a mirror leakage current to the bandgap reference circuit module, so that the two output branches of the reference bandgap circuit module leak the same current at the same time, so that the reference bandgap circuit module is still in a balanced working state, thereby ensuring that the ultra-low power consumption bandgap reference can be normally started at high temperature and maintain good working performance, thereby solving the technical problem that the existing starting circuit based on the bandgap reference circuit design is difficult to ensure that the ultra-low power consumption bandgap reference is normally started under high temperature conditions and maintain good working performance of the bandgap reference. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0041] Figure 1 A schematic diagram of module connections of an ultra-low power bandgap reference circuit with a startup circuit suitable for high temperature conditions provided in the present application;

[0042] Figure 2 A specific circuit connection diagram of a bandgap reference circuit with an ultra-low power consumption and a startup circuit suitable for high temperature conditions provided by the present application;

[0043] Figure 3The startup circuit and ultra-low power consumption bandgap reference circuit diagram provided in this application without considering the leakage of MOS tube;

[0044] Figure 4 A circuit diagram of an amplifier AMP of a bandgap reference circuit module provided in this application. DETAILED DESCRIPTION

[0045] The embodiment of the present invention provides an ultra-low power bandgap reference circuit with a startup circuit suitable for high temperature conditions, which is used to solve the technical problem that the startup circuit designed based on the existing bandgap reference circuit is difficult to ensure that the ultra-low power bandgap reference starts normally under high temperature conditions and maintains good working performance of the bandgap reference.

[0046] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0048] Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0049] See also Figure 1-Figure 4 , an embodiment of an ultra-low power consumption bandgap reference circuit with a startup circuit suitable for high temperature conditions provided by the present application comprises: a control circuit module, a startup circuit module and a bandgap reference circuit module; the startup circuit module is composed of a startup core circuit unit and a leakage compensation circuit (leakage elimination circuit) unit;

[0050] The control circuit module is connected to the start-up circuit module, and is used to establish a start-up identification signal for starting the core circuit unit based on the enable signal Ven, and send the start-up identification signal to the start-up core circuit unit;

[0051] The startup core circuit unit is connected to the bandgap reference circuit module and is used to provide a startup temporary current to the bandgap reference circuit module according to the startup identification signal, so that the bandgap reference circuit module can get rid of the degenerate electrical state of zero current;

[0052] The leakage compensation circuit unit is connected to the startup circuit module and the bandgap reference circuit module respectively, and is used to generate a corresponding mirror leakage current when leakage occurs in the startup core circuit unit, thereby maintaining a balanced state of the bandgap reference circuit module;

[0053] The bandgap reference circuit module is used to generate and output a reference voltage based on an input power supply voltage Vdd and a start-up identification signal.

[0054] Specifically, when the enable signal Ven is low, the start identification signal is a non-start signal, and the start core circuit unit will not provide a temporary start current to the bandgap reference circuit module. At this time, the bandgap reference circuit module is in a non-working state; and when the enable signal is high, the start identification signal is a start signal, and the start core circuit unit will provide a temporary start current to the bandgap reference circuit module, so that the bandgap reference circuit module can get rid of the degenerate electrical state of zero current. At this time, the bandgap reference circuit module is in a working state, thereby outputting a reference voltage;

[0055] When the bandgap reference circuit module is working, the startup core circuit unit will extract a little current from the bandgap reference circuit module to form a leakage current. Under high temperature conditions, the leakage current will seriously affect the performance of the bandgap reference. The present invention sets a leakage compensation circuit unit between the startup core circuit unit and the bandgap reference circuit module to generate a corresponding mirror leakage current, so that the bandgap reference circuit module can remain in a balanced state and will not cause an imbalance in its operation, thereby ensuring that the bandgap reference circuit module is still in a good working state and ensuring the working performance of the bandgap reference circuit module under high temperature conditions.

[0056] See also Figure 1 , Figure 2 and Figure 4 The following further describes the specific circuit structure of the bandgap reference circuit with ultra-low power consumption and startup circuit provided by the present invention.

[0057] The control circuit module is composed of an inverter INV1, an inverter INV2, a PMOS tube Mp1 and an NMOS tube Mn4; the input end of the inverter INV1 is connected to an enable signal, the output end of the inverter INV1 is connected to the input end of the inverter INV2; the gate of the PMOS tube Mp1 is connected to the output end of the inverter INV1, and the drain of the PMOS tube Mp1 is connected to the input power supply Vdd; the gate of the NMOS tube Mn4 is connected to the output end of the inverter INV2, and the source of the NMOS tube Mn4 is grounded. The first end of the control circuit module is specifically the source of the PMOS tube Mp1, and the second end of the control circuit module is specifically the drain of the NMOS tube Mn4.

[0058] It can be understood that when the enable signal Ven is low, the output signal Ven_B of the inverter INV1 is high, and the output signal Ven_S of the inverter INV2 is low, thereby establishing a start signal; conversely, when the enable signal Ven is high, the output signal Ven_B of the inverter INV1 is low, and the output signal Ven_S of the inverter INV2 is high, thereby establishing a non-start signal, and finally the control circuit module transmits a start identification signal to the start core circuit unit through Mp1 and Mn4 according to the enable signal.

[0059] Furthermore, the startup core circuit unit is composed of a PMOS tube Mp2, an NMOS tube Mn1 and an NMOS tube Mn2; the gate of the PMOS tube Mp2 is respectively connected to the gate of the NMOS tube Mn1 and the first end of the bandgap reference circuit module, the drain of the PMOS tube Mp2 is connected to the first end of the control circuit module, and the source of the PMOS tube Mp2 is respectively connected to the second end of the control circuit module, the drain of the NMOS tube Mn1 and the gate of the NMOS tube Mn2; the gate of the NMOS tube Mn1 is connected to the first end of the bandgap reference circuit module, the drain of the NMOS tube Mn1 is respectively connected to the gate of the NMOS tube Mn2 and the second end of the control circuit module, and the source of the NMOS tube Mn1 is grounded; the gate of the NMOS tube Mn2 is connected to the second end of the control circuit module, the drain of the NMOS tube Mn2 is connected to the second end of the bandgap reference circuit module, and the source of the NMOS tube Mn2 is grounded.

[0060] The startup core circuit unit adjusts the working state of the transistor in the startup core circuit unit according to the startup identification signal output by the first end and the second end of the control circuit module; wherein, when the startup identification signal is a non-startup signal, the transistors in the startup core circuit unit are all in a closed state; and when the startup identification signal is a startup signal, the transistor Mn2 in the startup core circuit unit is turned on, thereby providing a temporary current to the second end of the bandgap reference circuit module, so that the bandgap reference circuit module escapes from the degenerate point where the current is zero.

[0061] Furthermore, the bandgap reference circuit module is composed of a PMOS tube Mp3, a PMOS tube Mp4, a PMOS tube Mp5, a PMOS tube Mp6, a resistor Res1, a transistor Bipolar1, a transistor Bipolar2 and an amplifier AMP;

[0062] Among them, the gate of the PMOS tube Mp3 is respectively connected to the gate of the PMOS tube Mp4 and the first output terminal of the amplifier AMP, the drain of the PMOS tube Mp3 is connected to the input power supply Vdd, and the source of the PMOS tube Mp3 is connected to the drain of the PMOS tube Mp5; the gate of the PMOS tube Mp4 is connected to the first output terminal of the amplifier AMP, the drain of the PMOS tube Mp4 is connected to the input power supply Vdd, and the source of the PMOS tube Mp4 is connected to the drain of the PMOS tube Mp6; the gate of the PMOS tube Mp5 is connected to the gate of the PMOS tube Mp6, and the source of the PMOS tube Mp5 is connected to the gate of the PMOS tube Mp6. The electrodes are respectively connected to the positive input terminal of the amplifier AMP and one end of the resistor Res1; the source of the PMOS tube Mp6 is respectively connected to the reverse input terminal of the amplifier AMP, the base and the collector of the transistor Bipolar2; one end of the resistor Res1 is connected to the positive input terminal of the amplifier AMP, and the other end of the resistor Res1 is respectively connected to the base and the collector of the transistor Bipolar1; the emitter of the transistor Bipolar1 is grounded; the base of the transistor Bipolar2 is respectively connected to its collector and the reverse input terminal of the amplifier AMP, and the emitter of the transistor Bipolar2 is grounded.

[0063] The first end of the bandgap reference circuit module is specifically the inverting input end of the amplifier AMP, the second end of the bandgap reference circuit module is specifically the first output end of the amplifier AMP, and the third end of the bandgap reference circuit module is specifically the second output end of the amplifier AMP.

[0064] See also Figure 4 , the amplifier AMP is composed of NMOS tube Man1, NMOS tube Man2, NMOS tube Man3, NMOS tube Man4, NMOS tube Man5, NMOS tube Man6, NMOS tube Man7, PMOS tube Map1, PMOS tube Map2, PMOS tube Map3, PMOS tube Map4 and PMOS tube Map5; wherein, NMOS tube Man1 and NMOS tube Man2 constitute the input pair of tubes of the amplifier AMP, PMOS tube Map1 and PMOS tube Map2 constitute the current mirror load of the amplifier AMP, and NMOS tube Man4 and PMOS tube Map5 constitute the current mirror load mirror current branch of the amplifier AMP. wherein, the first output end of the amplifier AMP is specifically the output end of the current mirror load mirror current branch (i.e., node B); the second output end of the amplifier AMP is specifically the output end of the current mirror load (i.e., node C). Figure 4In the figure, Vin+ represents the input signal at the positive input terminal of the amplifier AMP, and Vin- represents the input signal at the negative input terminal of the amplifier AMP.

[0065] See also Figure 2 and Figure 4 , the more specific working principle of starting the core circuit module is as follows:

[0066] 1) When the enable signal Ven is low, the output signal Ven_B of the inverter INV1 is high, and the output signal Ven_S of the inverter INV2 is low. At this time, the gate voltage of the PMOS tube Mp1 is high, and the PMOS tube Mp1 is in a closed state, that is, no current flows through the branch where the PMOS tube Mp1 is located, and the PMOS tube Mp2 is in a closed state; and the gate voltage of the NMOS tube Mn4 is high, and the NMOS tube Mn4 is in a conducting state, but it pulls down the gate voltages of the NMOS tubes Mn2 and Mn3. At this time, the transistors Mn2 and Mn3 are both in a closed state.

[0067] At the same time, when the enable signal Ven is low, in the amplifier AMP of the bandgap reference circuit module, the first voltage signal EN_B is low, and the second voltage signal EN_S is high, then the gate voltages of the NMOS tubes Man5, Man6, and Man7 are all high, and the gate voltages of the PMOS tubes Map3 and Map4 are low. At this time, the switch tubes Map3, Map4, Man5, Man6, and Man7 in the amplifier AMP are all in the on state, and the entire amplifier AMP does not work at this time, and the output voltage of the first output terminal (i.e., node B) of the amplifier AMP is pulled to the input power supply voltage Vdd by the switch tube Map4, so the entire bandgap reference circuit module is in a non-working state.

[0068] 2) When the enable signal Ven is high, the output signal Ven_B of the inverter INV1 is low, and the output signal Ven_S of the inverter INV2 is high. At this time, except for the PMOS tube Mp2, the other switch tubes of the startup core circuit module are in the off state.

[0069] When the enable signal is just high, the PMOS tube Mp2 is turned on. If the bandgap reference circuit module is in an abnormal working state at this time, that is, the bandgap reference circuit is locked in the degenerate point state of zero current, the current of the bandgap reference circuit module is 0, the transistor Bipolar2 is not turned on, and the gate voltage detection of the PMOS tube Mp2 and the NMOS tube Mn1 is low, then at this time the PMOS tube Mp2 will pull up its drain-source voltage (which is also the gate voltage of the NMOS tube Mn2, that is, the voltage of the node A), so the NMOS tube Mn2 is turned on. After the NMOS tube Mn2 is turned on, its drain-source voltage (which is also the gate voltage of the PMOS tube MP3 and the PMOS tube MP4) will be pulled down, so the PMOS tubes Mp3 and Mp4 will be turned on, and the bandgap reference circuit module will begin to have a temporary current, thereby getting rid of the degenerate point of zero current. After the bandgap reference circuit module is slowly started, the transistor Bipolar2 is turned on, and the gate voltages of the PMOS tube Mp2 and the NMOS tube Mn1 are high. The pull-down capability of the NMOS tube Mn1 is designed to be stronger than the pull-up capability of the PMOS tube Mp2. Then, when the NMOS tube Mn1 is turned on, the gate voltage of the NMOS tube Mn2 will be pulled down, and the NMOS tube Mn2 will no longer work. In this way, starting the core circuit unit will no longer affect the bandgap reference circuit module. The bandgap reference circuit module can work in a normal state due to the existence of the starting core circuit unit.

[0070] based on Figure 2 and Figure 4 It can be seen that the key transistor that allows the bandgap reference circuit module to have temporary current is Mn2, whose gate is connected to an inverter output terminal composed of Mp2 and Mn1, and its drain is connected to the first output terminal of the amplifier AMP in the bandgap reference circuit module. After the NMOS tube Mn2 is turned on, the PMOS tubes Mp3 and Mp4 of the bandgap reference circuit module will be turned on, allowing the bandgap reference circuit module to start to have temporary current.

[0071] Therefore, the startup core circuit module provided by the present invention can ensure that the bandgap reference circuit can get rid of the degenerate point working state of zero current when the enable signal is high, and is suitable for the design of ultra-low power consumption bandgap reference. At the same time, the startup core circuit module of the present invention has low design difficulty, and the power consumption of the startup circuit is extremely small, which meets the requirements of ultra-low power consumption design of the bandgap reference.

[0072] In order to further illustrate the technical effect of the ultra-low power consumption bandgap reference circuit with startup circuit suitable for high temperature conditions provided by the present invention, which can also maintain good working performance under high temperature conditions, please refer to Figure 3 , Figure 3 The invention shows a startup circuit and an ultra-low power consumption bandgap reference circuit diagram when MOS tube leakage is not considered.

[0073] Figure 3 The circuit is also composed of a control circuit module, a startup core circuit unit and a bandgap reference circuit module; wherein the control circuit module is composed of an inverter INV1, an inverter INV2, a PMOS tube Mp1 and an NMOS tube Mn4; the startup core circuit unit is composed of a PMOS tube Mp2, an NMOS tube Mn1 and an NMOS tube Mn2; the bandgap reference circuit module is composed of a PMOS tube Mp3, a PMOS tube Mp4, a PMOS tube Mp5, a PMOS tube Mp6, a resistor Res1, a transistor Bipolar1, a transistor Bipolar2 and an amplifier AMP.

[0074] exist Figure 3 In the figure, when the bandgap reference circuit module works normally, the gate voltage of the NMOS tube Mn2 is a low voltage. Under ideal conditions, the drain current flowing through it should be zero. However, due to the existence of leakage current, the NMOS tube Mn2 will draw a little current from the amplifier AMP. This current may be at the pA level, and for the design of a bandgap reference circuit with a power consumption of nA level, it cannot be ignored and is likely to affect the working performance of the bandgap reference circuit. That is, the circuit of the amplifier AMP will form a serious mismatch due to the leakage current, thereby reducing the working gain and output accuracy of the bandgap reference circuit.

[0075] Based on this, the present invention designs a corresponding leakage compensation circuit unit to eliminate or compensate for the influence of this part of leakage current. Figure 1 The leakage compensation circuit unit includes an NMOS tube Mn3 and a resistor Res2; the drain of the NMOS tube Mn3 is connected to one end of the resistor Res2, and the source of the NMOS tube Mn3 is grounded; the other end of the resistor Res2 is connected to the third end of the bandgap reference circuit module. The first end of the leakage compensation circuit unit is specifically the gate of the NMOS tube Mn3, and the gate of the NMOS tube Mn3 is connected to the gate of Mn2. At the same time, when designing, the transistors Mn2 and Mn3 need to adopt the same size structure.

[0076] Then, when the bandgap reference circuit module is working, when there is leakage current in the NMOS tube Mn2 of the startup core circuit unit, the NMOS tube Mn3 of the leakage compensation circuit unit will synchronously generate a mirror leakage current existing in the NMOS tube Mn2, and the transistor Mn2 branch of the startup core circuit unit is connected to the branch at the output end of the amplifier AMP (i.e., the branch where the node B is located), and the branch of the transistor Mn3 of the leakage compensation circuit unit is connected to the mirror output branch of the amplifier (i.e., the branch where the node C is located). Therefore, even if there is leakage in the transistor of the startup core circuit unit, since the two branches of the amplifier AMP (i.e., the branches where the nodes B and C are located respectively) leak the same current at the same time, the amplifier AMP is still in a balanced state at this time, and will not cause imbalance of the amplifier AMP, thereby ensuring the good working performance of the ultra-low power bandgap reference circuit at high temperature, and avoiding the problem that the ultra-low power bandgap reference circuit will affect the circuit performance due to the MOS tube leakage problem under high temperature conditions.

[0077] In the leakage compensation circuit unit of the present invention, the main function of the transistor Mn3 is to mirror the leakage current, and the function of the large resistor Res1 is to provide a temporary current for the bandgap reference core circuit module when the bandgap reference core circuit module is just started. The operation is still determined by Mn2 of the starting core circuit unit. If the two currents simultaneously pull down the voltage across the amplifier AMP, it may cause oscillation when the circuit is just started. At this time, the large resistor Res1 can be used. When the circuit is just started, due to the presence of the large resistor of the leakage compensation circuit unit, the voltage at the first output end of the amplifier AMP will be pulled down earlier than the output voltage of the mirror end.

[0078] The present invention provides an ultra-low power consumption bandgap reference circuit with a startup circuit suitable for high temperature conditions, which has the following advantages:

[0079] 1. The startup core circuit adopts a low-power design with low design difficulty. The startup core circuit provides temporary current to the bandgap reference circuit through a MOS transistor to prevent the bandgap reference circuit from falling into a deadlock state, thereby meeting the startup requirements of the ultra-low-power bandgap reference.

[0080] 2. When there is transistor leakage in the startup core circuit unit, the leakage compensation circuit unit provides a mirror leakage current to the bandgap reference circuit module, so that the two output branches of the amplifier of the reference bandgap circuit module leak the same current at the same time, so that the reference bandgap circuit module is still in a balanced working state, thereby ensuring that the ultra-low power bandgap reference can be started normally at high temperature, and the existence of the leakage compensation circuit unit will not affect the relevant performance of the bandgap reference, so that the bandgap reference maintains good working performance.

[0081] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A bandgap reference circuit with ultra-low power consumption and a start-up circuit suitable for high temperature conditions, characterized in that: include: A control circuit module, a startup circuit module and a bandgap reference circuit module; The startup circuit module is composed of a startup core circuit unit and a leakage compensation circuit unit; The control circuit module is connected to the startup circuit module, and is used to establish a startup identification signal for starting the core circuit unit based on the enable signal, and send the startup identification signal to the startup core circuit unit; The startup core circuit unit is connected to the bandgap reference circuit module and is used to provide a startup temporary current to the bandgap reference circuit module according to the startup identification signal, so that the bandgap reference circuit module can get rid of the degenerate electrical state of zero current; The leakage compensation circuit unit is connected to the startup circuit module and the bandgap reference circuit module respectively, and is used to generate a corresponding mirror leakage current when leakage occurs in the startup core circuit unit, thereby maintaining a balanced state of the bandgap reference circuit module; The bandgap reference circuit module is used to generate and output a reference voltage based on an input power supply and the start-up identification signal.

2. The ultra-low power consumption bandgap reference circuit with a startup circuit according to claim 1, characterized in that: The startup core circuit unit is composed of a PMOS tube Mp2, an NMOS tube Mn1 and an NMOS tube Mn2; The gate of the PMOS tube Mp2 is respectively connected to the gate of the NMOS tube Mn1 and the first end of the bandgap reference circuit module, the drain of the PMOS tube Mp2 is connected to the first end of the control circuit module, and the source of the PMOS tube Mp2 is respectively connected to the second end of the control circuit module, the drain of the NMOS tube Mn1 and the gate of the NMOS tube Mn2; The gate of the NMOS tube Mn1 is connected to the first end of the bandgap reference circuit module, the drain of the NMOS tube Mn1 is respectively connected to the gate of the NMOS tube Mn2 and the second end of the control circuit module, and the source of the NMOS tube Mn1 is grounded; The gate of the NMOS tube Mn2 is respectively connected to the second end of the control circuit module and the first end of the leakage compensation circuit unit, the drain of the NMOS tube Mn2 is connected to the second end of the bandgap reference circuit module, and the source of the NMOS tube Mn2 is grounded.

3. The ultra-low power consumption bandgap reference circuit with a startup circuit according to claim 2, characterized in that: The leakage compensation circuit unit includes an NMOS tube Mn3 and a resistor Res2; The drain of the NMOS tube Mn3 is connected to one end of the resistor Res2, and the source of the NMOS tube Mn3 is grounded; The other end of the resistor Res2 is connected to the third end of the bandgap reference circuit module.

4. The ultra-low power consumption bandgap reference circuit with a startup circuit according to claim 3, characterized in that: The first end of the leakage compensation circuit unit is specifically the gate of the NMOS transistor Mn3.

5. The ultra-low power consumption bandgap reference circuit with a startup circuit according to claim 2, characterized in that: The control circuit module is composed of an inverter INV1, an inverter INV2, a PMOS tube Mp1 and an NMOS tube Mn4; The input end of the inverter INV1 is connected to the enable signal, and the output end of the inverter INV1 is connected to the input end of the inverter INV2; The gate of the PMOS tube Mp1 is connected to the output end of the inverter INV1, and the drain of the PMOS tube Mp1 is connected to the input power supply; The gate of the NMOS transistor Mn4 is connected to the output end of the inverter INV2, and the source of the NMOS transistor Mn4 is grounded.

6. The ultra-low power consumption bandgap reference circuit with a startup circuit according to claim 5, characterized in that: The first end of the control circuit module is specifically the source of the PMOS transistor Mp1, and the second end of the control circuit module is specifically the drain of the NMOS transistor Mn4.

7. The ultra-low power consumption bandgap reference circuit with a startup circuit according to claim 4, characterized in that: The bandgap reference circuit module is composed of a PMOS tube Mp3, a PMOS tube Mp4, a PMOS tube Mp5, a PMOS tube Mp6, a resistor Res1, a triode Bipolar1, a triode Bipolar2 and an amplifier AMP; The gate of the PMOS tube Mp3 is respectively connected to the gate of the PMOS tube Mp4 and the first output terminal of the amplifier AMP, the drain of the PMOS tube Mp3 is connected to the input power supply, and the source of the PMOS tube Mp3 is connected to the drain of the PMOS tube Mp5; The gate of the PMOS tube Mp4 is connected to the first output terminal of the amplifier AMP, the drain of the PMOS tube Mp4 is connected to the input power supply, and the source of the PMOS tube Mp4 is connected to the drain of the PMOS tube Mp6; The gate of the PMOS tube Mp5 is connected to the gate of the PMOS tube Mp6, and the source of the PMOS tube Mp5 is connected to the positive input terminal of the amplifier AMP and one end of the resistor Res1 respectively; The source of the PMOS tube Mp6 is respectively connected to the reverse input terminal of the amplifier AMP, the base and the collector of the transistor Bipolar2; One end of the resistor Res1 is connected to the positive input end of the amplifier AMP, and the other end of the resistor Res1 is connected to the base and collector of the transistor Bipolar1 respectively; The emitter of the transistor Bipolar1 is grounded; The base of the transistor Bipolar2 is connected to its collector and the reverse input terminal of the amplifier AMP respectively, and the emitter of the transistor Bipolar2 is grounded.

8. The ultra-low power consumption bandgap reference circuit with a startup circuit according to claim 7, characterized in that: The first end of the bandgap reference circuit module is specifically the inverting input end of the amplifier AMP, the second end of the bandgap reference circuit module is specifically the first output end of the amplifier AMP, and the third end of the bandgap reference circuit module is specifically the second output end of the amplifier AMP.

9. The ultra-low power consumption bandgap reference circuit with a startup circuit according to claim 8, characterized in that: The amplifier AMP is composed of NMOS tube Man1, NMOS tube Man2, NMOS tube Man3, NMOS tube Man4, NMOS tube Man5, NMOS tube Man6, NMOS tube Man7, PMOS tube Map1, PMOS tube Map2, PMOS tube Map3, PMOS tube Map4 and PMOS tube Map5; Among them, the NMOS tube Man1 and the NMOS tube Man2 form an input pair of tubes of the amplifier AMP, the PMOS tube Map1 and the PMOS tube Map2 form a current mirror load of the amplifier AMP, and the NMOS tube Man4 and the PMOS tube Map5 form a mirror current branch of the current mirror load of the amplifier AMP.

10. The ultra-low power consumption bandgap reference circuit with a startup circuit according to claim 9, characterized in that: The first output end of the amplifier AMP is specifically the output end of the mirror current branch of the current mirror load; the second output end of the amplifier AMP is specifically the output end of the current mirror load.

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