Data caching method, system, device, equipment, medium and program, and memory processing method, system and device

Abstract

The embodiment of the invention discloses a data caching and memory processing method, system, device, equipment, medium and program, and the data caching method comprises the following steps: receiving a data caching request; the data caching request comprises the size of an application space of to-be-cached data; the application space represents the space occupied by the memory applied by the to-be-cached data; comparing the size of the application space with the size of a first fixing block; the first fixed block is the largest idle fixed block in the main memory blocks of the memory pool; the memory pool is used for realizing data caching, and the fixed block is a preset storage space in the main memory block; the main memory block comprises a plurality of fixed blocks with different sizes; and when the size of the application space is larger than that of the first fixed block, searching for an available memory from a standby memory block of the memory pool.

Description

Technical Field

[0001] The present application belongs to the field of storage technology, and in particular relates to a data cache, memory processing method, system, device, equipment, medium and program. Background Art

[0002] In a distributed file system, when the cached data size is larger than the available continuous memory storage space, the operating system or memory management library provides a memory defragmentation (or defragmentation) function to reduce the number and size of memory fragments by reorganizing the data in memory. Although this method may help create larger continuous memory blocks, it consumes certain computing resources and reduces the data caching speed. Summary of the invention

[0003] Embodiments of the present application provide a data cache, memory processing method, system, device, equipment, medium and program.

[0004] The present application provides a data caching method, the method comprising:

[0005] Receive a data cache request; the data cache request includes the size of the application space for the data to be cached; the application space indicates the memory space occupied by the data to be cached;

[0006] Compare the size of the application space with the size of the first fixed block; the first fixed block is the largest free fixed block in the main memory block of the memory pool; the memory pool is used to implement data caching, and the fixed block is a preset storage space in the main memory block; the main memory block includes multiple fixed blocks of different sizes;

[0007] When the size of the requested space is larger than the size of the first fixed block, available memory is searched from the spare memory blocks of the memory pool.

[0008] In some embodiments, when the size of the application space is less than or equal to the size of the first fixed block, the method further includes: searching for available memory from the main memory block.

[0009] It can be seen that when the requested space is smaller than the largest free fixed block in the main memory block, the data to be cached will be stored in the main fixed block first, which is helpful for the centralized management of cached data.

[0010] In some embodiments, when the size of the application space is not equal to the size of each fixed block in the main memory block, searching for available memory from the main memory block includes: searching for a second fixed block from the main memory block; the size of the second fixed block is larger than the size of the application space; splitting the second fixed block to obtain a first memory space and a second memory space; wherein the size of the first memory space is equal to the size of the application space; placing the data to be cached in the first memory space, and dividing the second memory space into the spare memory block.

[0011] It can be seen that when the applied space size is not equal to the fixed block size, a free second fixed block can be found. By splitting the second fixed block and dividing the remaining second memory space after the split into a spare memory block, memory fragmentation in the main memory block can be reduced, memory utilization can be improved, and the speed of data caching in the main memory block can be improved, thereby effectively utilizing memory space.

[0012] In some embodiments, the method further includes: when there is a third fixed block in the main memory block whose size is equal to that of the requested space, placing the data to be cached in the third fixed block.

[0013] In some embodiments, after searching for available memory from the backup memory block of the memory pool, the method further includes: when the size of the application space is larger than the size of the preset memory in the backup memory block, splitting the application space into multiple subspaces, and searching for available space in the main memory block and the backup memory block based on the size of each subspace in the multiple subspaces; wherein the preset memory represents the largest continuous and free memory.

[0014] It can be seen that this embodiment provides a method for caching relatively large data. When the application space for data to be cached is larger than the size of the largest continuous and free memory in the spare memory block, by splitting the application space before caching, no memory optimization or other processing is required, thereby improving data caching efficiency.

[0015] In some embodiments, the method further includes: returning the memory address of the data to be cached in the memory pool to the data segment layer; wherein the data segment layer is used to manage the memory address of the data in the memory pool and map the discontinuous physical addresses in the memory pool to continuous logical addresses.

[0016] It can be seen that this embodiment builds a data segment layer and uniformly manages the memory address of the data through the data segment layer, which can improve the read and write speed of cached data, shield the influence of discrete physical addresses on data cache, and improve the read and write speed of cached data.

[0017] In some embodiments, the method also includes: obtaining first dirty data to be flushed; wherein the first dirty data to be flushed includes at least two groups of dirty data to be flushed, and there is an idle memory interval between the at least two groups of dirty data to be flushed; reading back first data from the disk; the storage interval of the first data includes the storage interval of the first dirty data to be flushed; filling the idle memory interval between the at least two groups of dirty data to be flushed with data based on the first data to obtain second dirty data to be flushed; and flushing the second dirty data to be flushed to the disk storage space.

[0018] It can be seen that this embodiment provides a method for flushing dirty data to disk storage space. When there are idle memory intervals between different data in the dirty data to be flushed, that is, when there are idle memory intervals between at least two groups of dirty data to be flushed, the idle memory intervals are filled with data to make the at least two groups of dirty data to be flushed become continuous data, so that only at least two continuous groups of dirty data to be flushed need to be flushed once, thereby improving the speed of flushing dirty data.

[0019] In some embodiments, flushing the second dirty data to be flushed to the disk storage space includes: when there is third dirty data to be flushed, waiting for the third dirty data to be flushed to be flushed to the disk storage space, and then flushing the second dirty data to be flushed to the disk storage space; wherein, there is dirty data to be flushed whose storage intervals overlap with those of the third dirty data to be flushed and the second dirty data to be flushed.

[0020] It can be seen that when the same dirty data to be flushed exists in the dirty flushing queue, the orderly data flushing can ensure that the data finally stored on the disk is the latest data, thereby ensuring data consistency.

[0021] In some embodiments, the method further includes: obtaining a read request for second data; wherein the read request for the second data includes a first disk interval corresponding to the second data; the read request is used to read data from the disk storage space to a memory pool; obtaining a second disk interval corresponding to the third data currently read back from the disk, and when the first disk interval overlaps with the second disk interval, waiting for the third data to be read back to be completed, and then reading back the fourth data to the memory pool; wherein the disk interval corresponding to the fourth data is different from the second disk interval.

[0022] It can be seen that, through the method of this embodiment, the data read from the disk to the memory does not need to be read repeatedly, thereby improving the speed of reading data.

[0023] The present application also provides a memory processing method, the method comprising:

[0024] Receive a memory release request; the memory release request includes a first memory interval of memory to be released; the memory to be released is located in a memory pool, the memory pool includes a main memory block and a spare memory block; the main memory block includes a first fixed block, the first fixed block is the largest free fixed block in the main memory block; when the application space required for the data cache is greater than the size of the first fixed block, the memory occupied by the data cache includes the memory in the spare memory block;

[0025] The first memory interval is marked as a memory interval that can be used for data caching.

[0026] In some embodiments, after marking the first memory interval as a memory interval that can be used for data caching, the above method also includes: determining whether the first memory interval contains a first address where the main memory block and the backup memory block intersect; when the first memory interval does not contain the first address, determining whether there is an adjacent second memory interval to the first memory interval; wherein the second memory interval is an idle memory interval; when the second memory interval exists, merging the marked first memory interval with the second memory interval to obtain a fixed block in the main memory block.

[0027] In some embodiments, the memory release request also includes the size of the memory to be released, and when there is no adjacent second memory interval to the first memory interval, the method also includes: when the size of the memory to be released is equal to the size of any fixed block in the main memory block, using the first memory interval as a fixed block in the main memory block.

[0028] It can be seen that when the size of the memory to be released is equal to the size of any fixed block in the main memory block, the memory release speed can be improved by directly using the first memory interval as a fixed block in the main memory block.

[0029] In some embodiments, after marking the first memory interval as a memory interval that can be used for data caching, the method further includes: when the first memory interval contains a first address where the main memory block and the spare memory block intersect, dividing the marked first memory interval into the spare memory block.

[0030] In some embodiments, the method further includes: dividing the first memory interval into a plurality of fixed blocks in order from large to small fixed blocks.

[0031] It can be seen that, through the method of this embodiment, the first memory interval can be quickly and effectively divided into multiple fixed blocks, and the divided fixed blocks have different sizes, which is conducive to adjusting the number of free fixed blocks in the main memory block and ensuring the diversity of the fixed block sizes in the main memory block.

[0032] The embodiment of the present application also provides a data cache system, which includes a memory pool layer and a data segment layer, wherein the memory pool layer is used to implement data cache; the memory pool layer includes a memory pool, the memory pool includes a main memory block and a backup memory block, the main memory block includes a plurality of fixed blocks of different sizes, and the fixed block is a preset storage space in the main memory block; the memory pool is used to receive a data cache request; the data cache request includes the size of the application space for the data to be cached; the application space indicates the space occupied by the memory requested by the data to be cached; the size of the application space is compared with the size of the first fixed block; the first fixed block is the largest free fixed block in the main memory block; when the size of the application space is larger than the size of the first fixed block, the available memory is searched from the backup memory block;

[0033] The data segment layer is used to manage the memory addresses of the data in the memory pool; and map the discontinuous physical addresses in the memory pool into continuous logical addresses.

[0034] In some embodiments, the data cache system further includes a monitoring layer, wherein the monitoring layer is used to control the data size in the memory pool to be smaller than a threshold.

[0035] It can be seen that by setting up a monitoring layer in the data cache system, the total size of the data cached in the memory pool can be effectively controlled to prevent the cached data from exceeding the set threshold, thereby avoiding obtaining memory space from the system memory, and effectively ensuring the normal operation of the system.

[0036] The present application also provides a data cache device, the device comprising:

[0037] A first receiving module is used to receive a data cache request; the data cache request includes the size of the application space for the data to be cached; the application space indicates the space occupied by the memory requested by the data to be cached;

[0038] The first processing module is used to compare the size of the application space with the size of the first fixed block; when the size of the application space is larger than the size of the first fixed block, search for available memory from the spare memory block of the memory pool; wherein the first fixed block is the largest free fixed block in the main memory block of the memory pool; the memory pool is used to implement data caching, and the fixed block is a preset storage space in the main memory block; the main memory block includes multiple fixed blocks of different sizes.

[0039] The present application also provides a memory processing device, the device comprising:

[0040] A second receiving module is used to receive a memory release request; the memory release request includes a first memory interval of the memory to be released; the memory to be released is located in a memory pool, and the memory pool includes a main memory block and a spare memory block; the main memory block includes a first fixed block, and the first fixed block is the largest free fixed block in the main memory block; when the application space required for the data cache is greater than the size of the first fixed block, the memory occupied by the data cache includes the memory in the spare memory block;

[0041] The second processing module is configured to mark the first memory interval as a memory interval that can be used for data caching.

[0042] An embodiment of the present application provides an electronic device, the electronic device comprising a processor and a memory for storing a computer program that can be run on the processor; wherein:

[0043] The processor is used to run the computer program to execute any one of the above-mentioned data caching methods, or to execute any one of the above-mentioned memory processing methods.

[0044] An embodiment of the present application provides a computer storage medium on which a computer program is stored. When the computer program is executed by a processor, it implements any of the above-mentioned data caching methods or any of the above-mentioned memory processing methods.

[0045] An embodiment of the present application provides a computer program product, including a computer program, which implements any of the above-mentioned data caching methods or any of the above-mentioned memory processing methods when executed by a processor.

[0046] The embodiments of the present application provide a data cache, a memory processing method, a system, a device, a equipment, a medium and a program. When the application space size of the data to be cached is larger than the size of the maximum free fixed block, by directly storing the data to be cached in the spare memory block of the memory pool, there is no need to perform memory management, and there is no need to use the discrete memory space in the main memory block for storage, thereby improving the efficiency of caching data. When it is necessary to release the memory space, through the method provided in the embodiments of the present application, it is not necessary to delete the data in the memory to be released, only the space to be released needs to be marked, and when it is necessary to cache data in the memory space to be released, the new data to be cached is directly written into the memory space to be released, and the original data in the memory space to be released is replaced. It can be seen from this that through the method of the embodiments of the present application, it is not necessary to delete the data in the memory to be released, and the memory release speed can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A flow chart of a data caching method provided in an embodiment of the present application;

[0048] Figure 2 A schematic diagram of a memory pool structure provided in an embodiment of the present application;

[0049] Figure 3 A schematic diagram of data segment layer address management provided in an embodiment of the present application;

[0050] Figure 4 A memory pool memory allocation logic diagram provided in an embodiment of the present application;

[0051] Figure 5 A data flushing logic diagram provided in an embodiment of the present application;

[0052] Figure 6 A data reading logic schematic diagram provided for an embodiment of the present application;

[0053] Figure 7 A data writing logic schematic diagram provided for an embodiment of the present application;

[0054] Figure 8 A flow chart of a memory processing method provided in an embodiment of the present application;

[0055] Fig. 9 A memory pool memory release logic diagram provided in an embodiment of the present application;

[0056] Fig.10 A data cache system framework diagram provided for an embodiment of the present application;

[0057] Fig.11 A schematic diagram of the structure of a data cache device provided in an embodiment of the present application;

[0058] Fig.12 A schematic diagram of the structure of a memory processing device provided in an embodiment of the present application;

[0059] Fig.13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] Traditional file systems are limited by the performance bottleneck of a single machine and cannot meet the rapidly growing data processing needs of the business. Through a distributed file system, the storage resources of multiple servers can be integrated together, and when accessing business data, there is no need to know the actual physical location of each server. In a distributed file system, when the cached data size is larger than the available continuous memory storage space, the operating system or memory management library provides a memory defragmentation (or defragmentation) function to reduce the number and size of memory fragments by reorganizing the data in memory. Although this method may help create larger continuous memory blocks, it will consume a certain amount of computing resources and reduce the caching speed of large data.

[0061] The data cache of the open source distributed file system Ceph still has the following disadvantages:

[0062] The data cache architecture is designed with both block storage and file storage in mind. Although it has better compatibility, there is a redundant hierarchical design for the data cache of file storage, and the performance of the file data cache cannot be optimized. For example, when reading small data of a few bytes, the memory range will be repeatedly split and merged, and multiple invalid memory applications and releases will be performed, affecting the cache performance.

[0063] The data cache is implemented using the common memory management module bufferlist in Ceph. Although this module can more conveniently apply for, release, and count memory, it allocates memory with 4k alignment. When a few bytes of small input and output (IO) are read and written, memory amplification will occur. When data segments are split, memory amplification will also occur. Release logic needs to be added to avoid this phenomenon. However, the resulting problem reduces storage performance and makes it impossible to accurately count the actual size of cached data used.

[0064] The data / file cache is protected by a large lock. Multiple data / files cannot be read or written concurrently. Only one data / file can be read or written at a time. The same data / file cannot be read concurrently. For scenarios where multiple clients need to access multiple different data / files at the same time, the performance is very poor.

[0065] In response to the above-mentioned problems, the embodiments of the present application provide a data cache, memory processing method, system, device, equipment, medium and program, which can improve the data cache speed.

[0066] The following is a further detailed description of the embodiments of the present application in conjunction with the accompanying drawings and examples. It should be understood that the embodiments provided herein are only used to explain the embodiments of the present application and are not intended to limit the embodiments of the present application. In addition, the embodiments provided below are partial embodiments for implementing the present application, rather than providing all embodiments for implementing the present application. In the absence of conflict, the technical solutions recorded in the embodiments of the present application can be implemented in any combination.

[0067] It should be noted that, in the embodiments of the present application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a method or device including a series of elements includes not only the elements explicitly recorded, but also includes other elements not explicitly listed, or also includes elements inherent to the implementation of the method or device. In the absence of further restrictions, an element defined by the sentence "includes..." does not exclude the presence of other related elements (such as steps in the method or units in the device, such as a unit in the device may be a part of a circuit, a part of a processor, a part of a program or software, etc.) in the method or device including the element.

[0068] The data caching method and memory processing method provided in the embodiments of the present application include a series of steps, but the data caching method and memory processing method provided in the embodiments of the present application are not limited to the recorded steps. Similarly, the data caching device and memory processing device provided in the embodiments of the present application include a series of modules, but the device provided in the embodiments of the present application is not limited to including the modules explicitly recorded, and may also include modules required to obtain relevant information or perform processing based on the information.

[0069] The present application embodiment provides a data caching method, such as Figure 1 As shown, Figure 1 The data caching method shown includes:

[0070] Step 101: receiving a data cache request; the data cache request includes the size of the application space for the data to be cached; the application space indicates the memory space occupied by the data to be cached.

[0071] The data to be cached in this step may be data or files that need to be written into the memory. The application space for the data to be cached may include the size, type, storage structure, etc. of the data to be cached.

[0072] In the present application, the size of the space applied for the data to be cached is determined by the minimum memory allocation unit. For example, when the minimum memory allocation unit is 4k, the size of the memory occupied by the data to be cached is determined to be N*4k, where N is a positive integer greater than or equal to 1.

[0073] Step 102: Compare the size of the applied space with the size of the first fixed block; the first fixed block is the largest free fixed block in the main memory block of the memory pool; the memory pool is used to implement data caching, and the fixed block is a preset storage space in the main memory block; the main memory block includes multiple fixed blocks of different sizes.

[0074] When the size of the requested space for the data to be cached is obtained, the size of the space required for the data to be cached in the memory can be determined. The memory occupied space refers to the memory space required for the data actually stored in the memory. When requesting to occupy memory space, a sufficiently large free fixed block is usually found, the starting address of the fixed block is returned, and the memory block is marked as occupied.

[0075] In this step, unified management of data cache is achieved by setting a memory pool in the memory. Memory pool is a memory allocation method. In the related art, before the memory is actually used, the memory pool usually pre-applies for allocation of a certain number of memory blocks of equal size for backup. However, the memory pool in the embodiment of the present application is different from the management method of the memory pool in the related art. The memory pool in the embodiment of the present application is divided into a main memory block and a backup memory block, wherein fixed blocks of different sizes are pre-set in the main memory block. Through fixed blocks of different sizes, the cache of data of different sizes can be satisfied, thereby speeding up the data caching speed. According to general understanding, the size of the fixed block is divided into multiples of the minimum memory allocation unit, and the multiples of the minimum memory allocation unit corresponding to fixed blocks of different sizes are different.

[0076] The main memory block includes free fixed blocks and occupied fixed blocks. Free fixed blocks refer to fixed blocks that can be used for data caching. Free fixed blocks include fixed blocks with empty data in the current memory interval, and also include fixed blocks that have been released with preset identifiers. The preset identifier here can be, for example, a "free" mark. By setting a mark for the fixed block, the fixed block is marked as available for data caching. Occupied fixed blocks refer to fixed blocks that have currently cached data and do not have preset identifiers. Therefore, data caching can be performed in free fixed blocks. In the present application, the fixed blocks used for data caching are all free fixed blocks.

[0077] In actual applications, a free list can be set in the main memory block. The free fixed blocks in the main memory block are recorded and managed by the free list. When data is cached, the free fixed blocks that can be used for data caching can be quickly located by comparing the size of the requested space with the size of the fixed blocks in the free list.

[0078] like Figure 2 As shown, Figure 2 FIG. 1 shows a schematic diagram of a memory pool structure. It can be seen that the address of the main memory block in the memory pool is connected to the address of the backup memory block. Figure 2 As shown in the example, the fixed block size in the main memory block is set to 4k, 8k, 16k, ..., 1024K, etc. This embodiment does not specifically limit the size of the fixed block and the division method.

[0079] like Figure 2As shown, the main memory block can use 4k as a minimum memory allocation unit, and the memory pool is flattened through a bitmap for easy management. The memory pool in the bitmap is divided into two large blocks, one of which is a pre-allocated main memory block, wherein the main memory block includes a free fixed block managed by a free list, and the free fixed block is cut according to a fixed block size, such as 4k, 8k, 16k, etc., and the cut memory address is stored in a free list. The other block is a spare memory block, which is set as a large memory with continuous addresses, and is used to allocate a size that exceeds the maximum free fixed block managed by the free list in the main memory block, or when the fixed blocks in the free list are insufficient, memory can be allocated from the spare memory block.

[0080] There is a junction point between the main memory block and the backup memory block. When moving from a low address to a high address, when it has moved to the highest address point, it will move from the lowest address to a high address again. When this happens, it means that the memory pool is almost used up and the allocation efficiency will be relatively low.

[0081] like Figure 2 As shown, when the memory pool is divided into fixed blocks with 4k as the minimum memory allocation unit, when the data to be cached is small, it is no longer necessary to split the fixed blocks of 4k, which can reduce repeated memory splitting. When the data to be cached is small, this embodiment can manage the memory pool so that the smaller data to be cached is merged and stored in the 4k fixed block instead of placing one data to be cached in one fixed block, which can improve memory utilization.

[0082] Step 103: When the size of the requested space is larger than the size of the first fixed block, search for available memory from the spare memory blocks of the memory pool.

[0083] When the size of the requested space is larger than the size of the first fixed block, it is considered that the continuous free memory addresses in the main memory block can no longer meet the cache requirements of the data to be cached. At this time, the spare memory block is preferentially searched for available memory.

[0084] Here, preferentially searching for available addresses in the spare memory block refers to searching for free continuous memory addresses in the spare memory block to ensure that the data to be cached can be preferentially stored in continuous memory addresses, which is beneficial to improving the reading and writing efficiency of the data to be cached.

[0085] This embodiment provides a data caching method, which manages memory through a memory pool. When caching data with a larger application space, there is no need to reorganize the memory. This ensures that the data to be cached is stored in a continuous memory space, which is beneficial to improving the data caching speed and further beneficial to improving the reading and writing speed of the cached data.

[0086] In practical applications, steps 101 to 103 can be implemented based on a processor, and the processor can be at least one of an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a CPU, a controller, a microcontroller, and a microprocessor.

[0087] In some embodiments, when the size of the requested space is less than or equal to the size of the first fixed block, the method further includes: searching for available memory from the main memory block.

[0088] When the size of the application space for the data to be cached is less than or equal to the size of the first fixed block, it is considered that the size of the data to be cached can be stored in the main memory block, and now the main memory block is searched for available memory.

[0089] When the size of the application space is less than or equal to the size of the first fixed block, data is cached preferentially in the main memory block, which is beneficial to achieve unified management of data and improve the reading and writing speed of cache data.

[0090] In some embodiments, when the size of the application space is not equal to the size of each fixed block in the main memory block, searching for available memory from the main memory block includes: searching for a second fixed block from the main memory block; the size of the second fixed block is larger than the size of the application space; splitting the second fixed block to obtain a first memory space and a second memory space; wherein the size of the first memory space is equal to the size of the application space; placing the data to be cached in the first memory space, and dividing the second memory space into spare memory blocks.

[0091] When the size of the requested space is not equal to the size of each fixed block, the available memory can be searched from the main memory block. Specifically, the free list in the main memory can be searched to obtain the free second fixed block currently suitable for storing the data to be cached. Here, the second fixed block can be a fixed block in the free list whose size is larger than the size of the requested space and the smallest fixed block among all fixed blocks whose size is larger than the size of the requested space. For example, when the size of the requested space is 192k, according to Figure 2The second fixed block can also be any fixed block in the free list whose size is larger than the size of the application space. For example, when the size of the application space is 192k, according to Figure 2 As shown in the free list shown, the second fixed block may be a fixed block of 256k in size, or a fixed block of 512k in size, or a fixed block of 640k in size.

[0092] After the second fixed block is confirmed, the second fixed block is split into a first memory space equal to the size of the applied space, the remaining memory space is used as the second memory space, and the second memory space is divided into the spare memory block.

[0093] Referring to the above example, when the application space size is 192k and the second fixed block size is 256k, the first memory space size is 192k, the second memory size is 64k, and 64k of memory is divided into the spare memory block.

[0094] It can be seen that through the method of this embodiment, when the size of the application space for the data to be cached is not equal to the size of any fixed block, the fixed block can be split and the remaining memory interval after the split can be divided into spare memory blocks, thereby improving the utilization rate of the memory space of the memory pool and reducing memory fragmentation in the memory pool.

[0095] In some embodiments, the above method further includes: when there is a third fixed block in the main memory block whose size is equal to the requested space, placing the data to be cached in the third fixed block.

[0096] It can be seen that when there is an idle third fixed block in the main memory block with a size equal to the requested space of the data to be cached, the data cache speed can be effectively improved by directly placing the data to be cached in the third fixed block.

[0097] In some embodiments, after searching for available memory from the backup memory block of the memory pool, the above method also includes: when the size of the application space is larger than the size of the preset condition memory in the backup memory block, splitting the application space into multiple subspaces, and based on the size of each subspace in the multiple subspaces, searching for available space in the main memory block and the backup memory block; wherein the preset condition memory represents the largest continuous and free memory.

[0098] This embodiment provides a method for processing when the size of the application space is larger than the first fixed block size and larger than the size of the largest continuous and free memory in the spare memory block. The application space size is split to obtain multiple subspaces, and based on the size of each subspace, available free space is searched from the main memory block and the spare memory block.

[0099] When the application space is split, the corresponding application space can be split according to different data attributes in the data to be cached, so that data with the same attributes can be stored in a continuous memory interval.

[0100] When splitting the application space, the application space can also be split directly considering the size of the application space. For example, the size of the application space is first halved, and the available space is searched from the main memory block and the backup memory block according to half of the size of the application space. When the size of the continuous available memory space in the main memory block or the backup memory block is greater than or equal to half of the size of the application space, the data to be cached is split and placed in two segments of available memory. When the size of the available space in the main memory block or the backup memory block is less than half of the size of the application space, the available space can be searched from the main memory block and the backup memory block according to one quarter of the size of the application space, and so on, until the size of the continuous available memory space in the main memory block or the backup memory block meets the size of the application space after the split, and the data is cached.

[0101] In some embodiments, the above method also includes: returning the memory address of the data to be cached in the memory pool to the data segment layer; wherein the data segment layer is used to manage the memory address of the data in the memory pool and map the discontinuous physical addresses in the memory pool to continuous logical addresses.

[0102] This embodiment sets up a data segment layer for managing the address of cached data in the memory pool and encapsulating discrete physical addresses allocated by the memory pool. When the data to be cached is stored in the memory pool, the memory address of the data to be cached in the memory pool will be returned to the data segment layer. When there is a lot of data cached in the memory pool, there may not be a large fixed block in the memory pool, or continuous storage space cannot be allocated. At this time, the memory pool will store the data to be cached in a discrete memory space, and record the address of the discrete memory space through the data segment layer, and connect the discontinuous fixed blocks or memory addresses together through an algorithm, and map the discontinuous physical addresses to continuous logical addresses, thereby shielding the cache effect caused by the discreteness of the physical address.

[0103] In the data segment layer, the memory address of the cached data in the memory pool can be recorded through the data segment. When performing cached data reading and writing and other processing, the memory range of the cached data to be processed can be confirmed through the data segment in the data segment layer, thereby speeding up the processing of the cached data.

[0104] Figure 3A schematic diagram of data segment layer address management is shown, where each discrete physical address is linked through a bidirectional linked list. When a certain address in a data segment needs to be accessed, a cursor is used to locate the specific physical address in the memory and the offset address in the memory. The cursor will move left and right to the specified position in the data segment according to the access needs.

[0105] In combination with the above embodiments, a data caching method is provided. Figure 4 A memory pool memory allocation logic diagram is shown, such as Figure 4 The memory pool allocation logic is as follows:

[0106] Step 401: Allocate application space size N.

[0107] After receiving the data cache request, the file system or memory pool allocates corresponding application space according to the size of the data to be cached in the data cache request, and determines the size of the application space to be N, where N is a multiple of the minimum memory allocation unit.

[0108] Step 402: Determine whether N is greater than the remaining memory size of the memory pool.

[0109] When N is greater than the remaining memory size of the memory pool, step 419 is executed.

[0110] When N is less than or equal to the remaining memory size of the memory pool, step 403 is executed.

[0111] The remaining memory of the memory pool includes each free fixed block in the main memory block of the current memory pool and the free memory in the backup memory block, that is, the remaining memory size of the memory pool represents the total available memory size in the current memory pool. When N is greater than the remaining memory size of the memory pool, it means that N is greater than the sum of all available memory sizes of the current memory pool, and the memory pool cannot meet the cache demand for N at this time.

[0112] Step 403: Determine whether the memory allocation address is obtained.

[0113] When the memory allocation address is obtained, execute step 418, otherwise execute step 404.

[0114] In some cases, for example, when the data to be cached is system data, system memory will be directly allocated to the data instead of memory allocation through the memory pool. Therefore, for some specific data, the memory address may be directly obtained. Alternatively, after the memory allocation address of the application space is obtained through the following steps, step 418 is executed.

[0115] Step 404: Determine whether N is less than or equal to the first fixed block.

[0116] When N is less than or equal to the first fixed block size, execute step 405 ; otherwise, execute step 414 .

[0117] The first fixed block in this step is the same as the first fixed block in the above embodiment, and represents the largest free fixed block in the main memory block of the memory pool.

[0118] Step 405: Determine whether there is a fixed block equal to N and free.

[0119] When there is a free fixed block with the same size as N, execute step 406; otherwise, execute step 408.

[0120] Step 406: Delete the fixed block from the free list.

[0121] When there are fixed blocks equal to N and free, the data to be cached is placed in the fixed block, and the fixed block is deleted from the free list. The free list here is the same as the free list in the above embodiment, and is used to manage the free fixed blocks in the main memory block. When data is cached, the currently available fixed blocks can be quickly determined by searching the free list. After data is placed in the fixed block in the free list, the fixed block is deleted from the free list.

[0122] Step 407: Get the fixed block memory address.

[0123] After obtaining the fixed block memory address, that is, obtaining the memory allocation address, return to execute step 403.

[0124] Step 408: Determine whether there are free fixed blocks greater than N in the free list.

[0125] If there are more than N free fixed blocks in the free list, execute step 409; otherwise, execute step 413.

[0126] Step 409: Delete the fixed block from the free list.

[0127] When there are more than N free fixed blocks, the data to be cached is put into the fixed block, and the fixed block is deleted from the free list.

[0128] Step 410: Split the fixed block into two blocks, A and B, where the size of A is N.

[0129] When the fixed block size is larger than the application space size, the fixed block is split into a first memory space A and a second memory space B through the method provided in the above embodiment, wherein the size of A is equal to the size of the application space N.

[0130] Step 411: Divide B into a spare memory block.

[0131] Step 412: Get A's address.

[0132] Here, the address of the first memory space A may be the start and end addresses of the fixed block where the first memory space A is located and the offset address of the first memory space A, or may be recorded as a unique identifier of the fixed block where the first memory space A is located.

[0133] After obtaining the address of A, that is, obtaining the memory allocation address, the process returns to step 403 .

[0134] Step 413: Reduce N by half and re-enter the allocation logic.

[0135] When there is no free fixed block greater than N in the free list, N is halved and the process returns to step 403 until the memory allocation address is obtained. At this time, the actual size of N processed in step 403 is half of the size of the space requested in step 401.

[0136] Step 414: Determine whether there is continuous free memory greater than or equal to N in the spare memory block.

[0137] When there is continuous free memory greater than or equal to N in the spare memory block, execute step 415; otherwise, execute step 417.

[0138] Step 415: Move the spare memory block cursor.

[0139] By moving the spare memory block cursor, the memory address of the data cache can be located in the memory area of ​​the spare memory block, thereby realizing data cache of the spare memory block.

[0140] Step 416: Get the memory allocation address.

[0141] After obtaining the memory allocation address, return to execute step 403.

[0142] Step 417: Reduce N by half and re-enter the allocation logic.

[0143] The specific implementation of this step may refer to the above embodiment and step 413.

[0144] After N is halved, the process returns to step 403 until the memory allocation address is obtained.

[0145] Step 418: Return the memory address.

[0146] After determining the memory address of the data to be cached, the memory address of the data to be cached is returned to the data segment layer, the memory address is recorded through the data segment in the data segment layer, and the storage and management of the data address in the memory pool are realized through the data segment layer.

[0147] Step 419: Return the null reference identifier NULL.

[0148] Figure 4The memory pool allocation logic diagram shown corresponds to the data caching method provided in the above embodiment, and can realize fast caching of data by setting a memory pool.

[0149] In some embodiments, the above method also includes: obtaining first dirty data to be flushed; wherein the first dirty data to be flushed includes at least two groups of dirty data to be flushed, and there is an idle memory interval between at least two groups of dirty data to be flushed; reading back the first data from the disk; the storage interval of the first data includes the storage interval of the first dirty data to be flushed; based on the first data, filling the idle memory interval between at least two groups of dirty data to be flushed with data to obtain second dirty data to be flushed; flushing the second dirty data to be flushed to the disk storage space.

[0150] Based on the above embodiments, this embodiment provides a data flushing method. The flushing operation refers to the process of writing the modified data in the memory back to the persistent storage (such as a disk). This process ensures the persistence and consistency of the data. Among them, dirty data refers to the data that has been modified in the memory and has not been solidified to the disk.

[0151] The dirty flushing operation is mainly triggered in two scenarios. One is that the upper-layer application actively calls the dirty flushing interface to flush the dirty data to the disk storage space; the other is that the internal dirty flushing thread periodically flushes the dirty data from the dirty data queue to the disk storage space. When the dirty data is flushed to the disk storage space, the dirty data segment is changed to a clean state, that is, the dirty data is changed to clean data. At this time, the data will not be lost due to power failure of the device, etc., and can be deleted at any time to release the corresponding memory space. Here, clean data refers to data that has been solidified to the disk.

[0152] When dirty data needs to be flushed to disk storage space, there are two special scenarios that require attention:

[0153] First, since there may be concurrent refresh scenarios, in order to ensure data consistency, the overlapping parts of the data intervals need to be refreshed in an orderly manner.

[0154] The second type is that since the minimum allocation unit of a general memory pool is fixed, assuming it is 4k, the minimum unit of the corresponding data segment layer is also 4k. When a hole write occurs, for example, the first write interval is [0,1k) and the second write is [2k,3k). At this time, there is a hole in the 4k data segment. When flushing the data segment, it is necessary to first read back the data in [0,4k) from the disk to fill the hole intervals [1k,2k) and [3k,4k). When the 4k space is filled and the hole is eliminated, the data in the interval is flushed.

[0155] In actual processing, it is necessary to ensure that the length of all data segments with holes is the minimum memory allocation unit. This ensures that when the data segments with holes are refreshed, there is no need to read back very long data, thereby improving the performance of refreshing data.

[0156] The above method is applicable to the flushing of dirty data with hole intervals. Through the dirty data flushing method provided in this embodiment, when there are hole intervals in the dirty data, the flushing times can be reduced and the dirty data flushing efficiency can be improved by filling the hole intervals with data.

[0157] In some embodiments, flushing the second dirty data to be flushed to the disk storage space includes: when there is third dirty data to be flushed, waiting for the third dirty data to be flushed to be flushed to the disk storage space, and then flushing the second dirty data to be flushed to the disk storage space; wherein the third dirty data to be flushed and the second dirty data to be flushed have overlapping storage intervals.

[0158] When there is data being flushed in the current dirty flushing queue, it is necessary to compare whether there is dirty data to be flushed in the dirty flushing queue that overlaps with the storage interval of the second dirty data to be flushed. The storage interval here can be a memory interval or a disk storage interval. When there is dirty data to be flushed that overlaps with the storage interval of the second dirty data to be flushed, it means that before the second dirty data to be flushed, there is another data processing on the overlapping dirty data to be flushed, and the second dirty data to be flushed is the latest data processing process. Through the method provided in this embodiment, after waiting for the third dirty data to be flushed that is being flushed to be flushed to the disk storage space, the second dirty data to be flushed is flushed to the disk storage space, which can ensure that the data finally flushed to the disk is the latest data.

[0159] In combination with the above embodiments, a data flushing method is provided. Figure 5 A data flushing logic diagram is shown, such as Figure 5 The data flushing logic is as follows:

[0160] Step 501: Add a write lock to the file.

[0161] The file contains dirty data to be flushed. When processing part of the data in the file in memory, the data is considered dirty data and needs to be flushed. Before flushing, first add a write lock to the file. When the data in the file is flushed, the file cannot be written to ensure the consistency of the file flushing process.

[0162] Step 502: Determine whether there is a hole in the memory interval.

[0163] If there is a hole in the memory interval, execute step 503; otherwise, execute step 504.

[0164] Specifically, this step is used to determine whether there is a hole in the dirty data to be flushed, that is, the first dirty data to be flushed in the above embodiment. Here, a hole means that there is an idle memory interval between two groups of dirty data to be flushed in the first dirty data to be flushed.

[0165] Step 503: Read back data from the disk to eliminate holes.

[0166] The data read back from the disk here is the same data as the file in step 501. Specifically, the storage interval corresponding to the data read back from the disk at least includes the storage interval corresponding to the data to be flushed.

[0167] For example, when the storage intervals of at least two groups of dirty data to be flushed are [0,1k) and [2k,3k) respectively, it can be seen that there are holes in the 4k storage interval. At this time, it is necessary to read back the data in [0,4k) from the disk and fill the holes based on the data in [0,4k).

[0168] Step 504: Determine the data segment 1 that needs to be refreshed.

[0169] According to the interval to be flushed, find the data segment 1 to be flushed in the corresponding data segment layer. Here, the data segment 1 is the data after data filling, corresponding to the second dirty data to be flushed in the above embodiment.

[0170] Step 505: Determine whether there is any overlap between the data segment 2 being refreshed and the data segment 1.

[0171] If the data segment 2 being refreshed has an overlapped section with the data segment 1, execute step 506; otherwise, execute step 508.

[0172] According to the dirty flushing queue being flushed, it is necessary to compare with data segment 1 to determine whether there is data segment 2 in the dirty flushing queue that overlaps with data segment 1. The overlapping interval here means that there is an overlapping storage interval between data segment 2 and data segment 1, that is, there is the same dirty data to be flushed.

[0173] Step 506: Add data segment 1 to the dirty-to-be-flushed queue.

[0174] When the data segment 2 being flushed overlaps with the data segment 1, the data segment 1 is added to the dirty queue to be flushed.

[0175] Step 507: After the data segment 2 is refreshed, the data segment 1 is triggered to refresh.

[0176] Step 508: Add data segment 1 to the dirty flushing queue.

[0177] Step 509: flush the data of data segment 1 to the disk storage space.

[0178] At this time, after data segment 1 is flushed to the disk storage space, the overlapping portion between data segment 2 and data segment 1 in the disk storage space will be overwritten by data segment 1.

[0179] Step 510: After the dirty flushing is successful, data segment 1 is removed from the dirty flushing queue.

[0180] Step 511: Unlock the file write lock.

[0181] The above steps provide the logic of data flushing. By combining the data segments in the data segment layer to determine the overlap of memory intervals, data consistency can be guaranteed when flushing data. At the same time, data flushing efficiency can be improved by filling data to be flushed.

[0182] In some embodiments, the above method also includes: obtaining a read request for second data; wherein the read request for second data includes a first disk interval corresponding to the second data; the read request is used to read data from the disk storage space to a memory pool; obtaining a second disk interval corresponding to the third data currently read back from the disk, and when the first disk interval overlaps with the second disk interval, waiting for the third data to be read back to be completed, and then reading back the fourth data to the memory pool; wherein the disk interval corresponding to the fourth data is different from the second disk interval.

[0183] The read logic mainly returns the data of the disk storage space that needs to be read to the upper-level application.

[0184] When data needs to be read from the disk storage space to the memory space, first determine whether the second disk interval corresponding to the third data currently being read overlaps with the first disk interval corresponding to the second data. When there are overlapping disk intervals, it means that the third data currently being read includes a portion of the second data. In this case, after waiting for the third data to be read back, the fourth data of the second data excluding the overlapping data is read back. It can be seen that through the read-back method provided in this embodiment, when the same read data exists, the same data only needs to be read once, which improves the speed of reading data from the disk storage space.

[0185] When the data is read back from the disk storage space to the internal space of the memory pool, the memory address of the data will be recorded in the data segment layer. By obtaining the memory interval of the second data in the memory pool at the data segment layer, the second data can be read to the specified memory interval through the memory interval of the second data in the memory pool.

[0186] According to the data reading method provided in the above embodiment, there are cache hits and cache misses in the read disk interval. The specific logic of reading data is as follows: Figure 6 shown. Figure 6 A complete data reading logic diagram is shown. Figure 6The data read logic shown includes:

[0187] Step 601: Determine whether there is a data segment being read back in the read interval.

[0188] When there is a data segment being read back in the read interval, step 602 is executed; otherwise, step 603 is executed.

[0189] This step corresponds to the above embodiment, and determines whether there is third data being read back, wherein the third data and the second data have overlapping disk sections.

[0190] First, determine whether the storage interval of the data to be read overlaps with the storage interval of the data being read back from the disk. The storage interval here can be a memory storage interval or a disk storage interval. If there is an overlapping storage interval, you need to wait for the current data to be read back. This waiting operation can avoid reading back the same interval of data from the disk space at the same time when read requests are concurrent, that is, the same interval of data in the disk only needs to be read once, which improves the reading efficiency.

[0191] Step 602: Wait for the read-back data segment to be completed.

[0192] Step 603: Add a read lock to the file.

[0193] When the third data is read back, a read lock is added to the file (ie, the second data) to prohibit the read operation when the second data is read back, which is conducive to ensuring the consistency of the second data.

[0194] Step 604: Determine whether there is an overlapping interval in the read-back data segment.

[0195] When there is an overlapping interval in the read-back data segment, execute step 605; otherwise, execute step 609.

[0196] Here, it is determined whether there is an overlapping interval in the read-back data segment, that is, whether there is overlapping storage space between the third data and the second data. For example, when it is necessary to read data in the [64k, 256k) interval, if there is currently [64k, 128k) data being cached or already in the memory, this phenomenon is a partial cache hit.

[0197] Step 605: Add the read-back data segment to the read-back queue.

[0198] Step 606: Read back the corresponding data from the disk storage.

[0199] The data segment read back at this time can be understood as the fourth data given in the above embodiment.

[0200] Step 607: Allocate a memory interval of corresponding size in the memory pool, and fill the read-back data into the memory interval.

[0201] At this time, the memory interval allocated from the memory pool is the memory interval corresponding to the fourth data.

[0202] Step 608: Delete the read-back data segment from the read-back queue.

[0203] After deleting the read-back data segment from the read-back queue, the process returns to step 604 until there is no overlapping interval in the read-back data.

[0204] Step 609: Find all data segments within the read interval.

[0205] When there is no missing data segment in the read-back data segment, that is, there is no partial cache hit, or in other words, when there is no fourth data, all the second data is read.

[0206] Step 610: Fill the data in the data segment into the specified memory interval.

[0207] At this time, the data in the data segment in step 610 corresponds to all the data in the second data.

[0208] Step 611: Unlock the file read lock.

[0209] When the file is read back from the disk storage space to the memory space of the memory pool, it is also necessary to fill the data in the memory pool into the specified memory space through the data segment layer, release the file read lock, and the file can be read normally.

[0210] The above steps correspond to the data reading method provided in the above embodiment, and can improve the data readback efficiency.

[0211] Based on the above embodiments, Figure 7 A complete data write logic schematic diagram is also shown. The write logic mainly writes the incoming data into a memory interval of a specified offset and length, and marks the data in the memory interval as dirty data, and then returns success. According to the method given in the above embodiment, the data write logic given in this application includes:

[0212] Step 701: Add a write lock to the file.

[0213] Step 702: Determine whether there is a vacant memory interval for writing data.

[0214] When there is a vacant memory interval for writing data, execute step 703; otherwise, execute step 704.

[0215] In this step, the memory interval where the data to be written is judged to have a vacant memory interval indicates whether the memory interval allocated for the data to be written is insufficient. For example, when [4k, 128k) data needs to be written, but the current data segment only has [4k, 64k), then a 64k memory interval needs to be taken out from the memory pool to fill the memory gap of [64k, 128k).

[0216] Step 703: Allocate a memory interval of corresponding size in the memory pool.

[0217] For the specific implementation process of this step, please refer to the above step 702.

[0218] After allocating a memory interval of a corresponding size in the memory pool, the process returns to step 702 until there is no vacant memory interval for writing data.

[0219] Step 704: Find all existing memory intervals according to the memory interval to be written.

[0220] After writing data to a vacant memory interval, search for an existing memory interval in the memory pool.

[0221] Step 705: Perform splitting processing according to the status and length of the existing memory interval.

[0222] In order to reduce the length of data when flushing dirty data and improve the efficiency of flushing dirty data, the existing data segments are split as needed. For example, when the data of [64k, 128k) needs to be written, but there is a data segment [4k, 128k) in the clean state, it needs to be split into a data segment [4k, 64k) in the clean state and a dirty data segment [64k, 128k). Therefore, when flushing dirty data, only 64k of data in [64k, 128k) needs to be flushed to the disk storage space, and the data segment [4k, 64k) does not need to be flushed dirty.

[0223] Step 706: Fill the data to be written into the corresponding position of the memory interval.

[0224] Fill the data to be written into the corresponding memory interval and mark these data segments as dirty data.

[0225] Step 707: Merge the memory intervals.

[0226] In this step, the memory data connected head to tail can be merged according to actual needs.

[0227] Step 708: Unlock the file write lock.

[0228] Those skilled in the art will appreciate that, in the above-described specific implementation method, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0229] Based on the data caching method proposed in the above embodiment, the present application embodiment also proposes a memory processing method, such as Figure 8 As shown, the memory processing method includes:

[0230] Step 801: Receive a memory release request.

[0231] The memory release request includes a first memory interval of the memory to be released; the memory to be released is located in a memory pool, and the memory pool includes a main memory block and a backup memory block; the main memory block includes a first fixed block, and the first fixed block is the largest free fixed block in the main memory block; when the application space required for the data cache is greater than the size of the first fixed block, the memory occupied by the data cache includes the memory in the backup memory block.

[0232] Step 802: Mark the first memory interval as a memory interval that can be used for data caching.

[0233] Corresponding to the data caching method given in the above embodiment, the data in the memory to be released in this embodiment is cached based on the above data caching method. Based on the above embodiment, this embodiment provides a memory release method for the memory pool. When there is unnecessary data in the memory pool, the corresponding memory release can be achieved by the method given in this embodiment. In the related art, when memory data needs to be released, the data in the memory to be released needs to be deleted from the memory interval to improve the resource utilization of the memory.

[0234] In this embodiment, after receiving a memory release request, the first memory interval of the memory to be released is obtained by parsing the memory release request, wherein the first memory interval can specifically be a memory address interval corresponding to the memory to be released. Based on the first memory interval, the first memory interval is marked as a memory interval that can be used for data caching. For example, the first memory interval is marked as "free" without deleting the data in the first memory interval. When it is necessary to rewrite the data to be cached in the first memory interval, the data to be cached can be directly written in the first memory interval, and the original data in the first memory interval is overwritten and replaced by the new data to be cached.

[0235] Based on the data caching method given in the above embodiment, when a memory release request is received, the data segment layer searches for the corresponding data segment, releases the address of the data to be released, that is, the first memory interval, deletes the data segment, and then adds the first memory interval to the free list in the memory pool to indicate that the current first memory interval is a free memory interval and can be used for data caching. Specifically, the first memory interval can also be marked to indicate that the current first memory interval is a free memory interval and can be used for data caching.

[0236] It can be seen that, through the method of this embodiment, there is no need to delete the data in the memory to be released. It is only necessary to mark the first memory interval of the memory to be released to achieve the effect of memory release. The new data overwrites the old data instead of deleting the old data, thereby improving the efficiency of memory release.

[0237] In practical applications, steps 801 to 802 may be implemented based on a processor, and the processor may be at least one of ASIC, DSP, DSPD, PLD, FPGA, CPU, controller, microcontroller, and microprocessor.

[0238] In some embodiments, after marking the first memory interval as a memory interval that can be used for data caching, the above method also includes: determining whether the first memory interval contains a first address where the main memory block and the backup memory block intersect; when the first memory interval does not contain the first address, determining whether there is an adjacent second memory interval to the first memory interval; wherein the second memory interval is an idle memory interval; when the second memory interval exists, merging the marked first memory interval with the second memory interval to obtain a fixed block in the main memory block.

[0239] According to the above embodiment, since the size of the application space for the data to be cached is determined by the minimum memory allocation unit, the size of the first memory interval is also determined by the minimum memory allocation unit.

[0240] In some embodiments, the memory release request also includes the size of the memory to be released. When there is no adjacent second memory interval in the first memory interval, the above method also includes: when the size of the memory to be released is equal to the size of any fixed block in the main memory block, using the first memory interval as a fixed block in the main memory block.

[0241] When the size of the memory to be released is equal to the size of any fixed block in the main memory block, directly using the first memory interval as a fixed block in the main memory block can improve the memory release speed.

[0242] In some embodiments, after marking the first memory interval as a memory interval that can be used for data caching, the method further includes: when the first memory interval contains a first address where the main memory block and the spare memory block intersect, dividing the marked first memory interval into the spare memory block.

[0243] Combination Figure 2 It can be seen from the schematic diagram of the memory pool structure that when the first memory interval includes the first address, directly dividing the first memory interval into spare memory blocks can avoid the first memory interval from being split and can realize rapid release of memory.

[0244] When the first memory interval includes the first address, it means that the starting address of the first memory interval is located in the main memory block, and the ending address of the first memory interval is located in the spare memory block. After the first memory interval is divided into the spare memory block, the starting address of the spare memory block (i.e., the first address) will be migrated, and the starting address of the first memory interval after release will be used as the starting address of the spare memory block (i.e., the first address).

[0245] In some embodiments, the method further includes: dividing the first memory interval into a plurality of fixed blocks in order from large to small fixed blocks.

[0246] In practical applications, the first memory interval can be released in order from large to small fixed blocks to obtain multiple fixed blocks of different sizes. For example, when the size of the memory to be released is not equal to the size of any fixed block, the first memory interval can be divided into multiple fixed blocks in sequence according to the method of this embodiment; or, when the number of free fixed blocks in the free list is insufficient, the first memory interval can be divided into multiple fixed blocks in sequence according to the method of this embodiment to increase the number of free fixed blocks in the free list.

[0247] Reference Figure 2 As shown in the schematic diagram of the memory pool structure, when the size of the memory to be released is 204k, the size to be released is first determined to be 128k according to the fixed block size, and the memory interval corresponding to 128k in the first memory interval is released; the size of the memory to be released after the release becomes 76k, and at this time, according to the fixed block size, the size to be released this time is determined to be 64k, and then the memory interval corresponding to 64k in the first memory interval is released; the size of the memory to be released after the release becomes 12k, and at this time, according to the fixed block size, the size to be released this time is determined to be 8k, and then the memory interval corresponding to 8k in the first memory interval is released; the size of the memory to be released after the release becomes 4k, and at this time, according to the fixed block size, the memory interval corresponding to the remaining 4k in the first memory interval is directly released, and the release of the first memory interval is completed in sequence. It can be seen that 204k of the memory to be released is released into fixed blocks of 128k, 64k, 8k and 4k in size in sequence.

[0248] Through the first memory interval release method provided in this embodiment, the first memory interval can be released in sequence to obtain fixed blocks of different sizes, which is convenient for subsequent data caching and can maintain the number of fixed blocks in the free list. Fixed blocks are released in order from large to small, which can ensure that the released fixed blocks contain both large fixed blocks and small fixed blocks, can meet the direct storage of data of different application space sizes, and improve data storage speed.

[0249] In combination with the above embodiments, a data caching method is provided. Fig. 9 A memory pool memory release logic diagram is shown, such as Fig. 9 As described above, taking the case where the size of the memory to be released is equal to the fixed block size in the internal pool as an example, the memory pool memory release logic is as follows:

[0250] Step 901: Release the fixed block.

[0251] Step 902: according to the released memory interval, find and merge adjacent free fixed blocks in the interval to obtain continuous free fixed blocks G.

[0252] In this step, the released memory interval may be the first memory interval in the above embodiment, wherein the released memory interval in this step is the memory interval of the fixed block to be released. The adjacent free fixed block corresponds to the second memory interval in the above embodiment.

[0253] When there is no free fixed block adjacent to the released memory interval, directly execute the following steps.

[0254] Step 903: Determine whether the continuous free fixed blocks contain the first address.

[0255] If the continuous free fixed blocks contain the first address, execute step 904; otherwise, execute step 905.

[0256] The first address in this step corresponds to the above embodiment, and represents the address where the main memory block and the spare memory block intersect.

[0257] Step 904: Release the free fixed blocks to the spare memory blocks.

[0258] After releasing the free fixed blocks to the spare memory blocks, step 910 is executed.

[0259] Step 905: Determine whether all the currently continuous free fixed blocks have been recorded in the free list.

[0260] If all the currently continuous free fixed blocks have been recorded in the free list, execute step 910 ; otherwise, execute step 906 .

[0261] Step 906: Determine whether the number of currently free fixed blocks is equal to the number of fixed blocks preset in the free list.

[0262] When the number of currently free fixed blocks is equal to the number of fixed blocks preset in the free list, step 907 is executed; otherwise, step 908 is executed.

[0263] When the fixed blocks in the free list are set to a fixed value, if the number of currently free fixed blocks is equal to the number of fixed blocks preset in the free list, it means that the number of currently free fixed blocks meets the number requirement of fixed blocks in the free list. Otherwise, it means that the number of currently free fixed blocks is less than the number requirement of fixed blocks in the free list, indicating that the number of currently larger fixed blocks may be large, and the released fixed blocks need to be split.

[0264] Step 907: Add the free fixed block to the free list.

[0265] When the number of current free fixed blocks meets the number requirement of fixed blocks in the free list, the free fixed blocks obtained after release are directly added to the free list.

[0266] After the idle fixed blocks are added to the idle list, step 905 is executed until all the currently continuous idle fixed blocks have been recorded in the idle list.

[0267] Step 908: Get the largest memory block x in the free list that is less than or equal to G.

[0268] When the number of currently idle fixed blocks does not meet the number requirement of fixed blocks preset in the idle list, the released fixed blocks are split in combination with the method provided in the above embodiment.

[0269] Step 909: Split the released fixed block, one of which is of size x, and add this memory to the free list.

[0270] According to the method provided in the above embodiment, the released fixed blocks are split in order from large to small, until the number requirement of fixed blocks preset in the free list is met.

[0271] After this step, the process returns to step 905 until all the currently continuous free fixed blocks have been recorded in the free list.

[0272] Step 910: Release completed.

[0273] pass Fig. 9 The memory pool memory release logic shown, when the number of fixed blocks in the memory list is constant, can maintain the fixed blocks in the memory list at a fixed number through the above steps and the method provided in the above embodiment, which helps to ensure the normal operation of data caching.

[0274] Based on the data caching method proposed in the above-mentioned embodiment, the embodiment of the present application further proposes a data caching system, which includes a memory pool layer and a data segment layer.

[0275] A memory pool layer is used to implement data caching; wherein the memory pool layer includes a memory pool, the memory pool includes a main memory block and a backup memory block, the main memory block includes a plurality of fixed blocks of different sizes, and the fixed block is a preset storage space in the main memory block; the memory pool is used to receive a data cache request; the data cache request includes the size of the application space for the data to be cached; the application space indicates the space occupied by the memory requested by the data to be cached; the size of the application space is compared with the size of the first fixed block; the first fixed block is the largest free fixed block in the main memory block; when the size of the application space is larger than the size of the first fixed block, search for available memory from the backup memory block.

[0276] The data segment layer is used to manage the memory addresses of data in the memory pool; it maps discontinuous physical addresses in the memory pool to continuous logical addresses.

[0277] The memory pool layer provided in the embodiment of the present application mainly includes a memory pool, and the memory pool is specifically used to implement the data caching method provided in the above embodiment.

[0278] The memory pool layer is located at the bottom layer of the data cache system and is used to cache data. The management of the memory pool in the memory pool layer is implemented by an algorithm, which can achieve fast allocation and release of data cache and effectively control the size of the total data cache to avoid uncontrollable total memory size.

[0279] The data segment layer is the upper layer of the memory pool layer. The data segment layer is used to implement the method given in the above embodiment. In addition, when the memory space of the memory pool is close to the usage limit and the memory pool cannot allocate the required continuous memory intervals at one time, the discontinuous memory intervals can be linked together through the data segment layer, and the difference caused by the discrete physical address can be shielded from the upper layer, and the actually discrete physical address can be accessed normally through the continuous logical address of the file.

[0280] In some embodiments, the data cache system further includes a monitoring layer for controlling the data size in the memory pool to be smaller than a threshold.

[0281] The monitoring layer is the top layer in the data cache system. In this application, a threshold is set when the memory pool is initialized, and the threshold is used to ensure that the size of the cached data of the file cannot exceed the set threshold size. In this way, during the data caching process, the cached data can be controlled to avoid the cached data being too large, occupying the system memory and affecting the normal operation of the system.

[0282] In addition, if Fig.10As shown, the data cache system also includes a file layer. The file layer is located above the data segment layer and below the monitoring layer.

[0283] The file layer is used to manage different memory intervals within the same file provided by the data segment layer. When a file is read or written, different memory intervals within the file are read or written. Different memory intervals exist in different states and are managed through the file layer. When file reading and writing overlap, the file layer will perform sorting to ensure data consistency.

[0284] It can be seen that the file layer mainly controls the reading and writing of files, mainly corresponding to Figure 5 , Figure 6 and Figure 7 The related logical operations shown include file reading and writing operations, as well as background dirty flushing logic and clean data elimination. The main problem solved by the file layer is lock logic control in concurrent scenarios to ensure data consistency. Since there are few actual application scenarios where a file is written by multiple applications at the same time, a read-write lock is added to each file through the file layer to ensure that a single file can be read concurrently but can only be written serially.

[0285] The monitoring layer located above the file layer is also used to manage the file data provided by the file layer, the usage status of the memory in the memory pool, and record the size of all data segments in different states, etc., to ensure that the dirty data does not exceed the set threshold, flush the dirty data to the disk storage space, eliminate the clean data, ensure that the cached data space does not exceed the maximum limit of the memory pool, and make the memory pool work in a state with the highest allocation efficiency.

[0286] In addition, in the above embodiment, the security of cached data is guaranteed by the upper layer application. For example, the vim application opens an existing file, edits the content, and then exits after saving the edited content with the command wq. In this process, the application calls the cache read interface, then calls the cache write interface, and finally calls the cache dirty flush interface. Only when the dirty flush interface returns successfully will the edited dirty data be actually written to the disk, and the data is safe at this time. When the file is opened again, the previously edited memory can be read out again.

[0287] Based on the data caching method proposed in the above embodiment, the embodiment of the present application also proposes a data caching device, such as Fig.11 As shown, Fig.11 A schematic diagram of the structure of a data cache device is shown, the device comprising:

[0288] The first receiving module 1101 is used to receive a data cache request; the data cache request includes the size of the application space for the data to be cached; the application space indicates the memory space occupied by the data to be cached.

[0289] The first processing module 1102 is used to compare the size of the application space with the size of the first fixed block; when the size of the application space is larger than the size of the first fixed block, search for available memory from the spare memory block of the memory pool; wherein the first fixed block is the largest free fixed block in the main memory block of the memory pool; the memory pool is used to implement data caching, and the fixed block is a preset storage space in the main memory block; the main memory block includes multiple fixed blocks of different sizes.

[0290] In practical applications, the first receiving module 1101 and the first processing module 1102 can be implemented based on a processor and a communication device.

[0291] In some embodiments, when the size of the requested space is less than or equal to the size of the first fixed block, the first processing module 1102 is further configured to search for available memory from the main memory block.

[0292] In some embodiments, when the size of the application space is not equal to the size of each fixed block in the main memory block, the first processing module 1102 is specifically used to search for a second fixed block from the main memory block; the size of the second fixed block is larger than the size of the application space; the second fixed block is split to obtain a first memory space and a second memory space; wherein the size of the first memory space is equal to the size of the application space; the data to be cached is placed in the first memory space, and the second memory space is divided into spare memory blocks.

[0293] In some embodiments, the first processing module 1102 is further configured to place the data to be cached in the third fixed block when there is a third fixed block in the main memory block whose size is equal to the requested space.

[0294] In some embodiments, after searching for available memory from the spare memory block of the memory pool, the first processing module 1102 is also used to split the application space into multiple subspaces when the size of the application space is larger than the size of the preset condition memory in the spare memory block, and search for available space in the main memory block and the spare memory block based on the size of each subspace in the multiple subspaces; wherein the preset condition memory represents the largest continuous and free memory.

[0295] In some embodiments, the first processing module 1102 is also used to return the memory address of the data to be cached in the memory pool to the data segment layer; wherein the data segment layer is used to manage the memory address of the data in the memory pool and map the discontinuous physical addresses in the memory pool to continuous logical addresses.

[0296] In some embodiments, the first processing module 1102 is also used to obtain first dirty data to be flushed; wherein the first dirty data to be flushed includes at least two groups of dirty data to be flushed, and there is an idle memory interval between at least two groups of dirty data to be flushed; read back the first data from the disk; the storage interval of the first data includes the storage interval of the first dirty data to be flushed; fill the idle memory interval between at least two groups of dirty data to be flushed with data based on the first data to obtain second dirty data to be flushed; flush the second dirty data to be flushed to the disk storage space.

[0297] In some embodiments, the first processing module 1102 is specifically used to flush the second dirty data to be flushed to the disk storage space after waiting for the third dirty data to be flushed to the disk storage space when there is third dirty data to be flushed being flushed; wherein the third dirty data to be flushed and the second dirty data to be flushed have overlapping storage intervals.

[0298] In some embodiments, the first processing module 1102 is also used to obtain a read request for second data; wherein the read request for second data includes a first disk interval corresponding to the second data; the read request is used to read data from the disk storage space to a memory pool; obtain the second disk interval corresponding to the third data currently read back from the disk, and when the first disk interval overlaps with the second disk interval, wait for the third data to be read back to be completed, and then read back the fourth data to the memory pool; wherein the disk interval corresponding to the fourth data is different from the second disk interval.

[0299] It should be noted that the description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the same method embodiment. For technical details not disclosed in the device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0300] Based on the memory processing method proposed in the above embodiment, the present application embodiment also proposes a memory processing device, such as Fig.12 As shown, Fig.12 A schematic diagram of the structure of a memory processing device is shown, the device comprising:

[0301] The second receiving module 1201 is used to receive a memory release request; the memory release request includes a first memory interval of the memory to be released; the memory to be released is located in a memory pool, and the memory pool includes a main memory block and a spare memory block; the main memory block includes a first fixed block, and the first fixed block is the largest free fixed block in the main memory block; when the application space required for the data cache is greater than the size of the first fixed block, the memory occupied by the data cache includes the memory in the spare memory block.

[0302] The second processing module 1202 is configured to mark the first memory interval as a memory interval that can be used for data caching.

[0303] In practical applications, the second receiving module 1201 and the second processing module 1202 can be implemented based on a processor and a communication device.

[0304] In some embodiments, after marking the first memory interval as a memory interval that can be used for data caching, the second processing module 1202 is further used to determine whether the first memory interval contains a first address where the main memory block and the backup memory block intersect; when the first memory interval does not contain the first address, determine whether there is an adjacent second memory interval to the first memory interval; wherein the second memory interval is an idle memory interval; when the second memory interval exists, merge the marked first memory interval with the second memory interval to obtain a fixed block in the main memory block.

[0305] In some embodiments, the memory release request also includes the size of the memory to be released. When there is no adjacent second memory interval in the first memory interval, the second processing module 1202 is also used to use the first memory interval as a fixed block in the main memory block when the size of the memory to be released is equal to the size of any fixed block in the main memory block.

[0306] In some embodiments, after marking the first memory interval as a memory interval that can be used for data caching, the second processing module 1202 is further used to divide the marked first memory interval into a spare memory block when the first memory interval contains a first address where a main memory block and a spare memory block intersect.

[0307] In some embodiments, the second processing module 1202 is further configured to divide the first memory interval into a plurality of fixed blocks in order from large to small fixed blocks.

[0308] It should be noted that in the embodiments of the present application, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium, including a number of instructions to enable a computer device (which can be a terminal, a server, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a disk or an optical disk. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0309] An embodiment of the present application also provides an electronic device. Fig.13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Fig.13 As shown, the electronic device 130 may include:

[0310] The memory 1301 is used to store executable instructions.

[0311] The processor 1302 is used to implement any of the above-mentioned data caching methods or memory processing methods when executing the executable instructions stored in the memory 1301.

[0312] The processor 1302 may be at least one of an ASIC, a DSP, a DSPD, a PLD, a FPGA, a CPU, a controller, a microcontroller, and a microprocessor.

[0313] The above-mentioned computer-readable storage medium or memory 1301 can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory (Flash Memory), a magnetic surface memory, an optical disk, or a compact disc read-only memory (CD-ROM) and other memories; it can also be various terminals including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0314] Correspondingly, an embodiment of the present application further provides a computer storage medium, on which computer executable instructions are stored, and the computer executable instructions are used to implement any one of the data caching methods or memory processing methods provided in the above embodiments.

[0315] Correspondingly, an embodiment of the present application further provides a computer program product, which includes computer executable instructions, and the computer executable instructions are used to implement any one of the data caching methods or memory processing methods provided in the above embodiments.

[0316] In some embodiments, the functions or modules included in the device provided in the embodiments of the present application can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0317] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0318] The methods disclosed in the various method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0319] The features disclosed in the various product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0320] The features disclosed in the various method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0321] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0322] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A data caching method, characterized in that: The method comprises: Receive a data cache request; the data cache request includes the size of the application space for the data to be cached; the application space indicates the memory space occupied by the data to be cached; Compare the size of the application space with the size of the first fixed block; the first fixed block is the largest free fixed block in the main memory block of the memory pool; the memory pool is used to implement data caching, and the fixed block is a preset storage space in the main memory block; the main memory block includes multiple fixed blocks of different sizes; When the size of the requested space is larger than the size of the first fixed block, available memory is searched from the spare memory blocks of the memory pool.

2. The method according to claim 1, characterized in that When the size of the application space is smaller than or equal to the size of the first fixed block, the method further includes: searching for available memory from the main memory block.

3. The method according to claim 2, characterized in that When the size of the application space is not equal to the size of each fixed block in the main memory block, searching for available memory from the main memory block includes: Searching for a second fixed block from the main memory block; the size of the second fixed block is larger than the size of the application space; Splitting the second fixed block to obtain a first memory space and a second memory space; wherein the size of the first memory space is equal to the size of the application space; The data to be cached is placed in the first memory space, and the second memory space is divided into the spare memory blocks.

4. The method according to claim 2, characterized in that: The method further comprises: When there is a third fixed block in the main memory block whose size is equal to that of the requested space, the data to be cached is placed in the third fixed block.

5. The method according to claim 1, characterized in that After searching for available memory from the spare memory blocks in the memory pool, the method further comprises: When the size of the application space is larger than the size of the preset conditional memory in the backup memory block, the application space is split into multiple subspaces, and based on the size of each subspace in the multiple subspaces, available space is searched in the main memory block and the backup memory block; wherein the preset conditional memory represents the largest continuous and free memory.

6. The method according to any one of claims 2 to 5, characterized in that: The method further comprises: Return the memory address of the data to be cached in the memory pool to the data segment layer; wherein the data segment layer is used to manage the memory address of the data in the memory pool and map the discontinuous physical addresses in the memory pool to continuous logical addresses.

7. The method according to claim 1, characterized in that The method further comprises: Acquire first dirty data to be flushed; wherein the first dirty data to be flushed includes at least two groups of dirty data to be flushed, and there is an idle memory interval between the at least two groups of dirty data to be flushed; Read back first data from a disk; the storage interval of the first data includes the storage interval of the first dirty data to be flushed; Filling the idle memory interval between the at least two groups of dirty data to be flushed with data based on the first data to obtain second dirty data to be flushed; The second dirty data to be flushed is flushed to the disk storage space.

8. The method according to claim 7, characterized in that: The step of flushing the second dirty data to be flushed to the disk storage space includes: When there is third dirty data to be flushed, wait for the third dirty data to be flushed to be flushed to the disk storage space, and then flush the second dirty data to be flushed to the disk storage space; wherein, there is dirty data to be flushed whose storage intervals overlap between the third dirty data to be flushed and the second dirty data to be flushed.

9. The method according to claim 1, characterized in that: The method further comprises: Obtaining a read request for second data; wherein the read request for the second data includes a first disk interval corresponding to the second data; the read request is used to read data from the disk storage space to the memory pool; Obtain the second disk range corresponding to the third data currently read back from the disk. When the first disk range overlaps with the second disk range, wait for the third data to be read back and then read back the fourth data to the memory pool; wherein the disk range corresponding to the fourth data is different from the second disk range.

10. A memory processing method, characterized in that: The method comprises: Receive a memory release request; the memory release request includes a first memory interval of memory to be released; the memory to be released is located in a memory pool, the memory pool includes a main memory block and a spare memory block; the main memory block includes a first fixed block, the first fixed block is the largest free fixed block in the main memory block; when the application space required for the data cache is greater than the size of the first fixed block, the memory occupied by the data cache includes the memory in the spare memory block; The first memory interval is marked as a memory interval that can be used for data caching.

11. The method according to claim 10, characterized in that After marking the first memory interval as a memory interval that can be used for data caching, the method further includes: Determining whether the first memory interval includes a first address where the main memory block and the backup memory block intersect; When the first memory interval does not include the first address, determining whether there is a second memory interval adjacent to the first memory interval; wherein the second memory interval is an idle memory interval; When the second memory interval exists, the marked first memory interval and the second memory interval are merged to obtain a fixed block in the main memory block.

12. The method according to claim 11, characterized in that The memory release request also includes the size of the memory to be released. When there is no adjacent second memory interval in the first memory interval, the method further includes: When the size of the memory to be released is equal to the size of any fixed block in the main memory block, the first memory interval is used as a fixed block in the main memory block.

13. The method according to claim 10, characterized in that After marking the first memory interval as a memory interval that can be used for data caching, the method further includes: When the first memory interval includes a first address where the main memory block and the spare memory block intersect, the marked first memory interval is divided into the spare memory block.

14. The method according to claim 10, characterized in that The method further comprises: The first memory interval is divided into a plurality of fixed blocks in order from large to small fixed blocks.

15. A data cache system, characterized in that: The data cache system includes a memory pool layer and a data segment layer, wherein: The memory pool layer is used to implement data caching; the memory pool layer includes a memory pool, the memory pool includes a main memory block and a backup memory block, the main memory block includes a plurality of fixed blocks of different sizes, and the fixed block is a preset storage space in the main memory block; the memory pool is used to receive a data cache request; the data cache request includes the size of the application space for the data to be cached; the application space indicates the space occupied by the memory requested by the data to be cached; the size of the application space is compared with the size of the first fixed block; the first fixed block is the largest free fixed block in the main memory block; when the size of the application space is larger than the size of the first fixed block, the available memory is searched from the backup memory block; The data segment layer is used to manage the memory addresses of the data in the memory pool; and map the discontinuous physical addresses in the memory pool into continuous logical addresses.

16. The system according to claim 15, characterized in that The data cache system further includes a monitoring layer, wherein the monitoring layer is used to control the data size in the memory pool to be smaller than a threshold.

17. A data cache device, characterized in that: The device comprises: A first receiving module is used to receive a data cache request; the data cache request includes the size of the application space for the data to be cached; the application space indicates the space occupied by the memory requested by the data to be cached; The first processing module is used to compare the size of the application space with the size of the first fixed block; when the size of the application space is larger than the size of the first fixed block, search for available memory from the spare memory block of the memory pool; wherein the first fixed block is the largest free fixed block in the main memory block of the memory pool; the memory pool is used to implement data caching, and the fixed block is a preset storage space in the main memory block; the main memory block includes multiple fixed blocks of different sizes.

18. A memory processing device, characterized in that: The device comprises: A second receiving module is used to receive a memory release request; the memory release request includes a first memory interval of the memory to be released; the memory to be released is located in a memory pool, and the memory pool includes a main memory block and a spare memory block; the main memory block includes a first fixed block, and the first fixed block is the largest free fixed block in the main memory block; when the application space required for the data cache is greater than the size of the first fixed block, the memory occupied by the data cache includes the memory in the spare memory block; The second processing module is configured to mark the first memory interval as a memory interval that can be used for data caching.

19. An electronic device, characterized in that: The electronic device comprises a processor and a memory for storing a computer program that can be run on the processor; wherein, The processor is configured to run the computer program to execute the method according to any one of claims 1 to 9, or to execute the method according to any one of claims 10 to 14.

20. A computer storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method described in any one of claims 1 to 9 is implemented, or the method described in any one of claims 10 to 14 is implemented.

21. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the computer program implements the method according to any one of claims 1 to 9 or the method according to any one of claims 10 to 14.

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