Data prefetching method, device and processor

Abstract

The present invention provides a data prefetching method, apparatus and processor, relating to the technical field of computer processors. By responding to a data cache access miss, a data prefetching unit generates a prefetching pattern based on the data cache access miss and records the reorder queue number of the miss instruction, and attaches it to the corresponding prefetching pattern; receives a branch misprediction cancellation signal sent by a branch predictor, and parses the branch misprediction cancellation signal to obtain the reorder queue number of the branch misprediction instruction; matches the reorder queue number of the branch misprediction instruction with the reorder queue number in the prefetching pattern, and cancels the prefetching training and prefetching requests triggered by the branch misprediction instruction in the data prefetching unit according to the matching result. According to the reorder queue number of the miss instruction and the branch misprediction cancellation signal, the present invention cancels the internal logic of the data prefetching unit, making the training of the prefetching unit and the issued prefetching requests more accurate, reducing the demand for memory access bandwidth, and improving the overall performance of the processor.

Description

Technical Field

[0001] The present invention relates to the technical field of computer processors, and in particular, to a data prefetching method, apparatus, and processor. Background Art

[0002] A cache is a storage mechanism designed using the principle of program access locality, and its purpose is to bridge the huge gap between the computing speed of the processor and the storage access speed as much as possible. The prefetching technology is the key to improving the memory access performance of the processor. An important way to improve the access performance of the processor storage system is to reduce the miss rate of cache access. Prefetching is a way to reduce compulsory misses by prefetching cache blocks that the processor may need in advance. Inevitably, prefetching will occupy the storage bandwidth of the processor and generate additional power consumption. In addition, if unnecessary cache blocks are fetched or the prefetching timing is incorrect, it may also cause cache pollution. The memory access miss requests on the mispredicted path of branch instructions will also train the data prefetching unit to generate prefetch requests. This actually trains the data prefetching unit with the memory access addresses that are not really needed by the processor to access the storage system, resulting in incorrect prefetch requests being issued, wasting memory access bandwidth, and reducing the overall performance of the processor. Summary of the Invention

[0003] The present invention provides a data prefetching method, apparatus, and processor, which are used to solve the defect that the memory access instructions on the mispredicted path of branch instructions in the traditional data prefetching method will incorrectly train the data prefetching unit, resulting in incorrect prefetch requests being issued, wasting memory access bandwidth, and reducing the overall performance of the processor.

[0004] The present invention provides a data prefetching method, including:

[0005] In response to a data cache access miss, a data prefetching unit generates a prefetching pattern according to the data cache access miss and records the reorder queue number of the miss instruction corresponding to the data cache access miss, and attaches the reorder queue number to the corresponding prefetching pattern;

[0006] Receiving a branch misprediction cancellation signal sent by a branch predictor, and parsing the branch misprediction cancellation signal to obtain the reorder queue number of the branch misprediction instruction;

[0007] Matching the reorder queue number of the branch misprediction instruction with the reorder queue numbers in all prefetching patterns, and canceling the prefetching training and prefetching requests triggered by the branch misprediction instruction in the data prefetching unit according to the matching result.

[0008] According to the data prefetching method provided by the present invention, the data prefetch unit includes a prefetch training component, a prefetch filtering component, and a prefetch issuing component;

[0009] The prefetch training component is used to receive a cache miss memory access instruction of a data cache, and generate a prefetch pattern according to the cache miss of the data cache access;

[0010] The prefetch filtering component is used to record the access requests or prefetch requests that have been issued by the prefetch training component. When the prefetch training component sends a new prefetch request, it is first filtered by the prefetch filtering component. If it matches successfully with the access requests or prefetch requests in the prefetch filtering component, the new prefetch request with the same address is not issued repeatedly;

[0011] The prefetch issuing component issues a prefetch request to the next-level storage system according to the prefetch pattern generated by the prefetch training component after being filtered by the prefetch filtering component.

[0012] According to the data prefetching method provided by the present invention, each prefetch pattern generated by the prefetch training component includes a reorder queue number corresponding to the cache miss memory access instruction. When a branch misprediction cancellation occurs, according to the reorder queue number of the cancelled branch misprediction instruction, it is judged which or which prefetch pattern trainings are generated by the memory access instructions on the wrong path after the cancelled branch prediction instruction, and only the trainings of the prefetch patterns generated by the cache misses of the memory access instructions after the branch misprediction are cancelled.

[0013] According to the data prefetching method provided by the present invention, each prefetch pattern issued by the prefetch issuing component includes a reorder queue number corresponding to the cache miss memory access instruction;

[0014] When a branch misprediction cancellation occurs, according to the reorder queue number of the cancelled branch misprediction instruction, it is judged which or which pending prefetch requests are generated by the memory access instructions on the wrong path after the cancelled branch prediction instruction, and the prefetch requests generated by the cache misses of the memory access instructions after the branch misprediction are not issued.

[0015] According to the data prefetching method provided by the present invention, the prefetch filtering component is further used to learn the prefetch addresses that have been filtered continuously for multiple times, generate a reverse training signal, and the reverse training signal is used to inhibit the prefetch training of the prefetch training component for the same address.

[0016] According to the data prefetching method provided by the present invention, the reorder queue number is used to identify the order of an instruction in the reorder queue;

[0017] The instructions on the correct path and the mispredicted path are distinguished according to the sequence order of the reorder queue numbers.

[0018] The present invention also provides a data prefetching device, including:

[0019] A data prefetching unit, configured to generate a prefetching pattern according to the data cache access failure and record the reorder queue number of the failure instruction corresponding to the data cache access failure when the data cache access fails, and attach the reorder queue number to the corresponding prefetching pattern;

[0020] A branch predictor, configured to send a branch misprediction cancellation signal to the data prefetching unit;

[0021] The data prefetching unit is further configured to receive the branch misprediction cancellation signal sent by the branch predictor, parse the branch misprediction cancellation signal to obtain the reorder queue number of the branch misprediction instruction; match the reorder queue number of the branch misprediction instruction with the reorder queue numbers in all prefetching patterns, and cancel the prefetching training and prefetching requests triggered by the branch misprediction instruction in the data prefetching unit according to the matching result.

[0022] According to the data prefetching device provided by the present invention, the branch predictor is connected to the data prefetching unit, and is configured to transmit the misprediction cancellation signal and the reorder queue number of the branch misprediction instruction in real time.

[0023] According to the data prefetching device provided by the present invention, the data prefetching unit includes a prefetching training component, a prefetching filtering component, and a prefetching issuing component;

[0024] The prefetching training component is configured to receive the failure memory access instruction of the data cache and generate a prefetching pattern according to the data cache access failure;

[0025] The prefetching filtering component is configured to record the access requests or prefetching requests that have been issued by the prefetching training component. When the prefetching training component sends a new prefetching request, it is first filtered by the prefetching filtering component. If it matches successfully with the access requests or prefetching requests in the prefetching filtering component, the new prefetching request with the same address is not issued repeatedly;

[0026] The prefetching issuing component issues a prefetching request to the next-level storage system according to the prefetching pattern generated by the prefetching training component after being filtered by the prefetching filtering component.

[0027] The present invention also provides a processor, including: the data prefetching device and a cache as described above.

[0028] The data prefetching method, device and processor provided by the present invention respond to a data cache access miss. The data prefetcher generates a prefetch pattern based on the data cache access miss and records the reorder queue number of the invalid instruction corresponding to the data cache access miss, and attaches the reorder queue number to the corresponding prefetch pattern; receives a branch misprediction cancellation signal sent by a branch predictor, and parses the branch misprediction cancellation signal to obtain the reorder queue number of the branch misprediction instruction; matches the reorder queue number of the branch misprediction instruction with the reorder queue numbers in all prefetch patterns, cancels the prefetch training and prefetch requests triggered by the branch misprediction instruction in the data prefetcher according to the matching result, and cancels the internal logic of the data prefetcher according to the reorder queue number of the invalid instruction and the branch misprediction cancellation signal, so that the training of the data prefetcher and the issued prefetch requests are more accurate, reduce the demand for memory access bandwidth, and thus improve the overall performance of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 is a flowchart of the data prefetching method provided by the embodiment of the present invention;

[0031] Figure 2 is a schematic diagram of the branch prediction error cancellation data prefetching logic provided by the embodiment of the present invention.

[0032] Figure 3 is a schematic diagram of the functional structure of the data prefetching device provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] To make the objectives, technical solutions and advantages of the present invention clearer, the following clearly and completely describes the technical solutions in the present invention with reference to the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the scope of protection of the present invention.

[0034] Figure 1 is a flowchart of the data prefetching method provided by the embodiment of the present invention. As Figure 1 shown, the data prefetching method provided by the embodiment of the present invention includes:

[0035] Step 101: In response to a data cache access miss, the data prefetcher generates a prefetch pattern based on the data cache access miss and records the reorder queue number of the instruction corresponding to the data cache access miss, and attaches the reorder queue number to the corresponding prefetch pattern;

[0036] Step 102: Receive a branch misprediction cancellation signal sent by the branch predictor, and parse the branch misprediction cancellation signal to obtain the reorder queue number of the branch misprediction instruction;

[0037] Step 103: Match the reorder queue number of the branch misprediction instruction with the reorder queue numbers in all prefetch patterns, and cancel the prefetch training and prefetch requests triggered by the branch misprediction instruction in the data prefetcher according to the matching result.

[0038] In the embodiment of the present invention, the reorder queue number is used to identify the order of an instruction in the reorder queue; the instructions on the correct path and the mispredicted path are distinguished according to the order of the reorder queue numbers. The reorder queue is a circular queue, and the reorder queue numbers are circularly allocated in the order in which the instructions enter the pipeline. The order of the reorder queue numbers of the instructions after the branch misprediction instruction is arranged after the reorder queue number of the branch misprediction instruction.

[0039] In traditional data prefetch methods, a miss request also trains the data prefetcher to generate a prefetch request. This actually trains the data prefetcher using the memory access address that the real processor does not need to access the memory system, resulting in incorrect prefetch requests being issued, wasting memory access bandwidth, and reducing the overall performance of the processor.

[0040] The data prefetch method provided by the embodiment of the present invention, by responding to a data cache access miss, the data prefetcher generates a prefetch pattern based on the data cache access miss and records the reorder queue number of the instruction corresponding to the data cache access miss, and attaches the reorder queue number to the corresponding prefetch pattern; receives a branch misprediction cancellation signal sent by the branch predictor, and parse the branch misprediction cancellation signal to obtain the reorder queue number of the branch misprediction instruction; matches the reorder queue number of the branch misprediction instruction with the reorder queue numbers in all prefetch patterns, and cancels the prefetch training and prefetch requests triggered by the branch misprediction instruction in the data prefetcher according to the matching result, and cancels the internal logic of the data prefetcher according to the reorder queue number of the miss instruction and the branch misprediction cancellation signal, making the training of the data prefetcher and the issued prefetch requests more accurate, reducing memory access bandwidth, and thus improving the overall performance of the processor.

[0041] Based on any of the above embodiments, as Figure 2As shown, the data prefetcher includes a prefetch training component, a prefetch filtering component, and a prefetch issuing component;

[0042] The prefetch training component is used to receive a cache miss memory access instruction of a data cache, and generate a prefetch pattern according to the data cache access miss;

[0043] The prefetch filtering component is used to record access requests or prefetch requests that the prefetch training component has issued. When the prefetch training component sends a new prefetch request, it first passes through the prefetch filtering component for filtering. If it matches successfully with the access requests or prefetch requests in the prefetch filtering component, the new prefetch request with the same address will not be issued repeatedly;

[0044] The prefetch issuing component issues a prefetch request to the next-level storage system according to the prefetch pattern generated by the prefetch training component after passing through the filtering of the prefetch filtering component.

[0045] In an embodiment of the present invention, the cache miss memory access instructions include Load instructions and Store instructions that miss when accessing the data cache. The prefetch filtering component records the access requests and prefetch requests from the Miss Queue of the next-level storage system that have been issued. When there is a new prefetch request sent by the prefetch training component, it first checks the prefetch filtering component. If the access request or prefetch request with the same address has been issued, the new prefetch request with the same address will not be issued repeatedly to save memory access bandwidth. The prefetch issuing component issues a prefetch request to the next-level storage system according to the prefetch pattern generated by the prefetch training component after passing through the filtering of the prefetch filtering component.

[0046] In an embodiment of the present invention, each prefetch pattern generated by the prefetch training component includes a reorder queue number corresponding to the cache miss memory access instruction. When a branch misprediction cancellation occurs, according to the reorder queue number of the cancelled branch misprediction instruction, it is determined which prefetch pattern or patterns are trained by the memory access instructions on the wrong path after the cancelled branch prediction instruction, and only the training of the prefetch patterns generated by the cache misses of the memory access instructions after the branch misprediction is cancelled.

[0047] In an embodiment of the present invention, each prefetch pattern issued by the prefetch issuing component includes a reorder queue number corresponding to the cache miss memory access instruction; when a branch misprediction cancellation occurs, according to the reorder queue number of the cancelled branch misprediction instruction, it is determined which pending prefetch requests or which are trained by the memory access instructions on the wrong path after the cancelled branch prediction instruction, and the prefetch requests generated by the cache misses of the memory access instructions after the branch misprediction are not issued.

[0048] In the embodiment of the present invention, by reordering the queue number (Reorder Buffer Id, robid), the source path of the prefetch request can be accurately traced, avoiding affecting the prefetch of the correct path.

[0049] In the embodiment of the present invention, the prefetch filtering component is further configured to learn the prefetch addresses that have been filtered continuously for multiple times, generate a reverse training signal, and the reverse training signal is used to inhibit the prefetch training of the prefetch training component for the same address.

[0050] Based on any of the above embodiments, in the branch prediction stage, when the processor encounters a branch misprediction instruction (such as if (x>0)), the branch predictor predicts "jump" and jumps to address A (assuming the correct path should be address B). At this time, the processor starts to execute subsequent instructions out of order according to the predicted path (address A), including data prefetch operations.

[0051] On the wrong path (address A), there is a memory access instruction Load [addr_A_data], but a cache miss occurs when this instruction accesses the data cache. The prefetch training component of the data prefetching unit generates a prefetch pattern based on this miss address and plans to prefetch data at an adjacent address (such as addr_A_data + 64).

[0052] In a subsequent stage of the pipeline, it is found that the branch should actually jump to address B. The branch predictor issues a branch misprediction cancellation signal and attaches the robid of this branch misprediction instruction (for example, robid = 50). After receiving the cancellation signal, the prefetch training component of the data prefetching unit checks the robids corresponding to all the prefetch patterns being trained. If a certain prefetch pattern is generated by an instruction with a robid number after 50 (i.e., an instruction after the branch wrong path), then directly cancel this training.

[0053] In the implementation of the present invention, the robid of Load [addr_A_data] is 55 (belonging to the wrong path), and the prefetch pattern (addr_A_data + 64) generated by it will be marked as invalid.

[0054] The prefetch issuing component originally planned to issue a prefetch request addr_A_data + 64, but after receiving the branch cancellation signal, it checks the robid (55) of this request. Since the instruction with robid 55 is after the instruction with robid 50, it is determined that this request belongs to the wrong path and directly cancels the issuance, avoiding prefetching useless data.

[0055] The processor starts to execute the correct path (address B), and a new memory access instruction Load [addr_B_data] triggers a data cache miss.

[0056] The data prefetcher retrains based on the invalid address of the correct path, generates a new prefetch request (such as addr_B_data + 64), and issues it normally through the filtering component.

[0057] In the embodiment of the present invention, bandwidth waste can be avoided, the prefetch request (addr_A_data + 64) on the wrong path is cancelled, and the storage bandwidth is saved. Moreover, the data on the wrong path will not be prefetched into the cache, avoiding occupying valid data.

[0058] In the data prefetch method provided by the embodiment of the present invention, the data prefetcher only trains and issues requests for the correct path, improving the prefetch hit rate and accelerating program execution; the branch misprediction signal is triggered in real time to ensure that the state of the prefetcher is consistent with the actual execution path of the processor.

[0059] The data prefetch device provided by the present invention will be described below. The data prefetch device described below can be correspondingly referred to the data prefetch method described above.

[0060] Figure 3 is a schematic structural diagram of the data prefetch device provided by the embodiment of the present invention, as Figure 3 shown, the data prefetch device provided by the embodiment of the present invention includes:

[0061] A data prefetcher 301, configured to generate a prefetch mode according to the data cache access failure and record the reorder queue number of the invalid instruction corresponding to the data cache access failure when the data cache access fails, and attach the reorder queue number to the corresponding prefetch mode;

[0062] A branch predictor 302, configured to send a branch misprediction cancellation signal to the data prefetcher;

[0063] The data prefetcher 301 is further configured to receive the branch misprediction cancellation signal sent by the branch predictor, parse the branch misprediction cancellation signal to obtain the reorder queue number of the branch misprediction instruction; match the reorder queue number of the branch misprediction instruction with the reorder queue numbers in all prefetch modes, and cancel the prefetch training and prefetch requests triggered by the branch misprediction instruction in the data prefetcher according to the matching result.

[0064] In the example of the present invention, the branch predictor is connected to the data prefetcher for real-time transmission of the misprediction cancellation signal and the reorder queue number of the branch misprediction instruction.

[0065] In an embodiment of the present invention, the branch misprediction cancellation signal of the branch predictor is connected to the prefetch training component and the prefetch issuing component of the data prefetch unit. When a branch misprediction occurs for a branch mispredicted instruction, the branch misprediction signal is sent to the data predictor, and the data predictor cancels the prefetch training and prefetch issuing according to the branch misprediction signal, so as to avoid the incorrect training of the data prefetch unit caused by the memory access instruction failure (Miss) on the branch mispredicted path, and thus issue an incorrect prefetch request.

[0066] In an embodiment of the present invention, the data prefetch unit includes a prefetch training component, a prefetch filtering component, and a prefetch issuing component;

[0067] The prefetch training component is used to receive the memory access instruction that fails in the data cache, and generate a prefetch pattern according to the data cache access failure;

[0068] The prefetch filtering component is used to record the access requests or prefetch requests that have been issued by the prefetch training component. When the prefetch training component sends a new prefetch request, it first passes through the prefetch filtering component for filtering. If it matches successfully with the access requests or prefetch requests in the prefetch filtering component, the new prefetch request with the same address will not be issued repeatedly;

[0069] The prefetch issuing component issues a prefetch request to the next-level storage system according to the prefetch pattern generated by the prefetch training component after passing through the filtering of the prefetch filtering component.

[0070] The data prefetch device provided by the embodiment of the present invention, by responding to the data cache access failure, the data prefetch unit generates a prefetch pattern according to the data cache access failure and records the reorder queue number of the invalidation instruction corresponding to the data cache access failure, and attaches the reorder queue number to the corresponding prefetch pattern; receives the branch misprediction cancellation signal sent by the branch predictor, and parses the branch misprediction cancellation signal to obtain the reorder queue number of the branch mispredicted instruction; matches the reorder queue number of the branch mispredicted instruction with the reorder queue numbers in all prefetch patterns, cancels the prefetch training and prefetch requests triggered by the branch mispredicted instruction in the data prefetch unit according to the matching result, and cancels the internal logic of the data prefetch unit according to the reorder queue number of the invalidation instruction and the branch misprediction cancellation signal, so that the training of the data prefetch unit and the issued prefetch requests are more accurate, reduce the demand for memory access bandwidth, and thus improve the overall performance of the processor.

[0071] An embodiment of the present invention further provides a processor, including: the data prefetch device and cache as described in the above embodiment.

[0072] Instructions for accessing the memory system in traditional processors, including load instructions and store instructions, will access the data cache (DCache). For load instructions and store instructions, it is possible to cause data cache access misses. The miss request will train the data prefetcher to generate a prefetch request.

[0073] High-performance superscalar processors use out-of-order pipeline technology. As a result, the problem of branch mis-prediction will occur. When the processor is executing out of order, the memory access instructions accessing the data cache may come from the branch mis-prediction path, resulting in misses of the memory access instructions on the branch mis-prediction path, which wrongly trains the data prefetcher. In fact, the data prefetcher is trained with the memory access addresses that are not the actual ones required by the processor to access the memory system, resulting in the issuance of incorrect prefetch requests.

[0074] In the embodiments of the present invention, each instruction of the processor has a reorder queue number that can identify the instruction order. When a branch is cancelled, the robid of the branch mis-prediction instruction that has a branch mis-prediction is sent to the data prefetcher together with the branch mis-prediction signal.

[0075] The prefetch training component and the prefetch issuing component of the data prefetcher also attach the robid corresponding to the memory access miss instruction that generates each prefetch mode when generating each prefetch mode. When a branch mis-prediction is cancelled, according to the robid number of the cancelled branch mis-prediction instruction, it is determined which prefetch mode trainings are generated by the memory access instructions on the wrong path after the cancelled branch prediction instruction, and only the prefetch mode trainings generated by the misses of the memory access instructions after the branch mis-prediction are cancelled.

[0076] Similarly, for the prefetch issuing component, when a branch mis-prediction is cancelled, according to the robid number of the cancelled branch mis-prediction instruction, it is determined which pending prefetch requests are generated by the memory access instructions on the wrong path after the cancelled branch prediction instruction, and only the prefetch requests generated by the prefetch mode trainings generated by the misses of the memory access instructions after the branch mis-prediction are no longer issued.

[0077] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0078] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data prefetching method, characterized in that, including: In response to a data cache access miss, a data prefetcher generates a prefetch pattern based on the data cache access miss and records the reorder queue number of the mispredicted instruction corresponding to the data cache access miss, and attaches the reorder queue number to the corresponding prefetch pattern; The reorder queue number is used to identify the order of an instruction in the reorder queue; instructions on the correct path and the mispredicted path are distinguished according to the order of the reorder queue numbers; the reorder queue is a circular queue, and the reorder queue numbers are cyclically allocated in the order in which instructions enter the pipeline, and the order of the reorder queue numbers of the instructions after a branch mispredicted instruction is arranged after the reorder queue number of the branch mispredicted instruction; Receiving a branch misprediction cancellation signal sent by a branch predictor, and parsing the branch misprediction cancellation signal to obtain the reorder queue number of the branch mispredicted instruction; Matching the reorder queue number of the branch mispredicted instruction with the reorder queue numbers in all prefetch patterns, and canceling the prefetch training and prefetch requests triggered by the branch mispredicted instruction in the data prefetcher according to the matching result.

2. The data prefetching method according to claim 1, wherein The data prefetcher includes a prefetch training component, a prefetch filtering component, and a prefetch issuing component; The prefetch training component is configured to receive a cache miss memory access instruction of a data cache and generate a prefetch pattern based on the data cache access miss; The prefetch filtering component is configured to record the access requests or prefetch requests already issued by the prefetch training component. When the prefetch training component sends a new prefetch request, it is first filtered by the prefetch filtering component. If it matches successfully with the access requests or prefetch requests in the prefetch filtering component, the new prefetch request with the same address is not issued repeatedly; The prefetch issuing component issues a prefetch request to the next-level storage system according to the prefetch pattern generated by the prefetch training component after being filtered by the prefetch filtering component.

3. The data prefetching method according to claim 2, wherein Each prefetch pattern generated by the prefetch training component includes the reorder queue number corresponding to the cache miss memory access instruction. When a branch misprediction cancellation occurs, according to the reorder queue number of the cancelled branch mispredicted instruction, it is determined which prefetch pattern or patterns are trained by the memory access instructions on the wrong path after the cancelled branch prediction instruction, and only the training of the prefetch patterns generated by the cache misses of the memory access instructions after the branch misprediction is cancelled.

4. The data prefetching method according to claim 2, wherein Each prefetch pattern issued by the prefetch issuing component includes the reorder queue number corresponding to the cache miss memory access instruction; When a branch misprediction cancellation occurs, according to the reorder queue number of the cancelled branch mispredicted instruction, it is determined which prefetch request or requests to be issued are trained by the memory access instructions on the wrong path after the cancelled branch prediction instruction, and the prefetch requests generated by the cache misses of the memory access instructions after the branch misprediction are not issued.

5. The data prefetching method according to claim 2, wherein The prefetch filtering component is further configured to learn the prefetch addresses that have been filtered continuously for multiple times to generate a reverse training signal, and the reverse training signal is used to inhibit the prefetch training of the same address by the prefetch training component.

6. A data prefetching device, characterized in that, including: A data prefetcher, which is used to generate a prefetch pattern according to the data cache access miss when the data cache access fails, record the reorder queue number of the mispredicted instruction corresponding to the data cache access miss, and append the reorder queue number to the corresponding prefetch pattern; the reorder queue number is used to identify the order of the instruction in the reorder queue; distinguish the instructions on the correct path and the mispredicted path according to the sequence order of the reorder queue numbers; the reorder queue is a circular queue, and the reorder queue numbers are cyclically allocated in the order of the instructions entering the pipeline, and the order of the reorder queue numbers of the instructions after the branch misprediction instruction is arranged after the reorder queue number of the branch misprediction instruction; A branch predictor, which is used to send a branch misprediction cancellation signal to the data prefetcher; The data prefetcher is further used to receive the branch misprediction cancellation signal sent by the branch predictor, parse the branch misprediction cancellation signal to obtain the reorder queue number of the branch misprediction instruction; match the reorder queue number of the branch misprediction instruction with the reorder queue numbers in all prefetch patterns, and cancel the prefetch training and prefetch requests triggered by the branch misprediction instruction in the data prefetcher according to the matching result.

7. The data prefetching device according to claim 6, wherein The branch predictor and the data prefetcher are connected by a bus, and are used to transmit the misprediction cancellation signal and the reorder queue number of the branch misprediction instruction in real time.

8. The data prefetching device according to claim 6, wherein The data prefetcher includes a prefetch training component, a prefetch filtering component and a prefetch issuing component; The prefetch training component is used to receive the memory access instruction for the data cache miss, and generate a prefetch pattern according to the data cache access miss; The prefetch filtering component is used to record the access requests or prefetch requests that the prefetch training component has issued. When the prefetch training component sends a new prefetch request, it first passes through the prefetch filtering component for filtering. If it matches successfully with the access requests or prefetch requests in the prefetch filtering component, the new prefetch request with the same address will not be issued repeatedly; The prefetch issuing component issues a prefetch request to the next-level storage system according to the prefetch pattern generated by the prefetch training component after passing through the filtering of the prefetch filtering component.

9. A processor, characterized in that, Comprising: The data prefetch device and cache according to any one of claims 6 to 8.

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