I2C bus detection circuit and semiconductor chip

Abstract

The embodiment of the invention provides a detection circuit of an I2C bus and a semiconductor chip. The circuit comprises a three-stage trigger unit and a logic unit, the three-stage trigger unit samples an SCL signal to obtain a start bit detection signal when an SDA signal is turned to a low level, samples the start bit detection signal to obtain a first reset detection signal when the SCL signal is turned to a low level, and samples the start bit detection signal to obtain a second reset detection signal when the SCL signal is turned to a high level. The logic unit samples the first reset detection signal to obtain a second reset detection signal, pulls down the third reset signal to reset the second reset detection signal when the start bit detection signal is at a high level, and pulls down the first reset signal to reset the start bit detection signal when the first reset detection signal is at a high level. When the second reset detection signal is at a low level, the second reset signal is pulled down to reset the first reset detection signal. According to the circuit, START and STOP can be decoupled to cope with complex working conditions, so that the detection accuracy is improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to an I2C bus detection circuit and a semiconductor chip. Background Art

[0002] The Inter-Integrated Circuit (I2C) is a very popular serial communication bus. The I2C protocol stipulates that the transmission frame needs to start with a start bit (START) and end with a stop bit (STOP). START and STOP can be detected using a high-speed clock detection system or the I2C clock itself. The former has high flexibility but high power consumption, while the latter has low power consumption but is difficult to balance flexibility, robustness and complexity.

[0003] In the prior art, the I2C clock itself is usually used to detect START and STOP, and START is reset based on STOP, which results in a greater risk of frame loss under complex working conditions, for example, the start and end occur continuously, thereby affecting the accuracy of detection. Summary of the invention

[0004] The embodiments of the present disclosure provide an I2C bus detection circuit and a semiconductor chip, which can decouple START and STOP, avoid the problem of insufficient START reset establishment time caused by directly using the SCL signal to reset START, so as to cope with complex working conditions and improve the accuracy of detection.

[0005] In a first aspect, the present disclosure provides an I2C bus detection circuit, comprising: a three-stage trigger unit and a logic unit.

[0006] The three-stage trigger unit is configured to, when the serial data SDA signal flips from a high level to a low level, sample the serial clock SCL signal to obtain a start bit detection signal; when the SCL signal flips from a high level to a low level, sample the start bit detection signal to obtain a first reset detection signal; when the SCL signal flips from a low level to a high level, sample the first reset detection signal to obtain a second reset detection signal.

[0007] The logic unit is configured to, when the start bit detection signal is at a high level, pull down the third reset signal to reset the second reset detection signal, when the first reset detection signal is at a high level, pull down the first reset signal to reset the start bit detection signal, and when the second reset detection signal is at a low level, pull down the second reset signal to reset the first reset detection signal.

[0008] In some embodiments of the present disclosure, the first input terminal of the three-stage trigger unit is connected to the SDA line, the second input terminal of the three-stage trigger unit is connected to the SCL line, the reset terminal of the three-stage trigger unit is connected to the output terminal of the logic unit, the input terminal of the logic unit is connected to the output terminal of the three-stage trigger unit, and the common terminal of the logic unit is connected to the system reset signal.

[0009] The logic unit is further configured to, when the system reset signal is at a high level, pull down the third reset signal when the start bit detection signal is at a high level so that the three-stage trigger unit pulls up the second reset detection signal, and when the first reset detection signal is at a high level, pull down the first reset signal so that the three-stage trigger unit pulls down the start bit detection signal, and when the second reset detection signal is at a low level, pull down the second reset signal so that the three-stage trigger unit pulls down the first reset detection signal; when the system reset signal is at a low level, pull down the first reset signal, the second reset signal and the third reset signal.

[0010] In some embodiments of the present disclosure, the three-stage trigger unit includes a first D trigger, a second D trigger and a third D trigger, and the reset ends of the first D trigger, the second D trigger and the third D trigger are valid at a low level.

[0011] The input end of the first D flip-flop is connected to the SCL line, the clock end of the first D flip-flop is connected to the SDA line, the output end of the first D flip-flop is connected to the input end of the second D flip-flop, the inverting output end of the first D flip-flop is connected to the first input end of the logic unit, and the reset end of the first D flip-flop is connected to the first output end of the logic unit.

[0012] The clock terminal of the second D flip-flop is connected to the SCL line, the output terminal of the second D flip-flop is connected to the input terminal of the third D flip-flop, the inverting output terminal of the second D flip-flop is connected to the second input terminal of the logic unit, and the reset terminal of the second D flip-flop is connected to the second output terminal of the logic unit.

[0013] The clock terminal of the third D flip-flop is connected to the SCL line, the inverting output terminal of the third D flip-flop is connected to the third input terminal of the logic unit, and the reset terminal of the third D flip-flop is connected to the third output terminal of the logic unit.

[0014] The logic unit is configured to determine the third reset signal based on the inverted signal of the start bit detection signal and the system reset signal, determine the first reset signal based on the inverted signal of the first reset detection signal and the system reset signal, and determine the second reset signal based on the second reset detection signal and the system reset signal.

[0015] In some embodiments of the present disclosure, the logic unit includes a first AND gate, a second AND gate and a third AND gate, the first input terminal of the first AND gate is connected to the inverting output terminal of the first D flip-flop, the second input terminal of the first AND gate is connected to the system reset signal, and the output terminal of the first AND gate is connected to the reset terminal of the third D flip-flop.

[0016] The first input terminal of the second AND gate is connected to the inverting output terminal of the second D flip-flop, the second input terminal of the second AND gate is connected to the system reset signal, and the output terminal of the second AND gate is connected to the reset terminal of the first D flip-flop. The first input terminal of the third AND gate is connected to the inverting output terminal of the third D flip-flop, the second input terminal of the third AND gate is connected to the system reset signal, and the output terminal of the third AND gate is connected to the reset terminal of the second D flip-flop.

[0017] In some embodiments of the present disclosure, the three-stage trigger unit includes a first D trigger, a second D trigger and a third D trigger, and the reset ends of the first D trigger, the second D trigger and the third D trigger are valid at a low level.

[0018] The input end of the first D flip-flop is connected to the SCL line, the clock end of the first D flip-flop is connected to the SDA line, the output end of the first D flip-flop is connected to the input end of the second D flip-flop and the first input end of the logic unit, and the reset end of the first D flip-flop is connected to the first output end of the logic unit.

[0019] The clock terminal of the second D flip-flop is connected to the SCL line, the output terminal of the second D flip-flop is connected to the input terminal of the third D flip-flop and the second input terminal of the logic unit, and the reset terminal of the second D flip-flop is connected to the second output terminal of the logic unit.

[0020] A clock terminal of the third D flip-flop is connected to the SCL line, an output terminal of the third D flip-flop is connected to a third input terminal of the logic unit, and a reset terminal of the third D flip-flop is connected to a third output terminal of the logic unit.

[0021] The logic unit is configured to determine the third reset signal based on the start bit detection signal and the system reset signal, determine the first reset signal based on the first reset detection signal and the system reset signal, and determine the second reset signal based on the inverted signal of the second reset detection signal and the system reset signal.

[0022] In some embodiments of the present disclosure, the logic unit includes a first AND gate, a second AND gate, a third AND gate, a first inverter, a second inverter and a third inverter, the input end of the first inverter is connected to the output end of the first D flip-flop, the output end of the first inverter is connected to the first input end of the first AND gate, the second input end of the first AND gate is connected to the system reset signal, and the output end of the first AND gate is connected to the reset end of the third D flip-flop.

[0023] The input end of the second inverter is connected to the output end of the second D flip-flop, the output end of the second inverter is connected to the first input end of the second AND gate, the second input end of the second AND gate is connected to the system reset signal, and the output end of the second AND gate is connected to the reset end of the first D flip-flop. The input end of the third inverter is connected to the output end of the third D flip-flop, the output end of the third inverter is connected to the first input end of the third AND gate, the second input end of the third AND gate is connected to the system reset signal, and the output end of the third AND gate is connected to the reset end of the second D flip-flop.

[0024] In some embodiments of the present disclosure, the detection circuit further includes a clock gating unit, an enable terminal of the clock gating unit is connected to the SCL line, and a clock terminal of the clock gating unit is connected to the SDA line.

[0025] The clock gating unit is configured to pull up the end bit detection signal when the SDA signal flips from a low level to a high level and the SCL signal is at a high level; and pull down the end bit detection signal when the SDA signal flips from a high level to a low level to reset the end bit detection signal.

[0026] In some embodiments of the present disclosure, the clock gating unit includes a latch and a fourth AND gate, the input end of the latch is connected to the SCL line, the enable end of the latch and the first input end of the fourth AND gate are connected to the SDA line, and the output end of the latch is connected to the second input end of the fourth AND gate.

[0027] In some embodiments of the present disclosure, the detection circuit also includes a fifth AND gate, a first input terminal of the fifth AND gate is connected to the SDA line, a second input terminal of the fifth AND gate is used to receive a power-on reset signal, and an output terminal of the fifth AND gate is connected to a clock terminal of the clock gating unit.

[0028] In a second aspect, the present disclosure provides a semiconductor chip, comprising any detection circuit provided in the first aspect.

[0029] In the technical solution of the embodiment of the present disclosure, the detection circuit of the I2C bus includes a three-level trigger unit and a logic unit. When the SDA signal flips from a high level to a low level, the SCL signal is sampled to obtain a start bit detection signal. When the SCL signal flips from a high level to a low level, the start bit detection signal is sampled to obtain a first reset detection signal. When the SCL signal flips from a low level to a high level, the first reset detection signal is sampled to obtain a second reset detection signal. When the start bit detection signal is a high level, the logic unit pulls down the third reset signal to reset the second reset detection signal. When the first reset detection signal is a high level, the first reset signal is pulled down to reset the start bit detection signal. When the second reset detection signal is a low level, the second reset signal is pulled down to reset the first reset detection signal. In this way, the START reset starts at the falling edge of the SCL signal and ends at the next rising edge of the SCL signal, that is, the START is reset after the START is tapped at the falling edge of the SCL signal. START and STOP can be decoupled, and the problem of insufficient START reset establishment time caused by directly using the SCL signal to reset START can be avoided to cope with complex working conditions and improve the accuracy of detection.

[0030] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 Schematic diagram of the start bit and end bit specified for the I2C protocol.

[0033] Figure 2 A schematic diagram of the structure of an I2C bus detection circuit provided in an embodiment of the present disclosure.

[0034] Figure 3 A circuit diagram of an I2C bus detection circuit provided in an embodiment of the present disclosure.

[0035] Figure 4 An operating timing diagram of an I2C bus detection circuit provided in an embodiment of the present disclosure.

[0036] Figure 5 Another working timing diagram of an I2C bus detection circuit provided in an embodiment of the present disclosure.

[0037] Figure 6 A circuit diagram of another I2C bus detection circuit provided by an embodiment of the present disclosure.

[0038] Figure 7 A working timing diagram of another I2C bus detection circuit provided in an embodiment of the present disclosure.

[0039] Figure 8 A circuit diagram of another I2C bus detection circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the disclosed subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0042] Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0043] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0044] The term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0045] In the description of the present disclosure, unless otherwise specified, "plurality" and "at least two" mean more than two (including two), and similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0046] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0047] The I2C bus in the present disclosure includes a serial data (SDA) line and a serial clock (SCL) line, wherein the SDA line can transmit an SDA signal, which can be a high level or a low level, and the SCL line can transmit an SCL signal, which can be a high level or a low level.

[0048] Figure 1 The schematic diagram of the start bit and end bit specified for the I2C protocol is as follows: Figure 1 As shown, when the SCL signal is high and the SDA signal flips from high to low, that is, when the SDA signal has a falling edge, the START condition is met; when the SCL signal is high and the SDA signal flips from low to high, that is, when the SDA signal has a rising edge, the STOP condition is met.

[0049] Figure 2 A schematic diagram of a detection circuit of an I2C bus provided for the implementation of the present disclosure is shown in FIG. Figure 2 As shown, the detection circuit 100 includes a three-stage trigger unit 110 and a logic unit 120 .

[0050] Among them, the first input end of the three-level trigger unit 110 is connected to the SDA line, the second input end of the three-level trigger unit 110 is connected to the SCL line, the reset end of the three-level trigger unit 110 is connected to the output end of the logic unit 120, and the input end of the logic unit 120 is connected to the output end of the three-level trigger unit 110.

[0051] The three-stage trigger unit 110 is configured to, when the SDA signal flips from a high level to a low level, sample the SCL signal to obtain a start bit detection signal Start_det; when the SCL signal flips from a high level to a low level, sample the start bit detection signal Start_det to obtain a first reset detection signal Reset_det1; when the SCL signal flips from a low level to a high level, sample the first reset detection signal Reset_det1 to obtain a second reset detection signal Reset_det2.

[0052] The logic unit 120 is configured to, when the start bit detection signal Start_det is at a high level, pull down the third reset signal Reset3 to reset the second reset detection signal Reset_det2; when the first reset detection signal Reset_det1 is at a high level, pull down the first reset signal Reset1 to reset the start bit detection signal Start_det; when the second reset detection signal Reset_det2 is at a low level, pull down the second reset signal Reset2 to reset the first reset detection signal Reset_det1.

[0053] For example, Figure 3 A circuit diagram of an I2C bus detection circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the three-stage trigger unit 110 includes a first D flip-flop FF1, a second D flip-flop FF2 and a third D flip-flop FF3, and the reset terminals RSTn of the first D flip-flop FF1, the second D flip-flop FF2 and the third D flip-flop FF3 are low level effective.

[0054] The input terminal D of the first D flip-flop FF1 is connected to the SCL line, the clock terminal CK of the first D flip-flop FF1 is connected to the SDA line, the output terminal Q of the first D flip-flop FF1 is connected to the input terminal D of the second D flip-flop FF2, the inverting output terminal Qn of the first D flip-flop FF1 is connected to the first input terminal of the logic unit 120, and the reset terminal RSTn of the first D flip-flop FF1 is connected to the first output terminal of the logic unit 120.

[0055] The clock terminal CK of the second D flip-flop FF2 is connected to the SCL line, the output terminal Q of the second D flip-flop FF2 is connected to the input terminal D of the third D flip-flop FF3, the inverting output terminal Qn of the second D flip-flop FF2 is connected to the second input terminal of the logic unit 120, and the reset terminal RSTn of the second D flip-flop FF2 is connected to the second output terminal of the logic unit 120.

[0056] The clock terminal CK of the third D flip-flop FF3 is connected to the SCL line, the inverting output terminal Qn of the third D flip-flop FF3 is connected to the third input terminal of the logic unit 120 , and the reset terminal RSTn of the third D flip-flop FF3 is connected to the third output terminal of the logic unit 120 .

[0057] For example, the first D flip-flop FF1 can sample at the falling edge of the clock signal, and the SDA line is directly connected to the clock terminal CK of the first D flip-flop FF1. Figure 3 As shown, when the SDA signal flips from a high level to a low level, the clock terminal CK of the first D flip-flop FF1 receives a falling edge of the signal, and the first D flip-flop FF1 samples the SCL signal.

[0058] Alternatively, the first D flip-flop FF1 can sample on the rising edge of the clock signal, and the SDA line is connected to the clock terminal CK of the first D flip-flop FF1 through an inverter. When the SDA signal flips from a high level to a low level, the clock terminal CK of the first D flip-flop FF1 receives the rising edge of the signal, and the first D flip-flop FF1 samples the SCL signal.

[0059] For example, the second D flip-flop FF2 can sample at the falling edge of the clock signal, and the SCL line is directly connected to the clock terminal CK of the second D flip-flop FF2. Figure 3 As shown, when the SCL signal flips from a high level to a low level, the clock terminal CK of the second D flip-flop FF2 receives a falling edge of the signal, and the second D flip-flop FF2 starts detecting the signal Start_det.

[0060] Alternatively, the second D flip-flop FF2 can sample on the rising edge of the clock signal, and the SCL line is connected to the clock terminal CK of the second D flip-flop FF2 through an inverter. When the SCL signal flips from a high level to a low level, the clock terminal CK of the second D flip-flop FF2 receives the rising edge of the signal, and the second D flip-flop FF2 samples the SCL signal.

[0061] For example, the third D flip-flop FF3 can sample at the rising edge of the clock signal, and the SCL line is directly connected to the clock terminal CK of the third D flip-flop FF3. Figure 3 As shown, when the SCL signal flips from a low level to a high level, the clock terminal CK of the third D flip-flop FF3 receives a rising edge of the signal, and the third D flip-flop FF3 samples the first reset detection signal Reset_det1.

[0062] Alternatively, the third D flip-flop FF3 can sample at the falling edge of the clock signal, and the SCL line is connected to the clock terminal CK of the third D flip-flop FF3 through an inverter. When the SCL signal flips from a low level to a high level, the clock terminal CK of the third D flip-flop FF3 receives the falling edge of the signal, and the third D flip-flop FF3 samples the first reset detection signal Reset_det1.

[0063] Below Figure 3 Taking the example that the first D flip-flop FF1 and the second D flip-flop FF2 sample at the falling edge of the clock signal and the third D flip-flop FF3 samples at the rising edge of the clock signal, the working process of the detection circuit 100 is exemplarily described.

[0064] Figure 4 This is a working timing diagram of the detection circuit of the I2C bus provided in the embodiment of the present disclosure. When the I2C bus communicates normally, Figure 4 As shown, at time T1, the SDA signal flips from a high level to a low level, and the SCL signal is a high level, then the clock terminal CK of the first D flip-flop FF1 receives the falling edge of the SDA signal, the input terminal D of the first D flip-flop FF1 receives a high level, and the start bit detection signal Start_det outputted from the output terminal Q of the first D flip-flop FF1 flips from a low level to a high level, and the start bit detection signal Start_det is output to the input terminal D of the second D flip-flop FF2.

[0065] At time T2, the SCL signal flips from a high level to a low level, and the start bit detection signal Start_det is a high level. The clock terminal CK of the second D flip-flop FF2 receives the falling edge of the SCL signal, and the input terminal D of the second D flip-flop FF2 receives a high level. The first reset detection signal Reset_det1 outputted from the output terminal Q of the second D flip-flop FF2 flips from a low level to a high level, and the first reset detection signal Reset_det1 is output to the input terminal D of the third D flip-flop FF3.

[0066] At time T3, the SCL signal flips from low level to high level, and the first reset detection signal Reset_det1 is high level. The clock terminal CK of the third D flip-flop FF3 receives the rising edge of the SCL signal, the input terminal D of the third D flip-flop FF3 receives the high level, and the output terminal Q of the third D flip-flop FF3 outputs a high level.

[0067] For example, see Figure 2 and Figure 3 The common end of the logic unit 120 is connected to the system reset signal Reset_n, and the logic unit 120 includes a first AND gate AND1, a second AND gate AND2 and a third AND gate AND3.

[0068] Among them, Figure 3 As shown, the first input terminal of the first AND gate AND1 is connected to the inverting output terminal Qn of the first D flip-flop FF1, the first input terminal of the second AND gate AND2 is connected to the inverting output terminal Qn of the second D flip-flop FF2, the first input terminal of the third AND gate AND3 is connected to the inverting output terminal Qn of the third D flip-flop FF3, the second input terminal of the first AND gate AND1, the second input terminal of the second AND gate AND2 and the second input terminal of the third AND gate AND3 are connected to the system reset signal Reset_n, the output terminal of the first AND gate AND1 is connected to the reset terminal RSTn of the third D flip-flop FF3, the output terminal of the second AND gate AND2 is connected to the reset terminal RSTn of the first D flip-flop FF1, and the output terminal of the third AND gate AND3 is connected to the reset terminal RSTn of the second D flip-flop FF2.

[0069] The first AND gate AND1 can perform AND calculation on the inverted signal of the start bit detection signal Start_det and the system reset signal Reset_n to obtain the third reset signal Reset3, and provide it to the reset terminal RSTn of the third D flip-flop FF3. The second AND gate AND2 can perform AND calculation on the inverted signal of the first reset detection signal Reset_det1 and the system reset signal Reset_n to obtain the first reset signal Reset1, and provide it to the reset terminal RSTn of the first D flip-flop FF1. The third AND gate AND2 can perform AND calculation on the second reset detection signal Reset_det2 and the system reset signal Reset_n to obtain the second reset signal Reset2, and provide it to the reset terminal RSTn of the second D flip-flop FF2.

[0070] When the system reset signal Reset_n is at a low level, the first reset signal Reset1, the second reset signal Reset2 and the third reset signal Reset3 are all at a low level, the first D flip-flop FF1 is reset, and the start bit detection signal Start_det is pulled down from a high level to a low level, the second D flip-flop FF2 is reset, and the first reset detection signal Reset_det1 is pulled down from a high level to a low level, and the third D flip-flop FF3 is reset, and the second reset detection signal Reset_det2 is pulled up from a low level to a high level.

[0071] When the system reset signal Reset_n is at a high level, continue to refer to Figure 4 At time T1, the inverted signal of the start bit detection signal Start_det output by the inverting output terminal Qn of the first D flip-flop FF1 flips from a high level to a low level, and the third reset signal Reset3 is a low level. The third D flip-flop FF3 is reset, and the second reset detection signal Reset_det2 is pulled up from a low level to a high level.

[0072] At time T2, the inverted signal of the first reset detection signal Reset_det1 output by the inverting output terminal Qn of the second D flip-flop FF2 flips from a high level to a low level, and the first reset signal Reset1 is a low level. The first D flip-flop FF1 starts to reset, and pulls down the start bit detection signal Start_det from a high level to a low level, that is, START starts to reset.

[0073] Therefore, the start bit detection signal Start_det maintains a high level between the falling edge of the SDA signal and the adjacent falling edge of the SCL signal, that is, START is detected from time T1 to time T2, and the falling edge of the SCL signal can reset START. Compared with the prior art of directly using the SCL signal to reset START, the problem of insufficient START reset establishment time can be avoided to cope with complex working conditions, thereby improving the accuracy of detection.

[0074] At time T3, the second reset detection signal Reset_det2 output by the inverting output terminal Qn of the third D flip-flop FF3 flips from a high level to a low level, and the second reset signal Reset2 is a low level. The second D flip-flop FF2 starts to reset, and pulls down the first reset detection signal Reset_det1 from a high level to a low level, and the reset of the first D flip-flop FF1 ends, that is, the START reset ends.

[0075] Therefore, the first reset detection signal Reset_det1 maintains a high level between the falling edge of the SCL signal and the next rising edge of the SCL signal, that is, START is reset from time T2 to time T3, and the rising edge of the SCL signal can reset the first reset detection signal Reset_det1. The high level output by the output terminal Q of the third D flip-flop FF3 lasts for at most one cycle. Even if the START condition is met again within this cycle, since the START reset has been completed at this time, it will not affect the detection of START. Figure 5 , Figure 5 Another working timing diagram of an I2C bus detection circuit provided in an embodiment of the present disclosure.

[0076] like Figure 5 As shown, START is detected from time T1 to time T2, START is reset from time T2 to time T3, START is detected again from time T1' to time T2', and START is reset again from time T2' to time T3'. Therefore, the detection circuit can accurately detect START under the condition of continuous START.

[0077] In this way, when the system reset signal Reset_n is at a high level, the logic unit 120 can pull down the third reset signal Reset3 when the start bit detection signal Start_det is at a high level, so that the three-level trigger unit 110 pulls up the second reset detection signal Reset_det2; when the first reset detection signal Reset_det1 is at a high level, pull down the first reset signal Reset1, so that the three-level trigger unit 110 pulls down the start bit detection signal Start_det; when the second reset detection signal Reset_det2 is at a low level, pull down the second reset signal Reset2, so that the three-level trigger unit 110 pulls down the first reset detection signal Reset_det1.

[0078] When the system reset signal Reset_n is at a low level, the logic unit 120 pulls down the first reset signal Reset1, the second reset signal Reset2, and the third reset signal Reset3, so that the three-stage trigger unit 110 pulls up the second reset detection signal Reset_det2 and pulls down the first reset detection signal Reset_det1 and the start position detection signal Start_det. In this way, the detection and reset of START are independent of the detection and reset of STOP, and START and STOP can be decoupled to cope with complex working conditions, thereby improving the accuracy of detection.

[0079] To sum up, the detection circuit of the I2C bus provided by the present invention starts the START reset at the falling edge of the SCL signal and ends the START reset at the next rising edge of the SCL signal, that is, the START is reset after beating at the falling edge of the SCL signal. This can decouple START and STOP, and can avoid the problem of insufficient START reset establishment time caused by directly using the SCL signal to reset START, so as to cope with complex working conditions and improve the accuracy of detection.

[0080] In some embodiments, Figure 6 A circuit diagram of another I2C bus detection circuit provided by an embodiment of the present disclosure is shown as follows: Figure 6 As shown, the detection circuit 100 further includes a clock gating unit 130 , an enable terminal of the clock gating unit 130 is connected to the SCL line, and a clock terminal of the clock gating unit 130 is connected to the SDA line.

[0081] For example, Figure 6As shown, the clock gating unit 130 includes a latch Latch and a fourth AND gate AND4, the input terminal D of the latch Latch is connected to the SCL line, the enable terminal E of the latch Latch and the first input terminal of the fourth AND gate AND4 are connected to the SDA line, the output terminal Q of the latch Latch is connected to the second input terminal of the fourth AND gate AND4, and the fourth AND gate AND4 can perform an AND operation on the SDA signal and the output signal of the latch Latch to obtain the end bit detection signal Stop_det.

[0082] Continue to see Figure 4 and Figure 5 At time T4, the SCL signal is at a high level, and the SDA signal flips from a low level to a high level. The latch Latch can latch the high level of the SCL signal and transmit it to the fourth AND gate AND4. The end bit detection signal Stop_det calculated by the fourth AND gate AND4 is at a high level, that is, STOP is detected.

[0083] When the SDA signal flips from high level to low level, no matter the SCL signal is high level or low level, the stop bit detection signal Stop_det calculated by the fourth AND gate AND4 is low level, that is, STOP is reset. Figure 4 and Figure 5 As shown, at time T1, the SCL signal is high, the SDA signal flips from high to low, the latch Latch can output the SCL signal, that is, transmit the high level to the fourth AND gate AND4, and the end bit detection signal Stop_det calculated by the fourth AND gate AND4 is low, that is, STOP is reset.

[0084] Therefore, the rising edge of the SDA signal can be used to reset STOP without setting a delay element, which can simplify the circuit structure and is conducive to the digital integration of the circuit.

[0085] Figure 7 The working timing diagram of another I2C bus detection circuit provided by the embodiment of the present disclosure is as follows: Figure 7 As shown, START is detected from time T1 to time T2, START is reset from time T2 to time T3, START is detected again from time T1' to time T2', STOP and START are detected from time T2' to time T3', and STOP can still be detected when START is not reset. Therefore, the detection circuit can accurately detect STOP under the conditions of continuous START, START and STOP.

[0086] In this way, when the SDA signal flips from a low level to a high level and the SCL signal is a high level, the clock gating unit 130 can pull up the end bit detection signal Stop_det; when the SDA signal flips from a high level to a low level, the clock gating unit 130 can pull down the end bit detection signal Stop_det to reset the end bit detection signal Stop_det. The detection and reset of STOP are independent of the detection and reset of START. START and STOP can be further decoupled to cope with complex working conditions, thereby improving the accuracy of detection.

[0087] In some embodiments, Figure 8 A circuit diagram of another I2C bus detection circuit provided by an embodiment of the present disclosure is shown as follows: Figure 8 As shown, the three-stage trigger unit 110 includes a first D flip-flop FF1, a second D flip-flop FF2 and a third D flip-flop FF3, and the reset terminals RSTn of the first D flip-flop FF1, the second D flip-flop FF2 and the third D flip-flop FF3 are low level effective.

[0088] The input terminal D of the first D flip-flop FF1 is connected to the SCL line, the clock terminal CK of the first D flip-flop FF1 is connected to the SDA line, the output terminal Q of the first D flip-flop FF1 is connected to the input terminal D of the second D flip-flop FF2 and the first input terminal of the logic unit 120, and the reset terminal RSTn of the first D flip-flop FF1 is connected to the first output terminal of the logic unit 120.

[0089] The clock terminal CK of the second D flip-flop FF2 is connected to the SCL line, the output terminal Q of the second D flip-flop FF2 is connected to the input terminal D of the third D flip-flop FF3 and the second input terminal of the logic unit 120, and the reset terminal RSTn of the second D flip-flop FF2 is connected to the second output terminal of the logic unit 120.

[0090] A clock terminal CK of the third D flip-flop FF3 is connected to the SCL line, an output terminal Q of the third D flip-flop FF3 is connected to the third input terminal of the logic unit 120 , and a reset terminal RSTn of the third D flip-flop FF3 is connected to the third output terminal of the logic unit 120 .

[0091] The first D flip-flop FF1 , the second D flip-flop FF2 , and the third D flip-flop FF3 may each sample at a falling edge of the clock signal or at a rising edge of the clock signal, and the present disclosure does not impose any specific limitation on this. Figure 8 It is only exemplarily shown that the first D flip-flop FF1 and the second D flip-flop FF2 sample at the falling edge of the clock signal, and the third D flip-flop FF3 samples at the rising edge of the clock signal.

[0092] Continue to see Figure 8The logic unit 120 includes a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a first inverter INV1, a second inverter INV2 and a third inverter INV3, an input end of the first inverter INV1 is connected to the output end Q of the first D flip-flop FF1, an output end of the first inverter INV1 is connected to the first input end of the first AND gate AND1, an output end of the first AND gate AND1 is connected to the reset end RSTn of the third D flip-flop FF3, and a second input end of the first AND gate AND1, a second input end of the second AND gate AND2 and a second input end of the third AND gate AND3 are connected to a system reset signal Reset_n.

[0093] The input end of the second inverter INV2 is connected to the output end Q of the second D flip-flop FF2, the output end of the second inverter INV2 is connected to the first input end of the second AND gate AND2, and the output end of the second AND gate AND2 is connected to the reset end RSTn of the first D flip-flop FF1. The input end of the third inverter INV3 is connected to the output end Q of the third D flip-flop FF3, the output end of the third inverter INV3 is connected to the first input end of the third AND gate AND3, and the output end of the third AND gate AND3 is connected to the reset end RSTn of the second D flip-flop FF2.

[0094] Exemplarily, the first inverter INV1 can invert the start bit detection signal Start_det to obtain an inverted signal of the start bit detection signal Start_det, and the first AND gate AND1 can perform AND calculation on the inverted signal of the start bit detection signal Start_det and the system reset signal Reset_n to obtain a third reset signal Reset3.

[0095] The second inverter INV2 can invert the first reset detection signal Reset_det1 to obtain an inverted signal of the first reset detection signal Reset_det1 , and the second AND gate AND2 can perform AND calculation on the inverted signal of the first reset detection signal Reset_det1 and the system reset signal Reset_n to obtain the first reset signal Reset1 .

[0096] The third inverter INV3 can invert the output signal of the third D flip-flop FF3 to obtain the second reset detection signal Reset_det2, and the third AND gate AND2 can perform AND calculation on the second reset detection signal Reset_det2 and the system reset signal Reset_n to obtain the second reset signal Reset2.

[0097] When the system reset signal Reset_n is at a high level, Figure 4 , Figure 5 and Figure 7As shown, at time T1, the start bit detection signal Start_det outputted from the output terminal Q of the first D flip-flop FF1 is flipped from a low level to a high level, and the inverted signal of the start bit detection signal Start_det outputted by the first inverter INV1 is flipped from a high level to a low level, then the third reset signal Reset3 is a low level, the third D flip-flop FF3 is reset, and the second reset detection signal Reset_det2 is pulled up from a low level to a high level.

[0098] At time T2, the first reset detection signal Reset_det1 output from the output terminal Q of the second D flip-flop FF2 flips from a low level to a high level, and the inverted signal of the first reset detection signal Reset_det1 output by the second inverter INV2 flips from a high level to a low level, then the first reset signal Reset1 is a low level, and the first D flip-flop FF1 starts to reset, pulling the start bit detection signal Start_det from a high level to a low level, that is, START starts to reset.

[0099] At time T3, the output terminal Q of the third D flip-flop FF3 flips from a low level to a high level, and the second reset detection signal Reset_det2 output by the third inverter INV3 flips from a high level to a low level, then the second reset signal Reset2 is a low level, and the second D flip-flop FF2 starts to reset, and pulls down the first reset detection signal Reset_det1 from a high level to a low level, then the reset of the first D flip-flop FF1 ends, that is, the START reset ends.

[0100] When the system reset signal Reset_n is at a low level, the first reset signal Reset1, the second reset signal Reset2 and the third reset signal Reset3 are all at a low level, the first D flip-flop FF1 is reset, and the start bit detection signal Start_det is pulled down from a high level to a low level, the second D flip-flop FF2 is reset, and the first reset detection signal Reset_det1 is pulled down from a high level to a low level, and the third D flip-flop FF3 is reset, and the second reset detection signal Reset_det2 is pulled up from a low level to a high level.

[0101] In this way, the logic unit 120 can determine the third reset signal Reset3 according to the start bit detection signal Start_det and the system reset signal Reset_n, determine the first reset signal Reset1 according to the first reset detection signal Reset_det1 and the system reset signal Reset_n, and determine the second reset signal Reset2 according to the inverted signal of the second reset detection signal Reset_det2 and the system reset signal Reset_n.

[0102] In some embodiments, see Figure 8The detection circuit also includes a fifth AND gate AND5, a first input end of the fifth AND gate AND5 is connected to the SDA line, a second input end of the fifth AND gate AND5 is used to receive the power-on reset signal POR_n, and an output end of the fifth AND gate AND5 is connected to the clock end of the clock gating unit 130.

[0103] Exemplarily, the fifth AND gate AND5 can perform AND calculation on the SDA signal and the power-on reset signal POR_n to obtain the clock signal of the clock gating unit 130, wherein the clock signal of the clock gating unit 130 is an enable signal of the latch Latch and is also an input signal of the fourth AND gate AND4.

[0104] In the case where the power-on reset signal POR_n is at a high level, when the SCL signal is at a high level and the SDA signal flips from a low level to a high level, the clock signal of the clock gating unit 130 output by the fifth AND gate AND5 flips from a low level to a high level, the output signal of the latch Latch is at a high level, and the end bit detection signal Stop_det output by the fourth AND gate AND4 is at a high level. When the SDA signal flips from a high level to a low level, the clock signal of the clock gating unit 130 output by the fifth AND gate AND5 flips to a low level, the enable signal of the latch Latch flips to a low level, and the end bit detection signal Stop_det output by the fourth AND gate AND4 is at a low level.

[0105] When the power-on reset signal POR_n is at a low level, the enable signal of the latch Latch is continuously at a low level, and the stop bit detection signal Stop_det is continuously at a low level.

[0106] An embodiment of the present disclosure further provides a semiconductor chip, comprising the I2C bus detection circuit 100 provided in any of the above embodiments.

[0107] The semiconductor chip provided by the embodiment of the present disclosure includes the I2C bus detection circuit 100 provided by any of the above embodiments, and has the same functional modules and beneficial effects as the I2C bus detection circuit 100, which will not be repeated here.

[0108] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0109] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0110] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A detection circuit for an I2C bus, characterized in that: include: Three-level flip-flop unit and logic unit; The three-stage trigger unit is configured to, when the serial data SDA signal flips from a high level to a low level, sample the serial clock SCL signal to obtain a start bit detection signal; when the SCL signal flips from a high level to a low level, sample the start bit detection signal to obtain a first reset detection signal; when the SCL signal flips from a low level to a high level, sample the first reset detection signal to obtain a second reset detection signal; The logic unit is configured to, when the start bit detection signal is at a high level, pull down the third reset signal to reset the second reset detection signal, when the first reset detection signal is at a high level, pull down the first reset signal to reset the start bit detection signal, and when the second reset detection signal is at a low level, pull down the second reset signal to reset the first reset detection signal.

2. The detection circuit according to claim 1, characterized in that: The first input end of the three-stage trigger unit is connected to the SDA line, the second input end of the three-stage trigger unit is connected to the SCL line, the reset end of the three-stage trigger unit is connected to the output end of the logic unit, the input end of the logic unit is connected to the output end of the three-stage trigger unit, and the common end of the logic unit is connected to the system reset signal; The logic unit is further configured to, when the system reset signal is at a high level, pull down the third reset signal when the start bit detection signal is at a high level so that the three-stage trigger unit pulls up the second reset detection signal, and when the first reset detection signal is at a high level, pull down the first reset signal so that the three-stage trigger unit pulls down the start bit detection signal, and when the second reset detection signal is at a low level, pull down the second reset signal so that the three-stage trigger unit pulls down the first reset detection signal; when the system reset signal is at a low level, pull down the first reset signal, the second reset signal and the third reset signal.

3. The detection circuit according to claim 2, characterized in that: The three-stage trigger unit includes a first D trigger, a second D trigger and a third D trigger, and the reset end of the first D trigger, the reset end of the second D trigger and the reset end of the third D trigger are low level effective; The input end of the first D flip-flop is connected to the SCL line, the clock end of the first D flip-flop is connected to the SDA line, the output end of the first D flip-flop is connected to the input end of the second D flip-flop, the inverting output end of the first D flip-flop is connected to the first input end of the logic unit, and the reset end of the first D flip-flop is connected to the first output end of the logic unit; The clock terminal of the second D flip-flop is connected to the SCL line, the output terminal of the second D flip-flop is connected to the input terminal of the third D flip-flop, the inverting output terminal of the second D flip-flop is connected to the second input terminal of the logic unit, and the reset terminal of the second D flip-flop is connected to the second output terminal of the logic unit; The clock terminal of the third D flip-flop is connected to the SCL line, the inverting output terminal of the third D flip-flop is connected to the third input terminal of the logic unit, and the reset terminal of the third D flip-flop is connected to the third output terminal of the logic unit; The logic unit is configured to determine the third reset signal based on the inverted signal of the start bit detection signal and the system reset signal, determine the first reset signal based on the inverted signal of the first reset detection signal and the system reset signal, and determine the second reset signal based on the second reset detection signal and the system reset signal.

4. The detection circuit according to claim 3, characterized in that: The logic unit includes a first AND gate, a second AND gate and a third AND gate; The first input end of the first AND gate is connected to the inverting output end of the first D flip-flop, the second input end of the first AND gate is connected to the system reset signal, and the output end of the first AND gate is connected to the reset end of the third D flip-flop; A first input terminal of the second AND gate is connected to an inverting output terminal of the second D flip-flop, a second input terminal of the second AND gate is connected to the system reset signal, and an output terminal of the second AND gate is connected to a reset terminal of the first D flip-flop; The first input terminal of the third AND gate is connected to the inverting output terminal of the third D flip-flop, the second input terminal of the third AND gate is connected to the system reset signal, and the output terminal of the third AND gate is connected to the reset terminal of the second D flip-flop.

5. The detection circuit according to claim 2, characterized in that: The three-stage trigger unit includes a first D trigger, a second D trigger and a third D trigger, and the reset end of the first D trigger, the reset end of the second D trigger and the reset end of the third D trigger are low level effective; The input end of the first D flip-flop is connected to the SCL line, the clock end of the first D flip-flop is connected to the SDA line, the output end of the first D flip-flop is connected to the input end of the second D flip-flop and the first input end of the logic unit, and the reset end of the first D flip-flop is connected to the first output end of the logic unit; A clock terminal of the second D flip-flop is connected to the SCL line, an output terminal of the second D flip-flop is connected to an input terminal of the third D flip-flop and a second input terminal of the logic unit, and a reset terminal of the second D flip-flop is connected to a second output terminal of the logic unit; The clock terminal of the third D flip-flop is connected to the SCL line, the output terminal of the third D flip-flop is connected to the third input terminal of the logic unit, and the reset terminal of the third D flip-flop is connected to the third output terminal of the logic unit; The logic unit is configured to determine the third reset signal based on the start bit detection signal and the system reset signal, determine the first reset signal based on the first reset detection signal and the system reset signal, and determine the second reset signal based on the inverted signal of the second reset detection signal and the system reset signal.

6. The detection circuit according to claim 5, characterized in that: The logic unit includes a first AND gate, a second AND gate, a third AND gate, a first inverter, a second inverter and a third inverter; The input end of the first inverter is connected to the output end of the first D flip-flop, the output end of the first inverter is connected to the first input end of the first AND gate, the second input end of the first AND gate is connected to the system reset signal, and the output end of the first AND gate is connected to the reset end of the third D flip-flop; The input end of the second inverter is connected to the output end of the second D flip-flop, the output end of the second inverter is connected to the first input end of the second AND gate, the second input end of the second AND gate is connected to the system reset signal, and the output end of the second AND gate is connected to the reset end of the first D flip-flop; The input end of the third inverter is connected to the output end of the third D flip-flop, the output end of the third inverter is connected to the first input end of the third AND gate, the second input end of the third AND gate is connected to the system reset signal, and the output end of the third AND gate is connected to the reset end of the second D flip-flop.

7. The detection circuit according to any one of claims 1 to 6, characterized in that: Also included is a clock gating unit; The enable end of the clock gating unit is connected to the SCL line, and the clock end of the clock gating unit is connected to the SDA line; The clock gating unit is configured to pull up the end bit detection signal when the SDA signal flips from a low level to a high level and the SCL signal is at a high level; and pull down the end bit detection signal when the SDA signal flips from a high level to a low level to reset the end bit detection signal.

8. The detection circuit according to claim 7, characterized in that: The clock gating unit includes a latch and a fourth AND gate; The input end of the latch is connected to the SCL line, the enable end of the latch and the first input end of the fourth AND gate are connected to the SDA line, and the output end of the latch is connected to the second input end of the fourth AND gate.

9. The detection circuit according to claim 7, characterized in that: Also includes the fifth AND gate; The first input end of the fifth AND gate is connected to the SDA line, the second input end of the fifth AND gate is used to receive a power-on reset signal, and the output end of the fifth AND gate is connected to the clock end of the clock gating unit.

10. A semiconductor chip, characterized in that: The detection circuit comprises the detection circuit described in any one of claims 1 to 9.

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