Current source equivalent method, computing device and computer readable storage medium

Abstract

This application discloses a current source equivalent method, computing device, and computer-readable storage medium. The method comprises: obtaining a target pattern on a target metal layer based on target device information, the target pattern including a target metal pattern and a pin pattern; determining an effective pin pattern within the pin pattern; and determining the current source equivalent point of the target device based on the target metal pattern and the effective pin pattern. Thus, by obtaining the effective pin pattern on the target metal layer and combining it with the target metal pattern, the current source equivalent point of the target device is determined. The method is simple and convenient, while also simplifying the layout, accelerating verification iterations, and ensuring simulation accuracy.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a current source equivalent method, a computing device, and a computer-readable storage medium. Background Art

[0002] The layout of an integrated circuit is composed of metal interconnects and devices. During layout simulation and verification, a standard device library provides power consumption information under given voltages and connection relationships, thereby deriving the magnitude of the current source formed by the standard device. However, since the pins of standard devices have a certain area, the area where the pins connect to the metal wires becomes the range for electron flow and the current flowing on the chip, resulting in effects such as voltage drop. Therefore, to simplify the simulation verification process and ensure simulation accuracy, it is necessary to convert the actual circuit and current source into a topological network to shorten simulation time and speed up iterations. At the same time, it is necessary to adopt certain methods to equate the device pins to ensure accuracy. However, how to determine the current source equivalent point corresponding to the device pins has been an ongoing research. Summary of the Invention

[0003] The purpose of this application is to provide an equivalent method of a current source, a computing device, and a computer-readable storage medium to at least solve the problems in the related art.

[0004] To achieve the above objectives:

[0005] In a first aspect, an embodiment of the present application provides an equivalent method of a current source, the method comprising:

[0006] Acquire a target pattern on a target metal layer according to information of a target device, wherein the target pattern includes a target metal pattern and a pin pattern;

[0007] determining a valid pin pattern among the pin patterns;

[0008] A current source equivalent point of the target device is determined based on the target metal pattern and the effective pin pattern.

[0009] In one embodiment, before determining a valid pin pattern among the pin patterns, the method includes:

[0010] Obtaining a pin pattern block after splitting and merging the pin pattern;

[0011] The determining of a valid pin pattern in the pin patterns includes:

[0012] Determining a valid pin pattern based on the weight relationship between the pin pattern blocks; and / or,

[0013] The pin pattern block is determined to be a valid pin pattern.

[0014] In one embodiment, determining the effective pin pattern according to the weight relationship between the pin pattern blocks includes:

[0015] Determine the weight of each pin pattern block according to the area of each pin pattern block, and determine at least one pin pattern block with the largest weight as a valid pin pattern;

[0016] and / or,

[0017] The weight of each pin pattern block is determined according to the number of edges of each pin pattern block contacting the target device boundary, and at least one pin pattern block with the largest weight is determined as a valid pin pattern.

[0018] In one embodiment, determining the current source equivalent point of the target device based on the target metal pattern and the effective pin pattern includes:

[0019] determining the number of the valid pin patterns;

[0020] According to the number of the effective pin patterns, a current source equivalent point of the target device is determined based on the target metal pattern and the effective pin pattern.

[0021] In one embodiment, determining the current source equivalent point of the target device based on the target metal pattern and the effective pin pattern according to the number of the effective pin patterns includes:

[0022] If the number of the effective pin patterns is less than or equal to a preset number threshold, simplifying the effective pin pattern to a center point of the effective pin pattern, and when the center point of the effective pin pattern overlaps with the target metal pattern, determining the center point of the effective pin pattern as a current source equivalent point of the target device;

[0023] If the number of the effective pin patterns is greater than a preset number threshold, a center point of an overlapping portion of the target metal pattern and the effective pin pattern is determined as a current source equivalent point of the target device.

[0024] In one embodiment, after determining a valid pin pattern among the pin patterns, the method further includes:

[0025] In response to a requirement for segmenting the effective pin pattern, obtaining at least two effective pin segmentation patterns after segmenting the effective pin pattern;

[0026] The determining of the current source equivalent point of the target device based on the target metal pattern and the effective pin pattern according to the number of effective pin patterns includes:

[0027] If the number of the valid pin patterns is less than or equal to a preset number threshold, simplifying the at least two valid pin patterns after cutting into the center points of the valid pin patterns respectively, and when the target metal pattern overlaps with the center points of the valid pin patterns, determining the center points of the valid pin patterns as the current source equivalent points of the target device;

[0028] If the number of the effective pin patterns is greater than a preset number threshold, a center point of an overlapping portion of the target metal pattern and the effective pin cutting pattern is determined as a current source equivalent point of the target device.

[0029] In one embodiment, the target metal pattern includes a metal line pattern and a via pattern.

[0030] In one embodiment, before acquiring the target pattern on the target metal layer according to the information of the target device, the method includes:

[0031] In response to the received input information, the target metal layer is determined.

[0032] In a second aspect, an embodiment of the present application provides a computing device, comprising: a processor and a memory storing a computer program, wherein when the processor runs the computer program, the equivalent method of the current source described in the first aspect is implemented.

[0033] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the equivalent method of the current source described in the first aspect above is implemented.

[0034] In the current source equivalent method, computing device and computer-readable storage medium provided in the embodiments of the present application, the current source equivalent point of the target device is determined by obtaining the effective pin pattern on the target metal layer and combining it with the target metal pattern. The operation is simple and convenient, and at the same time, the layout can be simplified, the verification iteration speed can be accelerated, and the accuracy of the simulation can be guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A flow chart of an equivalent method for a current source provided in an embodiment of the present application.

[0036] Figure 2 Schematic diagram of the target graphics in the embodiment of this application Figure 1 .

[0037] Figure 3 Schematic diagram of pin glitch pattern current in an embodiment of the present application.

[0038] Figure 4 Schematic diagram of the target graphics in the embodiment of this application Figure 2.

[0039] Figure 5 This is a schematic diagram of determining an effective pin pattern based on area in an embodiment of the present application.

[0040] Figure 6 This is a schematic diagram of determining a valid pin pattern based on the number of edges in an embodiment of the present application.

[0041] Figure 7 Schematic diagram of the generation of the current source equivalent point in the embodiment of the present application Figure 1 .

[0042] Figure 8 Schematic diagram of the generation of the current source equivalent point in the embodiment of the present application Figure 2 .

[0043] Figure 9 This is a schematic diagram of dividing the effective pin pattern in an embodiment of the present application.

[0044] Figure 10 Schematic diagram of selecting the target metal layer in the embodiment of the present application.

[0045] Figure 11 A schematic diagram of the process of an equivalent method for a current source provided in an embodiment of the present application.

[0046] Figure 12 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.

[0048] It should be noted that, in this document, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0049] It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the term "if" as used herein may be interpreted as "at the time of," "when," or "in response to a determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms "comprising" and "including" indicate the presence of the described features, steps, operations, elements, components, items, types, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, types, and / or groups. The terms "or" and "and / or" as used herein are to be interpreted as inclusive, meaning any one or any combination. Thus, “A, B, or C” or “A, B, and / or C” means “any of: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition occurs only when a combination of elements, functions, steps, or operations are inherently mutually exclusive in some manner.

[0050] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless clearly stated herein, the execution of these steps is not strictly limited in order, and they can be performed in other orders. Moreover, some of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or sub-steps of other steps or parts of stages.

[0051] It should be noted that in this article, step codes such as S101 and S102 are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the order. When implementing the step, those skilled in the art may execute S102 first and then S101, etc., but these should all be within the scope of protection of this application.

[0052] It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0053] In the subsequent description, the use of suffixes such as "module", "component" or "unit" to represent elements is only for the purpose of facilitating the description of the present application and has no specific meaning. Therefore, "module", "component" or "unit" can be used interchangeably.

[0054] See Figure 1 The embodiment of the present application provides an equivalent method for a current source. The equivalent method for a current source can be performed by an equivalent device for a current source provided in the embodiment of the present application. The equivalent device for a current source can be implemented in software and / or hardware, for example, a computing device such as a computer. The equivalent method for a current source provided in this embodiment includes:

[0055] Step S101: Acquire a target pattern on a target metal layer according to information of a target device, where the target pattern includes a target metal pattern and a pin pattern.

[0056] Among them, the target device is a device with pins and power consumption for which the current source equivalent point is to be obtained. The target device may have multiple pins and each pin can only be connected to one metal layer in the layout, but multiple pins can be connected to the same metal layer. The target device may specifically be a MOS tube, triode and other devices in the layout. It should be noted that the target device is connected to the metal layer through pins, and since the target device may have multiple pins, and the metal layers connected to different pins may be the same or different, the target device may be connected to only one metal layer or multiple metal layers. At the same time, when the pins of the target device are connected to the metal layer, a pin graphic is generated at the corresponding connection position on the metal layer. The target metal layer can be any metal layer connected to the pins of the target device. The metal layer refers to the conductive layer used for electrical connection in the layout. When the pins of the target device are connected to multiple metal layers, each of the multiple metal layers can be used as the target metal layer. The target metal pattern refers to a pattern on the target metal layer that is associated with the pin pattern of the target device. For example, it can be a pattern on the target metal layer that overlaps or connects with the pin pattern of the target device. Target metal patterns include metal line patterns and / or via patterns. A metal line pattern is a pattern formed by conductive paths on a metal layer, and a via pattern is a pattern formed by through holes on a metal layer. A pin pattern is a pattern corresponding to the pins of the target device on the target metal layer.

[0057] Wherein, the target pattern on the target metal layer is obtained according to the information of the target device, and the target pattern on the target metal layer can be obtained according to the pin distribution information of the target device and the boundary information of the target device. Figure 2 As shown, taking the target metal layer as layer 1 and the target metal pattern including the metal line pattern as an example, the target pattern includes a pattern set consisting of a pin pattern 11 located within the boundary of the target device 12 on layer 1 and a metal line pattern 10 connected to the pin pattern 11.

[0058] Step S102: Determine valid pin patterns in the pin patterns.

[0059] It can be understood that since part of the pin pattern may be a pin burr pattern, that is, the burr portion of the pin corresponds to the generated pattern, such as Figure 3 As shown, based on Ohm's law and Kirchhoff's law, the resistance of the burr part is very small, the current is also very small, and the total current I1+I2 and I3+I4 flowing out from both sides are always constant, which makes the proportion of the current source of the burr part very small. At the same time, considering that this part will increase the subsequent calculation amount and affect the simulation speed, the pin burr pattern in the pin pattern can be ignored, and only the effective pin pattern in the pin pattern can be extracted.

[0060] Valid pin patterns are pin patterns that can be used to determine the current source equivalent point of the target device. Of all pin patterns, only some or all may be valid pin patterns. It should be noted that pin patterns other than valid pin patterns are referred to as pin glitch patterns or glitch patterns.

[0061] In one embodiment, before determining a valid pin pattern in the pin patterns, the method includes:

[0062] Obtaining a pin graphic block after the pin graphic is split and merged;

[0063] Determine the valid pin patterns in the pin pattern, including:

[0064] Determine the effective pin pattern based on the weight relationship between the pin pattern blocks; and / or,

[0065] Identifies the pin pattern block as a valid pin pattern.

[0066] Among them, since the target device may have multiple pin patterns on the target metal layer, and some pin patterns may overlap or be connected, in order to prevent repeated processing caused by overlapping or connected pin patterns and improve processing efficiency, the pin patterns can be split-merged. In this embodiment, the pin patterns can be split-merged based on the scan line algorithm. The specific process can refer to the existing technology. For example, Figure 2 The pin pattern shown in FIG is not subjected to the split-merge process, and Figure 4 For Figure 2 By comparison, it can be seen that by performing split-merge processing on the pin graphics, the overlapping and / or connected pin graphics in the target graphics can be merged, thereby reducing the number of pin graphics.

[0067] It should be noted that when the target device is a standard device, the effective pin pattern can be determined based on the weight relationship between each pin pattern block. When the target device is a non-standard device, all pin pattern blocks can be determined as effective pin patterns. Among them, a standard device is a device with a pin length less than or equal to a preset length threshold, and a non-standard device is a device with a pin length greater than a preset length threshold. The pin length of a device refers to the length along the pin pattern of the device, that is, the distance of the pin pattern of the device along the pin direction of the device, such as Figure 4 As shown, the device pin length is L. Furthermore, the pin pattern block weight is used to evaluate whether the pin pattern block can be used as a valid pin pattern. A larger or smaller weight indicates a greater or smaller likelihood of the pin pattern block being a valid pin pattern. This allows for rapid identification of valid pin patterns for the target device type, further improving the speed of obtaining the current source equivalent point of the target device and accelerating verification iterations.

[0068] In one embodiment, determining a valid pin pattern based on a weight relationship between pin pattern blocks includes:

[0069] Determine the weight of each pin pattern block according to the area of each pin pattern block, and determine at least one pin pattern block with the largest weight as a valid pin pattern;

[0070] and / or,

[0071] The weight of each pin pattern block is determined according to the number of edges of each pin pattern block contacting the target device boundary, and at least one pin pattern block with the largest weight is determined as a valid pin pattern.

[0072] Among them, since the shape of the pin graphic blocks is rectangular, the area of the pin graphic blocks can be obtained based on the length and width of the pin graphic blocks. After obtaining the area of each pin graphic block, the area of each pin graphic block can be determined as the weight corresponding to each pin graphic block, or the pin graphic blocks can be sorted in order of area from small to large, and the sorting number can be used as the weight corresponding to each pin graphic block, or the ratio of the area of the pin graphic block to the sum of the areas of all pin graphic blocks can be used as the weight corresponding to the pin graphic block, which is not specifically limited here. Figure 5 As shown, taking the pin pattern block including Legend 1 and Legend 2 as an example, since the area of Legend 2 is larger than the area of Legend 1, Legend 2 can be selected and determined as the valid pin pattern.

[0073] Among them, based on the position information of the pin graphic block boundary and the position information of the target device boundary, by comparing whether there are identical parts in the position information, it can be determined whether the pin graphic block boundary is in contact with the target device boundary. For example, when the position information includes coordinates, if the coordinates of the pin graphic block boundary and the coordinates of the target device boundary intersect, it is determined that the pin graphic block boundary is in contact with the target device boundary; if the coordinates of the pin graphic block boundary and the coordinates of the target device boundary do not intersect, it is determined that the pin graphic block boundary and the target device boundary do not intersect. After obtaining the number of edges of each pin graphic block boundary in contact with the target device boundary, the number of edges of each pin graphic block boundary in contact with the target device boundary can be determined as the weight corresponding to each pin graphic block, or each pin graphic block can be sorted in order of the number of edges from small to large, and the sorting number can be used as the weight corresponding to each pin graphic block, etc., which is not specifically limited here. Figure 6 As shown, taking the pin graphic block including Legend 1 and Legend 2 as an example, the target device boundaries are edges a, b, c, and d in sequence. Since Legend 1 contacts edges a and c respectively, that is, the number of edges contacted between the boundary of Legend 1 and the boundary of the target device is 2, and the number of edges contacted between the boundary of Legend 2 and the boundary of the target device is 0, Legend 1 can be selected as the valid pin graphic.

[0074] Determining at least one pin pattern block with the largest weight as the valid pin pattern can involve determining the pin pattern block with the largest weight as the valid pin pattern, or determining the N pin pattern blocks with the largest weights as the valid pin patterns, where N is a positive integer. This allows for rapid determination of the valid pin pattern, further improving the speed of acquiring the current source equivalent point of the target device.

[0075] Step S103: Determine the current source equivalent point of the target device based on the target metal pattern and the effective pin pattern.

[0076] After determining the effective pin pattern from the pin patterns included in the target pattern, the current source equivalent point of the target device can be determined in combination with the target metal pattern. Here, the current source equivalent point of the target device can be regarded as the current source equivalent point of the pin of the target device on the target metal layer.

[0077] In one embodiment, determining a current source equivalent point of a target device based on a target metal pattern and an effective pin pattern includes:

[0078] Determine the number of valid pin patterns;

[0079] According to the number of effective pin patterns, a current source equivalent point of a target device is determined based on the target metal pattern and the effective pin pattern.

[0080] After determining the effective pin pattern, the number of effective pin patterns can be obtained accordingly. If the number of effective pin patterns varies, the method for determining the current source equivalent point of the target device based on the target metal pattern and the effective pin pattern may also vary. Thus, depending on the number of effective pin patterns, the current source equivalent point of the target device is determined based on the target metal pattern and the effective pin pattern, thereby accurately and quickly determining the current source equivalent point of the target device.

[0081] In one embodiment, determining a current source equivalent point of a target device based on a target metal pattern and an effective pin pattern according to the number of effective pin patterns includes:

[0082] If the number of valid pin patterns is less than or equal to a preset number threshold, simplifying the valid pin pattern to a center point of the valid pin pattern, and when the center point of the valid pin pattern overlaps with the target metal pattern, determining the center point of the valid pin pattern as a current source equivalent point of the target device;

[0083] If the number of valid pin patterns is greater than a preset number threshold, a center point of an overlapping portion of the target metal pattern and the valid pin pattern is determined as a current source equivalent point of the target device.

[0084] Among them, the preset number threshold can be set according to actual needs. In this embodiment, the preset number threshold is 1 as an example for explanation. If the number of valid pin graphics is less than or equal to the preset number threshold, it means that there are fewer valid pin graphics. Then, the valid pin graphics can be simplified to the center point of the valid pin graphics, and then it is detected whether the center point of the valid pin graphics overlaps with the target metal graphics. When the center point of the valid pin graphics overlaps with the target metal graphics, the center point of the valid pin graphics is determined as the current source equivalent point of the target device on the target metal layer. When the center point of the valid pin graphics does not overlap with the target metal graphics, the corresponding processing is not performed, that is, the center point of the valid pin graphics will not be determined as the current source equivalent point of the target device. Among them, the center point of the valid pin graphics overlaps with the target metal graphics, which can be the center point of the valid pin graphics overlapping with the metal wire graphics or the through-hole graphics. If the number of valid pin patterns exceeds a preset threshold, indicating a large number of valid pin patterns, the target metal pattern and the valid pin pattern are first detected for overlap. If the target metal pattern and the valid pin pattern overlap, the overlapping portion of the target metal pattern and the valid pin pattern is determined, and the center point of the overlapping portion is then determined as the current source equivalent point of the target device. If the target metal pattern and the valid pin pattern do not overlap, no processing is performed. Whether the center point of the valid pin pattern overlaps with the target metal pattern can be determined by detecting whether the coordinates of the center point of the valid pin pattern intersect with the coordinates of the target metal pattern. Similarly, whether the target metal pattern and the valid pin pattern overlap can be determined by detecting whether the coordinates of the target metal pattern intersect with the coordinates of the valid pin pattern.

[0085] For example, the target metal pattern includes a metal line pattern and a via (ie, through-hole) pattern. Figure 7 As shown in , when the pin pattern is a valid pin pattern and there is only one, since the pattern becomes the center point of the valid pin pattern after simplification, and this center point only coincides with the metal line pattern and does not coincide with the via, the current source equivalent point is at the center point of the valid pin pattern; as shown in Figure 8 As shown, when there are two valid pin patterns, no simplification is required. Instead, the overlap between the metal wire pattern and the via pattern and the valid pin pattern is directly determined. The center point of the overlap is then determined as the current source equivalent point. This allows the current source equivalent point of the target device to be determined based on the relationship between the number of valid pin patterns and a preset threshold, speeding up the acquisition of the target device's current source equivalent point.

[0086] In one embodiment, after determining a valid pin pattern in the pin patterns, the method includes:

[0087] In response to a requirement for segmentation of the effective pin pattern, obtaining at least two effective pin segmentation patterns after segmentation of the effective pin pattern;

[0088] According to the number of effective pin patterns, the current source equivalent point of the target device is determined based on the target metal pattern and the effective pin pattern, including:

[0089] If the number of valid pin patterns is less than or equal to a preset number threshold, simplifying the at least two valid pin patterns after segmentation into the center points of the valid pin patterns respectively, and when the target metal pattern overlaps with the center points of the valid pin patterns, determining the center points of the valid pin patterns as the current source equivalent points of the target device;

[0090] If the number of valid pin patterns is greater than a preset number threshold, the center point of the overlapping portion of the target metal pattern and the valid pin segmentation pattern is determined as the current source equivalent point of the target device.

[0091] It can be understood that according to the resistance calculation formula ΔR=ΔL*(Rho) / s, the longer the cutting length ΔL, the greater the resistance ΔR, where Rho is the resistivity and s is the cross-sectional area. According to Ohm's law ΔU=I*ΔR, when the current I remains unchanged, the greater the resistance ΔR, the greater the voltage difference ΔU, which makes the simulation accuracy loss greater. Therefore, in order to reduce the accuracy loss of the simulation and improve the accuracy of subsequent simulations, the effective pin graphic can be cut first, and then the current source equivalent point of the target device can be determined based on the effective pin graphic after cutting. Among them, the cutting requirements for the effective pin graphic may include the cutting length, and the user can set or adjust the cutting length based on actual needs. For each effective pin graphic, it can be cut according to the cutting length included in the cutting requirements, and then at least two effective pin cutting graphics after the effective pin graphic is cut are obtained. It should be noted that due to the influence of the length of the effective pin graphic and the cutting length, the length of some effective pin cutting graphics may be equal to the cutting length, while the length of some effective pin cutting graphics may be less than the cutting length. As Figure 9 As shown, the effective pin pattern can be cut according to a predefined cutting length ΔL.

[0092] If the number of valid pin patterns is less than or equal to a preset threshold, indicating a small number of valid pin patterns, the at least two valid pin patterns after segmentation can be simplified to the center point of each valid pin pattern. A detection is then made to determine whether the center point of the valid pin pattern overlaps with the target metal pattern. If the target metal pattern overlaps with the center point of the valid pin pattern, the center point of the valid pin pattern is determined as the current source equivalent point of the target device. If the center point of the valid pin pattern does not overlap with the target metal pattern, no corresponding processing is performed, i.e., the center point of the valid pin pattern is not determined as the current source equivalent point of the target device. If the number of valid pin patterns is greater than the preset threshold, indicating a large number of valid pin patterns, a detection is first made to determine whether the target metal pattern overlaps with the valid pin pattern. If the target metal pattern overlaps with the valid pin pattern, the overlapping portion of the target metal pattern and the valid pin pattern is determined. The center point of the overlapping portion of the target metal pattern and the valid pin pattern is then determined as the current source equivalent point of the target device. If the target metal pattern does not overlap with the valid pin pattern, no processing is performed. Whether the center point of the effective pin segmentation pattern overlaps with the target metal pattern can be determined by detecting whether the coordinates of the center point of the effective pin segmentation pattern intersect with the coordinates of the target metal pattern. Similarly, whether the target metal pattern overlaps with the effective pin segmentation pattern can be determined by detecting whether the coordinates of the target metal pattern intersect with the coordinates of the effective pin segmentation pattern. In this way, by segmenting the effective pin segmentation pattern and then determining the current source equivalent point of the target device based on the segmented effective pin segmentation pattern, simulation accuracy can be effectively reduced, further improving the accuracy of the simulation.

[0093] In one embodiment, before acquiring the target pattern on the target metal layer according to the information of the target device, the method includes: determining the target metal layer in response to the received input information.

[0094] Among them, the user can input information to the computing device based on demand to set the target metal layer. For example, considering that the voltage point of the chip is usually added to the highest metal layer, the user can input information to the computing device to select the highest metal layer where the target device is located as the target metal layer, so as to reduce the scale of data calculation and increase the speed of obtaining the equivalent point of the current source. At the same time, the voltage drop of the target device can be calculated as quickly as possible based on the above shortest path. Figure 10 As shown, if layer 1 is the highest metal layer, layer 1 can be selected as the target metal layer. Furthermore, based on accuracy considerations, all metal layers with metal line patterns can also be selected as target metal layers. This allows for more flexible operation by setting the target metal layer based on demand.

[0095] The following is an example of the equivalent process of the current source. Figure 11, including the following steps:

[0096] Step S201: Determine the device to be processed.

[0097] Step S202: Merge the pin patterns of the device.

[0098] Here, there are two ways to merge, namely, merging along the horizontal direction and merging along the vertical direction. In this embodiment, the direction with the smallest number of graphics after merging is selected, which is usually related to the direction in which the device is placed.

[0099] Step S203: Determine whether the device is a standard device. If so, execute step S204; otherwise, execute step S208.

[0100] Here, the type of device affects the subsequent processing flow because the pins of standard devices are usually simpler and have a limited length, while the pins of non-standard devices are usually longer.

[0101] Step S204 , determining whether the pin patterns of all metal layers are retained, if so, executing step S205 , otherwise executing step S206 .

[0102] Here, in this example, a setting is provided to select whether to retain the pin graphics of all metal layers. If not, the pin graphics of the highest metal layer will be selected. The pin graphics of the metal layers are retained based on accuracy considerations.

[0103] Step S205: Select the pin patterns of all metal layers as pin patterns to be processed.

[0104] Step S206: Select the pin pattern of the highest metal layer as the pin pattern to be processed.

[0105] Here, the pin pattern of the highest metal layer is selected as the pin pattern to be processed. On the one hand, it can reduce the data size. On the other hand, it is based on practical design considerations. Usually, the voltage point of the chip is added to the top layer. The voltage drop of the device can be calculated fastest according to the shortest path method.

[0106] Step S207: performing burr processing on the pin pattern to be processed to obtain a valid pin pattern.

[0107] Among them, burr processing on the pin pattern to be processed can be regarded as filtering out the pin burr pattern in the pin pattern, which can be specifically judged based on the number of edges of the pin pattern boundary contacting the device boundary and / or the pin pattern area. For details, please refer to the above embodiment.

[0108] Step S208: All pin patterns are regarded as valid pin patterns.

[0109] For non-standard devices, all pin patterns are directly used as valid pin patterns.

[0110] Step S209: Slice the effective pin pattern according to a preset length to obtain an effective pin segmentation pattern.

[0111] Step S210: determining a current source equivalent point based on the effective pin segmentation pattern.

[0112] For pins with more than one effective pin pattern (referring to pins with the same attributes), the effective pin pattern is not simplified. The final current source equivalent point is the center point of the overlap between the effective pin pattern and the metal line pattern or via. For pins with one effective pin pattern, the effective pin pattern is simplified to the center point of the effective pin pattern. The current source equivalent point is the overlap between this center point and the metal line pattern or via, which is usually the location of the center point itself.

[0113] In summary, in the current source equivalent method provided in the above embodiment, for standard devices, the simple equivalent center method can simplify the network and speed up the verification iteration speed. For complex BLOCKs or other devices with special functions, the number of analog current sources can be increased to increase the accuracy of the simulation. It can also allow users to balance the accuracy and performance requirements and choose a better method.

[0114] Based on the same inventive concept as the above embodiments, an embodiment of the present invention provides a computing device, such as Figure 12 As shown, the computing device includes: a processor 310 and a memory 311 storing a computer program; wherein, Figure 12 The processor 310 shown in the figure is not used to indicate that the number of processors 310 is one, but is only used to indicate the positional relationship of the processor 310 relative to other devices. In actual applications, the number of processors 310 may be one or more; similarly, Figure 12 The memory 311 shown in the figure has the same meaning, that is, it is only used to refer to the positional relationship of the memory 311 relative to other devices. In actual applications, the number of memories 311 can be one or more. When the processor 310 runs the computer program, it implements the equivalent method of the current source applied to the above-mentioned computing device.

[0115] The computing device may also include: a network interface 312. The various components in the electronic device are coupled together via a bus system 313. It is understood that the bus system 313 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 313 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 12 Various buses are labeled as bus system 313.

[0116] Memory 311 may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disk, or compact disc read-only memory (CD-ROM); magnetic surface memory may include magnetic disk or tape memory. Volatile memory may include random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus random access memory (DRRAM).The memory 311 described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memories.

[0117] Based on the same inventive concept as the above-mentioned embodiment, this embodiment further provides a computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium. The computer-readable storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); or various devices including one or any combination of the above-mentioned memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc. When the computer program stored in the computer-readable storage medium is executed by a processor, the equivalent method of the above-mentioned current source is implemented. For the specific steps implemented when the computer program is executed by the processor, please refer to Figure 1 The description of the illustrated embodiment will not be repeated here.

[0118] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion of elements other than the listed elements and may also include additional elements not specifically listed.

[0120] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A current source equivalent method, characterized in that: The method comprises: Acquire a target pattern on a target metal layer according to information of a target device, wherein the target pattern includes a target metal pattern and a pin pattern; determining a valid pin pattern among the pin patterns; determining the number of the valid pin patterns; If the number of the effective pin patterns is less than or equal to a preset number threshold, simplifying the effective pin pattern to a center point of the effective pin pattern, and when the center point of the effective pin pattern overlaps with the target metal pattern, determining the center point of the effective pin pattern as a current source equivalent point of the target device; If the number of the effective pin patterns is greater than a preset number threshold, a center point of an overlapping portion of the target metal pattern and the effective pin pattern is determined as a current source equivalent point of the target device.

2. The method according to claim 1, characterized in that Before determining a valid pin pattern among the pin patterns, the method includes: Obtaining a pin pattern block after splitting and merging the pin pattern; The determining of a valid pin pattern in the pin patterns includes: Determining a valid pin pattern based on the weight relationship between the pin pattern blocks; and / or, The pin pattern block is determined to be a valid pin pattern.

3. The method according to claim 2, characterized in that The determining of the effective pin pattern according to the weight relationship between the pin pattern blocks includes: Determine the weight of each pin pattern block according to the area of each pin pattern block, and determine at least one pin pattern block with the largest weight as a valid pin pattern; and / or, The weight of each pin pattern block is determined according to the number of edges of each pin pattern block contacting the target device boundary, and at least one pin pattern block with the largest weight is determined as a valid pin pattern.

4. The method according to claim 1, wherein After determining the valid pin patterns in the pin patterns, the method includes: In response to a requirement for segmenting the effective pin pattern, obtaining at least two effective pin segmentation patterns after segmenting the effective pin pattern; If the number of the valid pin patterns is less than or equal to a preset number threshold, simplifying the at least two valid pin patterns after cutting into the center points of the valid pin patterns respectively, and when the target metal pattern overlaps with the center points of the valid pin patterns, determining the center points of the valid pin patterns as the current source equivalent points of the target device; If the number of the effective pin patterns is greater than a preset number threshold, a center point of an overlapping portion of the target metal pattern and the effective pin cutting pattern is determined as a current source equivalent point of the target device.

5. The method according to claim 1, wherein The target metal pattern includes a metal line pattern and a through-hole pattern.

6. The method according to claim 1, characterized in that Before acquiring the target pattern on the target metal layer according to the information of the target device, the method includes: In response to the received input information, the target metal layer is determined.

7. A computing device, characterized in that The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, an equivalent method of the current source according to any one of claims 1 to 6 is implemented.

8. A computer-readable storage medium storing a computer program, wherein the computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the computer program implements the equivalent method of the current source according to any one of claims 1 to 6.

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