An integrated circuit 3D packaging structure and its packaging method

Abstract

The present invention discloses an integrated circuit 3D packaging structure and a packaging method thereof, relating to the technical field of semiconductor packaging. The packaging method includes the following steps: obtaining the number of layers of the integrated circuit; dividing the layout positions of the modules according to the number of layers of the integrated circuit to obtain a layout model of the integrated circuit; calculating the number of through-silicon vias in the chip layer according to the layout model of the integrated circuit; connecting the modules to each other through the through-silicon vias to obtain a three-dimensional model of the integrated circuit; evaluating the three-dimensional model of the integrated circuit to determine the packaging structure of the integrated circuit. By dividing the positions of the modules in the chip layer and inside the chip layer, calculating the number of through-silicon vias according to the layout model, and performing routing, through-silicon via, and temperature evaluations on the three-dimensional model obtained by connecting the through-silicon vias, the three-dimensional packaging structure of the integrated circuit is determined. While through-silicon vias are provided inside the modules, the routing and temperature consumption are reduced, improving the performance of the three-dimensional packaged integrated circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and particularly relates to a 3D packaging structure of an integrated circuit and a packaging method thereof. Background Art

[0002] With the rapid development of modern society, the performance requirements of electronic devices are constantly increasing, and the requirements for integrated circuit packaging technology are getting higher and higher. The traditional two-dimensional integrated circuit packaging technology has problems such as low space utilization, limited electrical performance, and insufficient heat dissipation capacity, which limit the further development and improvement of electronic devices.

[0003] Three-dimensional integrated circuit packaging usually uses through-silicon vias to connect each vertically stacked chip layer. Three-dimensional integrated circuit packaging has better performance and area compared to traditional two-dimensional integrated circuit packaging. Therefore, three-dimensional integrated circuit packaging is widely used in various electronic devices.

[0004] The existing three-dimensional integrated circuit packaging is carried out by setting through-silicon vias outside each module area inside the chip. The method of setting through-silicon vias outside the module area has problems such as large area, low signal quality, and low power integrity. Setting through-silicon vias inside the module area requires re-routing the chip layer. Therefore, a three-dimensional packaging method of an integrated circuit with through-silicon vias set inside the module is needed. Summary of the Invention

[0005] The purpose of the present invention is to provide a 3D packaging structure of an integrated circuit and a packaging method thereof. The present invention divides the positions of the modules in the chip layer and inside the chip layer, calculates the number of through-silicon vias according to the layout model, performs routing, through-silicon via, and temperature evaluation on the three-dimensional model obtained by connecting the through-silicon vias, determines the three-dimensional packaging structure of the integrated circuit, reduces routing and temperature consumption while setting through-silicon vias inside the module, and improves the performance of the three-dimensional packaged integrated circuit.

[0006] The purpose of the present invention is achieved by the following technical means:

[0007] In the first aspect, the present invention provides a packaging method for a 3D packaging structure of an integrated circuit, including the following steps:

[0008] Obtain the number of layers of the integrated circuit;

[0009] According to the number of layers of the integrated circuit, divide the layout positions of the modules to obtain a layout model of the integrated circuit;

[0010] According to the layout model of the integrated circuit, calculate the number of through-silicon vias in the chip layer;

[0011] Connect the modules with each other through through-silicon vias to obtain a three-dimensional model of the integrated circuit;

[0012] Evaluate the three-dimensional model of the integrated circuit to determine the packaging structure of the integrated circuit.

[0013] In some embodiments, dividing the layout positions of the modules according to the number of levels of the integrated circuit to obtain a layout model of the integrated circuit includes the following steps:

[0014] Initialize the integrated circuit;

[0015] Randomly divide the modules into chip layers according to the number of levels of the integrated circuit to obtain an initial layout;

[0016] According to the initial layout, adjust the layout positions of the modules within the chip layer and the layout position of the chip layer to obtain the layout model of the integrated circuit.

[0017] In some embodiments, calculating the number of through-silicon vias of a chip layer according to the layout model of the integrated circuit includes the following steps:

[0018] Obtain the interconnection relationship of the modules to get the connected modules;

[0019] According to the layout model of the integrated circuit, obtain the layer positions of the modules and the layer positions of the connected modules;

[0020] Calculate the number of through-silicon vias of the modules according to the layer positions of the modules and the layer positions of the connected modules;

[0021] Sum up the number of through-silicon vias of the modules to obtain the number of through-silicon vias of the chip layer.

[0022] In some embodiments, evaluating the three-dimensional model of the integrated circuit to determine the packaging structure of the integrated circuit includes the following steps:

[0023] Calculate the routing length of the modules according to the three-dimensional model of the integrated circuit;

[0024] Sum up the routing lengths of the modules to obtain the routing length of the chip layer

[0025] Estimate the temperature difference of the chip layer according to the three-dimensional model of the integrated circuit;

[0026] Obtain the maximum temperature difference of the integrated circuit according to the temperature difference of the chip layer;

[0027] Evaluate the integrated circuit according to the routing length of the chip layer, the number of through-silicon vias of the chip layer, and the maximum temperature difference of the integrated circuit to determine the packaging structure of the integrated circuit.

[0028] In some embodiments, estimating the temperature difference of the chip layer according to the three-dimensional model of the integrated circuit includes the following steps:

[0029] Obtain the interconnection relationship of the chip layer according to the three-dimensional model of the integrated circuit;

[0030] Calculate the vertical thermal resistance of the chip layer according to the interconnection relationship of the chip layer;

[0031] Obtain the through-silicon via diameter of the chip layer and the through-silicon via height of the chip layer;

[0032] Calculate the lateral thermal resistance of the through-silicon via according to the through-silicon via diameter of the chip layer;

[0033] Calculate the vertical thermal resistance of the through-silicon via according to the through-silicon via height of the chip layer;

[0034] Calculate the heat of the chip layer according to the vertical thermal resistance of the chip layer, the lateral thermal resistance of the through-silicon via, and the vertical thermal resistance of the through-silicon via;

[0035] Estimate the temperature difference of the chip layer according to the heat of the chip layer.

[0036] In some embodiments, the estimation formula for the temperature difference of the chip layer is expressed as follows:

[0037] ,

[0038] Wherein, is the temperature difference of the th layer of the chip, is the thermal resistance of the heat sink, is the number of levels, is the vertical thermal resistance of the th layer of the chip, is the thermal resistance of the package, is the th layer of the chip heat, is the layer number of the chip layer, .

[0039] In some embodiments, evaluating the integrated circuit according to the trace length of the chip layer, the number of through-silicon vias of the chip layer, and the maximum temperature difference of the integrated circuit, and determining the package structure of the integrated circuit includes the following steps:

[0040] Establish an evaluation function according to the trace length of the chip layer, the number of through-silicon vias of the chip layer, and the maximum temperature difference of the integrated circuit;

[0041] When the value of the evaluation function is greater than the set threshold, repeatedly divide the layout of the module;

[0042] When the value of the evaluation function is less than the set threshold, determine the package structure of the integrated circuit;

[0043] The formula of the evaluation function is expressed as follows:

[0044] ,

[0045] where, is the evaluation function, is the number of levels, is the routing length of the chips on the th layer, is the th layer of the chip, is the number of through-silicon vias of the chips on the th layer, is the maximum temperature difference of the integrated circuit,

[0046] In a second aspect, the present invention provides an integrated circuit 3D package structure, applying the above-mentioned packaging method for an integrated circuit 3D package structure, including: a substrate and multiple chip layers;

[0047] Each chip layer includes multiple modules, each module includes one or more through-silicon vias, and the module is electrically connected to one or more of the modules through the through-silicon vias.

[0048] In a third aspect, the present invention provides an electronic device, including a processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, and when the processor executes the computer instructions, the electronic device executes the above-mentioned packaging method for an integrated circuit 3D package structure.

[0049] In a fourth aspect, the present invention provides a computer-readable storage medium, in which a computer program is stored, the computer program includes program instructions, and when the program instructions are executed by the processor of the electronic device, the processor is caused to execute the above-mentioned packaging method for an integrated circuit 3D package structure.

[0050] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0051] By dividing the positions of the modules in the chip layer and inside the chip layer, calculating the number of through-silicon vias according to the layout model, evaluating the routing, through-silicon vias and temperature of the three-dimensional model obtained by connecting the through-silicon vias, and determining the integrated circuit three-dimensional package structure, the present invention reduces the routing and temperature consumption while arranging the through-silicon vias inside the module, and improves the performance of the three-dimensional packaged integrated circuit. Description of the Drawings

[0052] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing the embodiments consistent with the present invention and, together with the specification, used to explain the principles of the present invention.

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings required for use in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0054] Figure 1 It is a schematic flow chart of a packaging method for a 3D packaging structure of an integrated circuit provided in this embodiment;

[0055] Figure 2 It is a schematic flow chart of step S2 provided in this embodiment, which divides the layout positions of modules according to the number of levels of the integrated circuit to obtain the layout model of the integrated circuit;

[0056] Figure 3 It is a schematic flow chart of step S3 provided in this embodiment, which calculates the number of through-silicon vias in the chip layer according to the layout model of the integrated circuit;

[0057] Figure 4 It is a schematic flow chart of step S5 provided in this embodiment, which evaluates the 3D model of the integrated circuit to determine the packaging structure of the integrated circuit;

[0058] Figure 5 It is a schematic flow chart of step S53 provided in this embodiment, which estimates the temperature difference in the chip layer according to the 3D model of the integrated circuit;

[0059] Figure 6 It is a schematic flow chart of step S55 provided in this embodiment, which evaluates the integrated circuit according to the wire length in the chip layer, the number of through-silicon vias in the chip layer, and the maximum temperature difference of the integrated circuit to determine the packaging structure of the integrated circuit;

[0060] Figure 7 It is a schematic structural diagram of an electronic device provided in this embodiment. Detailed implementation manners

[0061] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0062] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative positional relationship, movement conditions, etc. between components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0063] In addition, the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0064] Embodiment 1

[0065] This embodiment provides a packaging method for an integrated circuit 3D packaging structure, as Figure 1 shown, including the following steps:

[0066] S1, obtaining the number of layers of the integrated circuit;

[0067] S2, dividing the layout positions of the modules according to the number of layers of the integrated circuit to obtain the layout model of the integrated circuit;

[0068] S3, calculating the number of through-silicon vias in the chip layer according to the layout model of the integrated circuit;

[0069] S4, connecting the modules to each other through through-silicon vias to obtain the 3D model of the integrated circuit;

[0070] S5, evaluating the 3D model of the integrated circuit to determine the packaging structure of the integrated circuit.

[0071] It should be noted that the number of layers of the integrated circuit is the number of chip layers required for the integrated circuit packaging. By setting the number of chip layers in advance, through-silicon vias are arranged inside the modules and the layout of the modules is optimized. The layout model of the integrated circuit includes the stacking state of the integrated circuit chip layers and the distribution positions of the modules inside each chip layer. In some embodiments, the position of each module can be allocated, and the position of the module inside the chip layer and the layer number of the chip layer can be represented by a three-dimensional coordinate. After connecting the modules in the layout model, the 3D model is evaluated, and according to the evaluation result, it is determined whether to select this 3D model for packaging.

[0072] In this embodiment, by dividing the positions of the modules in the chip layer and inside the chip layer, calculating the number of through-silicon vias according to the layout model, routing, evaluating the through-silicon vias and temperature for the three-dimensional model obtained by connecting the through-silicon vias, determining the three-dimensional packaging structure of the integrated circuit, while reducing routing and temperature consumption by arranging through-silicon vias inside the modules, the performance of the three-dimensional packaged integrated circuit is improved.

[0073] In some embodiments, in step S2, according to the number of levels of the integrated circuit, divide the layout positions of the modules to obtain the layout model of the integrated circuit, as Figure 2 shown, including the following steps:

[0074] S21, initialize the integrated circuit;

[0075] S22, according to the number of levels of the integrated circuit, randomly divide the modules into chip layers to obtain an initial layout;

[0076] S23, according to the initial layout, adjust the layout positions of the modules in the chip layer and the layout position of the chip layer to obtain the layout model of the integrated circuit.

[0077] It should be noted that when randomly dividing the modules into chip layers to obtain an initial layout, the area of the modules needs to be considered to ensure that the area of the chip layer is greater than the sum of the areas of the modules inside the chip layer. After obtaining the initial layout, the modules included inside the chip layer are determined. At this time, adjust the positions of the modules inside each chip layer and the positions between the chip layers, that is, move the modules within the layer and swap between the layers, to obtain the layout model of the integrated circuit.

[0078] In this embodiment, by randomly dividing the modules to obtain an initial layout, moving the modules within the layer and swapping between the layers for the initial layout, the layout model of the integrated circuit is obtained, improving the diversity of the integrated circuit module layout.

[0079] In some embodiments, in step S3, according to the layout model of the integrated circuit, calculate the number of through-silicon vias in the chip layer, as Figure 3 shown, including the following steps:

[0080] S31, obtain the interconnection relationship of the modules to get the connected modules;

[0081] S32, according to the layout model of the integrated circuit, obtain the layer positions of the modules and the layer positions of the connected modules;

[0082] S33, according to the layer positions of the modules and the layer positions of the connected modules, calculate the number of through-silicon vias of the modules;

[0083] S34, sum up the number of through-silicon vias of the modules to obtain the number of through-silicon vias in the chip layer.

[0084] It should be noted that the connection module is a module that interconnects with a certain module. When the layer position of the module and the layer position of the connection module are on the same chip layer, there is no need to set through-silicon vias for electrical connection; when the layer position of the module and the layer position of the connection module are on different chip layers, an additional through-silicon via needs to be set for connection every other chip layer. Specifically, the chip layer includes module A and module B. By obtaining the interconnection relationship of module A, connection modules B and C are obtained, that is, module B and module C are in an interconnection relationship with module A; by obtaining the interconnection relationship of module B, connection module A is obtained. The layer positions of module A, module B and module C are obtained from the layout model, and it is obtained that module A and module B are on chip layer 1, and module C is on chip layer 2. Since module A and module B are on the same chip layer, there is no need to set through-silicon vias. Module A and module C are on adjacent chip layers, and one through-silicon via is required for electrical connection, that is, the number of through-silicon vias in this chip layer is 1. Calculate the number of through-silicon vias in each chip layer in this way to obtain the number of through-silicon vias in each chip layer.

[0085] In this embodiment, by obtaining the layer positions of each module and the layer positions of the connection modules and connection modules interconnected therewith, the number of through-silicon vias in the chip layer is calculated, providing a data basis for subsequent evaluation and improving the performance of the three-dimensional packaged integrated circuit.

[0086] In some embodiments, in step S5, the three-dimensional model of the integrated circuit is evaluated to determine the package structure of the integrated circuit, as Figure 4 shown, including the following steps:

[0087] S51, According to the three-dimensional model of the integrated circuit, calculate the routing length of the module;

[0088] S52, Sum up the routing lengths of the modules to obtain the routing length of the chip layer;

[0089] S53, According to the three-dimensional model of the integrated circuit, estimate the temperature difference of the chip layer;

[0090] S54, According to the temperature difference of the chip layer, obtain the maximum temperature difference of the integrated circuit;

[0091] S55, According to the routing length of the chip layer, the number of through-silicon vias in the chip layer and the maximum temperature difference of the integrated circuit, evaluate the integrated circuit to determine the package structure of the integrated circuit.

[0092] It should be noted that the routing length of a module refers to the length of the signal line connecting the module to the modules in the same chip layer. By summing up the routing lengths of all modules in the chip layer, the routing length of the chip layer is obtained. The temperature difference of the chip layer is the temperature difference between the chip layer and the ambient temperature, and the temperature of the chip layer can be measured by summing up the temperature differences between the ambient temperature and the chip layer. The maximum temperature difference of the integrated circuit is obtained by comparing the temperature differences of each chip layer and selecting the maximum temperature difference of the chip layer. The layout is evaluated based on the routing length of the chip layer, the number of through-silicon vias in the chip layer, and the maximum temperature of the integrated circuit chip layer.

[0093] In this embodiment, by calculating the routing length and temperature difference of the chip layer according to the three-dimensional model of the integrated circuit, a data basis is provided for subsequent evaluation, improving the performance of the three-dimensional packaged integrated circuit.

[0094] In some embodiments, in step S53, according to the three-dimensional model of the integrated circuit, estimate the temperature difference of the chip layer, as Figure 5 shown, including the following steps:

[0095] S531, according to the three-dimensional model of the integrated circuit, obtain the interconnection relationship of the chip layer;

[0096] S532, according to the interconnection relationship of the chip layer, calculate the vertical thermal resistance of the chip layer;

[0097] S533, obtain the through-silicon via diameter of the chip layer and the through-silicon via height of the chip layer;

[0098] S534, according to the through-silicon via diameter of the chip layer, calculate the lateral thermal resistance of the through-silicon via;

[0099] S535, according to the through-silicon via height of the chip layer, calculate the vertical thermal resistance of the through-silicon via;

[0100] S536, according to the vertical thermal resistance of the chip layer, the lateral thermal resistance of the through-silicon via, and the vertical thermal resistance of the through-silicon via, calculate the heat of the chip layer;

[0101] S537, according to the heat of the chip layer, estimate the temperature difference of the chip layer.

[0102] In some embodiments, the estimation formula for the temperature difference of the chip layer is expressed as follows:

[0103] ,

[0104] Where is the temperature difference of the th layer of the chip, is the thermal resistance of the heat sink, is the number of levels, is the vertical thermal resistance of the th layer of the chip, is the thermal resistance of the package, is the heat of the nth layer of chips, is the layer number of the chip layer, .

[0105] It should be noted that the shape of the through-silicon via is cylindrical. When estimating the temperature difference, it is necessary to consider the thermal resistance of the chip layer vertically connected to the chip layer and the vertical thermal resistance of the through-silicon via required for connection. In addition, since the through-silicon via is arranged inside the module, the lateral thermal resistance of the through-silicon via needs to be considered. Therefore, the vertical thermal resistance of the chip layer, the lateral thermal resistance of the through-silicon via, and the vertical thermal resistance of the through-silicon via are obtained, and the heat generated by the chip layer is calculated. The vertical thermal resistance of the chip layer and the vertical thermal resistance of the through-silicon via can be calculated by conventional calculation methods and will not be elaborated here. The lateral thermal resistance of the through-silicon via can be obtained by integrating the through-silicon via along the radial direction in the formula for calculating the vertical thermal resistance.

[0106] In this embodiment, by obtaining the vertical thermal resistance of the chip layer, the lateral thermal resistance of the through-silicon via, and the vertical thermal resistance of the through-silicon via, the heat of the chip layer is calculated, thereby estimating the temperature difference of the chip layer, providing a data basis for subsequent evaluation, and improving the performance of the three-dimensional packaged integrated circuit.

[0107] In some embodiments, in step S55, according to the wire length of the chip layer, the number of through-silicon vias in the chip layer, and the maximum temperature difference of the integrated circuit, the integrated circuit is evaluated to determine the package structure of the integrated circuit, as Figure 6 shown, including the following steps:

[0108] S551, establish an evaluation function according to the wire length of the chip layer, the number of through-silicon vias in the chip layer, and the maximum temperature difference of the integrated circuit;

[0109] S552, when the value of the evaluation function is greater than the set threshold, repeatedly divide the layout of the module;

[0110] S553, when the value of the evaluation function is less than the set threshold, determine the package structure of the integrated circuit;

[0111] The formula of the evaluation function is expressed as follows:

[0112] ,

[0113] where, is the evaluation function, is the number of levels, is the wire length of the nth layer of chips, is the number of through-silicon vias of the nth layer of chips, is the maximum temperature difference of the integrated circuit, is the layer number of the chip layer, is the weight.

[0114] It should be noted that the wire length of the chip layer, the number of through-silicon vias in the chip layer, and the maximum temperature difference of the integrated circuit are input into the evaluation function. When the value output by the evaluation function is less than the set threshold, it indicates that the layout model meets the optimization requirements of the package design; when the value output by the evaluation function is greater than the set threshold, it indicates that there is still room for optimization in the layout model. Repeat steps S2 to S5 to divide the layout of the module, form a three-dimensional model and re-evaluate until the value output by the evaluation function is less than the set threshold.

[0115] In this embodiment, by setting up an evaluation function, the three-dimensional model is evaluated for wire routing, through-silicon vias, and temperature. When the evaluation output is not ideal, the module is re-divided and evaluated. When the evaluation output meets the package design requirements, the three-dimensional package structure of the integrated circuit is determined, reducing wire routing and temperature consumption and improving the performance of the three-dimensional packaged integrated circuit.

[0116] Embodiment 2

[0117] This embodiment provides a three-dimensional package structure of an integrated circuit, applying the above-mentioned package method of a three-dimensional package structure of an integrated circuit, including: a substrate and multiple chip layers;

[0118] The inside of the chip layer includes multiple modules, the inside of the module includes one or more through-silicon vias, and the module is electrically connected to one or more modules through the through-silicon vias.

[0119] In this embodiment, by dividing the positions of the modules in the chip layer and inside the chip layer, calculating the number of through-silicon vias according to the layout model, evaluating the three-dimensional model obtained by connecting the through-silicon vias for wire routing, through-silicon vias, and temperature, and determining the three-dimensional package structure of the integrated circuit, reducing wire routing and temperature consumption while arranging through-silicon vias inside the module, and improving the performance of the three-dimensional packaged integrated circuit.

[0120] Embodiment 3

[0121] This embodiment provides an electronic device 2, as Figure 7 shown, a processor 21 and a memory 22. The memory 22 is used to store computer program code, and the computer program code includes computer instructions. When the processor 21 executes the computer instructions, the electronic device executes the above-mentioned package method of a three-dimensional package structure of an integrated circuit.

[0122] The electronic device 2 includes a processor 21, a memory 22, an output device 23, and an input device 24. The processor 21, the memory 22, the output device 23, and the input device 24 are coupled through a connector, which includes various interfaces, transmission lines, buses, etc., and the embodiments of the present invention do not limit this. It should be understood that in various embodiments of the present invention, coupling refers to the mutual connection through a specific manner, including direct connection or indirect connection through other devices. For example, they can be connected through various interfaces, transmission lines, buses, etc.

[0123] The processor 21 can be one or more graphics processing units (GPUs). When the processor 21 is a single GPU, the GPU can be a single-core GPU or a multi-core GPU. Optionally, the processor 21 can be a processor group composed of multiple GPUs, and multiple processors are coupled to each other through one or more buses. Optionally, the processor 21 can also be other types of processors, etc., and the embodiments of the present invention do not limit this.

[0124] The memory 22 can be used to store computer program instructions and various computer program codes including the program codes for executing the solution of the present invention. Optionally, the memory 22 includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM), and the memory 22 is used for relevant instructions and data.

[0125] The input device 24 is used to input data and / or signals, and the output device 23 is used to output data and / or signals. The output device 23 and the input device 24 can be independent devices or an integrated device.

[0126] This embodiment provides a computer-readable storage medium. A computer program is stored in the computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by the processor of the electronic device, the processor is enabled to execute the above-mentioned packaging method of an integrated circuit 3D packaging structure.

[0127] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A packaging method for an integrated circuit 3D packaging structure, characterized in that: The following steps are involved: Get the number of layers of the integrated circuit; Dividing the layout positions of the modules according to the number of levels of the integrated circuit to obtain a layout model of the integrated circuit; Calculating the number of through silicon vias in a chip layer according to a layout model of the integrated circuit; Connect modules to each other through silicon vias to obtain a three-dimensional model of the integrated circuit; Evaluating the three-dimensional model of the integrated circuit to determine the packaging structure of the integrated circuit includes the following steps: Calculating the wiring length of the module according to the three-dimensional model of the integrated circuit; The wiring lengths of the modules are summed to obtain the wiring length of the chip layer. estimating a temperature difference of a chip layer according to the three-dimensional model of the integrated circuit; Obtaining a maximum temperature difference of the integrated circuit according to the temperature difference of the chip layer; Evaluate the integrated circuit according to the wiring length of the chip layer, the number of through silicon vias of the chip layer and the maximum temperature difference of the integrated circuit, and determine the packaging structure of the integrated circuit; The step of estimating the temperature difference of the chip layer according to the three-dimensional model of the integrated circuit comprises the following steps: Acquire the interconnection relationship of the chip layer according to the three-dimensional model of the integrated circuit; Calculating the vertical thermal resistance of the chip layer according to the interconnection relationship of the chip layer; Obtaining the through silicon via diameter and the through silicon via height of the chip layer; Calculating the lateral thermal resistance of the through silicon via according to the through silicon via diameter of the chip layer; Calculating the vertical thermal resistance of the through silicon via according to the height of the through silicon via of the chip layer; Calculating the heat of the chip layer according to the vertical thermal resistance of the chip layer, the lateral thermal resistance of the through silicon via, and the vertical thermal resistance of the through silicon via; estimating a temperature difference of the chip layer according to the heat of the chip layer; The temperature difference of the chip layer is estimated by the following formula: ， in, For the The temperature difference of the chip layer, is the thermal resistance of the heat sink, is the number of levels, For the Vertical thermal resistance of the chip layer, is the thermal resistance of the package, For the The heat of the layer chip, is the layer number of the chip layer, .

2. The packaging method of an integrated circuit 3D packaging structure according to claim 1, characterized in that: The step of dividing the layout positions of the modules according to the number of layers of the integrated circuit to obtain a layout model of the integrated circuit includes the following steps: Initializing the integrated circuit; According to the number of levels of the integrated circuit, the modules are randomly divided into chip layers to obtain an initial layout; According to the initial layout, the layout positions of the modules in the chip layer and the layout positions of the chip layer are adjusted to obtain a layout model of the integrated circuit.

3. The packaging method of an integrated circuit 3D packaging structure according to claim 1, characterized in that: Calculating the number of through silicon vias in a chip layer according to the layout model of the integrated circuit comprises the following steps: Obtain the interconnection relationship of the modules and obtain the connection modules; According to the layout model of the integrated circuit, obtaining the layer position of the module and the layer position of the connection module; Calculating the number of through silicon vias of the module according to the layer position of the module and the layer position of the connection module; The number of through silicon vias of the modules is summed to obtain the number of through silicon vias of the chip layer.

4. The packaging method of an integrated circuit 3D packaging structure according to claim 1, characterized in that: The step of evaluating the integrated circuit according to the wiring length of the chip layer, the number of through silicon vias of the chip layer and the maximum temperature difference of the integrated circuit to determine the packaging structure of the integrated circuit includes the following steps: Establishing an evaluation function according to the wiring length of the chip layer, the number of through silicon vias of the chip layer and the maximum temperature difference of the integrated circuit; When the value of the evaluation function is greater than a set threshold, the layout of the modules is repeatedly divided; When the value of the evaluation function is less than a set threshold, determining the packaging structure of the integrated circuit; The evaluation function is expressed as follows: ， in, is the evaluation function, is the number of levels, For the The trace length of the layer chip, For the The number of through silicon vias in the layer chip, is the maximum temperature difference of the integrated circuit, is the layer number of the chip layer, is the weight.

5. An integrated circuit 3D packaging structure, using the packaging method of an integrated circuit 3D packaging structure according to any one of claims 1 to 4, characterized in that: include: Substrate and multi-layer chip layers; The chip layer includes a plurality of modules inside, each module includes one or more through silicon vias inside, and the module is electrically connected to one or more modules through the through silicon vias.

6. An electronic device, characterized in that: It includes a processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, when the processor executes the computer instructions, the electronic device executes the packaging method of an integrated circuit 3D packaging structure as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a packaging method for an integrated circuit 3D packaging structure as described in any one of claims 1 to 4.

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