Escape wiring method and system based on preset line sequence and storage medium

Abstract

The invention discloses an escape wiring method and system based on a preset line sequence and a storage medium, and the method comprises the steps: obtaining the positions of all pins to be subjected to escape packaging, the to-be-escaped pins and the line sequence of the to-be-escaped pins, recording the sequences of all pins on a boundary as Q1,..., Qt according to the sequence and direction of the boundary, solving all the maximum common subsequences T1,..., Pk of the sequence and the sequences P1,..., Pk, ..., Tp; selecting the boundary U in one direction, fixing the projection of the common pin in the boundary U and the Tj in situ, then deleting the pin, and directly moving the pin towards the inner side by one grid for the boundary U and the pin in the boundary U but not in the Tj; a common pin in the boundary U and the boundary Tj divides the boundary U into new boundary intervals B1,..., Bq. According to the invention, automatic preset line sequence escape wiring can be realized.

Description

Technical Field

[0001] The present invention relates to the field of wiring software technology, and in particular to an escape wiring method, system and storage medium based on a preset line sequence. Background Art

[0002] In PCB design, the main task is to lay out the PCB wires. With the advancement of integration technology, the integration of chips continues to increase, and the number of chip I / O pins has increased dramatically. In order to meet the needs of development, a new variety has been added: ball grid array package, referred to as BGA (Ball Grid Array Package). The pins of BGA are under the chip. In order to realize the connection between the BGA pins and the wires of other components, the wires of the BGA pins need to be led out from the inside of the PCB under the chip. This is called escape wiring. In some cases, since the pin sequence of the external components connected to the BGA chip is fixed, if the wire sequence of the wire changes after the escape wiring, it may be necessary to make vias or wrap the wires. In order to avoid such a situation, it is necessary to plan the BGA escape wiring in advance. At present, the wiring design software does not provide this function, and it is impossible to automatically perform preset wire sequence escape wiring. Summary of the invention

[0003] To this end, it is necessary to provide an escape wiring method, system and storage medium based on a preset line sequence to solve the problem that wiring design software cannot automatically perform escape wiring with a preset line sequence.

[0004] To achieve the above object, the present invention provides an escape wiring method based on a preset line sequence, comprising the following steps:

[0005] Get all pin positions of the package to be escaped, the pins to be escaped and their line sequence, recorded as P1, ..., Pk;

[0006] For the outermost pins of the escape package, the four boundaries of the rectangular frame are taken. The outermost pins are on the boundary. The rectangular frame contains all the pins. The pins on each boundary divide the boundary into multiple boundary intervals. The boundary intervals of all boundaries are numbered in sequence, and recorded as B1,...,Bn;

[0007] The optional escape range of pin Pi is the boundary interval B_{a_i} to B_{a_j}. In the initialization phase, the optional boundary intervals of all pins Pi are a_i 1 and a_j n, indicating that any boundary interval can be used by any Pi.

[0008] According to the order and direction of the boundary, let all the pin sequences on the boundary be Q1, ..., Qt, and find all the maximum common subsequences T1, ..., Tp of this sequence and the sequence P1, ..., Pk;

[0009] Select the boundary U in one direction, project and fix the common pins in boundary U and Tj in place, then delete the pins, and move the boundary U and the pins in boundary U but not in Tj directly one grid inward; the common pins in boundary U and Tj divide boundary U into new boundary intervals B1, ..., Bq;

[0010] For all undeleted pins Pi, their projection intervals are restricted to a certain boundary interval Bi according to the line sequence and cached;

[0011] Determine the number of remaining unprojected pins. If the number of unprojected pins Pk is zero, lead the wires from the projected pins through the previously restricted boundary interval Bi and lead them out of the package to be escaped.

[0012] If the number of unprojected fixed points is not zero, return to step: according to the boundary order and direction, re-calculate the maximum common subsequence and loop the above steps.

[0013] Furthermore, the method further comprises the steps of:

[0014] After leading the wire to the outside of the package to be escaped, connect the wire to the package outside the package to be escaped.

[0015] Furthermore, the method further comprises the steps of:

[0016] Get a rewiring operation request, delete the existing wiring, change one direction and select the boundary U in another direction.

[0017] Furthermore, the boundary of the selected one direction is the boundary where the first pin T1 in the largest common subsequence T1, ..., Tp is located.

[0018] Further, the boundary in one of the selected directions is a boundary passed by a line connecting the center of the package to be escaped and the center of the package to be escaped outside.

[0019] Furthermore, the method further comprises the steps of:

[0020] Get the operation of dragging the package to be escaped by the mouse;

[0021] When the boundary through which the connection line between the external package center and the package center to be escaped passes changes, rewiring is performed.

[0022] Furthermore, the method further comprises the steps of:

[0023] Get the package to be escaped and the external package selected by the mouse;

[0024] The pins connected to the package to be escaped and the external package are used as the pins to be escaped, and the line sequence of the external package is used as the line sequence of the pins to be escaped.

[0025] Further, it is determined whether the number of pins to be escaped is greater than 1. If it is less than or equal to 1, no escape routing is performed.

[0026] The present invention provides a storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of the embodiments of the present invention are implemented.

[0027] The present invention provides an escape wiring system based on a preset line sequence, comprising a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the steps of the method described in any one of the embodiments of the present invention are implemented.

[0028] Different from the prior art, the above technical solution calculates the maximum common subsequence and limits the projection each time after the boundaries are successively reduced, and limits its projection interval to a certain boundary interval Bi each time and caches it. After completion, the wires are led out from the previously restricted boundary interval Bi in turn and led to the outside of the package to be escaped, and finally the escape wiring of the preset wire sequence is realized, thus realizing the automatic escape wiring of the preset wire sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A method flow chart of a specific embodiment of the present invention;

[0030] Figure 2 A schematic diagram of the wiring pins to be escaped of the present invention;

[0031] Figure 3 It is a schematic diagram of reducing the boundary of the wiring to be escaped of the present invention;

[0032] Figure 4 A schematic diagram of the wiring to be escaped of the present invention after wiring is completed;

[0033] Figure 5 The present invention is a simplified diagram showing the method flow of a specific embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0035] Reference to "embodiment" herein means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present application. The term "embodiment" appearing in various places in the specification does not necessarily refer to the same embodiment, nor does it particularly limit its independence or association with other embodiments. In principle, in the present application, as long as there is no technical contradiction or conflict, the various technical features mentioned in the embodiments can be combined in any way to form a corresponding implementable technical solution.

[0036] Unless otherwise defined, the technical terms used in this document have the same meanings as those generally understood by those skilled in the art to which this application belongs; the use of relevant terms in this document is only for describing specific embodiments and is not intended to limit this application.

[0037] In the description of this application, the term "and / or" is an expression used to describe the logical relationship between objects, indicating that three relationships may exist, for example, A and / or B, which means: A exists, B exists, and A and B exist at the same time. In addition, the character " / " in this article generally indicates that the objects before and after are in an "or" logical relationship.

[0038] In the present application, terms such as “first” and “second” are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship of quantity, priority or sequence between these entities or operations.

[0039] Without further limitations, in this application, the words "include", "comprises", "has" or other similar expressions used in the sentences are intended to cover non-exclusive inclusion. These expressions do not exclude the presence of additional elements in the process, method or product including the elements, so that the process, method or product including a series of elements may include not only those limited elements, but also other elements not explicitly listed, or also include elements inherent to such process, method or product.

[0040] Similar to the understanding in the Patent Examination Guidelines, in this application, expressions such as "greater than", "less than", "exceed" and the like are understood to exclude the number itself; expressions such as "above", "below", "within" and the like are understood to include the number itself. In addition, in the description of the embodiments of this application, "multiple" means more than two (including two), and similar expressions related to "multiple" are also understood in this way, such as "multiple groups", "multiple times", etc., unless otherwise clearly and specifically limited.

[0041] In the description of the embodiments of the present application, space-related expressions used, such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "vertical", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the specific embodiments or drawings, and are only for the convenience of describing the specific embodiments of the present application or facilitating the reader's understanding, and do not indicate or imply that the referred device or component must have a specific position, a specific orientation, or be constructed or operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0042] Unless otherwise expressly specified or limited, in the description of the embodiments of the present application, the terms such as "install", "connect", "connect", "fix", "set", etc. used should be understood in a broad sense. For example, the "connection" can be a fixed connection, a detachable connection, or an integrated setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. For technicians in the technical field to which the present application belongs, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0043] See also Figures 1 to 5 The present invention provides an escape wiring method based on a preset line sequence, comprising the following steps: Step S101 obtains all pin positions of the package to be escaped, the pins to be escaped and their line sequence, recorded as P1, ..., Pk, k is a sequence number, which is a natural number starting from 1. Figure 2 In the example, the pins to be escaped are marked as 1-5, that is, P1 to P5. The P1 pin actually corresponds to the pin at coordinate (2,2).

[0044] Then, step S102 is entered to take the four boundaries of the rectangular frame for the outermost pins of the escaped package, the outermost pins are on the boundary, the rectangular frame contains all the pins, the pins on each boundary divide the boundary into multiple boundary intervals, and the boundary intervals of all boundaries are numbered in sequence, recorded as B1, ..., Bn; Figure 2 shown.

[0045] Then enter step S103 to record the optional escape range of pin Pi as the boundary interval B_{a_i} to B_{a_j}. In the initialization stage, the optional boundary intervals of all pins Pi are a_i 1 and a_j n, indicating that any boundary interval can be used by any Pi. And step S104 records all pin sequences on the boundary as Q1,...,Qt according to the boundary order and direction, and calculates all maximum common subsequences T1,...,Tp of the sequence and sequence P1,...,Pk. The maximum common subsequence is also called the longest common subsequence, which is to obtain a new sequence with the same order in two sequences. This sequence is a new sequence formed by deleting some elements of the original sequence without changing the relative order of the sequence (or without deleting any elements). For example Figure 2 In , the boundary U has three pins (including P3), and the pins to be escaped are P1-P5, so the common subsequence is P3. Figure 3 , then the common subsequences are P1, P5.

[0046] Then enter step S105 to select a boundary U in one direction. Taking the above boundary as an example, you can actually select any boundary. The common pins in the boundary U and Tj are projected and fixed in place (the projection fixation indicates that the wire can be led out here later), and then the pin is deleted. For the boundary U and the pins in the boundary U but not in Tj, the pin is moved directly inward by one grid. It should be noted here that if it is a pin to be escaped, but it may not be a common sequence pin due to the order mismatch, the non-common pin to be escaped pin must also be indented and moved for the next judgment and wiring. The common pins in the boundary U and Tj divide the boundary U into new boundary intervals B1,...,Bq, such as Figure 3 In step S106, for all the undeleted pins Pi, their projection intervals are restricted to a certain boundary interval Bi according to the line sequence and cached, as shown in FIG. Figure 3 As shown, pins 1 and 2 are restricted to the left side of pin 3 in sequence, i.e., boundary interval B2, and pin 5 is restricted to the left side of pin 3 in sequence, i.e., boundary interval B3. Each time, they are cached so that subsequent wires can be led out in sequence. Step S107 determines the number of pins that are not fixed by projection. If the number of pins Pk that are not fixed by projection is zero, the wires are led out from the pins that are fixed by projection in sequence from the previously restricted boundary interval Bi and led out of the package to be escaped; Figure 4As shown, the black line extending upward from the pins 1-5 to be escaped is the lead wire. Taking pin 2 as an example, when the boundary is indented for the first time, it is limited to interval B2, and it will be led out from B2. If the number of unprojected fixed pins in step S108 is not zero, return to step 104: according to the boundary order and direction, re-calculate the maximum common subsequence and loop the above steps. Until the boundary interval Bi of all common pins is determined, the wire can be laid out by passing through the cached boundary interval in turn.

[0047] The present invention adopts a method of shrinking the boundary in sequence. First, the boundary is shrunk from the center of the component until it contacts the first pin, and all the pins contacted by the boundary are recorded and sorted, and the other virtual pins are recorded on the boundary. The boundary is shrunk again, and other virtual pins are moved vertically or horizontally until they contact the next pin. If the virtual point overlaps with the actual point, the virtual point is placed in the left boundary interval or the right boundary interval of the actual point according to the preset line sequence, and all the pins contacted by the boundary are recorded again and excluded, and the virtual pin is recorded on the boundary. Repeat the above steps until all pin points are on the boundary, and then wire according to the sequence, and then enlarge the boundary, keep the already laid line unchanged, and continue to enlarge. The wiring extends on the boundary interval, and after encountering the pin, the wiring and extension are further performed until the maximum boundary is reached to complete the wiring.

[0048] After the boundary is successively reduced, the present invention calculates the maximum common subsequence each time and limits the projection, and limits its projection interval to a certain boundary interval Bi each time and caches it. After completion, the wires are successively led out from the previously restricted boundary interval Bi and led to the outside of the package to be escaped, and finally the escape wiring of the preset wire sequence is realized, thus realizing the automatic escape wiring of the preset wire sequence.

[0049] In order to realize automatic connection of the wire, the present invention further comprises the step of: after the wire is led to the outside of the package to be escaped, the wire is connected to the package outside the package to be escaped. In this way, the wire can be automatically routed to the external package to be connected, reducing manual wiring operations and facilitating wiring.

[0050] Furthermore, the method further includes the steps of obtaining a rewiring operation request, deleting the existing wiring, changing a direction and selecting a boundary U in another direction. That is, through a rewiring request, such as inputting a rewiring operation instruction, the software can automatically change the direction and then rewire to meet the wiring requirements in different directions.

[0051] In some embodiments, the boundary of the selected one direction is the boundary where the first pin T1 in the largest common subsequence T1, ..., Tp is located. Figure 2As shown, the boundary where the common pin 3 is located is the selected boundary and is successively retracted, so that the line can be arranged around the first common pin, and the wiring is more optimized.

[0052] Or in other embodiments, the boundary of one of the selected directions is the boundary through which the line connecting the center of the package to be escaped and the center of the package to be escaped passes. If the package to be escaped needs to be connected is on the right side, the two package centers will pass through the right boundary after being connected, so that wiring can be started from the right boundary, which can reduce the length of the wire after wiring and optimize the wiring effect.

[0053] On the basis of the above embodiment, the package to be escaped can also be dragged, and the present invention further comprises the steps of: obtaining the operation of dragging the package to be escaped by the mouse; when the boundary through which the line connecting the external package center and the package center to be escaped passes changes, rewiring is performed. In this way, the user can drag the package to be escaped, and then after automatic rewiring, it can be seen which wiring is better, so that the user can quickly select the better wiring.

[0054] The pins and sequence to be escaped of the present invention can be realized through the function of software input, such as inputting a pin coordinate sequence, such as A12 (pin at the position of row 1 and column 2), A34, A36; then the input pins are the pins to be escaped, and the order is the order from front to back. In some embodiments, the software can also automatically obtain the pins and sequence to be escaped, and also includes the steps of: obtaining the package to be escaped and the external package selected by the mouse; using the pins connected to the package to be escaped and the external package as the pins to be escaped, and using the line sequence of the external package as the line sequence of the pins to be escaped. The package to be escaped is a BGA package, and the external package can be a dual-row package, etc. By selecting two packages with connections, the pins and sequence to be escaped can be quickly selected. Of course, the user can also manually modify the pins and sequence.

[0055] In order to avoid performing escape wiring on a single wire, the present invention can determine whether the number of pins to be escaped is greater than 1 before running, and if it is less than or equal to 1, no escape wiring is performed.

[0056] The present invention also provides a storage medium, the storage medium stores a computer program, and the computer program implements the steps of the above method when executed by a processor. The storage medium of this embodiment can be a storage medium set in an electronic device, and the electronic device can read the content of the storage medium and implement the effect of the present invention. The storage medium can also be a separate storage medium, and the storage medium is connected to the electronic device, and the electronic device can read the content in the storage medium and implement the method steps of the present invention. The present invention provides an escape wiring system based on a preset line sequence, including a memory and a processor, and the memory stores a computer program, and the computer program implements the steps of the method as described in any one of the embodiments of the present invention when executed by the processor. After the storage medium or system of this embodiment is reduced in sequence by the boundary, the maximum common subsequence is calculated each time and the projection is restricted, and each time its projection interval is restricted to a certain boundary interval Bi and cached, and after completion, the wires are led out from the previously restricted boundary interval Bi in sequence and led to the outside of the package to be escaped, and finally the escape wiring of the preset line sequence is realized, so that the escape wiring of the preset line sequence is automatically performed.

[0057] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. An escape wiring method based on a preset line sequence, characterized in that: The steps include: Get all pin positions of the package to be escaped, the pins to be escaped and their line sequence, recorded as P1, ..., Pk; For the outermost pins of the escape package, the four boundaries of the rectangular frame are taken. The outermost pins are on the boundary. The rectangular frame contains all the pins. The pins on each boundary divide the boundary into multiple boundary intervals. The boundary intervals of all boundaries are numbered in sequence, and recorded as B1,...,Bn; The optional escape range of pin Pi is the boundary interval B_{a_i} to B_{a_j}. In the initialization phase, the optional boundary intervals of all pins Pi are a_i 1 and a_j n, indicating that any boundary interval can be used by any Pi. According to the order and direction of the boundary, let all the pin sequences on the boundary be Q1, ..., Qt, and find all the maximum common subsequences T1, ..., Tp of this sequence and the sequence P1, ..., Pk; Select the boundary U in one direction, project and fix the common pins in boundary U and Tj in place, then delete the pins, and move the boundary U and the pins in boundary U but not in Tj directly one grid inward; the common pins in boundary U and Tj divide boundary U into new boundary intervals B1, ..., Bq; For all undeleted pins Pi, their projection intervals are restricted to a certain boundary interval Bi according to the line sequence and cached; Determine the number of remaining unprojected pins. If the number of unprojected pins Pk is zero, lead the wires from the projected pins through the previously restricted boundary interval Bi and lead them out of the package to be escaped. If the number of unprojected fixed points is not zero, return to step: according to the boundary order and direction, re-calculate the maximum common subsequence and loop the above steps.

2. The method for escaping wiring based on a preset line sequence according to claim 1, characterized in that: Also includes the steps: After leading the wire to the outside of the package to be escaped, connect the wire to the package outside the package to be escaped.

3. The method for escaping wiring based on a preset line sequence according to claim 1, characterized in that: Also includes the steps: Get a rewiring operation request, delete the existing wiring, change a direction and select the boundary U in another direction.

4. The method for escaping wiring based on a preset line sequence according to claim 1, characterized in that: The boundary of the selected one direction is the boundary where the first pin T1 in the largest common subsequence T1, ..., Tp is located.

5. The method for escaping wiring based on a preset line sequence according to claim 1, characterized in that: The boundary of the selected one direction is a boundary passed by a line connecting the center of the package to be escaped and the center of the package to be escaped.

6. The method for escaping wiring based on a preset line sequence according to claim 5, characterized in that: Also includes the steps: Get the operation of dragging the package to be escaped by the mouse; When the boundary through which the connection line between the external package center and the package center to be escaped passes changes, rewiring is performed.

7. The method for escaping wiring based on a preset line sequence according to claim 1, characterized in that: Also includes the steps: Get the package to be escaped and the external package selected by the mouse; The pins connected to the package to be escaped and the external package are used as the pins to be escaped, and the line sequence of the external package is used as the line sequence of the pins to be escaped.

8. The method for escaping wiring based on a preset line sequence according to claim 1, characterized in that: Determine whether the number of pins to be escaped is greater than 1. If it is less than or equal to 1, no escape routing is performed.

9. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

10. The escape wiring system based on the preset line sequence is characterized by: The method comprises a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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