Active driving circuit for display

Abstract

The active driving circuit is characterized by comprising a row power line, a transmission tube, a scanning shift circuit and a pixel circuit, the row power lines (Vddline) are mutually independent metal lines and are connected with a reset signal (Vini) or a light-emitting power supply (VDD) through a transmission tube (CT), a switch of the transmission tube is controlled by an output signal (Cn) of a scanning control circuit (CGOA), when the Cn is at a high level, the Vddline is connected to the Vini, and when the Cn is at a low level, the Vddline is connected to the VDD, so that the Vddline forms a pulse type signal; the pixel circuit is characterized in that the pixel circuit is connected with the Vddline. In the reset stage, Vini resets internal nodes of the whole row of pixel circuits through a row voltage source. In the compensation stage, VDD passes through a row voltage source, and a threshold value (Vth) is grabbed for driving tubes of a whole row of pixel circuits. In the light emitting stage, the VDD passes through a row voltage source and provides current for the whole row of pixels to emit light. Therefore, the line voltage source has multiple functions, so that the number of transistors in pixels can be reduced, and the PPI of the display panel is improved.

Description

Technical Field

[0001] The invention relates to a display driving circuit, in particular to an active driving power supply circuit for OLED and LED, belonging to the technical field of display. Background Art

[0002] Active drive circuits are generally used to drive array pixel displays, and their characteristic is that each pixel is equipped with an active device such as a transistor. For pixel self-luminous displays such as OLED and micro-LED, their active drive is generally current-type drive, that is, the light-emitting device of each pixel is driven by controlling the current through active devices. The most typical pixel architecture of the active drive circuit is 2T1C, that is, each pixel is equipped with 2 transistors and 1 capacitor, which generally writes data (voltage) into the capacitor through row scanning and transistor 1, and then controls the drive tube (transistor 2) in series with the light-emitting device through the capacitor, thereby achieving current and light brightness adjustment of the light-emitting device.

[0003] However, due to manufacturing deviations, the characteristics of driving tubes of different pixels are not consistent, resulting in uneven brightness of different pixels.

[0004] The 7T1C architecture (7 transistors + 1 capacitor) proposed by Samsung can solve the problem of uneven driving tube characteristics through compensation. However, due to the excessive number of transistors set for each pixel, it has a significant limitation on pixel density (PPI). For example, its PPI is mostly maintained in the range of 400-500 and it is difficult to break through 600. Summary of the invention

[0005] The purpose of the present invention is to provide an active driving circuit, which has a compensating effect on the inconsistency of driving tube characteristics, and the number of transistors per pixel is smaller, which is conducive to improving the pixel density of the display. The technical solution adopted is as follows: An active driving circuit is characterized by comprising a row power supply line, a transmission tube, a scanning shift circuit and a pixel circuit; The row power line (Vddline) is an independent metal line, connected to the reset signal (Vini) or the light-emitting power supply (VDD) through a transmission tube (CT), the switch of the transmission tube is controlled by the output signal (Cn) of the scanning control circuit (CGOA), when Cn is high level, Vddline is connected to Vini, when Cn is low level, Vddline is connected to VDD, so that Vddline becomes a pulse signal; The pixel circuit is characterized by being connected to Vddline, and the reset phase, compensation phase and light-emitting phase of the pixel circuit are all completed through Vddline; In the reset phase, Vini resets the internal nodes of the entire row of pixel circuits through the row voltage source.

[0006] In the compensation stage, the VDD signal passes through the row voltage source to capture the threshold (Vth) of the driving tube of the entire row of pixel circuits and perform Vth compensation.

[0007] In the light-emitting stage, the VDD signal passes through the row voltage source to provide current to the entire row of pixels for light emission.

[0008] Therefore, it can be seen from the description that the row voltage source Vddline has multiple functions, so that the number of transistors in the pixel can be reduced and the PPI of the display panel can be improved.

[0009] The abbreviations are as follows The transmission tube (TG) is a combination of an N transistor and a P transistor. The P tube is used to transmit high-level signals, and the N tube is used to transmit low-level signals.

[0010] GOA (gate driver on array) is a row scan shift circuit and is a well-known technology in the industry. The first scan shift circuit (CGOA) is a GOA that generates a Cn signal, the second scan shift circuit (SGOA) is a GOA that generates a Sn signal, the third scan shift circuit (EGOA) is a GOA that generates an Emn signal, and the fourth scan shift circuit (KGOA) is a GOA that generates a Kn signal.

[0011] Vdt is the data voltage, Vini is the low level signal, VDD is the light emitting power supply. The first transistor is T1, the second transistor is T2, and the driving tube is T3. The cathode power supply is Vss, the second power supply is Vss2, and the size can be set to Vss. The first capacitor is C1, and the second capacitor is C2.

[0012] Embodiment 1, the specific connection mode, for the convenience of description, is divided into the connection mode of the row power supply Vddline and the connection mode of the internal transistor of the pixel using Vddline: the connection mode of the row power supply is that each row of pixels has a row voltage source, and there are independent metal lines between them. CT is a transmission tube, the input of CT is Vini and VDD, the output of CT is Vddline, the control of CT is Cn, and Cn is the output of CGOA. The connection mode of the transistor inside the pixel is that T1T2 is a switch tube, T3 is a driving tube, Sn is connected to the gate of T1, Vdt and point a are connected to the source and drain of T1, Emn is connected to the gate of T2, Vddline and point c are connected to the source and drain of T2, point a is connected to the gate of T3, point c and point b are connected to the source and drain of T3, the anode of the light-emitting device is connected to point b, the cathode of the light-emitting device is connected to Vss, one end of the capacitor C1 is connected to point a and the other end is connected to point b, one end of the capacitor C2 is connected to point b and the other end is connected to Vss2, and Vss2 can also be set to Vss. Sn is the output signal of SGOA, and Emn is the output signal of EGOA.

[0013] The specific connection mode of embodiment 2 is divided into the connection mode of row power supply Vddline and the connection mode of the internal transistor of the pixel using Vddline for the convenience of description: the connection mode of row power supply is that each row of pixels has a row voltage source, and there are independent metal lines between them. CT is a transmission tube, the input of CT is Vini and VDD, the output of CT is Vddline, the control of CT is Cn, and Cn is the output of CGOA. The connection mode of the transistor inside the pixel is that T1T2 is a switch tube, T3 is a driving tube, Sn is connected to the gate of T1, Vdt and point a are connected to the source and drain of T1, Emn is connected to the gate of T2, point c and point b are connected to the source and drain of T2, point a is connected to the gate of T3, Vddline and point c are connected to the source and drain of T3, the anode of the light-emitting device is connected to point b, the cathode of the light-emitting device is connected to Vss, one end of capacitor C1 is connected to point a and the other end is connected to point b, one end of capacitor C2 is connected to point b and the other end is connected to Vss2, and Vss2 can also be set to Vss. Sn is the output signal of SGOA, and Emn is the output signal of EGOA.

[0014] The specific connection mode of embodiment 3 is divided into the connection mode of row power supply Vddline and the connection mode of the internal transistor of the pixel using Vddline for the convenience of description: the connection mode of row power supply is that each row of pixels has a row voltage source, and there are independent metal lines between them. CT is a transmission tube, the input of CT is Vini and VDD, the output of CT is Vddline, the control of CT is Cn, and Cn is the output of CGOA. The connection mode of the transistor inside the pixel is that T1 is a switch tube, T3 is a driving tube, Sn is connected to the gate of T1, Vdt and point a are connected to the source and drain of T1, point a is connected to the gate of T3, Vddline and point b are connected to the source and drain of T3, the anode of the light-emitting device is connected to point b, the cathode of the light-emitting device is connected to Vss, one end of capacitor C1 is connected to point a and the other end is connected to point b, one end of capacitor C2 is connected to point b and the other end is connected to Vss2, and Vss2 can also be set to Vss. Sn is the output signal of SGOA.

[0015] The specific connection method of Example 4 is divided into the connection method of the row power supply Vddline and the connection method of the internal transistor of the pixel using Vddline for the convenience of description: the connection method of the row power supply is that each row of pixels has a row voltage source, and there are independent metal lines between them. CT is a transmission tube, the input of CT is Vini and VDD, the output of CT is Vddline, the control of CT is Cn, and Cn is the output of CGOA. Insert a switch tube between VDD and TG (1 place), or insert a switch tube between TG and Vddline (2 places), or insert a switch tube at 1 place and 2 places at the same time. The switch tube is controlled by Kn, and Kn is the output of KGOA. The connection mode of the transistors inside the pixel is as follows: T1 is a switch tube, T3 is a driving tube, Sn is connected to the gate of T1, Vdt and point a are connected to the source and drain of T1, point a is connected to the gate of T3, Vddline and point b are connected to the source and drain of T3, the anode of the light-emitting device is connected to point b, the cathode of the light-emitting device is connected to Vss, one end of capacitor C1 is connected to point a and the other end is connected to point b, one end of capacitor C2 is connected to point b and the other end is connected to Vss2, and Vss2 can also be set to Vss. Sn is the output signal of SGOA. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 , Vini or VDD through TG and line power connection diagram Figure 2 , waveform of the row power supply signal under CGOA control Figure 3 , Pixel 1, Relationship between row pixels and row power lines Figure 4a , working waveform of pixel 1 a Figure 4b , working waveform of pixel 1 b Figure 5 , Pixel 2, Relationship between row pixels and row power lines Figure 6a , working waveform of pixel 2 a Figure 6b , working waveform of pixel 2 b Figure 7 , Pixel 3, Relationship between row pixels and row power lines Figure 8a , Pixel 3 working waveform a Figure 8b , Pixel 3 working waveform diagram b Fig. 9 , Pixel 4, Relationship between row pixels and row power lines Fig.10a , working waveform of pixel 4 a Fig.10b , working waveform diagram b of pixel 4 DETAILED DESCRIPTION Example

[0017] The connection and generation principle of the power line: Figure 1 In the figure, Vini is a low-level reset voltage; VDD is a mesh surface power supply that covers the entire display pixel area; Vddline row power supply is an independent metal line, and each row of pixels has its own row power supply; TG is a transmission tube composed of N tube and P tube, Vini is connected to the row power supply through the N tube of TG, and VDD is connected to the row power supply through the P tube of TG; CGOA is a scan shift unit, and its output signals C1, C2,,, Cn control the gate switches of the N tube and P tube in TG, and select Vini or VDD to connect to Vddline.

[0018] Figure 2 In the figure, it shows the waveform relationship between C1, C2, Cn and Vddline1, Vddline2, Vddlinen. When C1 is high, C1 selects Vini to connect to vddline1. When C1 is low, C1 selects VDD to connect to Vddline1. Similarly, Vddline2, Vddlinen are generated.

[0019] How pixels using row power lines work: Figure 3 In the figure, the connection relationship between pixel 1 and row power supply is shown, and a row of pixels is connected to a row of row power supplies. Inside the pixel, T1T2 is a switch tube, T3 is a drive tube, C1C2 is a capacitor, VSS and VSS2 can be the same low-level signal, or they can be set to different signals. Point a is the data line writing point and is also the gate of T3, and point b is the anode of the light-emitting device and is also the source of T3. SN is the output signal of SGOA, and EMn is the output signal of EGOA.

[0020] Figure 4a In the figure, the working waveform of pixel 1 illustrates the working process of pixel 1.

[0021] In the T1 reset phase, SN is high and T1 tube is turned on, the voltage of Vdt is Vofs, and Vofs is written to point a; EMn is high and T2 tube is turned on, Vddline is Vini, Vofs>Vini, Vini≈VSS, Vini is written to point b, and the OLED is reset.

[0022] In the T2 compensation stage, Sn is high T1 tube turned on, Va=Vofs, EMn is high T2 tube turned on, Vddline is VDD, b is written with voltage, Vb=Vofs-Vth.

[0023] In the T3 data writing phase, Sn is high, T1 tube is turned on, Vdt voltage is Vdt, Va=Vdt; EMn is low, T2 is disconnected, Vb=Vofs-Vth+(Vdt-Vofs)*C1 / (C 1+C2).

[0024] In the T4 light-emitting stage, Sn is low and T1 is disconnected, EMn is high and T2 is turned on. At this time, VDD provides light-emitting current to the light-emitting device through Vddline. The current size is determined by Va-Vb-Vth=(Vdt-Vofs)*C2 / (C1+C2), and the current size is I=K(Vdt-Vofs)*C2 / (C1+C2).

[0025] Figure 4b middle, and Figure 4a The only difference is the phase of Sn and Vdt. Figure 4a In the circuit, Sn turns on T1 first, and then Vdt jumps; Figure 4a In the example, Vdt jumps first, and then Sn turns on T1. The other two are the same and will not be described again. Example

[0026] The connection and generation of Vddline are the same as in Example 1 and will not be described here. However, the pixels are slightly different. Figure 5 In the embodiment, pixel 2 is another embodiment, and compared with pixel 1, the difference is that the position of T2 tube is different: in pixel 1, T2 tube is between Vddline and T3, and in pixel 2, T2 tube is between T3 and the light emitting device. The rest is the same and will not be described again.

[0027] Figure 6a , the principle is the same as Figure 4a , no longer narrate Figure 6b , the principle is the same as Figure 4b , no longer narrate Example

[0028] The connection and generation of Vddline are the same as in Example 1 and will not be described here. However, the pixels are slightly different. Figure 7 , another implementation of pixel 3, compared with pixel 1 and pixel 2, the difference is that pixel 3 does not have T2 transistor, Figure 8a , Figure 8b , is the working waveform diagram of pixel 3, Figure 8a and Figure 4a Figure 6a Compared with no EMn signal, Figure 8b and Figure 4b Figure 6b Compared with no Emn signal, the rest is the same.

[0029] Compared with pixel 1 and pixel 2, because there is no T2 transistor, during the T3 data writing stage, under the control of Va and Vb, T3 is slightly open, and the maximum leakage current value is about nA level. There will be leakage current flowing from VDD through Vddline into point b, causing the voltage Vb value of point b to change slightly, and the controlled leakage current can still be used. The same is true for other reasons, which will not be described. Example

[0030] The connection between Vddline and VDD is different from that in Example 1, Example 2, and Example 3. Fig. 9 , the connection relationship between pixel 4 and row power supply is another connection form, inserting a switch tube at 1, 2, or 1 plus 2 between Vddline and VDD, the purpose of which is to disconnect the switch tube in the T3 stage, disconnect Vddline and VDD, and leave Vddline floating, and turn on the switch tube in the T1T2T4 stage, and connect Vddline and VDD to each other. The switch tube can be an N tube, a P tube, or a transmission gate tube, and the P tube is selected as an example here.

[0031] Fig.10a and Figure 8a compared to, Fig.10b and Figure 8b In comparison, Kn signal is added. In the T1T2T4 stage, Kn is low, and Vddline and VDD are connected to each other. In the T3 stage, Kn is high, and VDD and Vddline are disconnected. At this time, Vddline is suspended. Kn is the output of KGOA.

[0032] and Figure 7 In contrast, because Vddline is disconnected from VDD and is suspended, in the T3 stage, the leakage current through the T3 tube flows from Vddline to point b, and the total charge will be much smaller than that in Example 3, because in Example 3, the leakage current through the T3 tube is the charge flowing from VDD to point b, and VDD is an external high-current voltage source. In Example 4, Vddline is suspended in the T3 stage, and the charge of Vddline is small, which is conducive to controlling the change in the Vb value.

Claims

1. An active drive circuit, characterized in that: It includes a light-emitting power supply, a row power supply, a transmission tube, a reset signal, a first scanning shift circuit, and a pixel circuit; Each row of the panel has its own row power supply, and each row is connected by independent metal wires; The light-emitting power source is connected to the row power source through the P-type transistor in the transmission tube, and the reset signal is connected to the row power source through the N-type transistor in the transmission tube. The first scanning shift circuit controls the gate of the P transistor and the gate of the N transistor in the transmission tube. When the output is high, the N transistor is turned on and the P transistor is turned off, and the row power supply is connected to the reset signal. When the output is low, the P transistor is turned on and the N transistor is turned off, and the row power supply is connected to the light-emitting power supply, so that the row voltage source becomes a pulse signal. The pixel circuit is directly connected to the row voltage source.

2. Based on claim 1, in the reset phase of the pixel, the reset signal is input into the entire row of pixel circuits through the row power metal line to reset the anode of the light-emitting device.

3. Based on claim 1, in the threshold compensation stage of the pixel, the light-emitting power source is input into the entire row of pixel circuits through the row power metal wire to capture the threshold of the driving tube.

4. Based on claim 1, in the light-emitting stage of the pixel, the light-emitting power supply provides current to the entire row of pixel circuits through the row power supply metal line to emit light.

5. Based on claim 1, a three-tube pixel circuit, characterized in that: It includes a row power supply, a first transistor, a second transistor, a driving tube, a first capacitor, and a second capacitor; the drain of the first transistor is connected to the data line, the source is connected to the gate of the driving tube, and the gate is controlled by a peripheral second scanning shift circuit; the row power supply, the second transistor, the driving tube, and the light-emitting device are connected in series from top to bottom; that is, the drain of the second transistor is connected to the row power supply, the source is connected to the drain of the driving tube, and the gate is controlled by a peripheral third scanning shift circuit; the drain of the driving tube is connected to the source of the second transistor, the source is connected to the anode of the light-emitting device, and the gate is connected to the source of the first transistor; The anode of the light emitting device is connected to the source of the driving tube, and the cathode is connected to the cathode power line. One end of the first capacitor is connected to the gate of the driving tube and the other end is connected to the source of the driving tube. One end of the second capacitor is connected to the source of the driving tube and the other end is connected to the second power supply.

6. Based on claim 1, another three-tube pixel circuit is characterized in that: It includes a row power supply, a first transistor, a second transistor, a driving tube, a first capacitor, and a second capacitor; the drain of the first transistor is connected to the data line, the source is connected to the gate of the driving tube, and the gate is controlled by a peripheral first scanning shift circuit; the row power supply, the driving tube, the second transistor, and the light-emitting device are connected in series from top to bottom; that is, the drain of the driving tube is connected to the row power supply, the source is connected to the drain of the second transistor, and the gate is connected to the source of the first transistor; The drain of the second transistor is connected to the source of the driving tube, the source is connected to the anode of the light-emitting device, and the gate is controlled by a third peripheral scan shift circuit; the anode of the light-emitting device is connected to the source of the second transistor, and the cathode is connected to the cathode power line, one end of the first capacitor is connected to the gate of the driving tube and the other end is connected to the anode of the light-emitting device, and one end of the second capacitor is connected to the anode of the light-emitting device and the other end is connected to the second power supply.

7. Based on claim 1, a two-tube pixel circuit, characterized in that: It includes a row power supply, a first transistor, a driving tube, a first capacitor, and a second capacitor; the drain of the first transistor is connected to the data line, the source is connected to the gate of the driving tube, and the gate is controlled by a peripheral second scanning shift circuit; the drain of the driving tube is connected to the row power supply, the source is connected to the anode of the light-emitting device, and the gate is connected to the source of the first transistor; The cathode of the light emitting device is connected to the cathode power line, one end of the first capacitor is connected to the gate of the driving tube and the other end is connected to the anode of the light emitting device, and one end of the second capacitor is connected to the anode of the light emitting device and the other end is connected to the second power supply.

8. Based on claim 7, the row power connection is characterized in that a switching tube is inserted between the light-emitting power line and the transmission tube (1 place), or a switching tube is inserted between the transmission tube and the row power supply (2 places), or a switching tube is inserted at 1 place and 2 places at the same time, and the switching of the switching tube is controlled by a fourth peripheral scanning shift circuit.

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