Etching method for reducing wafer fragmentation rate and wafer
By applying a low-energy electric field and pre-detection of the inert gas variation during the wafer etching process, adjusting the inert gas inlet to balance the force on the wafer, the problem of increased wafer fragmentation rate is solved, and a more stable etching process is achieved.
Patent Information
- Application Number
- CN202411907580.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2025-05-06
AI Technical Summary
During wafer etching, due to uneven internal stress and particle residues in the wafer, the wafer fragmentation rate increases, and it is difficult for the prior art to effectively detect and avoid this situation.
By applying a low-energy electric field in the etching cavity to stabilize the etching gas atmosphere, and pre-detect the inert gas variation before the reaction, adjust the inert gas inlet to balance the forces on the wafer, avoid stress imbalance and arc breakdown.
It effectively reduces the wafer fragmentation rate, avoids wafer rupture caused by stress imbalance and arc breakdown, and improves the stability and reliability of the etching process.
Smart Images
Figure CN119943662A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of wafer production, and in particular to an etching method and a wafer for reducing a wafer fragmentation rate. Background Art
[0002] In the semiconductor production process, when the production process reaches the second half, the internal stress of the wafer is uneven due to the stacking of various films inside the wafer, which leads to the expansion of lattice defects or the residue of particles, and then the wafer fragmentation rate will increase, and this defect or residue cannot be observed using microscopes and other appearance inspection methods. This problem also occurs on thinner wafers. When the wafer enters the etching reaction chamber, the inside of the chamber will be filled with a plasma environment. In order to ensure the stability of the physical position of the wafer during production in the chamber, the carrier carrying the wafer is electrostatically adsorbed to form a weak electric field between the wafer and the carrier, giving the wafer a downward force, thereby ensuring the relative stillness of the physical position of the wafer.
[0003] During the reaction, inert gas will flow through the small holes on the carrier to cool the wafer, and the inert gas will give the wafer an upward force. During the etching reaction, a high-energy electric field or magnetic field will be applied between the carrier and the upper plate to dissociate the gas in the reaction chamber for etching reaction. When the high-energy electric field is added, the position of the wafer with uneven stress is prone to instantaneous electron accumulation, resulting in arc breakdown and wafer breakage. Figure 1 In the wafer etching process, arc breakdown will bombard the breakdown products onto the carrier or the inside of the cavity, destroying the normal reaction environment of the cavity and causing production to stop. Summary of the invention
[0004] The purpose of the present invention is to avoid the shortcomings of the prior art and provide an etching method for reducing the wafer fragmentation rate. The etching method for reducing the wafer fragmentation rate can effectively adjust the overall stress of the wafer and avoid the problem of wafer fragmentation.
[0005] To achieve the above object, the present invention provides the following technical solutions:
[0006] An etching method for reducing wafer fragmentation rate is provided, comprising the following steps:
[0007] (1) placing a wafer in a working chamber, introducing etching gas and inert gas into the working chamber, and applying a first electric field to stabilize the etching gas atmosphere. The first electric field is a low-energy electric field, which stabilizes the etching gas atmosphere and avoids arc breakdown caused by instantaneous high voltage, which may cause wafer fragmentation.
[0008] (2) Before the etching of the working chamber occurs, pre-detect the change in the inert gas △Q in the working chamber. If |△Q|≥M 阈， M 阈is a preset value, the amount of inert gas introduced is adjusted to make the force acting on the upper surface of the wafer and the force acting on the lower surface of the wafer in the working chamber balanced with each other.
[0009] (3) Applying a second electric field to dissociate the internal etching gas in the working chamber and perform an etching process. The RF power used to generate the first electric field is 2.5% to 15% of the RF power used to generate the second electric field, so that the first electric field is a low-energy electric field and the second electric field is a high-energy electric field. Specifically, in the closed vacuum pressure container of the etching chamber, the RF power supply is fed between the two plates of the vacuum chamber to generate an alternating electric field. Under the action of the alternating electric field, the gas molecules gain energy and ionize to generate electrons and ions. The electrons respond to the alternating electric field and gain energy, while the ions are relatively heavy and gain less energy. When the alternating electric field is strong enough, it will cause the so-called electron avalanche. After avalanche breakdown, the gas becomes conductive due to the presence of a large number of free electrons, accompanied by light emission from excited atoms or molecules in the gas; under the action of the alternating electric field, the electrons are accelerated and collide with gas molecules or atoms. When the electron energy reaches a certain level, the collision becomes an inelastic collision, generating secondary electrons, which further collide with gas molecules, continuously ionizing the gas molecules and eventually forming plasma. The RF field allows electrons to oscillate in the plasma, resulting in multiple collisions with gas atoms, which leads to a high ionization rate, which is essential for maintaining the plasma state. Therefore, the RF power supply generates gas ionization in the etching chamber to form plasma, and uses the plasma for etching. Therefore, alternating electric fields of different intensities can be obtained by controlling the power of the RF power supply.
[0010] Before the etching chamber reacts, a pre-inspection step is added to detect the gas change of the inert gas in the working chamber. By observing the change of the inert gas, the amount of inert gas introduced is adjusted, so that the stress of the entire wafer can be adjusted, effectively avoiding the problem of fragmentation caused by the imbalance of the overall stress of the wafer. The first electric field as a low-energy electric field is applied to stabilize the etching gas atmosphere, avoid arc breakdown caused by instantaneous high voltage, and facilitate monitoring of the change of the inert gas.
[0011] Place the wafer on the carrier in the working chamber, and start the high voltage of the carrier. The carrier is used to place the wafer, and after the carrier is connected to the high voltage, a weak electrostatic adsorption electric field will be generated, so that the wafer is adsorbed on the carrier. The electrostatic adsorption electric field generates a downward adsorption force on the wafer, which is marked as F1;
[0012] As the inert gas flows on the bottom surface of the wafer, an upward force is generated on the wafer, which is marked as F2;
[0013] Due to the action of the second electric field, the atmosphere in the working chamber will cause ion reaction to form a plasma atmosphere, and the plasma atmosphere will generate a downward force on the wafer, marked as F3.
[0014] Whether the force acting on the upper surface of the wafer and the force acting on the lower surface of the wafer are balanced with each other is evaluated by judging whether the following formula is satisfied: ɑF1+F3≥βF2,
[0015] Within the set time, detect the gas change of the inert gas in the working chamber. If the inert gas change |△Q|≥M 阈 , M 阈 If it is a preset value, the amount of inert gas introduced and / or the voltage of the high voltage is adjusted until F2, F1 and F3 satisfy the following relationship: ɑF1+F3≥βF2, and then the wafer is etched.
[0016] When the force on the wafer changes, it will directly act on the wafer. Since the inert gas is located at the bottom of the wafer, it is possible to monitor the amount of inert gas to detect whether the working chamber needs to adjust the force on the wafer. The force state on the wafer can be corrected by adjusting the amount of inert gas introduced and / or the carrier voltage, wherein ɑF1+F3≥βF2 is satisfied.
[0017] Among them, ɑ is the ratio coefficient between the normal environment atmosphere and the plasma environment atmosphere in the working chamber;
[0018] β is the proportionality coefficient between the normal air pressure flow rate and the air pressure flow rate at the distance between the wafer and the stage.
[0019] F1=G+U / D*C*u, C is the capacitance between the stage and the wafer, u is the voltage difference between the wafer and the stage, U is the potential difference between the wafer and the stage, D is the distance from the wafer to the stage, and G is the gravity of the wafer;
[0020] F2=Q-[(1 / 2)ρv^2]-G, where Q is the inert gas flow rate, ρ is the inert gas density, v is the inert gas flow rate, and G is the gravity of the wafer.
[0021] For the electrostatic adsorption electric field, that is, the force applied to the wafer to adsorb downward:
[0022] F1=G+U / D*C*u, where C is the capacitance between the stage and the wafer, usually a fixed value, u is the voltage difference between the wafer and the stage, U is the potential difference between the wafer and the stage, D is the distance from the wafer to the stage, and G is the gravity of the wafer;
[0023] For the force generated by the flow of inert gas, the difference in upward force applied to the wafer is the upward force minus gravity: F2 = Q-[(1 / 2)ρv^2]-G, where Q is the flow rate, ρ is the density of the inert gas, v is the flow rate, and G is the weight of the wafer;
[0024] The working principle of the above method is that the present invention adds a pre-test step to the original process. Under the action of the first electric field, the first electric field is a low-energy electric field, which can ensure that the wafer will not be instantly broken down by the strain electric field. The size change of the inert gas originally used to cool the wafer in the chamber is used to detect whether the wafer has cracks or displacement, etc. According to the size of the inert gas, it can be inferred whether the above F2 is too large or too small for the wafer;
[0025] According to the preliminary inspection results, the size of the inert gas is synchronously adjusted to change F2. At the same time, in order to satisfy the dynamic balance, the electrostatic adsorption electric field needs to be synchronously adjusted. The size of the above F1 is adjusted by the size of the above u, where u is the voltage difference between the wafer and the carrier. When θ{Q-[(1 / 2)ρv^2]-G}≥ɑ(G+U / D*C*u)+F3≥β{Q-[(1 / 2)ρv^2]-G} is satisfied, the upward and downward directions applied to the wafer can reach a equilibrium state.
[0026] In some embodiments, when the inert gas in the working chamber is detected to rise, the inert gas introduced into the working chamber is reduced, F2 is reduced, and the voltage F1 of the high voltage is reduced at the same time, until F2 and F1 decrease until ɑF1+F3≥βF2 is satisfied;
[0027] If the inert gas rises, especially when it rises suddenly, it is necessary to reduce the inert gas flow rate and reduce the carrier high pressure at the same time to achieve the effect of reducing F2 and F1 at the same time, so that ɑF1+F3≥βF2
[0028] When it is detected that the inert gas in the working chamber decreases, only the voltage of the high voltage is reduced to reduce F1 until ɑF1+F3≥βF2 is satisfied.
[0029] It is necessary to lower the high voltage of the carrier and reduce the adsorption of F1 on the wafer so that ɑF1+F3≥βF2 is satisfied.
[0030] By detecting the inert gas and checking the wafer before formal production, it is possible to promptly detect whether the size of the inert gas has changed, and then deduce whether the force of mutual adsorption between the carrier and the wafer needs to be adjusted, thereby avoiding the wafer from breaking in the cavity due to the imbalance of two opposite forces applied to the wafer; at the same time, it also avoids the use of high-energy electric fields in formal production to promote electron aggregation at weak points with uneven stress inside the wafer, or thin thickness, resulting in instantaneous arc breakdown and wafer breakage.
[0031] In some embodiments, F2, F1 and F3 also satisfy the following relationship, θF2≥ɑF1+F3, θ wafer characteristic coefficient.
[0032] Combined with the wafer material and considering factors such as the brittleness and hardness of the wafer, the force applied to the wafer should also satisfy θF2≥ɑF1+F3, that is, θF2≥ɑF1+F3≥βF2, where θ is a fixed coefficient related to the wafer material, thickness and weight.
[0033] The higher the density, thickness and weight of the wafer substrate material, the smaller θ is. Affected by the plasma atmosphere, θ is a fixed value related to the wafer material that is far less than 1. Generally, θ has a stronger correlation with the wafer characteristics, and θ is different for different wafers.
[0034] In some embodiments, the high voltage connected to the carrier is 800V to 2000V.
[0035] In operation, the voltage of the carrier can be adjusted according to this range.
[0036] In some embodiments, the adjustment amount of the high voltage is 0-800V.
[0037] Control the voltage adjustment correction range of the carrier to avoid excessive adjustment.
[0038] In some embodiments, the amount of the inert gas introduced is 8 to 20 T.
[0039] During operation, the amount of inert gas introduced can be adjusted according to this range.
[0040] In some embodiments, the reduced amount of the inert gas is 2 to 8 T.
[0041] Control the correction range of the inert gas intake to avoid excessive adjustments.
[0042] In some embodiments, the step of performing an etching reaction on the wafer includes:
[0043] A second electric field is applied to dissociate the internal etching gas in the working chamber to carry out the etching process, and then the electric field is gradually extinguished, the inert gas is stopped from being introduced, and the high voltage of the carrier is turned off; the working chamber is evacuated, and then the wafer is taken out.
[0044] Beneficial effects of the etching method for reducing wafer fragmentation rate of the present invention:
[0045] (1) The present invention provides an etching method for reducing the wafer fragmentation rate. Before the etching chamber reacts, the present invention adds a pre-inspection step to detect the gas change of the inert gas in the working chamber. By observing the change of the inert gas, the inert gas introduction amount is adjusted, so that the overall stress of the wafer can be adjusted, effectively avoiding the problem of fragmentation caused by overall stress imbalance of the wafer.
[0046] (2) The present invention provides an etching method for reducing wafer fragmentation rate, wherein a low-energy electric field is applied and then the etching gas atmosphere is stabilized, thereby avoiding arc breakdown caused by instantaneous high voltage and facilitating monitoring of changes in the amount of inert gas.
[0047] Also provided is a wafer, which is produced by the above-mentioned etching method for reducing wafer fragmentation rate. BRIEF DESCRIPTION OF THE DRAWINGS
[0048] Figure 1 This is a schematic diagram of the traditional wafer etching process.
[0049] Figure 2 It is a schematic diagram of the process of wafer etching according to an embodiment of the present invention.
[0050] Figure 3 Schematic diagram of the relationship between the downward forces θF2, βF2 and F3 applied to the wafer and the voltage u according to an embodiment of the present invention.
[0051] Figure 4 3 is a diagram showing the effect of the downward forces θF2 and βF2 applied to the wafer according to an embodiment of the present invention.
[0052] Figure 5 Schematic diagram of the force on the wafer in the working chamber according to the embodiment of the present invention. DETAILED DESCRIPTION
[0053] The preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.
[0054] The terms used in the present invention are only for the purpose of describing specific implementation regulations, and are not intended to limit the present invention. The singular forms "a", "the" used in the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items.
[0055] It should be understood that although the terms "first", "second", "third", etc. may be used to describe various information in the present invention, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present invention, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.
[0056] Example
[0057] The etching method for reducing the wafer fragmentation rate disclosed in this embodiment is described in detail in Figure 2 , 5 , where F1 is the downward force generated by the electrostatic adsorption electric field between the wafer and the carrier, as shown by the lower left arrow 1 in the figure, F2 is the upward force generated on the wafer due to the flow of inert gas, as shown by the right arrow 2 in the figure, and F3 is the downward force formed by the plasma atmosphere, as shown by the middle arrow 3 in the figure.
[0058] The reduction method shown comprises the following steps:
[0059] (1) placing a wafer in a working chamber, introducing etching gas and inert gas into the working chamber, applying a first electric field to stabilize the etching gas atmosphere, wherein the first electric field has a low electric field intensity and is a low-energy electric field, so as to stabilize the etching gas atmosphere and avoid arc breakdown caused by instantaneous high voltage, which may cause wafer fragmentation.
[0060] (2) Before the etching of the working chamber occurs, pre-detect the change in the inert gas △Q in the working chamber. If |△Q|≥M 阈， M 阈 is a preset value, the amount of inert gas introduced is adjusted to make the force acting on the upper surface of the wafer and the force acting on the lower surface of the wafer in the working chamber balanced with each other.
[0061] Before the etching chamber reacts, a pre-inspection step is added to detect the gas change of the inert gas in the working chamber. By observing the change of the inert gas, the amount of inert gas introduced is adjusted, so that the stress of the entire wafer can be adjusted, and the problem of fragmentation caused by the imbalance of the overall stress of the wafer can be effectively avoided. A first electric field is applied, which is a low-energy electric field, to stabilize the etching gas atmosphere, avoid arc breakdown caused by instantaneous high voltage, and facilitate monitoring of the change of the inert gas.
[0062] (3) applying a second electric field to dissociate the internal etching gas in the working chamber to perform an etching process.
[0063] The RF power used to generate the first electric field is 2.5% to 15% of the RF power used to generate the second electric field. Specifically, the first electric field is a low-energy electric field and the second electric field is a high-energy electric field; that is, the electric field strength of the second electric field is higher than that of the first electric field. Specifically, in the closed vacuum pressure vessel of the etching cavity, the RF power supply is fed between the two plates of the vacuum chamber to generate an alternating electric field. Under the action of the alternating electric field, the gas molecules gain energy and ionize, generating electrons and ions. The electrons respond to the alternating electric field and gain energy, while the ions are relatively heavy and gain less energy. When the alternating electric field is strong enough, it will cause the so-called electron avalanche. After the avalanche breakdown, due to the large number of free electrons, the gas becomes conductive, accompanied by the light emission of excited atoms or molecules in the gas; under the action of the alternating electric field, the electrons are accelerated and collide with gas molecules or atoms. When the electron energy reaches a certain level, the collision becomes an inelastic collision, generating secondary electrons, which further collide with gas molecules, continuously ionizing the gas molecules, and finally forming plasma. The RF field allows electrons to oscillate in the plasma, resulting in multiple collisions with gas atoms, which leads to a high ionization rate, which is essential for maintaining the plasma state. Therefore, the RF power supply generates gas ionization in the etching chamber to form plasma, and uses the plasma for etching. Therefore, by controlling the power of the RF power supply, alternating electric fields of different intensities can be obtained.
[0064] Exemplarily, the power of the machine used to generate the first electric field is less than 50W, and the power of the machine used to generate the second electric field is 300-2000W.
[0065] More specifically,
[0066] The wafer is placed on a stage in the working chamber, and the high voltage of the stage is turned on to form an electrostatic adsorption electric field between the wafer and the stage. The electrostatic adsorption electric field generates a downward adsorption force on the wafer, which is marked as F1;
[0067] The carrier is used to place the wafer, and when the carrier is connected to a high voltage, an electrostatic adsorption electric field is generated, so that the wafer is adsorbed on the carrier. At this time, the electrostatic adsorption electric field generates a downward adsorption force on the wafer, which is marked as F1;
[0068] Introducing etching gas into the working chamber to form an etching gas atmosphere;
[0069] A first electric field is applied, which is a low-energy electric field. Technical personnel in this field can adjust it according to actual conditions during production to stabilize the etching gas atmosphere and avoid arc breakdown caused by instantaneous high voltage, which may cause wafer fragmentation.
[0070] Inert gas is introduced into the working chamber, and the inert gas flows on the bottom surface of the wafer and generates an upward force on the wafer, which is marked as F2.
[0071] As the inert gas flows on the bottom surface of the wafer, an upward force is generated on the wafer, marked as F2.
[0072] The working chamber is formed into a plasma atmosphere, and the plasma atmosphere exerts a downward force on the wafer, which is marked as F3.
[0073] Due to the action of the first electric field, an ion reaction occurs in the atmosphere of the working chamber to form a plasma atmosphere, and the plasma atmosphere generates a downward force on the wafer.
[0074] Within the set time, set at a time interval of 2 to 5 seconds, the gas change of the inert gas in the working chamber is detected. If the inert gas change |△Q|≥M 阈 , M 阈 If it is a preset value, the amount of inert gas introduced and / or the voltage of the high voltage is adjusted until F2, F1 and F3 satisfy the following relationship: ɑF1+F3≥βF2, and then the wafer is etched.
[0075] When the force on the wafer changes, it will directly act on the wafer. Since the inert gas is located at the bottom of the wafer, it is possible to monitor the amount of inert gas to detect whether the working chamber needs to adjust the force on the wafer. The force state on the wafer can be corrected by adjusting the amount of inert gas introduced and / or the carrier voltage, wherein ɑF1+F3≥βF2 is satisfied.
[0076] Among them, ɑ is the ratio coefficient between the normal environment atmosphere and the plasma environment atmosphere in the working chamber;
[0077] β is the proportionality coefficient between the normal air pressure flow rate and the air pressure flow rate at the distance between the wafer and the stage.
[0078] F1=G+U / D*C*u, C is the capacitance between the stage and the wafer, u is the voltage difference between the wafer and the stage, U is the potential difference between the wafer and the stage, D is the distance from the wafer to the stage, and G is the gravity of the wafer;
[0079] F2=Q-[(1 / 2)ρv^2]-G, where Q is the inert gas flow rate, ρ is the inert gas density, v is the inert gas flow rate, and G is the gravity of the wafer.
[0080] For the electrostatic adsorption electric field, that is, the force applied to the wafer to adsorb downward:
[0081] F1=G+U / D*C*u, where C is the capacitance between the stage and the wafer, usually a fixed value, u is the voltage difference between the wafer and the stage, U is the potential difference between the wafer and the stage, D is the distance from the wafer to the stage, and G is the gravity of the wafer;
[0082] For the force generated by the flow of inert gas, the difference in upward force applied to the wafer is the upward force minus gravity: F2 = Q-[(1 / 2)ρv^2]-G, where Q is the flow rate, ρ is the density of the inert gas, v is the flow rate, and G is the weight of the wafer;
[0083] Since the cavity is a plasma environment, it is microscopically different from the normal environment. Usually, F1 and F2 both need to increase a coefficient: ɑ and β; wherein ɑ is the proportional coefficient between the normal environment atmosphere and the plasma environment, and this value is usually much smaller than 1. This is because in the plasma atmosphere, the original gas molecules need to be dissociated, and will absorb part of the energy formed by the second electric field to increase their own free path and dissociation energy, and in this environment atmosphere, gravity is also reduced synchronously; β is the distance between the wafer and the carrier in an extremely small space, that is, the distance between the wafer and the carrier mentioned in the present invention, and this value is usually much smaller than 1. This is because in an extremely small space, inert gas particles, in addition to flowing, increase the collision and friction between each other and the liquid side walls, resulting in the actual flow rate being limited, and in a microscopic environment, the gas density is also different from that in an ordinary atmospheric environment; usually, inert gases include but are not limited to helium.
[0084] The plasma will also move downward under the action of high-energy electric and magnetic fields in the chamber, bombarding the wafer surface to form a downward force F3. Usually, F3 is strongly related to the process in the working chamber. When the wafer is operating a certain process menu in the working chamber, its F3 is a relatively fixed value. Under normal production conditions, ɑF1+F3≥βF2 is required, so that the downward force applied to the wafer is not less than the upward force applied to the wafer, so that the wafer can be kept on the table without displacement, ensuring that the wafer is not affected by its position inside the premise during the production process, that is, ensuring etching uniformity.
[0085] However, due to the uneven stress inside the wafer caused by the stacking of various films inside the wafer, the expansion of lattice defects, the residue of particles, or the uneven thickness of the wafer, the downward force F1 and F3 applied to the wafer is very easy to form local aggregation under the influence of the electric field and plasma atmosphere, and the process causes the carrier to be damaged due to the "breakdown effect". Therefore, ɑF1+F3 should be less than the maximum force that the carrier can withstand when it is intact. Usually, the surface material of the carrier includes but is not limited to nitrogen aluminum or aluminum oxide ceramics, and the maximum weight that can be borne is not more than 10 2 N.
[0086] That is, the working principle of the above method is that the present invention adds a pre-test step to the original process. Under the action of the first electric field (the first electric field is a low-energy electric field), it can be ensured that the wafer will not be instantly broken down by the high-energy electric field. By using the size change of the inert gas originally used to cool the wafer in the chamber, it is detected whether the wafer has cracks or displacement, etc. According to the size of the inert gas, it can be inferred whether the above F2 is too large or too small for the wafer;
[0087] According to the preliminary inspection results, the size of the inert gas is synchronously adjusted to change F2. At the same time, in order to satisfy the dynamic balance, the electrostatic adsorption electric field needs to be synchronously adjusted. The size of the above F1 is adjusted by the size of the above u, where u is the voltage difference between the wafer and the carrier. When θ{Q-[(1 / 2)ρv^2]-G}≥ɑ(G+U / D*C*u)+F3≥β{Q-[(1 / 2)ρv^2]-G} is satisfied, the upward and downward directions applied to the wafer can reach a equilibrium state.
[0088] When the weight of the wafer increases, θ and β will decrease synchronously. When the same etching process is carried out in the same reaction chamber, u needs to be reduced synchronously. However, since θ and β are coefficients far less than 1, in order to avoid excessive reduction of θF2 and βF2, it is necessary to reduce the inert gas flow rate v. Usually, it is different from the calculation method under conventional atmospheric pressure. The flow rate is expressed in gas flow per second, which is generally not less than 2sccm. The schematic diagram of the force relationship applied to the wafer according to the above formula is as follows Figure 3 and 4 .
[0089] According to the correction result, the process parameters are set so that the wafer can be etched under the action of more balanced forces.
[0090] When the inert gas in the working chamber is detected to rise, the inert gas is reduced from entering the working chamber, F2 is reduced, and the voltage F1 of the high voltage is reduced at the same time, until F2 and F1 decrease until ɑF1+F3≥βF2 is satisfied;
[0091] If the inert gas rises, especially when it rises suddenly, it is necessary to reduce the inert gas flow rate and reduce the carrier high pressure at the same time, so as to achieve the effect of reducing F2 and F1 at the same time, so that ɑF1+F3≥βF2;
[0092] When it is detected that the inert gas in the working chamber decreases, only the voltage of the high voltage is reduced to reduce F1 until ɑF1+F3≥βF2 is satisfied.
[0093] It is necessary to lower the high voltage of the carrier and reduce the adsorption of F1 on the wafer so that ɑF1+F3≥βF2 is satisfied.
[0094] It can be seen that by detecting the inert gas and checking the wafer before formal production, it is possible to promptly discover whether the size of the inert gas has changed, and then deduce whether the force of mutual adsorption between the carrier and the wafer needs to be adjusted, thereby avoiding the wafer from breaking in the cavity due to the imbalance of two opposite forces applied to the wafer; at the same time, it also avoids the high-energy electric field used in formal production, which causes electrons to gather at weak points with uneven stress inside the wafer or thin thickness, resulting in instantaneous arc breakdown and wafer breakage.
[0095] Specifically,
[0096] Control strategy when inert gas rises:
[0097] The pressure or concentration of the inert gas in the working chamber is continuously monitored to detect if it increases.
[0098] Once the inert gas is found to rise, especially when it rises suddenly, the amount of inert gas introduced should be reduced immediately to control the gas pressure in the chamber.
[0099] At the same time, the high voltage is lowered to reduce the electric field force on the wafer.
[0100] Continue to adjust until the condition αF1+F3≥βF2 is met;
[0101] Likewise, the pressure or concentration of the inert gas within the working chamber is continuously monitored to detect if it drops.
[0102] To reduce the high voltage voltage only:
[0103] Once the inert gas is detected, only the high voltage is reduced to reduce the electric field force on the wafer.
[0104] Adjust the high voltage voltage until αF1+F3≥βF2 to reduce the adsorption force of the wafer and ensure the stability of the wafer processing process.
[0105] By precisely controlling the inert gas flow and high voltage voltage, the force acting on the wafer can be effectively regulated, ensuring that the wafer will not be damaged due to excessive adsorption force or pressure during processing.
[0106] This control strategy helps maintain environmental stability within the working chamber while protecting the wafer from damage, improving the reliability and efficiency of the semiconductor manufacturing process.
[0107] This dynamic adjustment strategy is a common feedback control mechanism in semiconductor manufacturing. It can respond to changes in process variables and ensure that process conditions are always optimal.
[0108] In this embodiment, the M 阈 The value can be adjusted according to production needs.
[0109] In this embodiment, F2, F1 and F3 also satisfy the following relationship: θF2≥ɑF1+F3, θ wafer characteristic coefficient.
[0110] Combined with the wafer material and considering factors such as the brittleness and hardness of the wafer, the force applied to the wafer should also satisfy θF2≥ɑF1+F3, that is, θF2≥ɑF1+F3≥βF2, where θ is a fixed coefficient related to the wafer material, thickness and weight.
[0111] The higher the density, thickness and weight of the wafer substrate material, the smaller θ is. Affected by the plasma atmosphere, θ is a fixed value related to the wafer material that is far less than 1. Generally, θ has a stronger correlation with the wafer characteristics, and different wafers have different θ.
[0112] β has a stronger correlation with the gap between the wafer and the stage, and has certain microscopic properties. θ has a larger value than β, and the difference between the two is generally 2 to 3 orders of magnitude. When designing and processing wafers, the brittleness and hardness of the wafer need to be considered to avoid wafer cracking or damage due to improper force application. The force during the processing needs to be precisely controlled to ensure the integrity and processing quality of the wafer.
[0113] In this embodiment, the high voltage connected to the carrier is 800V to 2000V.
[0114] In operation, the voltage of the carrier can be adjusted according to this range.
[0115] In this embodiment, the adjustment amount of the high voltage is 0-800V.
[0116] Control the voltage adjustment correction range of the carrier to avoid excessive adjustment.
[0117] In this embodiment, the amount of inert gas introduced is 8-20T.
[0118] During operation, the amount of inert gas introduced can be adjusted according to this range.
[0119] In this embodiment, the reduction amount of the inert gas is 2-8T.
[0120] Control the correction range of the inert gas intake to avoid excessive adjustments.
[0121] In this embodiment, the step of performing an etching reaction on the wafer includes:
[0122] A second electric field is applied to dissociate the internal etching gas in the working chamber to carry out the etching process, and then the second electric field is gradually extinguished, the inert gas is stopped from being introduced, and the high voltage of the carrier is turned off; the working chamber is evacuated, and then the wafer is taken out.
[0123] Specifically,
[0124] Under the corrected inert gas flow rate and the stage high pressure, the etching gas is introduced to form an etching gas atmosphere;
[0125] Applying a second electric field (the second electric field is a high-energy electric field), and those skilled in the art can adjust the value of the second electric field according to specific operations to dissociate the etching gas in the working chamber and complete the etching process;
[0126] Gradually extinguish the high-energy electric field and stop the inert gas flow;
[0127] Turn off the stage high voltage;
[0128] The working chamber is continuously evacuated to remove residual gas, production by-products and other particles of various forms from the process chamber;
[0129] Transfer the wafer out of the working chamber.
[0130] Usually, the materials of wafers include but are not limited to Si, sapphire, SiC and other materials;
[0131] The carrier high voltage is generally set to 800-2000V. The carrier high voltage needs to be corrected, usually in the range of 0-800V.
[0132] Inert gas is usually an inert gas with a relatively small molecular mass, including but not limited to helium. From a qualitative analysis point of view, when the inner diameter of the pipeline is constant, the pressure and flow rate in the pipeline are directly proportional, that is, the greater the pressure, the greater the flow rate. According to the common saying in the industry, the setting size of the inert gas is usually characterized by pressure. Generally, the pressure of the inert gas in the etching machine is set to 8-20T. It is necessary to reduce the gas flow rate, usually adjusted at around 2-8T.
[0133] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values of the parts and steps described in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship. The technology, methods and equipment known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the technology, methods and equipment should be regarded as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.
[0134] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.
[0135] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.
[0136] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of this application.
[0137] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. An etching method for reducing wafer fragmentation rate, characterized in that: The following steps are involved: (1) placing a wafer in a working chamber, introducing an etching gas and an inert gas into the working chamber, and applying a first electric field to stabilize the etching gas atmosphere; (2) Before the etching of the working chamber occurs, pre-detect the change in the inert gas △Q in the working chamber. If |△Q|≥M 阈， M 阈 is a preset value, adjusting the amount of inert gas introduced so that the force acting on the upper surface of the wafer and the force acting on the lower surface of the wafer in the working chamber are balanced with each other; (3) applying a second electric field to dissociate the internal etching gas in the working chamber and perform an etching process; The radio frequency power used to generate the first electric field is 2.5% to 15% of the radio frequency power used to generate the second electric field.
2. The etching method for reducing wafer fragmentation rate according to claim 1, characterized in that: The step (1) comprises: The wafer is placed on a stage in the working chamber, and the high voltage of the stage is turned on to form an electrostatic adsorption electric field between the wafer and the stage. The electrostatic adsorption electric field generates a downward adsorption force on the wafer, which is marked as F1; The inert gas flows on the bottom surface of the wafer and generates an upward force on the wafer, which is marked as F2. A plasma atmosphere is formed in the working chamber, and the plasma atmosphere generates a downward force on the wafer, which is marked as F3.
3. The etching method for reducing wafer fragmentation rate according to claim 2, characterized in that: The step (2) comprises: Whether the force acting on the upper surface of the wafer and the force acting on the lower surface of the wafer are balanced with each other is evaluated by judging whether the following formula is satisfied: ɑF1+F3≥βF2, Among them, ɑ is the ratio coefficient between the normal environment atmosphere and the plasma environment atmosphere in the working chamber; β is the proportionality coefficient between the normal air pressure flow rate and the air pressure flow rate at the distance between the wafer and the stage.
4. The etching method for reducing wafer fragmentation rate according to claim 3, characterized in that: F1=G+U / D*C*u, C is the capacitance between the stage and the wafer, u is the voltage difference between the wafer and the stage, U is the potential difference between the wafer and the stage, D is the distance from the wafer to the stage, and G is the gravity of the wafer; F2=Q-[(1 / 2)ρv^2]-G, where Q is the inert gas flow rate, ρ is the inert gas density, v is the inert gas flow rate, and G is the gravity of the wafer.
5. The etching method for reducing wafer fragmentation rate according to claim 3, characterized in that: When it is detected that the inert gas in the working chamber rises, the inert gas introduced into the working chamber is reduced, and at the same time, the high voltage of the carrier is reduced to reduce F2 and F1 until ɑF1+F3≥βF2 is satisfied.
6. The etching method for reducing wafer fragmentation rate according to claim 3, characterized in that: When it is detected that the inert gas in the working chamber decreases, only the high voltage of the carrier is reduced to reduce F1 until ɑF1+F3≥βF2 is satisfied.
7. The etching method for reducing wafer fragmentation rate according to claim 2, characterized in that: The F2, F1 and F3 also satisfy the following relationship: θF2≥ɑF1+F3, where θ is the wafer characteristic coefficient.
8. The etching method for reducing wafer fragmentation rate according to claim 2, characterized in that: The high voltage connected to the carrier is 800V to 2000V, and the adjustment amount of the high voltage is 0 to 800V.
9. The etching method for reducing wafer fragmentation rate according to claim 1, characterized in that: The amount of the inert gas introduced is 8T to 20T, and the amount of the inert gas reduced is 2T to 8T.
10. A wafer, characterized in that: The wafer is prepared by the etching method for reducing wafer fragmentation rate as described in any one of claims 1 to 11.