Process method for preventing grid electrode of power device with ESD (Electro-Static Discharge) structure from generating arc
By first forming a thermal oxide layer in the ESD structure process of the power device, and using the silicon nitride layer as the etching barrier layer during wet etching, the problem of thermal oxide layer piercing on the gate polycrystalline silicon surface caused by wet etching is solved, which significantly reduces the occurrence of arc and leakage abnormalities, and improves the film uniformity of the ESD oxide layer.
Patent Information
- Application Number
- CN202510105521.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-05-06
AI Technical Summary
In the prior art, when making the ESD structure of a power device, the thermal oxide layer on the gate polysilicon surface is easily etched during the wet etching process, causing arc and leakage abnormalities.
After gate polysilicon etching, a thermal oxide layer with a thickness of 150 Å is formed first, and a silicon nitride layer with a thickness of 60 Å is used as an etching barrier layer during the wet etching of the ESD oxide layer to prevent local overetching.
It effectively prevents the thermal oxide layer on the surface of the gate polysilicon to be engraved, reduces the occurrence of arc and leakage abnormalities, and improves the film uniformity of the ESD oxide layer.
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Figure CN119943684A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor device technology, and in particular to a process method for preventing arcs from being generated on a gate of a power device with an ESD structure. Background Art
[0002] In order to prevent power devices (Power MOS) from being damaged by electrostatic discharge (ESD) and causing the oxide layer, PN junction and even insulation layer to break down, polysilicon diode protection structures are introduced into power devices to form ESD protection structures to enhance the device's anti-static ability. Below the ESD polysilicon layer with a thickness of about 6000Å is a thermal oxide layer (thermal OX) and an APCVD NSG layer (Nondoped Silicate Glass) with a thickness of about 2000Å, while the polysilicon layer is covered with an interlayer dielectric layer ILD.
[0003] The traditional process flow of the ESD structure is to insert an ESD loop process between the gate polysilicon etching of the power device and the body injection process. For example, a common process includes: The polysilicon process after the gate trench etching, followed by the formation of the CVD layer under the ESD and the deposition of the ESD polysilicon layer, B ion implantation and photolithography of the ESD polysilicon, polysilicon dry etching process, annealing and wet etching process of the oxide layer; then the body region injection and source region injection of the power device are carried out, followed by the contact hole process, including isolation layer, metal tungsten deposition and back etching, etc.
[0004] In the above process, the ESD loop process needs to use wet etching to remove the 2000Å thick APCVD NSG layer before conventional body and source region implantation. Due to the insufficient density of the APCVD NSG film layer, there is a greater risk of excessive wet etching in the wafer, which may cause the thinner thermal oxide layer on the gate polysilicon surface to be etched through and damage the gate oxide layer on the trench sidewalls, such as Figure 1 and Figure 2 As shown. The gate polysilicon is prone to accumulate more ions from the ion implantation process during the ESD polysilicon dry etching process, forming a charge accumulation, thereby triggering the antenna effect (the antenna effect in the semiconductor process refers to the fact that the polysilicon in the semiconductor process collects charges like an overlong metal wire, such as Figure 2 As shown in the figure, the charge comes from various plasma-related processes. If the polysilicon gate accumulates too much charge, it will cause the gate oxide layer to break down, causing the MOS tube to fail), which will cause the polysilicon to form a discharge arc and the short channel to cause the source-drain current I DS Abnormal leakage. Summary of the invention
[0005] The technical problem to be solved by the present invention is to provide a process method for preventing arcing from occurring at the gate of a power device with an ESD structure.
[0006] In order to solve the above problems, the present invention provides a process for preventing arcing at the gate of a power device with an ESD structure, comprising: The process method for preventing arcing at the gate of a power device with an ESD structure is to perform the following process steps after completing the etching process of the gate polysilicon: First, a thermal oxide layer with a certain thickness is formed; Then, a silicon nitride layer is deposited; Depositing an oxide layer as an ESD oxide layer; depositing an ESD polysilicon layer of the ESD structure; Perform ion implantation process for ESD structure; Performing photolithography and etching processes on the ESD polysilicon layer to pattern the ESD polysilicon layer; Perform ESD annealing process; Performing a wet etching process for the ESD oxide layer; The silicon nitride layer is removed by wet etching.
[0007] Furthermore, the thermal oxide layer is formed by a furnace tube process at 925°C to have a thickness of 150Å.
[0008] Furthermore, the silicon nitride layer is formed by LPCVD deposition using a furnace tube process; the thickness of the silicon nitride layer is 60Å.
[0009] Furthermore, the silicon nitride layer serves as an etching barrier layer when the ESD oxide layer above the silicon nitride layer is wet-etched, thereby preventing the antenna effect caused by local over-etching during the wet etching of the ESD oxide layer.
[0010] Furthermore, the silicon nitride layer is removed by etching with a phosphoric acid solution, which can improve the problem of poor uniformity of the retained ESD oxide layer or even partial etching through caused by uneven film quality of the ESD oxide layer.
[0011] Furthermore, in order to avoid stress problems caused by direct contact between the silicon nitride layer and the gate polysilicon surface in the gate trench of the power device, a 150Å thick thermal oxide layer is first thermally oxidized using a furnace tube process as a transitional intermediate layer.
[0012] Furthermore, the wet etching process of the ESD oxide layer adopts BOE solution for removal.
[0013] Furthermore, after completing the above process steps, body region implantation of the power device and subsequent processes are performed.
[0014] The process method for preventing arcing at the gate of a power device with an ESD structure described in the present invention forms an etching barrier layer after etching the polysilicon gate, and forms an etching barrier during the wet etching of the ESD oxide layer to protect the gate polysilicon thereunder, prevent local over-etching, and reduce the impact of the wet etching of the ESD oxide layer on the gate polysilicon. The retained thermal oxide layer can prevent the gate polysilicon from being damaged by discharge caused by charge accumulation introduced during the dry etching of the previous film layer and the subsequent ion implantation process, and the film quality of the ESD oxide layer can also be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figures 1-2 It is a schematic diagram illustrating the antenna effect of polysilicon.
[0016] Figure 3 It is a cross-sectional micrograph of the present invention retaining a thermal oxide layer above the gate polysilicon in the gate trench.
[0017] Figure 4 It is a flow chart of the process steps of the present invention (mainly the ESD structure process part). DETAILED DESCRIPTION
[0018] The following is a specific implementation of the present invention in conjunction with the accompanying drawings, and the technical solutions in the present invention are clearly and completely described, but the present invention is not limited to the following implementations. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0019] The present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, for clarity, the size and relative size of the layers and zones may be exaggerated, and the same reference numerals represent the same elements from beginning to end. In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0020] As described in the background technology section, in the existing power devices, when making the ESD structure, a 2000Å thick APCVD NSG ESD oxide layer needs to be removed by a wet etching process before the body region and source / drain injection of the conventional power device are performed, which causes etching damage to the gate polysilicon and the gate dielectric layer and causes defects. Therefore, the present invention provides a new process method, which first performs the following process steps after completing the etching process of the gate polysilicon: First, a thermal oxide layer is formed. The thermal oxide layer is formed at 925°C using a furnace tube process to form a 150Å thick thermal oxide layer. The reason for forming the thermal oxide layer is to improve the stress problem caused by the direct contact between the silicon nitride layer deposited later and the gate polysilicon surface in the gate trench of the power device.
[0021] Then, a silicon nitride layer is deposited. The silicon nitride layer is formed by LPCVD deposition using a furnace tube process. The preferred thickness of the silicon nitride layer in this embodiment is 60Å. The silicon nitride layer acts as an etching barrier when the ESD oxide layer above it is wet-etched to prevent the antenna effect caused by local over-etching during the wet etching process of the ESD oxide layer. If the silicon nitride layer is too thin, the blocking and protection ability of the thermal oxide film layer below it is limited during the wet etching process. If it is too thick, it will take more process time and there will be a greater stress risk. The role of introducing the silicon nitride layer is to act as an etching barrier in the subsequent wet etching process of the ESD oxide layer to prevent the antenna effect caused by local over-etching during the wet etching process of the ESD oxide layer. However, the introduction of the silicon nitride layer may cause new problems. When the silicon nitride layer is deposited by the direct furnace tube process, the silicon nitride layer will also be deposited and covered on the polysilicon surface in the groove at the same time, and the direct contact between the silicon nitride layer and the polysilicon layer will cause defects in the thin film layer due to stress problems. Therefore, in the ESD structure manufacturing process, the present invention first performs a thermal oxide layer formation process. The 150Å thick thermal oxide layer formed first serves as an intermediate layer to isolate the subsequent silicon nitride layer from the polysilicon layer to balance the stress, which can significantly improve the stress problem and enhance the process stability.
[0022] Deposit an oxide layer as an ESD oxide layer. The ESD oxide layer is an APCVDNSG layer with a thickness of about 2000Å.
[0023] re-depositing an ESD polysilicon layer of the ESD structure; Perform ion implantation of ESD structure. The type of ion implantation is selected according to N-type or P-type products, such as implantation B.
[0024] The ESD polysilicon layer is subjected to photolithography and etching processes to pattern the ESD polysilicon layer, and then an ESD structure annealing process is performed.
[0025] Wet etching process of ESD oxide layer is performed; BOE solution is used for etching the over-layer. BOE (Buffered Oxide Etch) is a buffered oxide etching solution. Buffered etching solution BOE is a mixture of HF acid and NH4F in different proportions. 6:1 BOE etching means a mixture of 49% HF aqueous solution: 40% NH4F aqueous solution = 1:6 (volume ratio). The etching speed is about 10nm per second. HF is the main etching solution, and NH4F is used as a buffer. NH4F is used to fix the concentration of [H+] to maintain a certain etching rate.
[0026] The silicon nitride layer is then removed by wet etching. The silicon nitride layer is removed by etching with phosphoric acid solution, which can improve the problem of poor uniformity of the retained ESD oxide layer or even partial etching through caused by uneven film quality of the ESD oxide layer.
[0027] After completing the above process steps, subsequent processes such as body region implantation and source region implantation of the power device are performed.
[0028] The process method provided by the present invention introduces a silicon nitride layer as an etching barrier layer for the WET ETCH of the ESD oxide layer, and removes it with a phosphoric acid solution after wet etching of the ESD oxide layer, which can effectively improve the problem of poor uniformity of the residual thermal oxide layer or even partial etching through caused by the uneven film quality of the ESD oxide layer (APCVD NSG).
[0029] In addition, in the process, in order to avoid stress problems caused by direct contact between the silicon nitride layer and the gate polysilicon surface in the groove, a thermal oxide layer with a thickness of about 150Å is first formed by thermal oxidation using a furnace tube as a transitional intermediate layer. Since the oxide layer formation speed on the gate polysilicon by the thermal oxidation process is more than twice that on crystalline silicon, that is, when the substrate silicon is partially thermally oxidized to form a thermal oxide layer with a thickness of 150Å, the thickness of the thermal oxide layer formed on the polysilicon surface exceeds 300Å. After the thermal oxide layer is wet-etched, the process of the present invention can retain a thermal oxide layer with a thickness of about 200Å on the surface of the gate polysilicon as a masking protection layer, which can prevent the gate polysilicon from being damaged by discharge after charge accumulation caused by subsequent dry etching of the previous layer and subsequent ion implantation processes.
[0030] After the ESD OX wet etching is completed, the process of the present invention uses phosphoric acid solution to etch the silicon nitride barrier layer cleanly, and then performs conventional body region implantation and source region implantation of the power device, which will not affect the stability and window size of other process steps.
[0031] The present invention improves the process of the ESD structure of the power device. Experiments show that the uniformity of the screen OX can be improved by about 80%, and the breakdown voltage BV and I DSS The convergence of leakage current can significantly improve the probability of low product yield problems.
[0032] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A process for preventing arcing at the gate of a power device with an ESD structure, characterized in that: After the etching process of the gate polysilicon is completed, a thermal oxide layer forming process is first performed.
2. A process for preventing arcing at the gate of a power device with an ESD structure as claimed in claim 1, characterized in that: The specific process steps include the following: First, a thermal oxide layer is formed; Then, a silicon nitride layer is deposited; Depositing an oxide layer as an ESD oxide layer; depositing an ESD polysilicon layer of the ESD structure; Perform ion implantation process for ESD structure; Performing photolithography and etching processes on the ESD polysilicon layer to pattern the ESD polysilicon layer; Perform ESD annealing process; Performing a wet etching process for the ESD oxide layer; The silicon nitride layer is removed by wet etching.
3. The process for preventing arcing at the gate of a power device with an ESD structure as claimed in claim 2, characterized in that: The thermal oxide layer is formed by a furnace tube process at 925°C to form a thermal oxide layer with a thickness of 150Å.
4. The process for preventing arcing at the gate of a power device with an ESD structure as claimed in claim 2, characterized in that: The silicon nitride layer is formed by LPCVD deposition using a furnace tube process; the thickness of the silicon nitride layer is 60Å.
5. The process for preventing arcing at the gate of a power device with an ESD structure as claimed in claim 2, characterized in that: The silicon nitride layer serves as an etching barrier when the ESD oxide layer above the silicon nitride layer is wet-etched, thereby preventing the antenna effect caused by local over-etching during the wet etching of the ESD oxide layer.
6. The process for preventing arcing at the gate of a power device with an ESD structure as claimed in claim 2, characterized in that: The silicon nitride layer is removed by using a phosphoric acid solution during etching, which can improve the problem of poor uniformity of the retained ESD oxide layer or even partial etching through caused by uneven film quality of the ESD oxide layer.
7. The process for preventing arcing at the gate of a power device with an ESD structure as claimed in claim 3, characterized in that: In order to avoid stress problems caused by direct contact between the silicon nitride layer and the gate polysilicon surface in the gate trench of the power device, a thermal oxide layer with a thickness of 150Å is thermally oxidized by a furnace tube process as a transitional intermediate layer to balance the stress.
8. The process for preventing arcing at the gate of a power device with an ESD structure as claimed in claim 2, characterized in that: The wet etching process of the ESD oxide layer adopts BOE solution to remove it.
9. The process for preventing arcing at the gate of a power device with an ESD structure as claimed in claim 2, characterized in that: After completing the above process steps, the body region of the power device is implanted and subsequent processes are performed.
10. The process for preventing arcing at the gate of a power device with an ESD structure as claimed in claim 2, characterized in that: Since the oxide layer formation speed on polysilicon during the thermal oxygen oxidation process is more than twice that on crystalline silicon, after the thermal oxide layer on the substrate surface is etched away, a certain thickness of thermal oxide layer can be retained on the surface of the gate polysilicon as a masking protection layer to prevent the gate polysilicon from being damaged by discharge after charge accumulation caused by subsequent dry etching of the previous layer and subsequent ion implantation process.