Substrate with side protection layer and manufacturing method thereof

Abstract

A substrate and a method of manufacturing the same according to an embodiment of the present invention relates to a substrate including a package substrate on which one or more electronic devices are arranged and a method of manufacturing the same, the substrate including: a glass core including a first surface and a second surface facing each other and a side surface connecting the first surface and the second surface; the upper layer is laminated above the first surface, the lower layer is laminated below the second surface, and the side surface protection layer surrounds the side surface of the glass core with a protection material; a defect is formed from a side surface of the glass core toward an inner side direction of the glass core, and the protective material fills the defect. According to the embodiment of the invention, the defects of the package substrate caused by defects such as package defects which are easy to appear (or appear) in the glass core in a manufacturing process or a using process can be reduced, and the durability is improved.

Description

Technical Field

[0001] The present implementation example relates to a substrate with a side protection layer that reduces defects and can be produced with an improved yield, and a method for manufacturing the same. The present implementation example relates to a substrate that has excellent usability as a packaging substrate, and a method for manufacturing the same. Background Art

[0002] When manufacturing electronic components, the realization of circuits on semiconductor wafers is called the front-end (FE) process, and the assembly of wafers into a state that can be used in actual products is called the back-end (BE) process. The back-end process includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products recently include semiconductor technology, semiconductor packaging technology, manufacturing process technology and software technology. Semiconductor technology is developing in various forms, such as line widths of nanometer units below microns, more than 10 million cells, high-speed operation and release of large amounts of heat, but there is still no technical support for relatively complete packaging of the above semiconductors. Therefore, the electrical performance of semiconductors depends not only on the performance of the semiconductor technology itself, but also often on the packaging technology and the corresponding electrical connections.

[0004] Ceramic or resin is used as the material of the packaging substrate. In the case of ceramic substrates such as silicon substrates, it is difficult to mount high-performance high-frequency semiconductor devices due to high resistance or high dielectric constant. In the case of resin substrates, although relatively high-performance high-frequency semiconductor devices can be mounted, there are limitations in reducing the spacing of wiring.

[0005] Recently, glass substrates can be applied to high-end packaging substrates. By forming through holes on the glass substrate and applying conductive materials to the through holes, the wiring length between the device and the motherboard is shortened, and the packaging substrate can have excellent electrical characteristics.

[0006] As related prior arts, there are Korean Patent No. 10-1406139, “Method for processing side surface of transparent substrate for display device and processing device using the same” and Korean Patent No. 10-1765198, “Method for manufacturing window glass using UV pattern”. Summary of the invention

[0007] Problem that the invention aims to solve

[0008] The purpose of the present implementation example is to provide a substrate with a side protection layer that reduces defects and can be produced with an improved yield, and a method for manufacturing the same.

[0009] Means used to solve problems

[0010] In order to achieve the above-mentioned purpose, a substrate according to one or more implementation examples is a substrate including a packaging substrate on which one or more electronic devices are arranged. The substrate includes: a glass core, including a first surface and a second surface opposite to each other and a side surface connecting the first surface and the second surface, an upper layer or a lower layer, the upper layer is stacked above the first surface, the lower layer is stacked below the second surface, and a side protective layer, which surrounds the side surface of the glass core with a protective material; a defect is formed from the side surface of the glass core toward the inner side of the glass core.

[0011] The protective material fills the space generated by the defect in the glass core.

[0012] The Young's modulus of the protective material at 24° C. may be 0.1 GPa to 17 GPa.

[0013] The package substrate may include the upper layer and the lower layer.

[0014] The side protection layer may surround the side surface of the upper layer, the side surface of the glass core, and the side surface of the lower layer.

[0015] The protective material may include an elastic polymer resin.

[0016] The curing temperature of the elastic polymer resin may be above 120°C.

[0017] The above-mentioned substrate can be: a strip substrate in which a plurality of the above-mentioned individual packaging substrates are arranged with virtual areas between them; a square substrate in which the above-mentioned virtual areas are arranged between the plurality of the above-mentioned strip substrates; a panel substrate in which the above-mentioned virtual areas are arranged between the plurality of the above-mentioned square substrates; or a single packaging substrate.

[0018] The side surface of the glass core may protrude more than the side surface of the upper layer or the side surface of the lower layer.

[0019] The protective material may include an elastic polymer containing a silane functional group.

[0020] In order to achieve the above-mentioned objective, a method for manufacturing a substrate having a side protection layer is provided according to a method for manufacturing a substrate according to one or more implementation examples.

[0021] The manufacturing method of the above-mentioned substrate includes: step A, preparing a glass core having a first surface and a second surface opposite to each other, and forming an upper layer above the above-mentioned first surface and a lower layer below the above-mentioned second surface to prepare the substrate, and step B, setting a side protective layer on the side of the above-mentioned substrate; defects are formed on the side of the glass core of the above-mentioned substrate, and the above-mentioned side protective layer fills the defects with protective material and surrounds the side of the above-mentioned glass core.

[0022] The method for manufacturing the substrate may include performing step C at least once during step A or between step A and step B.

[0023] The above step C is a step of confirming whether a defect occurs in the substrate in the above step A.

[0024] The method for manufacturing the substrate may further include performing step D after step A.

[0025] The substrate in the above step A is a substrate in which a plurality of the above-mentioned individual packaging substrates are arranged with virtual regions interposed therebetween, and the above-mentioned step D is a singulation step of separating the above-mentioned individual packaging substrates to obtain the above-mentioned packaging substrates.

[0026] Effects of the Invention

[0027] The substrate and manufacturing method of the present implementation example can reduce defects in the packaging substrate caused by defects such as packaging defects (Seware) that are easily present (or displayed) in the glass core during the manufacturing process or use, and improve durability.

[0028] The substrate and the manufacturing method thereof of the present implementation example can compensate for the generated defects even without separately performing a process for relieving the stress of the glass core, thereby improving the manufacturing yield of the substrate.

[0029] The substrate and the manufacturing method thereof of the present embodiment can minimize the occurrence of additional defects such as cracks and chipping at the edges and / or corners of the substrate that may occur when the substrate is placed on a tray or a boat for processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram illustrating the cross-sectional structure of a packaging substrate according to this implementation example.

[0031] Figure 2 A schematic diagram illustrating a cross-sectional structure of a packaging substrate according to another implementation example.

[0032] Figure 3 Part (a) and part (b) are schematic cross-sectional views of a portion of a packaging substrate according to the present implementation example.

[0033] Figure 4 A cross-sectional flow chart illustrating a process of generating a core distribution layer during the manufacturing process of a package substrate according to the present implementation example.

[0034] Figure 5 A cross-sectional flow chart illustrating a process of generating an insulating layer during the manufacturing process of a packaging substrate according to the present implementation example.

[0035] Figure 6It is a three-dimensional diagram of a substrate with a side protection layer according to this implementation example.

[0036] Fig. 7A For Figure 6 An exemplary conceptual diagram of a cross section of a substrate before forming a side protection layer as viewed from AA', Figure 7B For Figure 6 A schematic conceptual diagram of a cross section of a substrate after forming a side protection layer as viewed along line AA'.

[0037] Fig. 8A is from Figure 6 Another exemplary conceptual diagram of a cross section of a substrate before forming a side protection layer as viewed from AA', Figure 8B For Figure 6 Another schematic conceptual diagram of the cross section of the substrate after forming the side protection layer, as viewed along line AA'.

[0038] Fig.9A For Figure 6 Another exemplary conceptual diagram of a cross section of a substrate before forming a side protection layer as viewed from AA', Fig. 9B For Figure 6 Another schematic conceptual diagram of the cross section of the substrate after forming the side protection layer, as viewed along line AA'.

[0039] Description of Reference Numerals

[0040] 100: Semiconductor devices

[0041] 10: Motherboard

[0042] 30: Semiconductor Devices Department

[0043] 32: The first semiconductor device

[0044] 34: Second semiconductor device

[0045] 36: The third semiconductor device

[0046] 20: Package substrate

[0047] 21, 21a: Glass substrate, glass core

[0048] 22: Core layer

[0049] 223: Core insulation

[0050] 26: Upper layer

[0051] 28, 29a, 29b, 29c: Cavity

[0052] 213: First Surface

[0053] 214: Second Surface

[0054] 216: Side

[0055] 23: Core through hole

[0056] 24: Core distribution layer

[0057] 241: Core distribution pattern

[0058] 25: Upper distribution layer

[0059] 251: Upper distribution pattern

[0060] 253: Upper insulation layer

[0061] 27: Top connection layer

[0062] 271: Electrode connected above

[0063] 272: Connection pattern above

[0064] 28: Cavity

[0065] 29: Lower layer

[0066] 70: Side protection layer

[0067] C: Defect DETAILED DESCRIPTION

[0068] In order to help fully understand the method, device and / or system described in this specification, the following detailed description is provided. However, after understanding the content disclosed in this application, various changes, modifications and equivalents of the method, device and / or system described in this specification will become apparent. For example, the order of operations described in this specification is merely an example and is not limited to the operations recorded in this specification. Except for the steps that must be performed in a specific order, the order of operations can be changed according to the understanding of the content disclosed in this application. In addition, after understanding the disclosure of the application, the description of known features can be omitted to improve clarity and conciseness. However, the omission of its features and its description is not meant to be considered as common sense.

[0069] The features described in this specification may be embodied in different forms and should not be construed as being limited to the examples described in this specification. Rather, the embodiments described in this specification are provided to illustrate some of the many possible implementation methods of the methods, devices and / or systems described in this specification that become apparent after understanding the disclosure of this application.

[0070] In this specification, the terms "first", "second" and "third" may be used to describe various components, parts, regions, layers or sections, but these components, parts, regions, layers or sections should not be limited by these terms. Instead, these terms are only used to distinguish one component, part, region, layer or section from another component, part, region, layer or section. Therefore, without departing from the teachings of the embodiments, the first component, part, region, layer or section mentioned in the embodiments recorded in this specification may also be referred to as the second component, part, region, layer or section.

[0071] Throughout the specification, when a device such as a layer, a region or a substrate is described as being "on another device", "connected to another device" or "coupled to another device", it may be directly "on another device", "connected to another device" or "coupled to another device", or there may be one or more other devices interposed therebetween. Conversely, when a device is described as being "directly on another device", "directly connected to another device" or "directly coupled to another device", there may be no other devices intervening therebetween. Similarly, expressions such as "between" and "immediately between" and "in contact with" and "in direct contact with" may also be interpreted as described above.

[0072] The terms used in this specification are only used to describe specific examples and are not used to limit the present disclosure. Unless the context clearly indicates otherwise, the singular form used in this specification should be understood to also include the plural form. The term "and / or" used in this specification includes any one or a combination of more than two items listed in the relevant list. The terms "including", "constituting" and "having" used in this specification indicate the existence of the described features, numbers, operations, elements, constituent elements and / or their combinations, but do not exclude the existence or addition of one or more other features, numbers, operations, elements, constituent elements and / or their combinations. The use of the term "can" related to examples or implementation examples (for example, the content that can be included or implemented in examples or implementation examples) in this specification means that there is at least one example or implementation example that includes or implements such features, but all examples are not limited to this.

[0073] In the present application, “B is located on A” means that B is in direct contact with A or is placed on A with other layers or structures interposed therebetween, and thus should not be construed as being limited to B being in direct contact with A.

[0074] Unless otherwise defined, all terms used in this specification have the same meaning as commonly understood by one of the conventional techniques in the technical field to which the present invention belongs. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the prior art and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless clearly defined herein.

[0075] In one or more examples, the description regarding "A and / or B" means "A, B, or A and B."

[0076] In more than one instance, terms such as "first", "second", "A" or "B" are used to distinguish the same terms from each other.

[0077] In one or more examples, unless otherwise stated, a singular form is interpreted according to the context to include not only a singular form but also a plural form.

[0078] Figure 1 A schematic diagram illustrating a cross-sectional structure of a packaging substrate according to this implementation example is shown in FIG. Figure 2 FIG. 1 is a schematic diagram for illustrating a cross-sectional structure of a packaging substrate according to another implementation example. Figure 3 Part (a) and part (b) are schematic cross-sectional views of a portion of a packaging substrate according to the present implementation example.

[0079] In order to achieve the above-mentioned purpose, the semiconductor device 100 according to this implementation example includes: a semiconductor device unit 30, in which one or more semiconductor devices 32, 34, 36 are located; a packaging substrate 20, which is electrically connected to the semiconductor device; and a motherboard 10, which is electrically connected to the packaging substrate 20, transmits electrical signals between the semiconductor devices 32, 34, 36 and the outside and connects them to each other.

[0080] The package substrate 20 according to an implementation example includes: a core layer 22 ; an upper layer 26 located on one surface of the core layer 22 ; and a cavity portion 28 , in which the cavity device 40 may be located.

[0081] The semiconductor device section 30 is a device mounted on a semiconductor device, and is mounted on the package substrate 20 via connection electrodes, etc. Specifically, as the semiconductor device section 30, for example, a computing device such as a central processing unit (CPU), a graphics processing unit (GPU) (first device 32, second device 34), a storage device such as a memory chip (third device 36), etc. can be applied, but any semiconductor device mounted on a semiconductor device can be applied without limitation.

[0082] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0083] The package substrate 20 may selectively further include a lower layer (not shown) located below the core layer.

[0084] The core layer 22 may include: a glass substrate 21 including a first region 221 and a second region 222, wherein the first region 221 has a first thickness 211, and the second region 222 is adjacent to the first region 221 and has a second thickness 212 thinner than the first thickness (half cavity) or 0 mm (full cavity); a plurality of core through holes 23 penetrating the glass substrate 21 in the thickness direction; and a core distribution layer 24 located on the surface of the glass substrate 21 or the core through holes 23, and electrically connecting the first surface 213 of the glass substrate 21 and the second surface 214 facing the first surface 213 through the core through holes 23.

[0085] The second region 222 of the core layer 22 may function as a cavity structure.

[0086] In the same region, the glass substrate 21 has a first surface 213 and a second surface 214 facing each other. The two surfaces are substantially parallel to each other, so that the glass substrate 21 has a certain thickness as a whole.

[0087] The inner space 281 formed by the thickness difference between the first region 221 and the second region 222 serves to accommodate a part or all of the cavity device 40 .

[0088] The glass substrate 21 may include a core through hole 23 penetrating the first surface 213 and the second surface 214. The core through holes 23 may be formed in both the first region 221 and the second region 222, and may be formed at a desired pitch and pattern.

[0089] As a packaging substrate for semiconductor devices, a stacked form of silicon substrate and organic substrate has been used in the past. As for silicon substrates, due to the characteristics of semiconductors, there is a risk of parasitic devices when applied to high-speed circuits, and there is a disadvantage of relatively large power loss. In addition, as for organic substrates, a larger area is required to form a more complex distribution pattern, but this does not conform to the trend of manufacturing ultra-miniaturized electronic devices. In order to form a complex distribution pattern within a predetermined size, pattern refinement is actually required, but due to the characteristics of materials such as polymers suitable for organic substrates, pattern refinement actually has limitations.

[0090] In this embodiment, as a method for solving the above-mentioned problem, a glass substrate 21 is used as a support body of the core layer 22. In addition, by using the core through hole 23 formed through the glass substrate 21 together with the glass substrate 21, a package substrate 20 having a shorter current length, more miniaturization, faster response, and less loss characteristics is provided.

[0091] The glass substrate 21 is preferably a glass substrate suitable for semiconductors, for example, a borosilicate glass substrate, an alkali-free glass substrate, etc., but the present invention is not limited thereto.

[0092] The core through hole 23 penetrates the glass substrate 21. The core through hole 23 may be formed by removing a predetermined region of the glass substrate 21, and specifically, may be formed by etching a plate-shaped glass by a physical and / or chemical method.

[0093] Specifically, the core through hole 23 may be formed by forming a defect (stain) on the surface of the glass substrate by laser or the like and then performing chemical etching or laser etching, but the present invention is not limited thereto.

[0094] Based on the unit area (1 cm×1 cm) of the glass substrate 21, the number of the core through holes 23 may be 100 to 3000, or 100 to 2500, or 225 to 1024. When such spacing conditions are met, the formation of the conductive layer and the like and the performance of the packaging substrate may be improved.

[0095] The core distribution layer 24 includes a core distribution pattern 241 and a core insulation layer 223. The core distribution pattern 241 is a conductive layer that electrically connects the first surface and the second surface of the glass substrate through a through hole, and the core insulation layer 223 surrounds the core distribution pattern. The core layer 22 has a conductive layer formed therein through the core through hole, which serves as an electrical path passing through the glass substrate 21 and connects the upper and lower parts of the glass core at a relatively short distance, so that it can have faster electrical signal transmission and low loss characteristics. For example, the conductive layer can be applied with copper plating, but is not limited thereto.

[0096] The cavity 28 is generally in the shape of a circle, a triangle, a quadrilateral, a hexagon, an octagon, a cross, etc., and its shape is not limited.

[0097] The shape of the cavity device 40 may be cylindrical, rectangular or polygonal.

[0098] The cavity portion 28 may include a cavity allocation pattern as a conductive layer electrically connecting the cavity device 40 and the core allocation layer 24 , and an insulating layer surrounding the cavity allocation pattern.

[0099] On the other hand, the cavity portion according to another embodiment may be implemented in the form of penetrating the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion may be formed according to a process similar to that of forming the core through hole 23, and the area and shape of the cavity portion penetrating the glass substrate 21 may be different from those of the core through hole 23.

[0100] In this implementation example, after the cavity device 40 is arranged in the cavity portion, an insulating layer may be formed. In other words, the insulating layer may also be formed in the cavity portion through the above-mentioned process of forming the core insulating layer 223 .

[0101] The core allocation pattern 241 may be patterned to enable electrical connection to the above-mentioned cavity device 40 .

[0102] The cavity device 40 may include an active device such as a transistor or a power transmission device such as a multi-layer ceramic capacitor (MLCC), ie, a passive device.

[0103] When a device such as a transistor that converts an electrical signal between a motherboard and a semiconductor device into an appropriate level is used as the cavity device 40, the transistor is used in the path of the package substrate 20, so that a semiconductor device 100 with higher efficiency and speed can be provided.

[0104] In addition, power transmission devices such as multilayer ceramic capacitors (MLCC) play an important role in the performance of semiconductor devices. Usually more than 200 power transmission devices as passive devices are applied to semiconductor devices, and when transmitting power, the characteristics of the conductive layer around the device are also affected by its performance. In one implementation example, where a low-resistance conductive layer is required, such as the power transmission device described above, a non-circular core via can be applied instead of a circular core via.

[0105] On the other hand, passive devices such as capacitors can be inserted separately and applied to the above-mentioned cavity device 40, or after being formed to expose electrodes, a device group including multiple passive devices in the form of being embedded between insulator layers (electronic device insulating layers) can be inserted into the cavity device. In the latter case, the workability of manufacturing the package substrate can be made smoother, and it is more conducive to fully and reliably positioning the insulating layer in the space between complex devices.

[0106] The glass substrate 21 serves as an intermediate and mediating role for connecting the semiconductor device portion 30 and the motherboard 10 to the upper and lower parts, respectively. Since the core through hole 23 is used as a path for transmitting their electrical signals, smooth signal transmission is achieved. In order to distinguish from the core through hole in the second area 222 described later, the core through hole arranged in the first area 221 is referred to as the first area core through hole 231.

[0107] The upper layer 26 is located on the first surface 213 .

[0108] The upper layer 26 may include an upper distribution layer 25 and an upper connection layer 27 on the upper distribution layer 25 . The uppermost layer of the upper layer 26 may be protected by a cover layer 60 having an opening for directly contacting the connection electrode of the semiconductor device.

[0109] The upper distribution layer 25 may include: an upper insulating layer 253 located on the first surface; and an upper distribution pattern 251 as a conductive layer having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24, and the upper distribution pattern 251 is embedded in the upper insulating layer 253. The upper distribution layers 25 arranged one above the other may be connected to each other through blind holes 252.

[0110] The upper insulating layer 253 may be any insulating layer suitable for a semiconductor device or a package substrate, and may be, for example, an epoxy resin including a filler, but is not limited thereto.

[0111] The insulator layer may be formed by forming a coating and curing it, or may be formed by laminating an insulator film formed in an uncured or semi-cured state on the core layer 22 and curing it. In this case, if a reduced pressure lamination method or the like is adopted, the insulator is embedded in the space inside the core through hole 23, so that the process can be performed efficiently.

[0112] According to an implementation example, even if multiple insulator layers are stacked to apply, it may be difficult to distinguish the insulator layers in practice, and the multiple insulator layers are collectively referred to as the upper insulating layer. In addition, the core insulating layer 223 and the upper insulating layer 253 may be applied with the same insulating material, in which case, their boundaries may not be substantially distinguishable. Alternatively, according to another implementation example, the pressure and temperature for curing the multiple insulating layers are set differently, so that the boundaries of the insulating layers can be created.

[0113] The upper distribution pattern 251 refers to a conductive layer located in the upper insulating layer 253 in a preset shape, for example, it can be formed by a build-up layer method. Specifically, after forming an insulator layer and removing unnecessary parts of the insulator layer, a conductive layer is formed by copper plating or the like. Afterwards, the unnecessary parts of the conductive layer are selectively removed, and an insulator layer can be formed again on the conductive layer. After removing the unnecessary parts on the formed insulating layer, a conductive layer is formed on the insulating layer by electroplating or the like, and the above method is repeated. Thus, an upper distribution pattern 251 having a conductive layer formed in a vertical or horizontal direction in a desired pattern can be formed.

[0114] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor device portion 30, so that the electrical signal with the semiconductor device portion 30 is smoothly transmitted, and is formed to include a fine pattern in at least a portion thereof, so that the desired complex pattern can be fully accommodated. At this time, the fine pattern refers to a pattern with a width and a spacing less than 4 μm, or a pattern with a width and a spacing less than 3.5 μm, or a pattern with a width and a spacing less than 3 μm, or a pattern with a width and a spacing less than 2.5 μm, or a pattern with a width and a spacing of 1 μm to 2.3 μm (hereinafter, the description of the fine pattern is the same).

[0115] The upper connection layer 27 includes an upper connection pattern 272 , at least a portion of which is electrically connected to the upper distribution pattern 251 and is located on the upper insulating layer 253 ; and an upper connection electrode 271 , which electrically connects the semiconductor device portion 30 and the upper connection pattern 272 .

[0116] The upper connection pattern 272 may be located on one side of the upper insulating layer 253, or may be embedded in a manner that at least a portion thereof is exposed on the upper insulating layer. For example, in the case where the upper connection pattern is located on one side of the upper insulating layer, the upper insulating layer may be formed by electroplating or the like, and the upper connection pattern partially exposed on the upper insulating layer may be formed by forming a copper plating layer, and then a portion of the insulating layer or the conductive layer may be removed by surface polishing, surface etching or the like.

[0117] Similar to the upper distribution pattern 251 described above, at least a portion of the upper connection pattern 272 may include a fine pattern. The upper connection pattern 272 including the fine pattern can electrically connect more devices even in a narrow area, thereby making the electrical signal connection between devices or with the outside smoother and enabling a more integrated package.

[0118] The upper surface connection electrode 271 may be directly connected to the semiconductor device portion 30 through a terminal or the like, or may be connected through a device connection portion 51 such as a solder ball or the like.

[0119] The cavity portion 28 may include a cavity distribution layer 282 located above and / or below the second region 222 and electrically connected to the core distribution layer 241 and an inner space 281 where the cavity device 40 is located. The cavity distribution layer 282 may be formed through the second region core through hole 232.

[0120] Specifically, the second region 222 has a glass substrate 21 thinner than the first region 221, and the cavity device 40 may be located in the inner space 281 formed due to the thickness difference. In addition, the core through hole 23 and the core distribution layer 24 formed in the glass substrate 21 function as an electrical connection structure connecting the cavity device 40 and an external device.

[0121] In addition, as described above, a cavity portion in the form of penetrating the first region 221 instead of the second region 222 , ie, penetrating the first surface 213 and the second surface 214 of the glass substrate 1 may be generated, and the cavity device 40 may be arranged in the cavity portion.

[0122] The package substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 can be directly connected to the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, and the motherboard 10 and the package substrate 20 can also be electrically connected through a board connection portion 52 such as a solder ball. In addition, the core distribution pattern 241 in contact with the motherboard 10 can be connected to the motherboard 10 through a lower layer (not shown) located at the lower part of the core layer 22. The device connection portion 51 and the board connection portion 52 are collectively referred to as a connection portion 50.

[0123] According to an example, on the package substrate 20 located between the semiconductor device portion 30 and the motherboard 10 , substantially no other substrates may be used except the glass substrate 21 .

[0124] In the past, the interposer and the organic substrate were stacked together and applied to the connection part between the device and the motherboard. It is understood that the adoption of such a multilayer structure is based on at least two reasons. One is that there are scale problems in directly bonding the fine pattern of the device to the motherboard, and the other is that during the bonding process or the driving process of the semiconductor device, the wiring may be damaged due to the difference in thermal expansion coefficient. In this implementation example, the above problems are solved by applying a glass substrate having a thermal expansion coefficient similar to that of the semiconductor device, and forming a micro pattern having a scale sufficient for mounting the device on the first surface and the upper layer of the glass substrate.

[0125] A method for manufacturing a package substrate according to an implementation example of the present invention will be described below.

[0126] Figure 4 and Figure 5 A cross-sectional flow chart illustrating a manufacturing process of a packaging substrate according to this implementation example.

[0127] First, if Figure 4As shown in part (a), a glass substrate 21a having a flat first surface and a flat second surface is prepared, and a defect 21b (groove) is formed at a predetermined position on the glass surface to form a core through hole. The above-mentioned glass substrate can be a glass substrate suitable for a substrate of an electronic device, for example, an alkali-free glass substrate, etc. can be used, but it is not limited to this. As a commercial product, products manufactured by manufacturers such as Corning, Schott, and AGC can be used. The above-mentioned defect (groove) can be formed by mechanical etching, laser irradiation, etc.

[0128] like Figure 4 As shown in part (b) of FIG. 1 , an etching step of forming a core through hole 23 by a physical or chemical etching process is performed on a glass substrate 21a formed with a defect 21b (groove). During the etching process, a through hole is formed in the defective portion of the glass substrate, and the surface of the glass substrate 21a can be etched at the same time. In order to prevent such etching of the glass surface, a mask film or the like can also be applied. However, considering the trouble of applying and removing the mask film, etc., the glass substrate itself with the defect can be etched. In this case, the thickness of the glass substrate with the core through hole can be slightly thinner than the thickness of the original glass substrate.

[0129] Then, if Figure 4 As shown in parts (c) and (d) of FIG. 2 , the core layer preparation step may be performed by forming a conductive layer 21d on the glass substrate. Representatively, the conductive layer may be a metal layer including copper metal, but is not limited thereto.

[0130] The surface of the glass (including the surface of the glass substrate and the surface of the core through hole) and the surface of the copper metal have different properties, so the adhesion may be reduced. In this implementation example, the adhesion between the glass surface and the metal is improved by two methods, a dry method and a wet method.

[0131] The dry method is a method for applying sputtering, that is, a method for forming a seed layer 21c on the glass surface and the inner diameter of the core through hole by metal sputtering. When forming the above-mentioned seed layer, a dissimilar metal such as titanium, chromium, nickel, etc. can be sputtered together with copper, etc. In this case, the adhesion between glass and metal can be improved by the surface morphology of the glass and the anchoring effect of the interaction of metal particles.

[0132] Wet method is the method for carrying out primer treatment, is the method for forming primer layer 21c by pre-treatment with the compound substance with the functional group such as amine etc. According to the required adhesion degree, after pre-treatment with silane coupling agent, primer treatment can be carried out with the compound or particle with amine functional group.As mentioned above, the support substrate of this implementation example needs to have the high performance of the degree that is enough to form fine pattern, even after primer treatment, also need to keep.Therefore, when this primer comprises nanoparticle, preferably suitable average diameter is the nanoparticle below 150nm, for example, preferably suitable particle with amine group is as nanoparticle.For example, above-mentioned primer layer can be formed by being suitable for the adhesion improver made by the CZ series etc. of MEC company.

[0133] In the seed layer / primer layer 21c, the conductive layer can selectively form a metal layer with or without removing the portion where the conductive layer is not required to be formed. In addition, the seed layer / primer layer 21c selectively processes the portion where the conductive layer is required to be formed or the portion where the conductive layer is not required to be formed into an activated state or an inactivated state for metal electroplating to carry out subsequent processes. For example, the activation or inactivation treatment can use a light irradiation treatment or chemical treatment with a laser having a predetermined wavelength. When forming the metal layer, a copper electroplating method suitable for manufacturing semiconductor devices can be used, but it is not limited thereto.

[0134] like Figure 4 As shown in part (e), when a portion of the core distribution layer is not needed, it can be removed, and after partially removing or deactivating the seed layer, metal electroplating is performed to form a conductive layer in a predetermined pattern, thereby forming an etching layer 21e of the core distribution layer.

[0135] Figure 5 The preparation steps for forming an insulating layer and an upper distribution pattern according to an implementation example are described.

[0136] like Figure 5 As shown in part (a), after forming the core distribution layer as the above-mentioned conductive layer, the core through hole can undergo an insulating layer forming step of filling the empty space with an insulating layer. At this time, the insulating layer used can be prepared in the form of a film. For example, a method of reducing pressure laminating an insulating layer in the form of a film can be applied. When reducing pressure lamination is performed in this way, the insulating layer is fully embedded in the empty space inside the above-mentioned core through hole, thereby forming a core insulating layer without void formation.

[0137] Figure 5 Parts (b) to (e) of FIG. 1 illustrate the upper layer preparation steps.

[0138] The upper layer preparation step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition for forming the insulating layer 23a or stacking insulating films, preferably by a simple method of stacking insulating films. The insulating films can be stacked by laminating and curing the insulating films. At this time, if a reduced pressure lamination method is adopted, the insulating resin can be fully embedded in the core through hole, where no conductive layer is formed, etc. Since at least a portion of the upper insulating layer is also in direct contact with the glass substrate, a layer with sufficient adhesion is suitable. Specifically, the glass substrate and the upper insulating layer preferably have a property that the adhesion test value according to ASTMD3359 satisfies 4B or above.

[0139] The upper distribution pattern can be formed by repeatedly forming the above-mentioned insulating layer 23a, forming the conductive layer 23c in a predetermined pattern, and etching the unnecessary part to form the etching layer 23d of the conductive layer. In the case where the conductive layer is formed adjacent to each other through the insulating layer, it can be formed by performing an electroplating process after forming the blind hole 23b in the insulating layer. The formation of the blind hole can be applied to a dry etching method such as laser etching and plasma etching, a wet etching method using a mask layer and an etching solution, etc.

[0140] Thereafter, although not shown in the drawings, an upper connection layer and a cover layer may be formed.

[0141] The upper connection pattern and the upper connection electrode can also be formed by a process similar to the process of forming the upper distribution layer. Specifically, it can be formed by forming an etching layer of the insulating layer on the insulating layer 23e, and forming a conductive layer again on this basis, and then forming an etching layer of the conductive layer. However, it can also be formed by selectively forming only the conductive layer without etching. The covering layer is formed with an opening (not shown) at a position corresponding to the upper connection electrode, so that the upper connection electrode is exposed, and can be formed to be directly connected to the device connection part or the terminal of the device.

[0142] When the upper layer is generated, the lower layer can be processed by forming the lower connection layer and the cover layer. The lower distribution layer and / or the lower connection layer can be formed in a similar manner to the above-mentioned upper connection layer and cover layer formation steps, and a cover layer (not shown) can be optionally formed.

[0143] This embodiment uses a glass core as a support for the core layer. Unlike existing prepregs that use polymers to impregnate glass fibers, the glass core uses flat glass. Although the glass core has the above-mentioned advantages, it also has the disadvantage that it may be damaged, cracked, or have edge collapse.

[0144] The causes of defects in the glass core are believed to be caused by a variety of factors. During the manufacturing process of the glass core, the residual stress or tiny defects in the glass core itself may cause the glass core to break when it is impacted, which may appear as a defect. In addition, during the manufacturing process of the packaging substrate, stress may also be generated due to the influence of dissimilar materials formed by contact with the two sides of the packaging substrate and / or due to repeated temperature changes. These influences may cause defects. Defects are caused by impacts applied during movement or processing. Among the defects, defects that occur at the edges or corners of the glass core in a direction roughly perpendicular to the thickness direction are called "packaging defects (Seware)". During the manufacturing process, Seware becomes larger and deeper due to its progressive nature.

[0145] This implementation example proposes to form a protective layer to prevent tiny defects or small seware from developing into larger defects. In addition, in the manufacturing process of the packaging substrate, in order to suppress the occurrence of seware, an additional process of relieving substrate stress can be performed, but this may reduce the manufacturing efficiency of the packaging substrate. In this implementation example, an invention is proposed that induces the occurrence of seware, cracks, edge collapse and other defects without additional stress relief processes and is suitable for filling these parts with a side protective layer.

[0146] Figure 6 It is a three-dimensional diagram of a substrate with a side protection layer according to this implementation example. Fig. 7A , Fig. 8A and Fig.9A Respectively from Figure 6 An exemplary conceptual diagram of a cross section of a substrate before forming a side protection layer as viewed from AA', Figure 7B , Figure 8B and Fig. 9B Respectively from Figure 6 A schematic conceptual diagram of a cross section of a substrate after forming a side protection layer, as viewed from AA'. Figures 6 to 9B This implementation example is described in detail.

[0147] As one or more implementation examples, a substrate including a packaging substrate 20 on which one or more electronic devices are arranged is proposed. The substrate includes: a glass core 21, including a first surface 213 and a second surface 214 opposite to each other and a side surface 216 connecting the first surface and the second surface; an upper layer 26 stacked above the first surface or a lower layer 29 stacked below the second surface; and a side protection layer 70, which surrounds the side of the glass core with a protective material.

[0148] The same description as above applies to the description of the glass core, core, upper layer, lower layer, etc. In addition, the formation of the cavity, etc. can also be applied to this implementation example.

[0149] A defect C is formed from the side surface 216 of the glass core toward the inner side of the glass core, and the protective material fills a space formed by the defect in the glass core.

[0150] It is preferred that no defects are formed in the glass core, but the possibility of defects being formed during the manufacturing process of the packaging substrate is relatively high. The above-mentioned side protection layer 70 can be formed in the step of discovering defects. Exemplarily, the above-mentioned side protection layer 70 can be selectively formed once or multiple times on the substrate i) before forming the upper layer 26 and / or the lower layer 29 on the glass core, ii) during the process of forming the upper layer and / or the lower layer on the glass core, iii) after forming the upper layer 26 and / or the lower layer 29 on the glass core, and iv) after being separated (singulated) into one or more separate packaging substrates.

[0151] The side protection layer 70 surrounds the side surface 216 of the glass core and fills the defect C. The side protection layer includes a protection material.

[0152] The protective material may include an elastic material.

[0153] The elastic material may include an elastic polymer containing a silane functional group.

[0154] Specifically, the elastic material may be a silicone elastomer.

[0155] The Young's modulus of the elastic material at 24° C. may be 0.1 GPa or more, 1 GPa or more, or 2 GPa or more. The Young's modulus may be 17 GPa or less, 15 GPa or less, 12 GPa or less, or 10 GPa or less.

[0156] The above-mentioned protective material may have a viscosity of 1000 cP or more, 2000 cP or more, or 3000 cP or more at 25° C. in a solution state before solidification. The above-mentioned viscosity may be 50000 cP or less, 30000 cP or less, 20000 cP or less, or 10000 cP or less. If a protective material within the above-mentioned viscosity range is used, when the protective material is injected by increasing the temperature so that the protective material can penetrate smoothly into a tiny defect and then the temperature is lowered, it can help to stably maintain the injected state.

[0157] The elastic material can be cured at a curing temperature of 120°C or above. The curing can be achieved by initiating a chemical reaction between the main agent and the curing agent. During the curing process, the degree of chemical bonding in the elastic material can be increased, and the mechanical strength can be imparted to the protective material and adjusted. The curing temperature can be above 120°C, above 125°C, or above 130°C. The curing temperature can be below 180°C, below 175°C, or below 160°C.

[0158] The curing temperature can be maintained during the curing time. The curing time can be more than 3 minutes, more than 5 minutes or more than 7 minutes. The curing time can be less than 40 minutes, less than 35 minutes or less than 30 minutes. If curing is performed within the curing time, a protective material with stable mechanical properties can be obtained.

[0159] The protective material may include more than 70% by weight of the silicone elastomer. The protective material may include more than 80% by weight of the silicone elastomer. The protective material may include more than 90% by weight of the silicone elastomer. The protective material may include less than 100% by weight of the silicone elastomer.

[0160] The side protection layer 70 may be a silicone elastomer layer.

[0161] Silicone elastomers can be made by cross-linking a main agent of a silicone resin and a curing agent.

[0162] The main agent may contain an alkenyl group at one or more ends. The main agent may have a structure of the following Chemical Formula 1.

[0163] [Chemical formula 1]

[0164]

[0165] In the above Chemical Formula 1, n is an integer of 20 to 60.

[0166] The curing agent may have a structure of Chemical Formula 2 below.

[0167] [Chemical formula 2]

[0168]

[0169] In the above Chemical Formula 2, x and y are each independently an integer of 2 to 10.

[0170] During the curing process, the alkenyl groups contained in the main agent can form cross-linked bonds with the curing agent, thereby increasing the cross-linking density in the above-mentioned blended resin and imparting controlled rigidity to the protective material.

[0171] When forming the protective material, 3 parts by weight or more, 5 parts by weight or more, or 8 parts by weight or more of the curing agent may be used relative to 100 parts by weight of the main agent. When forming the protective material, 20 parts by weight or less, or 15 parts by weight or less of the curing agent may be used relative to 100 parts by weight of the main agent. When forming the protective material within this range, it is easier to fill the space generated by the defect, and it is helpful to give the side protective layer appropriate elasticity and strength, etc.

[0172] As a method for forming the side protective layer, a method of applying a pre-cured composition of the protective material to the side of the substrate having defects such as cracks or chipping, and then curing and fixing the composition can be applied. The coating can be performed by dip coating, slit coating, dry film coating, dispensing, etc., but is not limited thereto.

[0173] The tensile strength of the side protective layer 70 may be 1 MPa to 20 MPa. The tensile strength may be 2 MPa or more. The tensile strength may be 4 MPa or more. The tensile strength may be 15 MPa or less. The tensile strength may be 10 MPa or less. In this case, even if the glass core 21 has a structure that is susceptible to impact, the substrate may have stable durability. The tensile strength may be measured using a universal testing machine (UTM).

[0174] The thermal expansion coefficient of the side protective layer 70 is 100ppm / ℃ to 800ppm / ℃. The thermal expansion coefficient may be above 150ppm / ℃. The thermal expansion coefficient may be above 200ppm / ℃. The thermal expansion coefficient may be above 250ppm / ℃. The thermal expansion coefficient may be above 300ppm / ℃. The thermal expansion coefficient may be below 700ppm / ℃. The thermal expansion coefficient may be below 600ppm / ℃. The thermal expansion coefficient may be below 500ppm / ℃. The thermal expansion coefficient may be below 400ppm / ℃. In this case, the substrate may have stable durability and electrical reliability even after repeated heat treatment. The thermal expansion coefficient may be measured by thermomechanical analysis using a thermomechanical analyzer (TMA). For example, the thermal expansion coefficient may be measured using the Q400 model TMA of TA Instruments (TAINSTRUMENT).

[0175] The dielectric constant of the side protection layer 70 at a frequency of 100 Hz may be 4 or less. The dielectric constant may be 3.5 or less. The dielectric constant may be 3 or less. The dielectric constant may be 2.8 or less. The dielectric constant may be 1.5 or more.

[0176] The dielectric constant of the side protection layer 70 at a frequency of 100 kHz may be 4 or less. The dielectric constant may be 3.5 or less. The dielectric constant may be 3 or less. The dielectric constant may be 2.8 or less. The dielectric constant may be 1.5 or more.

[0177] In this case, the conductive layer pattern formed on the side protection layer 70 can effectively transmit a signal. The dielectric constant of the side protection layer 70 can be measured using a dielectric constant meter at room temperature.

[0178] If defects such as cracks or chipping occur in the glass core, the side protective layer can be formed. Therefore, when defects such as cracks and chipping occur in the glass core itself, the side protective layer can be formed on the glass core. In this case, the side protective layer can be formed only on the side of the glass core, not on the side of the upper layer or the side of the lower layer.

[0179] If defects such as cracks and chipping occur in the glass core during the formation of the upper layer and / or the lower layer, the side protection layer may be formed. In this case, a side protection layer may be formed to surround a portion or all of the sides of the upper layer and / or the lower layer.

[0180] The side protection layer may surround at least a portion of the upper layer or the lower layer through the protection material.

[0181] When observing the cross section of the substrate where the defect occurs, it may have a laminated structure of glass-protective material-glass. Thus, the defect is prevented from expanding, and even if glass damage such as defects occurs, the production of the package substrate product can be ensured, thereby improving the efficiency of the manufacturing process.

[0182] In one or more implementation examples, the substrate may be a stripe-shaped substrate in which a plurality of separate packaging substrates are arranged with virtual regions interposed therebetween.

[0183] In one or more implementation examples, the substrate may be a quad substrate in which a plurality of strip substrates are arranged with virtual regions interposed therebetween.

[0184] In one or more implementation examples, the substrate may be a panel substrate in which a plurality of square substrates are arranged with virtual areas interposed therebetween.

[0185] For a strip substrate, a square substrate or a panel substrate, defects generated in a virtual area at the edge of the substrate can be filled with a protective material, and a side protective layer can be formed to prevent the substrate from generating more defects or being broken due to external impact. When the strip substrate is divided into separate package substrates, the side protective layer can be removed.

[0186] In one or more implementation examples, the substrate may be a separate packaging substrate. In this case, during the singulation process of the separate packaging substrate, defects may occur on the side of the separate packaging substrate, which may cause additional seware during subsequent movement, device installation, etc. Therefore, a side protection layer may also be formed on the separate packaging substrate after the cutting process, thereby improving the preservation properties of the separate packaging substrate, such as impact resistance.

[0187] In one or more implementations, the entire side surface of the substrate (including the side surface of the upper layer and / or the lower layer and the side surface of the glass core) may be substantially perpendicular to the first surface and the second surface (see Fig. 7A and Figure 7B ). If it is substantially vertical, defects such as fractures and cracks may occur at corners, etc. Figure 7B As shown, the substrate is protected by forming a side protection layer.

[0188] In one or more implementations, the side surfaces of the upper layer and / or the lower layer of the substrate may be arranged inwardly relative to the side surfaces of the glass core (see Fig. 8A and Figure 8B ). In this case, the substrate can be protected by forming a side protection layer, such as Figure 8B As shown, the side protection layer may be formed in a manner of surrounding both the protrusion between the upper layer and the first surface and the protrusion between the lower layer and the second surface to protect the substrate.

[0189] In one or more implementation examples, the central portion of the side surface of the glass substrate may protrude. Specifically, the central portion of the side surface of the glass core protrudes and its upper and lower edges are chamfered, and the side surface of the upper layer and / or the lower layer may be arranged inwardly relative to the side surface of the glass core (see Fig.9A and Fig. 9B ). In this case, the side protection layer may be tapered along the first surface direction and the second surface direction with the side of the upper layer and / or the lower layer and the chamfered glass substrate as the center. Fig. 9B As shown, the side protection layer can protect the substrate by being formed to surround the tapered side surface of the upper layer, the side surface protruding from the central portion of the glass substrate, and the tapered side surface of the lower layer.

[0190] According to another implementation example, a method for manufacturing a substrate is a method for manufacturing a substrate with a side protective layer, which includes: step A, preparing a glass core having a first surface and a second surface opposite to each other, and forming an upper layer above the above-mentioned first surface and a lower layer below the above-mentioned second surface to prepare a substrate; and step B, setting a side protective layer on the side of the above-mentioned substrate.

[0191] Defects are formed on the side of the glass core of the above-mentioned substrate, and the above-mentioned side protective layer fills the above-mentioned defects with protective material and surrounds the side of the above-mentioned glass core. The detailed description of the specific structure, shape and physical properties is the same as the above description, so the detailed description will be omitted.

[0192] Since the method of preparing the above-mentioned upper layer and / or lower layer overlaps with the method explained above, a detailed description will be omitted.

[0193] As a method for forming the side protection layer, a method of preparing a protective material (composition) in the form of a liquid or dry film before curing, coating it and curing it can be applied. The thickness of the side protection layer is sufficient to surround the side of the glass core, and the side protection layer surrounding the side of the glass core while filling the defect space can substantially inhibit the damage extension of the glass core and protect the glass core from additional impact.

[0194] In the method for manufacturing the substrate, step C may be performed at least once during step A or between step A and step B.

[0195] The above step C is a step of confirming whether a defect occurs in the substrate in the above step A.

[0196] Step C may be repeatedly performed during the formation of the prepared glass core, the upper layer and / or the lower layer to confirm the generation of defects. Exemplarily, this step may be repeated after forming one or more insulating layers including a polymer.

[0197] In the above-mentioned method for manufacturing the substrate, step D may be further performed after the above-mentioned step A.

[0198] The substrate in the above step A is a substrate in which a plurality of packaging substrates are arranged with virtual regions interposed therebetween, and the above step D is a singulation step of separating the individual packaging substrates to obtain packaging substrates.

[0199] As the singulation method, a known method can be applied.

[0200] Exemplarily, as a singulation method, upper layers and / or lower layers may be removed along a cutting line, a groove may be formed on a portion of a glass core, and then an impact is applied to the substrate to obtain individual package substrates with dummy areas removed along the cutting line.

[0201] The cutting surface from which the virtual area is removed may be substantially in the shape of a straight line and may have Fig. 7A or Fig. 8A In addition, through subsequent grinding operations, etc., Figure 8B The edge of the glass core of the cross section may have a chamfered or ground shape, and may have Fig.9ABy confirming whether there are defects in the cross section, a side protection layer can also be formed on the side of the individual packaging substrate after the singulation.

[0202] The substrate of this implementation example can reduce defects in the encapsulation substrate caused by defects such as encapsulation defects (Seware) that are easy to appear (or present) in the glass core, and improve durability. Moreover, even if the process of relieving the stress of the glass core is not performed separately, the defects produced can be compensated, thereby improving the manufacturing yield of the substrate. In addition, when the substrate is placed on a tray or boat for processing, the generation of additional defects such as cracks and collapse of the edges and / or corners of the substrate that may occur can be minimized.

[0203] The preferred embodiments of the present invention are described in detail above, but the scope of the present invention is not limited thereto. Various modifications and improvements made by ordinary technicians in the technical field to which the present invention belongs using the basic concepts of the present invention defined in the scope of protection of the attached invention claims also fall within the scope of the present invention.

Claims

1. A substrate, comprising a packaging substrate on which one or more electronic devices are arranged, characterized in that: The above substrate comprises: The glass core comprises a first surface and a second surface opposite to each other and a side surface connecting the first surface and the second surface. an upper layer or a lower layer, the upper layer is stacked above the first surface, the lower layer is stacked below the second surface, and A side protection layer, which surrounds the side of the glass core with a protective material; forming defects from the side of the glass core toward the inner side of the glass core, The protective material fills the space generated by the defect in the glass core.

2. The substrate according to claim 1, characterized in that The Young's modulus of the protective material at 24° C. is 0.1 GPa to 17 GPa.

3. The substrate according to claim 1, characterized in that The packaging substrate includes the upper layer and the lower layer. The side protection layer surrounds the side surface of the upper layer, the side surface of the glass core, and the side surface of the lower layer.

4. The substrate according to claim 1, characterized in that The protective material includes an elastic polymer resin, and the curing temperature of the elastic polymer resin is above 120°C.

5. The substrate according to claim 1, characterized in that The substrate is: a strip substrate in which a plurality of individual packaging substrates are arranged with virtual areas between them; a square substrate in which the virtual areas are arranged between a plurality of strip substrates; a panel substrate in which the virtual areas are arranged between a plurality of square substrates; or a single packaging substrate.

6. The substrate according to claim 1, characterized in that The side surface of the glass core protrudes more than the side surface of the upper layer or the side surface of the lower layer.

7. The substrate according to claim 1, characterized in that The protective material comprises an elastic polymer containing a silane functional group.

8. A method for manufacturing a substrate, wherein the substrate has a side protection layer, characterized in that: The method for manufacturing the substrate comprises: Step A, preparing a glass core having a first surface and a second surface opposite to each other, and forming an upper layer above the first surface and a lower layer below the second surface to prepare a substrate, and Step B, providing a side protection layer on the side of the substrate; The glass core of the substrate has defects formed on the side surface; The side protection layer fills the defects with a protection material and surrounds the side surfaces of the glass core.

9. The method for manufacturing a substrate according to claim 8, characterized in that: In the method for manufacturing the substrate, step C is performed at least once during step A or between step A and step B. Among them, the above-mentioned step C is a step of confirming whether there are defects in the substrate of the above-mentioned step A.

10. The method for manufacturing a substrate according to claim 8, characterized in that: The method for manufacturing the substrate further includes performing step D after step A. The substrate in the above step A is a substrate in which a plurality of separate packaging substrates are arranged with virtual regions interposed therebetween, and the above step D is a singulation step of separating each of the above separate packaging substrates to obtain the above packaging substrates.

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