Process integration method for improving performance of low-voltage device in high-voltage integration process

What is AI technical title?
AI technical title is built by Patsnap AI team. It summarizes the technical point description of the patent document.
By integrating high-voltage, medium-voltage and a variety of low-voltage devices on the semiconductor substrate, and removing and growing the oxide layer in the low-voltage zone, the problem of excessive consumption of low-voltage devices in the high-voltage integrated process is solved, and the reliability and performance of the device are improved.

CN119943820APending Publication Date: 2025-05-06SHANGHAI HUALI INTEGRATED CIRCUIT CORP

View PDF 0 Cites 0 Cited by

Patent Information

Application Number: CN202510008245.7
Authority / Receiving Office: CN · China
Patent Type: Applications(China)
Current Assignee / Owner
Filing Date: 2025-01-02
Publication Date: 2025-05-06

AI Technical Summary

Technical Problem

In the existing high-voltage integrated processes, low-voltage devices in multiple oxidation and oxide removal processes lead to excessive consumption of field oxide layers and rough surfaces of the active region, affecting device performance.

Method used

High voltage devices, medium voltage devices and various types of low voltage devices are integrated on the semiconductor substrate at the same time. By forming a medium voltage gate oxide layer in the low voltage zone, and removing the medium voltage gate oxide layer and growing the low voltage gate oxide layer in sequence according to the operating voltage of the low voltage device, the oxide layer consumption in the low voltage zone is reduced.

Benefits of technology

It effectively reduces the field oxide layer consumption in the low-voltage zone and the roughness of the active zone surface, reduces the leakage of the device and improves reliability, thereby improving the performance of the low-voltage device.

✦ Generated by Eureka AI based on patent content.

Smart Images

Figure CN119943820A_ABST

Patent Text Reader

Abstract

The invention discloses a process integration method for improving the performance of a low-voltage device in a high-voltage integration process. A gate oxide layer of the low-voltage device is formed by adopting the following steps: step 1, forming a medium-voltage gate oxide layer; 2, low-voltage gate oxide layers of various low-voltage devices are sequentially formed according to the magnitude of the working voltage; the method for forming the low-voltage gate oxide layer of the selected low-voltage device comprises the following sub-steps: step 21, removing the medium-voltage gate oxide layer in the selected low-voltage region; and the medium-voltage gate oxide layer in the unselected low-voltage region or the formed low-voltage gate oxide layer is reserved. Step 22, forming a low-voltage gate oxide layer corresponding to the selected low-voltage device; in the first oxidation process, the thickness of the medium-voltage gate oxide layer in the low-voltage region corresponding to each low-voltage device of which the working voltage is smaller than that of the selected low-voltage device is increased. And repeating the steps 21 and 22 until the low-voltage gate oxide layers of various low-voltage devices are formed. According to the invention, the consumption of the field oxide layer of each low-voltage region and the roughness of the surface of the active region of each low-voltage region can be reduced.

Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit manufacturing method, and in particular to a process integration method for improving the performance of low voltage (LV) devices in a high voltage (HV) integration process. Background Art

[0002] As the third generation of display technology, organic light emitting diode (OLED) is a current injection composite light emitting type. Its main advantages are high brightness, high contrast, wide viewing angle, fast response speed, low operating voltage, strong adaptability, high energy conversion efficiency, simple manufacturing process, etc. Due to the huge technical advantages and application prospects of OLED, it has received widespread attention from academia and industry.

[0003] OLED is a current-driven type. The current density of OLED depends on the driving voltage at both ends. The higher the voltage, the greater the current density. With the advancement of logic device technology nodes, OLED technology combined with advanced technology nodes is being continuously developed. The most advanced mass production technology node is the technology that combines 28 nanometer high dielectric material metal gate (MG), namely 28HV MG, which can take advantage of the high performance and low voltage of advanced nodes. In 28HV MG technology, it is necessary to integrate low-voltage SRAM and high-voltage driver devices, and high voltage requires thick silicon oxide gate, which affects the subsequent process of Metal Gate. In order to be compatible with Metal Gate technology, the active area will be etched back (Recess) in the high-voltage (HV) area and the medium-voltage (MV) area, and then thick silicon oxide will be grown to make it as consistent as possible with the height of the active area, which is convenient for subsequent process development.

[0004] There are many types of devices in the 28nm process. For example, low-voltage devices also include 1.2V devices and low-voltage devices below 1.2V. In the existing process flow, the medium-voltage silicon oxide is removed once in the low-voltage area, and the silicon oxide grown by the 1.2V device is also removed once in the low-voltage area. In this way, when the thick silicon oxide in the low-voltage area is removed, the shallow trench isolation (STI) in the low-voltage (LV) area will be consumed more, which will cause the active area of the active device MOS and the passive diode to be lower than the STI, resulting in an increase in leakage. In order to maintain the original height, it is necessary to start adjusting from the liner silicon oxide and silicon nitride at the beginning of the process, and to readjust from the beginning, the entire cycle is relatively long. At the same time, multiple removals of silicon oxide will also cause the surface of the low-voltage device area to become very rough, leading to reliability issues with silicon oxide.

[0005] like Figure 1 As shown in FIG. 1 , it is a flow chart of forming a low voltage gate oxide layer in an existing high voltage integration process; FIG. 2A to FIG. 2B As shown, it is a schematic diagram of each region in each step of forming a low voltage gate oxide layer in the existing high voltage integration process; FIG. 3A to FIG. 3F FIG. 1 is a schematic diagram of the structure of low-voltage devices in various steps of the existing high-voltage integration process; the formation of a low-voltage gate oxide layer in the existing high-voltage integration process includes the following steps:

[0006] Step S101 , medium voltage silicon oxide in medium voltage, low voltage and 1.2V regions.

[0007] High voltage devices, medium voltage devices and two types of low voltage devices are integrated on the semiconductor substrate 101. One type of low voltage device has an operating voltage of 1.2 V, and the other type of low voltage device has an operating voltage less than 1.2 V. The 1.2 V low voltage device is represented by a 1.2 V device alone. Figure 2A In the figure, formation regions of the high voltage device, the medium voltage device, the 1.2 V device, and the low voltage device are indicated by reference numerals 101 a , 101 b , 101 c , and 101 d , respectively.

[0008] like Figure 3A As shown, the medium voltage silicon oxide, namely the medium voltage gate oxide layer 101, is also formed in the low voltage region, namely the region 101d. Figure 3A In the embodiment, the active region is composed of a semiconductor substrate such as a silicon substrate 101 isolated by a shallow trench isolation 102.

[0009] Step S102, removing the low-voltage silicon oxide in the 1.2V device area. Figure 2A As shown, the regions where the medium-voltage silicon oxide is removed in step S102 are regions 101c and 101d.

[0010] The cross-sectional view of the low voltage device corresponding to step S102 is as follows: Figure 3B As shown, it can be seen that the middle voltage gate oxide layer 103 is removed. Figure 1 In FIG. 1 , the removal amount is a, that is, the removal amount_a. Generally, a is the thickness of the medium voltage gate oxide layer 101 grown in step S101.

[0011] Step S103, growing 1.2V device silicon oxide, that is, growing a low-voltage gate oxide layer of a low-voltage device with an operating voltage of 1.2V. The cross-sectional view of the low-voltage device corresponding to step S103 is shown in FIG. Figure 3C As shown, the low voltage gate oxide layer 105 is 1.2V device silicon oxide.

[0012] Step S104, removing silicon oxide from the 1.2V device in the low voltage area. Figure 2B As shown, the area where the gate oxide layer is removed in step S104 is area 101d.

[0013] like Figure 3D As shown, the low voltage gate oxide layer 105 in the low voltage device region is removed.

[0014] Depend on Figure 1As shown, in step S104, the removal amount corresponding to the thickness of the low voltage gate oxide layer 105 is b, that is, the removal amount_b; usually, a is the thickness of the low voltage gate oxide layer 105 grown in step S103.

[0015] For the low-voltage area, after two silicon oxide removal steps in step S102 and step S104, the removal amounts are a and b respectively, so the thickness of the shallow trench isolation 102 consumed in the low-voltage area is a+b, which makes it easy for the top surface of the shallow trench isolation 102 in the low-voltage area to be lower than the surface of the active area, thereby easily making the isolation effect of the active area of the low-voltage device worse and easily causing leakage.

[0016] Step S105, growing low voltage device silicon oxide, such as Figure 3E As shown, a low-voltage gate oxide layer 105 of a low-voltage device is grown.

[0017] The follow-up also includes:

[0018] like Figure 3F As shown, a gate conductive material layer 106 is formed and patterned, and the first gate structure of each low-voltage device is formed by superposition of a low-voltage gate oxide layer 105 and a gate conductive material layer 106 in the gate formation region of each low-voltage device.

[0019] The second gate structure of the medium voltage device is formed by stacking the medium voltage gate oxide layer 103 and the gate conductive material layer 106 in the gate forming region of each medium voltage device.

[0020] The third gate structure of the high-voltage device is formed by superposition of the high-voltage gate oxide layer and the gate conductive material layer 106 in the gate formation region of each high-voltage device.

[0021] The patterned gate conductive material layer 106 is a polysilicon gate or a metal gate.

[0022] A spacer 106 is formed on the side of each gate structure, and a refractory silicide 107 is formed on the surface of the active region on both sides of the gate structure. Summary of the invention

[0023] The technical problem to be solved by the present invention is to provide a process integration method for improving the performance of low-voltage devices in a high-voltage integration process, which can ensure that when there are multiple types of low-voltage devices, multiple oxidation and oxide removal processes are prevented in each low-voltage area, thereby reducing the consumption of the field oxide layer of each low-voltage area and reducing the roughness of the active area surface of each low-voltage area, thereby improving the performance of the low-voltage device.

[0024] In order to solve the above technical problems, in the process integration method for improving the performance of low-voltage devices in the high-voltage integration process provided by the present invention, high-voltage devices, medium-voltage devices and various types of low-voltage devices are integrated on a semiconductor substrate at the same time, and the types of the low-voltage devices are distinguished according to the operating voltage; the medium-voltage gate oxide layer of the medium-voltage device and the low-voltage gate oxide layers of the various low-voltage devices are formed by the following steps:

[0025] Step 1: The medium-voltage gate oxide layer is formed on the surfaces of the active areas of the medium-voltage area and each low-voltage area on the semiconductor substrate. The active areas are isolated by field oxide layers. The medium-voltage area is the formation area of the medium-voltage device, and the low-voltage area is the formation area of the low-voltage device.

[0026] Step 2: forming the low-voltage gate oxide layers of the various low-voltage devices in sequence according to the operating voltage; the selected low-voltage device is made a selected low-voltage device, and the sub-steps of forming the low-voltage gate oxide layer of the selected low-voltage device include:

[0027] Step 21, make the low-voltage area corresponding to the selected low-voltage device the selected low-voltage area, and remove the medium-voltage gate oxide layer in the selected low-voltage area; the low-voltage gate oxide layers of the low-voltage devices whose operating voltage is greater than that of the selected low-voltage device have been formed, and the medium-voltage gate oxide layers in the low-voltage area corresponding to the low-voltage devices whose operating voltage is less than that of the selected low-voltage device are retained.

[0028] Step 22, performing a first oxidation process to form the low-voltage gate oxide layer corresponding to the selected low-voltage device on the surface of the active area in the selected low-voltage area; in the first oxidation process, the thickness of the medium-voltage gate oxide layer in the low-voltage area corresponding to each of the low-voltage devices whose operating voltage is lower than that of the selected low-voltage device will increase and the increased thickness will be less than the thickness of the low-voltage gate oxide layer corresponding to the selected low-voltage device.

[0029] Repeat the step of removing the medium voltage gate oxide layer in step 21 and the first oxidation process in step 22 until the low voltage gate oxide layers of the various low voltage devices have been formed, and ensure that before the low voltage gate oxide layers of the various low voltage devices are formed, the surface of the corresponding active area only undergoes the medium voltage gate oxide layer removal step once, so as to reduce the consumption of the field oxide layer around the active area of the low voltage area corresponding to the various low voltage devices, the thickness of each low voltage gate oxide layer is less than the thickness of the medium voltage gate oxide layer, and the thickness of each low voltage gate oxide layer decreases with the decrease of the operating voltage of the corresponding low voltage device.

[0030] A further improvement is that, before step 1, a high voltage gate oxide layer has been formed in the high voltage region, and the thickness of the high voltage gate oxide layer is greater than the thickness of the medium voltage gate oxide layer.

[0031] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0032] A further improvement is that the field oxide layer includes shallow trench isolation.

[0033] Further improvements include:

[0034] A gate conductive material layer is formed and patterned, and the first gate structure of each low-voltage device is formed by superposition of the low-voltage gate oxide layer and the gate conductive material layer in the gate formation region of each low-voltage device.

[0035] A further improvement is that the second gate structure of the medium voltage device is formed by superposition of the medium voltage gate oxide layer and the gate conductive material layer in the gate forming region of each medium voltage device.

[0036] A further improvement is that the third gate structure of the high-voltage device is formed by superposition of the high-voltage gate oxide layer and the gate conductive material layer in the gate formation region of each of the high-voltage devices.

[0037] A further improvement is that the patterned gate conductive material layer is a polysilicon gate or a metal gate.

[0038] A further improvement is that the low-voltage device includes at least two types, one type of the low-voltage device has an operating voltage of 1.2V, and the other type of the low-voltage device has an operating voltage less than 1.2V.

[0039] After forming the medium-voltage gate oxide layer, the present invention does not completely remove the medium-voltage gate oxide layers of each low-voltage area, and then sequentially form low-voltage gate oxide layers corresponding to different types of low-voltage devices, but sequentially selects selected low-voltage areas corresponding to the low-voltage devices according to the working voltage of the low-voltage devices to remove the medium-voltage gate oxide layers, and then grows the low-voltage gate oxide layers in the selected low-voltage areas, so that it can be ensured that the low-voltage areas corresponding to each low-voltage device are only subjected to the medium-voltage gate oxide layer removal process once, even if the removed medium-voltage gate oxide layer is superimposed with the thickness of the oxide layer formed by the first oxidation process of the low-voltage gate oxide layers corresponding to each low-voltage device with a larger working voltage, but because the thickness of the medium-voltage gate oxide layer is relatively thick, under the condition of having the medium-voltage gate oxide layer, the first oxidation process The thickness of the added medium-voltage gate oxide layer is less than the thickness formed when there is no medium-voltage gate oxide layer, which will eventually reduce the total thickness of the oxide layer removed before the low-voltage gate oxide layer is formed in each low-voltage area, and the consumption of the field oxide layer will inevitably be reduced, so as to prevent the field oxide layer from reducing the isolation effect of the active area and thus prevent the leakage caused by it; at the same time, the influence on the roughness of the surface of the active area will inevitably be reduced, thereby improving the reliability of the device; therefore, the present invention can ensure that when there are multiple types of low-voltage devices, multiple oxidation and oxide removal processes are prevented in each low-voltage area, thereby reducing the consumption of the field oxide layer in each low-voltage area and reducing the roughness of the surface of the active area of each low-voltage area, which can reduce the leakage of the device and improve the reliability of the device, thereby improving the performance of the low-voltage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments:

[0041] Figure 1 It is a flow chart of forming a low voltage gate oxide layer in an existing high voltage integration process;

[0042] Figure 2A-2B It is a schematic diagram of each region in each step of forming a low voltage gate oxide layer in an existing high voltage integration process;

[0043] Figure 3A-Figure 3F It is a schematic diagram of the structure of low-voltage devices in each step of the existing high-voltage integration process;

[0044] Figure 4 is a flow chart of a process integration method for improving the performance of low-voltage devices in a high-voltage integration process according to an embodiment of the present invention;

[0045] Figure 5 It is a flow chart of a process integration method for improving the performance of low voltage devices in a high voltage integration process according to a preferred embodiment of the present invention;

[0046] Figure 6A-6B It is a schematic diagram of each region in each step of a process integration method for improving the performance of low-voltage devices in a high-voltage integration process according to a preferred embodiment of the present invention;

[0047] Figure 7A-7F It is a schematic diagram of the structure of low-voltage devices in each step of a process integration method for improving the performance of low-voltage devices in a high-voltage integration process according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0048] like Figure 4 As shown, it is a flow chart of a process integration method for improving the performance of low voltage devices in a high voltage integration process according to an embodiment of the present invention; Figure 5 As shown, it is a flow chart of a process integration method for improving the performance of low voltage devices in a high voltage integration process according to a preferred embodiment of the present invention; FIG. 6A to FIG. 6B As shown, it is a schematic diagram of each region in each step of the process integration method for improving the performance of low-voltage devices in a high-voltage integration process according to a preferred embodiment of the present invention; 7A to 7F As shown, it is a schematic diagram of the structure of the low voltage device in each step of the process integration method for improving the performance of the low voltage device in the high voltage integration process according to the preferred embodiment of the present invention; in the process integration method for improving the performance of the low voltage device in the high voltage integration process according to the embodiment of the present invention, high voltage devices, medium voltage devices and various types of low voltage devices are integrated on the semiconductor substrate 201 at the same time, and the types of low voltage devices are distinguished according to the operating voltage.

[0049] In the embodiment of the present invention, the types of low-voltage devices include at least two types.

[0050] In some preferred embodiments, the operating voltage of one low-voltage device is 1.2V, and the operating voltage of another low-voltage device is less than 1.2V.

[0051] like Fig. 6A As shown, the high voltage region, i.e., the region where the high voltage device is formed, i.e., the high voltage device region, is indicated by a mark 201a, the medium voltage region, i.e., the region where the medium voltage device is formed, i.e., the medium voltage device region, is indicated by a mark 201b, and the low voltage region, i.e., the region where the low voltage device is formed, i.e., the low voltage device region, is indicated by a mark 201d. Fig. 6A The 1.2V device area is also marked separately with a mark 201c. In this application, the 1.2V device area is a low-voltage device with an operating voltage of 1.2V. The medium-voltage gate oxide layer 203 of the medium-voltage device and the low-voltage gate oxide layers of various low-voltage devices are formed by the following steps:

[0052] Step 1: Fig. 7A As shown, a medium-voltage gate oxide layer 203 is formed on the surfaces of the medium-voltage region and the active regions of each low-voltage region on the semiconductor substrate 201, and the active regions are isolated by a field oxide layer 202. The medium-voltage region is the formation region of the medium-voltage device, and the low-voltage region is the formation region of the low-voltage device. Fig. 7A Only one low voltage device formation area in the low voltage region is shown. Fig. 6AAs shown, a medium voltage gate oxide layer 203 is formed in regions 201b, 201c and 201d.

[0053] In the embodiment of the present invention, before step 1, a high voltage gate oxide layer has been formed in the high voltage region, and the thickness of the high voltage gate oxide layer is greater than the thickness of the medium voltage gate oxide layer 203 .

[0054] The semiconductor substrate 201 includes a silicon substrate. The medium voltage gate oxide layer 203 is silicon oxide, that is, medium voltage silicon oxide.

[0055] The field oxide layer 202 includes shallow trench isolation.

[0056] The medium voltage gate oxide layer 203 is usually grown using a thermal oxidation process. Fig. 6A In the figure, region 201a is a high voltage region. Since a high voltage gate oxide layer has been formed in the high voltage region, the high voltage gate oxide layer will have a certain blocking effect on the thermal oxidation process of the medium voltage gate oxide layer 203, so that the thickness of the high voltage gate oxide layer is increased to a certain extent, but the increased thickness is not as thick as the thickness of the medium voltage gate oxide layer 203 formed on the surface of the semiconductor substrate 201 in the active region.

[0057] exist Figure 5 In the preferred embodiment shown, step one corresponds to step S201, the medium voltage silicon oxide is in the medium voltage, low voltage and 1.2V regions.

[0058] Step 2: forming low-voltage gate oxide layers of various low-voltage devices in sequence according to the working voltage; the selected low-voltage device is the selected low-voltage device, and the sub-steps of forming the low-voltage gate oxide layer of the selected low-voltage device include:

[0059] Step 21, let the low-voltage area corresponding to the selected low-voltage device be the selected low-voltage area, and remove the medium-voltage gate oxide layer 203 in the selected low-voltage area; the low-voltage gate oxide layers of each low-voltage device whose operating voltage is greater than the selected low-voltage device have been formed, and the medium-voltage gate oxide layers 203 in the low-voltage area corresponding to each low-voltage device whose operating voltage is less than the selected low-voltage device are retained.

[0060] Step 22, perform a first oxidation process to form a low-voltage gate oxide layer corresponding to the selected low-voltage device on the surface of the active area in the selected low-voltage area; in the first oxidation process, the thickness of the medium-voltage gate oxide layer 203 in the low-voltage area corresponding to each low-voltage device whose operating voltage is lower than that of the selected low-voltage device will increase and the increased thickness will be less than the thickness of the low-voltage gate oxide layer corresponding to the selected low-voltage device.

[0061] Repeat the step of removing the medium voltage gate oxide layer 203 in step 21 and the first oxidation process in step 22 until the low voltage gate oxide layers of various low voltage devices have been formed, and ensure that before the low voltage gate oxide layers of various low voltage devices are formed, the surface of the corresponding active area only undergoes the medium voltage gate oxide layer 203 removal step once, so as to reduce the consumption of the field oxide layer 202 on the active area side of the low voltage area corresponding to various low voltage devices. The thickness of each low voltage gate oxide layer is less than the thickness of the medium voltage gate oxide layer 203, and the thickness of each low voltage gate oxide layer decreases with the decrease of the operating voltage of the corresponding low voltage device.

[0062] In a preferred embodiment of the present invention, a 1.2V low voltage device is represented by a 1.2V device alone. The above step 2 is further described below in conjunction with the specific steps of the preferred embodiment of the present invention:

[0063] Step S202, removing the low-voltage silicon oxide in the 1.2V device area. Fig. 6A As shown, the area where the medium-pressure silicon oxide is removed in step S202 is area 201c, and the medium-pressure silicon oxide in area 201d is not removed. Figure 2A The medium-pressure silicon oxide in the middle regions 101c and 101d needs to be removed simultaneously which is different.

[0064] The cross-sectional view of the low voltage device corresponding to step S202 is as follows: Figure 7B As shown, it can be seen that the middle voltage gate oxide layer 203 is not removed.

[0065] Step S203, growing 1.2V device silicon oxide, that is, growing a low-voltage gate oxide layer of a low-voltage device with an operating voltage of 1.2V. The cross-sectional view of the low-voltage device corresponding to step S203 is shown in FIG. Figure 7C As shown, since the medium-voltage gate oxide layer 203 is not removed, during the process of growing the low-voltage gate oxide layer of the 1.2V device, the thickness of the active area surface of the low-voltage device below 1.2V is also oxidized and becomes smaller due to the blocking of the medium-voltage gate oxide layer 203. Therefore, after the oxide layer formed by oxidation is superimposed on the medium-voltage gate oxide layer 203, although the thickness of the medium-voltage gate oxide layer 203 is increased to a certain extent, the increased thickness is not as thick as the thickness of the low-voltage gate oxide layer directly grown on the silicon in the active area.

[0066] The above steps S202 and S203 are equivalent to steps 21 and 22 in the first cycle. After step S203, the gate oxide layer of the 1.2V device has been formed.

[0067] After that, it also includes:

[0068] Step S204: Remove the 1.2V devices and medium-voltage silicon oxide in the low-voltage area. Figure 6BAs shown, the area where the gate oxide layer is removed in step S204 is only area 201d. The 1.2V device and medium voltage silicon oxide refer to the silicon oxide formed in the process of growing the 1.2V device silicon oxide in the medium voltage gate oxide layer 203 in area 201d in step S203 of the previous cycle.

[0069] like Fig.7D As shown, the medium voltage gate oxide layer 203 in the low voltage device region is removed.

[0070] Depend on Figure 5 As shown, in step S202 , the thickness of the removed medium-voltage silicon oxide corresponds to a removal amount, ie, removal amount_a; a is the initial thickness of the medium-voltage gate oxide layer 203 .

[0071] In step S204, the removal amount corresponding to the thickness of the medium-voltage gate oxide layer 203 is c, that is, the removal amount_c; c is the initial thickness of the medium-voltage gate oxide layer 203 superimposed with the thickness added by the silicon oxide growth process of the 1.2V device, and let, in step S203, the thickness of the low-voltage gate oxide layer grown in the 1.2V device area be b, then c must be less than the sum of a and b, that is, c<a+b. Therefore, the embodiment of the present invention can control the removal amount c so that c is less than a plus b, and finally it will inevitably reduce the consumption of the field oxide layer 202 in the region 201d, so that the top surface of the field oxide layer 202 in the low-voltage area will not be lowered below the top surface of the active area.

[0072] Step S205: growing low voltage device silicon oxide, such as Fig. 7E As shown, a low-voltage gate oxide layer 204 of a low-voltage device is grown.

[0073] The above steps S204 and S205 are equivalent to steps 21 and 22 in the second cycle. After step S205, the gate oxide layer of the low-voltage device with an operating voltage lower than 1.2V has been formed.

[0074] The follow-up also includes:

[0075] like Figure 7F As shown, a gate conductive material layer 205 is formed and patterned, and the first gate structure of each low-voltage device is formed by superposition of a low-voltage gate oxide layer 204 and a gate conductive material layer 205 in the gate formation region of each low-voltage device.

[0076] The second gate structure of the medium voltage device is formed by stacking the medium voltage gate oxide layer 203 and the gate conductive material layer 205 in the gate forming region of each medium voltage device.

[0077] The third gate structure of the high-voltage device is formed by superposition of the high-voltage gate oxide layer and the gate conductive material layer 205 in the gate formation region of each high-voltage device.

[0078] The patterned gate conductive material layer 205 is a polysilicon gate or a metal gate.

[0079] Also includes:

[0080] A spacer 206 is formed on the side of each gate structure, and a refractory silicide 207 is formed on the surface of the active region on both sides of the gate structure.

[0081] After forming the medium-voltage gate oxide layer 203, the embodiment of the present invention does not completely remove the medium-voltage gate oxide layer 203 of each low-voltage area, and then sequentially form low-voltage gate oxide layers corresponding to different types of low-voltage devices. Instead, the selected low-voltage areas corresponding to the low-voltage devices are sequentially selected according to the working voltage of the low-voltage devices to remove the medium-voltage gate oxide layer 203, and then the low-voltage gate oxide layer is grown in the selected low-voltage areas. In this way, it can be ensured that the low-voltage area corresponding to each low-voltage device is subjected to only one removal process of the medium-voltage gate oxide layer 203. Even if the removed medium-voltage gate oxide layer 203 is superimposed with the thickness of the oxide layer formed by the first oxidation process of the low-voltage gate oxide layers corresponding to each low-voltage device with a larger working voltage, due to the medium-voltage gate oxide layer 203 The thickness is relatively thick. Under the condition of having a medium-voltage gate oxide layer 203, the thickness increased by the first oxidation process on the medium-voltage gate oxide layer 203 is less than the thickness formed when there is no medium-voltage gate oxide layer 203. Finally, the total thickness of the oxide layer removed before the low-voltage gate oxide layer is formed in each low-voltage area will inevitably be reduced, the consumption of the field oxide layer 202 will inevitably be reduced, and the impact on the roughness of the surface of the active area will inevitably be reduced. Therefore, the embodiment of the present invention can ensure that when there are multiple types of low-voltage devices, multiple oxidation and oxide removal processes are prevented in each low-voltage area, thereby reducing the consumption of the field oxide layer 202 in each low-voltage area and reducing the roughness of the surface of the active area of each low-voltage area, which can reduce the leakage of the device and improve the reliability of the device, thereby improving the performance of the low-voltage device.

[0082] In a preferred embodiment of the present invention, the existing two silicon oxide removals in the low-voltage area are combined, and the thick oxygen in the medium-voltage area is used to block the growth of silicon oxide in the 1.2V device. Then, one removal is performed, and the total amount removed is lower than the original two removals, thereby reducing the loss of silicon oxide isolation in the low-voltage area and improving the depression of the isolation area adjacent to the active area, thereby improving device performance, and improving the surface roughness of the active area caused by multiple silicon oxide removals to improve reliability.

[0083] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A process integration method for improving the performance of low voltage devices in a high voltage integration process, characterized in that: A high-voltage device, a medium-voltage device and various types of low-voltage devices are integrated on a semiconductor substrate at the same time, and the types of the low-voltage devices are differentiated according to the operating voltage; a medium-voltage gate oxide layer of the medium-voltage device and low-voltage gate oxide layers of the various low-voltage devices are formed by the following steps: Step 1: forming the medium-voltage gate oxide layer on the surfaces of the medium-voltage region and the active regions of each low-voltage region on the semiconductor substrate, wherein the active regions are isolated by field oxide layers, the medium-voltage region is a formation region of the medium-voltage device, and the low-voltage region is a formation region of the low-voltage device; Step 2: forming the low-voltage gate oxide layers of various low-voltage devices in sequence according to the operating voltage; The selected low-voltage device is defined as a selected low-voltage device, and the sub-step of forming the low-voltage gate oxide layer of the selected low-voltage device includes: Step 21, the low voltage region corresponding to the selected low voltage device is set as the selected low voltage region, and the medium voltage gate oxide layer in the selected low voltage region is removed; the low voltage gate oxide layers of the low voltage devices having an operating voltage greater than that of the selected low voltage device have been formed, and the medium voltage gate oxide layers in the low voltage region corresponding to the low voltage devices having an operating voltage less than that of the selected low voltage device are retained; Step 22, performing a first oxidation process to form the low-voltage gate oxide layer corresponding to the selected low-voltage device on the surface of the active area in the selected low-voltage area; in the first oxidation process, the thickness of the medium-voltage gate oxide layer in the low-voltage area corresponding to each of the low-voltage devices having an operating voltage lower than that of the selected low-voltage device will increase, and the increased thickness will be less than the thickness of the low-voltage gate oxide layer corresponding to the selected low-voltage device; Repeat the step of removing the medium voltage gate oxide layer in step 21 and the first oxidation process in step 22 until the low voltage gate oxide layers of the various low voltage devices have been formed, and ensure that before the low voltage gate oxide layers of the various low voltage devices are formed, the surface of the corresponding active area only undergoes the medium voltage gate oxide layer removal step once, so as to reduce the consumption of the field oxide layer around the active area of the low voltage area corresponding to the various low voltage devices, the thickness of each low voltage gate oxide layer is less than the thickness of the medium voltage gate oxide layer, and the thickness of each low voltage gate oxide layer decreases with the decrease of the operating voltage of the corresponding low voltage device.

2. The process integration method for improving the performance of low voltage devices in a high voltage integration process according to claim 1, characterized in that: Before step 1, a high voltage gate oxide layer has been formed in the high voltage region, and the thickness of the high voltage gate oxide layer is greater than the thickness of the medium voltage gate oxide layer.

3. The process integration method for improving the performance of low voltage devices in a high voltage integration process according to claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.

4. The process integration method for improving the performance of low voltage devices in a high voltage integration process according to claim 1, characterized in that: The field oxide layer includes shallow trench isolation.

5. The process integration method for improving the performance of low voltage devices in high voltage integration process according to claim 2, characterized in that: The follow-up also includes: A gate conductive material layer is formed and patterned, and the first gate structure of each low-voltage device is formed by superposition of the low-voltage gate oxide layer and the gate conductive material layer in the gate formation region of each low-voltage device.

6. The process integration method for improving the performance of low voltage devices in a high voltage integration process according to claim 5, characterized in that: The second gate structure of the medium voltage device is formed by stacking the medium voltage gate oxide layer and the gate conductive material layer in the gate forming region of each medium voltage device.

7. The process integration method for improving the performance of low voltage devices in a high voltage integration process according to claim 5, characterized in that: The third gate structure of the high-voltage device is formed by stacking the high-voltage gate oxide layer and the gate conductive material layer in the gate forming region of each of the high-voltage devices.

8. The process integration method for improving the performance of low voltage devices in a high voltage integration process according to claim 5, characterized in that: The patterned gate conductive material layer is a polysilicon gate or a metal gate.

9. The process integration method for improving the performance of low voltage devices in a high voltage integration process according to claim 1, characterized in that: The low-voltage device includes at least two types, one of which has an operating voltage of 1.2V, and the other of which has an operating voltage less than 1.2V.