Input current adjusting method of driving switch and motor driving circuit

Abstract

The invention provides an input current adjusting method of a driving switch and a motor driving circuit. The DAC signal indicates the number of unit charge quantities respectively input to the driving switch in a plurality of clock periods, and a first clock period in which the input unit charge quantity needs to be increased in the plurality of clock periods; when the first current signal is adjusted to enable the switching delay of the driving switch to meet the requirement, the DAC signal is adjusted once, on one hand, the basic charge quantity needing to be input to the driving switch in multiple clock periods can be adjusted, and therefore coarse-grained adjustment of the first current signal is achieved; on the other hand, the unit charge quantity can be increased in the first clock period in the plurality of clock periods, so that the fine-grained adjustment of the first current signal is realized; that is to say, coarse-grained and fine-grained adjustment of the first current signal is realized by adjusting the DAC signal once, so that the adjustment resource overhead of the input current of the driving switch can be reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to an input current regulation method for a driving switch and a motor driving circuit. Background Art

[0002] A brushed DC motor is a rotating motor that contains a brush device that converts DC power into mechanical energy. The brush device is used to transmit the DC power from the power supply to the rotor of the motor, making the motor rotate. Brushed DC motors have the characteristics of simple structure, easy control and fast response speed. They are widely used in various power tools, household appliances, automobiles, automated robots and other fields.

[0003] The operation of a brushed DC motor requires a pulsed voltage signal from the motor drive circuit. The motor drive circuit controls the two drive switches to conduct alternately, chopping the continuous and constant power supply voltage to convert the power supply voltage into a pulsed voltage signal output, thereby adjusting the speed, torque and direction of the brushed DC motor in real time.

[0004] When the motor drive circuit is working, it is necessary to control the loss of the motor drive circuit. The loss of the motor drive circuit is related to the working delay of the drive switch; the working delay includes the turn-on delay and the turn-off delay of the drive switch. The working delay of the drive switch is positively correlated with the input current at the gate end of the drive switch; specifically, when the input current is increased, the working delay of the drive switch is reduced, which is beneficial to reducing the loss of the motor drive circuit; if the input current is higher than a certain threshold, the working speed of the drive switch is too fast, and the output voltage of the motor drive circuit will oscillate, and the oscillation phenomenon causes the loss of the motor drive circuit to increase. It can be seen that when using the motor drive circuit to drive the brushed DC motor, it is necessary to adjust the input current at the gate end of the drive switch in the motor drive circuit to keep the working delay of the drive switch within an appropriate range, thereby reducing the loss of the motor drive circuit.

[0005] However, when adjusting the input current of the gate terminal in the related art, the adjustment process is relatively complicated, which will occupy a large amount of adjustment resources. Summary of the invention

[0006] The present application provides an input current regulation method for a driving switch and a motor driving circuit, which can simultaneously achieve coarse-grained and fine-grained regulation of a current signal by adjusting a (Digital to Analog Converter, DAC) signal, thereby reducing the regulation resource overhead of the input current of the driving switch.

[0007] In a first aspect, the present application provides an input current regulation method for a driving switch, comprising: generating a first current signal based on a digital-to-analog converter DAC signal of a first regulation cycle, and sending the first current signal to the driving switch to switch the state of the driving switch; wherein the DAC signal is used to indicate the number of unit charges input to the driving switch in a plurality of clock cycles included in the first regulation cycle, and the first clock cycle in which the input unit charge needs to be increased in the plurality of clock cycles; obtaining a target DAC signal based on a state switching delay of the driving switch in the first regulation cycle and a preset condition; the target DAC signal is a DAC signal of the first regulation cycle or an adjusted DAC signal; generating a target current signal based on the target DAC signal in a second regulation cycle, and sending the target current signal to the driving switch to switch the state of the driving switch; in the second regulation cycle and at least one regulation cycle after the second regulation cycle, the absolute value of the delay difference between the state switching delay of the driving switch and the preset delay is less than the preset threshold.

[0008] In some embodiments, the DAC signal based on the first adjustment cycle generates a first current signal, including: based on the DAC signal, determining the total charge input to the drive switch for each clock cycle within the first adjustment cycle; wherein the total charge corresponding to the first clock cycle is the sum of the basic charge and the unit charge; the basic charge is the product of the number of unit charges and the unit charge; for each second clock cycle different from the first clock cycle within the first adjustment cycle, the total charge of the second clock cycle is the basic charge; and the first current signal is generated based on the total charges corresponding to the multiple clock cycles.

[0009] In some embodiments, the preset condition includes a first condition and a second condition; the target DAC signal is obtained based on the state switching delay of the drive switch in the first adjustment cycle and the preset condition, including: if the state switching delay of the drive switch in the first adjustment cycle satisfies the first condition, the DAC signal is adjusted; the first condition is that the state switching delay of the drive switch is greater than the preset delay, and the absolute value of the delay difference between the state switching delay and the preset delay is greater than or equal to a first preset threshold; if the state switching delay of the drive switch in the first adjustment cycle satisfies the second condition, the DAC signal is adjusted; the second condition is that the state switching delay of the drive switch is less than the preset delay, and the absolute value of the delay difference between the state switching delay and the preset delay is greater than a second preset threshold and less than or equal to the first preset threshold; wherein, the first preset threshold is greater than the second preset threshold.

[0010] In some embodiments, when the state switching delay of the driving switch in the first adjustment cycle satisfies the first condition, the DAC signal is adjusted, including: adjusting the DAC signal according to a first mapping relationship until the absolute value of the delay difference is less than or equal to the second preset threshold; wherein the first mapping relationship includes multiple sets of corresponding relationships between adjustment times and adjustment steps, and the adjustment times are negatively correlated with the adjustment step.

[0011] In some embodiments, the DAC signal is adjusted according to the first mapping relationship until the absolute value of the delay difference is less than or equal to the second preset threshold value to obtain a target DAC signal, including: determining a current adjustment number, and determining a first step length corresponding to the current DAC signal according to the current adjustment number and the first mapping relationship; generating an updated DAC signal according to a result of adding a coding value of the current DAC signal to the first step length, and updating the current adjustment number; and repeatedly executing until the absolute value of the delay difference is less than or equal to the second preset threshold value to obtain the target DAC signal.

[0012] In some embodiments, when the state switching delay of the driving switch in the first adjustment cycle satisfies the second condition, the DAC signal is adjusted, including: according to the first mapping relationship and the second mapping relationship, the DAC signal is adjusted until the absolute value of the delay difference is less than or equal to the second preset threshold value, so as to obtain the target DAC signal; wherein, the first mapping relationship and the second mapping relationship respectively include multiple sets of corresponding relationships between the number of adjustments and the adjustment step; in the first mapping relationship, the number of adjustments is negatively correlated with the adjustment step; in the second mapping relationship, the number of adjustments is positively correlated with the adjustment step.

[0013] In some embodiments, the DAC signal is adjusted according to the first mapping relationship and the second mapping relationship until the absolute value of the delay difference is less than or equal to the second preset threshold value to obtain the target DAC signal, including: determining the current adjustment number, and determining the second step size corresponding to the current DAC signal according to the current adjustment number and the second mapping relationship; generating an updated DAC signal according to the result of subtracting the coding value of the current DAC signal from the second step size, and updating the current adjustment number; repeatedly executing until the state switching delay of the driving switch is greater than the preset delay and the absolute value of the delay difference is greater than the second preset threshold value to obtain an intermediate DAC signal; increasing the coding value of the intermediate DAC signal according to the second step size used last time and the first mapping relationship until the absolute value of the delay difference is less than the preset threshold value to obtain the target DAC signal; or, until the absolute value of the delay difference is less than or equal to the second preset threshold value to obtain the target DAC signal.

[0014] In some embodiments, in the first mapping relationship, the adjustment times are increased by 1 and the adjustment step is reduced by half.

[0015] In some embodiments, in the second mapping relationship, the adjustment times are reduced or increased by 1, and the adjustment step is doubled.

[0016] In a second aspect, the present application provides a motor drive circuit, comprising: a digital control logic circuit, a digital-to-analog conversion circuit and a half-bridge circuit; wherein the output end of the digital control logic circuit is connected to the input end of the digital-to-analog conversion circuit, and the two output ends of the digital-to-analog conversion circuit are correspondingly connected to the control ends of two drive switches on the half-bridge circuit; for any of the drive switches, the digital control logic circuit is used to generate a digital-to-analog converter DAC signal of a first adjustment cycle; the digital-to-analog conversion circuit is used to generate a first current signal based on the DAC signal, and send the first current signal to the drive switch to switch the state of the drive switch; wherein the DAC signal is used to indicate the number of unit charges input to the drive switch respectively within multiple clock cycles included in the first adjustment cycle, and the The multiple clock cycles need to increase the first clock cycle of the input unit charge; the digital control logic circuit is also used to obtain the target DAC signal based on the state switching delay of the drive switch in the first adjustment cycle and the preset conditions, and send the target DAC signal to the digital-to-analog conversion circuit; the target DAC signal is the DAC signal of the first adjustment cycle or the adjusted DAC signal; the digital-to-analog conversion circuit is also used to generate a target current signal based on the target DAC signal in the second adjustment cycle, and send the target current signal to the drive switch to switch the state of the drive switch; in the second adjustment cycle and at least one adjustment cycle after the second adjustment cycle, the absolute value of the difference between the state switching delay of the drive switch and the preset delay is less than the preset threshold.

[0017] In a third aspect, the present application provides a motor driver chip, comprising: the motor driver circuit described in the second aspect.

[0018] In a fourth aspect, the present application provides a brushed DC motor system, comprising: a brushed DC motor body and the motor drive circuit described in the second aspect, wherein the output end of the motor drive circuit is connected to the drive end of the brushed DC motor body; the motor drive circuit is used to provide a pulse voltage signal to the brushed DC motor body to drive the brushed DC motor body to operate.

[0019] The present application provides an input current regulation method for a driving switch and a motor driving circuit. A DAC signal indicates the number of unit charges input to the driving switch in multiple clock cycles, and the first clock cycle in which the input unit charge needs to be increased in multiple clock cycles; when the present application adjusts the first current signal so that the switching delay of the driving switch meets the requirements, by adjusting the DAC signal once, on the one hand, it is possible to adjust the basic charge (number * unit charge) that needs to be input to the driving switch in multiple clock cycles, thereby achieving coarse-grained regulation of the first current signal; on the other hand, it is also possible to increase the unit charge in the first clock cycle in multiple clock cycles, thereby achieving fine-grained regulation of the first current signal; that is, the present application achieves coarse-grained and fine-grained regulation of the first current signal by adjusting the DAC signal once, so that the regulation resource overhead of the input current of the driving switch can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of a brushed DC motor system provided in an embodiment of the present application;

[0021] Figure 2 is the drain-source current I of the driving switch DS and the drain-source voltage V DS Waveform diagram of ;

[0022] Figure 3 is the gate input current I that drives the switch in the precharge (PCHG), charge (CHG) and postcharge (POCHG) phases. G and the gate-source voltage V GS Waveform diagram of ;

[0023] Figure 4A A flowchart of an implementation method of an input current regulation method of a driving switch provided in an embodiment of the present application;

[0024] Figure 4B A schematic diagram of the total charge amount in each clock cycle provided in an embodiment of the present application;

[0025] Figure 5 A flowchart of an implementation method of an input current regulation method of a driving switch provided in an embodiment of the present application;

[0026] Figure 6 A flowchart of an implementation method of an input current regulation method of a driving switch provided in an embodiment of the present application;

[0027] Figure 7 A schematic diagram of a first current signal adjustment process provided in an embodiment of the present application;

[0028] Figure 8 A flowchart of an implementation method of an input current regulation method of a driving switch provided in an embodiment of the present application;

[0029] Fig. 9 A schematic diagram of adjusting the step size based on a state machine provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0031] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0032] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] A brushed DC motor is a rotating motor that contains a brush device that converts DC power into mechanical energy. The brush device is used to transmit the DC power from the power supply to the rotor of the motor, making the motor rotate. Brushed DC motors have the characteristics of simple structure, easy control and fast response speed. They are widely used in various power tools, household appliances, automobiles, automated robots and other fields.

[0034] The current regulation method of the drive switch provided in the present application is applicable to a brushed DC motor system.

[0035] Figure 1 A schematic diagram of the structure of a brushed DC motor system provided in an embodiment of the present application; Figure 1 As shown, the brushed DC motor system 10 includes a motor drive circuit 101 and a brushed DC motor body Mm.

[0036] The motor driving circuit 101 includes a motor pre-driving circuit 102 and a half-bridge circuit 103 .

[0037] Specifically, the motor pre-drive circuit 102 includes a digital control logic circuit 20 and a digital-to-analog conversion circuit 21; the output end of the digital control logic circuit 20 is connected to the input end of the digital-to-analog conversion circuit 21, and the two output ends of the digital-to-analog conversion circuit 21 are correspondingly connected to the control ends of the two drive switches on the half-bridge circuit 103.

[0038] For any driving switch, the digital control logic circuit 20 is used to generate a DAC signal; the digital-to-analog conversion circuit 21 is used to generate a first current signal based on the DAC signal and send the first current signal to the driving switch to switch the state of the driving switch.

[0039] The two driving switches maintain opposite states, so that the half-bridge circuit 103 can convert the power supply voltage into a pulse voltage and output the pulse voltage to the brushed DC motor body Mm.

[0040] The output end of the motor driving circuit 101 is connected to the driving end of the brushed DC motor body Mm; the motor driving circuit 101 is used to provide a pulse voltage signal to the brushed DC motor body Mm to drive the brushed DC motor body Mm to work.

[0041] Specifically, Figure 1 As shown, the digital-to-analog conversion circuit 21 includes a first digital-to-analog converter DAC1 and a second digital-to-analog converter DAC2. The half-bridge circuit 103 includes a first drive switch M1 and a second drive switch M2. The digital-to-analog conversion circuit 21 includes two input terminals and two output terminals; the two input terminals are respectively the input terminals of the first digital-to-analog converter DAC1 and the input terminals of the second digital-to-analog converter DAC2; the two output terminals are respectively the output terminals of the first digital-to-analog converter DAC1 and the output terminals of the second digital-to-analog converter DAC2.

[0042] The output end of the digital control logic circuit 20 is connected to the input end of the first digital-to-analog converter DAC1 and the input end of the second digital-to-analog converter DAC2 respectively; the output end of the first digital-to-analog converter DAC1 and the output end of the second digital-to-analog converter DAC2 are connected to the control end of the first drive switch M1 and the control end of the second drive switch M2 respectively.

[0043] The first end of the first drive switch M1 is connected to the power supply voltage, the second end of the first drive switch M1 is connected to the first end of the second drive switch M2, the second end of the second drive switch M2 is grounded, and the second end of the first drive switch M1 is also connected to the brushed DC motor body Mm.

[0044] The first drive switch M1 may be an N-type metal oxide semiconductor (NMOS), the first end of the first drive switch M1 is the drain of the NMOS, the second end of the first drive switch M1 is the source of the NMOS, and the control end of the first drive switch M1 is the gate of the NMOS.

[0045] The second drive switch M2 may be an NMOS, a first terminal of the second drive switch M2 is a drain of the NMOS, a second terminal of the second drive switch M2 is a source of the NMOS, and a control terminal of the second drive switch M2 is a gate of the NMOS.

[0046] The DAC signal includes a first DAC signal and a second DAC signal, and the first current signal includes a first current sub-signal and a second current sub-signal. The digital control logic circuit 20 outputs the first DAC signal to the first digital-to-analog converter DAC1 and outputs the second DAC signal to the second digital-to-analog converter DAC2.

[0047] The first digital-to-analog converter DAC1 generates a first current sub-signal based on the first DAC signal, and inputs the first current sub-signal to the first drive switch M1 to switch the state of the first drive switch M1. The second digital-to-analog converter DAC2 generates a second current sub-signal based on the second DAC signal, and inputs the second current sub-signal to the second drive switch M2 to switch the state of the second drive switch M2.

[0048] The state switching of the driving switch refers to the driving switch switching from the on state to the off state, or switching from the off state to the on state.

[0049] Figure 1 In the embodiment, the first drive switch M1 and the second drive switch M2 are alternately turned on to chop the continuous and constant power supply voltage, converting the power supply voltage into pulses and inputting them into the brushed DC motor body Mm, thereby adjusting the speed, torque and direction of the brushed DC motor body Mm in real time.

[0050] The driving switch will generate loss during the state switching process. Next, the first driving switch M1 is used as an example to illustrate the relevant process of the driving switch state switching. The relevant process of the second driving switch M2 state switching is similar to the relevant process of the first driving switch M1 state switching, which will not be repeated here.

[0051] As described above, the first digital-to-analog converter DAC1 provides the first sub-current signal to the gate of the first drive switch M1 to control the operation of the first drive switch M1. Specifically, the polarity of the first sub-current signal is used to control the first drive switch M1 to be in an on or off state, and the magnitude of the first sub-current signal is used to control the state switching delay of the first drive switch M1.

[0052] State switching delay includes on-delay and off-delay. On-delay refers to the delay of driving the switch from off state to on state, and off-delay refers to the delay of driving the switch from on state to off state.

[0053] The motor pre-driving circuit 102 drives the brushed DC motor body Mm by means of pulse width modulation (PWM). Specifically, the digital control logic circuit 20 also sends PWM signals to the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 respectively to control the polarity of the corresponding sub-current signal input to the corresponding driving switch, thereby controlling the state of the corresponding driving switch to be on or off.

[0054] Figure 2 The drain-source current I of the first drive switch M1 in one PWM cycle is DS and the drain-source voltage V DS Waveform diagram of . Figure 2 As shown, in one PWM cycle, the first drive switch M1 undergoes one turn-on and one turn-off, and the drain-source current I DS and drain-source voltage V DS Under the action of input current, the drain-source voltage V DS and drain-source current I DS There are two non-zero overlap regions, representing the conduction loss E LOSS(ON) and disconnection loss E LOSS(OFF) .

[0055] The conduction loss of the first drive switch M1 is related to the conduction delay of the first drive switch M1 ; the turn-off loss of the first drive switch M1 is related to the turn-off delay of the first drive switch M1 .

[0056] The turn-on delay and turn-off delay of the first driving switch M1 are positively correlated with the magnitude of the first current signal provided by the first digital-to-analog converter DAC1 to the first driving switch.

[0057] Next, the relationship between the on-delay of the first driving switch M1 and the first current signal corresponding to the first driving switch M1 is exemplarily described. The relationship between the off-delay of the first driving switch M1 and the first current signal is similar and will not be elaborated here.

[0058] When the first current signal increases, the turn-on delay of the first drive switch M1 decreases, and the turn-on speed of the first drive switch M1 becomes faster, which can effectively reduce the drain-source voltage V DS and drain-source current I DS The overlap area in the process of switching from the off state to the on state reduces the conduction loss of the first drive switch M1; if the first current signal continues to increase until it exceeds a certain threshold, the conduction speed of the first drive switch M1 is too fast, and the drain-source voltage V DS An oscillation phenomenon may occur, which may increase the conduction loss of the first driving switch M1 .

[0059] The above delay loss analysis for the first driving switch M1 is also applicable to the second driving switch M2.

[0060] When the drive switch switches from the off state to the on state, the motor pre-drive circuit can use a three-stage current control strategy to control the input current of the drive switch; wherein, within one PWM cycle, the three stages corresponding to the input current are: pre-charging stage, charging stage, and post-charging stage. Figure 3 Provides gate input current I at different stages G Waveform diagram of the gate-source voltage V that drives the switch under the action of the input current at different stages GS Schematic diagram of the waveform.

[0061] When the drive switch switches from the off state to the on state, the time and input current of the three stages can be flexibly configured to adjust the state switching delay of the drive switch, thereby controlling the loss of the drive switch.

[0062] The input current can be adjusted in each PWM cycle to adjust the state switching delay of the PWM cycle drive switch.

[0063] Specifically, when the drive switch is switched from the off state to the on state, the state switching delay of the drive switch can be controlled by controlling the input current in the pre-charging stage. In this application, when the drive switch is switched from the off state to the on state, the first current signal is the current signal input to the drive switch in the pre-charging stage.

[0064] Correspondingly, when the drive switch switches from the on state to the off state, the motor pre-drive circuit can use a three-stage current control strategy to control the input current of the drive switch; wherein, within a PWM cycle, the three stages corresponding to the input current are: pre-discharge stage, discharge stage, and post-discharge stage; the input current I G Schematic diagram of the waveform, and the gate-source voltage V that drives the switch under different input currents GS The waveform diagram and Figure 3 Similar, I will not go into details here.

[0065] When the drive switch switches from the on state to the off state, the time and input current of the three stages can be flexibly configured to adjust the state switching delay of the drive switch, thereby controlling the loss of the drive switch.

[0066] Specifically, when the drive switch is switched from the on state to the off state, the state switching delay of the drive switch can be controlled by controlling the input current in the pre-discharge stage. In this application, when the drive switch is switched from the on state to the off state, the first current signal is the current signal input to the drive switch in the pre-discharge stage.

[0067] In the prior art, when adjusting the first current signal, the DAC signal needs to be adjusted twice to adjust the basic charge input to the drive switch in each clock cycle during the pre-charging stage or the pre-discharging stage, and to increase the input unit charge to the drive switch in the selected clock cycle; this will increase the adjustment resource overhead.

[0068] The reason is that the DAC signal input from the digital control logic circuit to the digital-to-analog conversion circuit in the prior art is used to indicate the number of unit charges input to the drive switch in multiple clock cycles, or to indicate the clock cycle in which the unit charge needs to be increased. Therefore, adjusting the DAC signal once can only adjust the basic charge input to the drive switch in each clock cycle, or increase the input unit charge to the drive switch in the selected clock cycle. It is not possible to adjust both at the same time, which increases the adjustment resource overhead.

[0069] Based on this, the present application provides an input current adjustment method for a driving switch, in which a DAC signal based on which a first current signal is generated indicates the number of unit charges input to the driving switch in multiple clock cycles of an adjustment cycle, and the first clock cycle in which the input unit charge needs to be increased in multiple clock cycles. Therefore, the coarse adjustment and fine adjustment of the first current signal can be achieved simultaneously by adjusting the DAC signal once; thus, the adjustment resource overhead of the motor pre-drive circuit can be reduced.

[0070] Fig. 4 is a flowchart of the implementation of the input current regulation method of the drive switch provided in the embodiment of the present application. The input current regulation method of the drive switch provided in the embodiment of the present application can be applied to a brushed DC motor system.

[0071] The brushed DC motor system of this application is Figure 1 The digital control logic circuit involved in this application is Figure 1 The digital control logic circuit 20 in.

[0072] The digital-to-analog conversion circuit involved in this application is Figure 1 The digital-to-analog conversion circuit 21 in.

[0073] The first driving switch involved in this application is Figure 1 The first driving switch M1 in.

[0074] The second driving switch involved in this application is Figure 1 The second driving switch M2 in.

[0075] The brushed DC motor body involved in this application is Figure 1 The brushed DC motor body Mm in.

[0076] like Figure 4A As shown, the method includes:

[0077] S401: The brushed DC motor system generates a first current signal based on a DAC signal of a first adjustment cycle, and sends the first current signal to a drive switch to switch a state of the drive switch.

[0078] Specifically, the digital-to-analog conversion circuit generates a first current signal based on a DAC signal of a first adjustment period.

[0079] The driving switch may be a first driving switch or a second driving switch. Accordingly, as described above, the DAC signal may be a first DAC signal or a second DAC signal, and the first current signal may be a first sub-current signal or a second sub-current signal.

[0080] Wherein, when the first current signal is used to switch the driving switch from the off state to the on state, the first adjustment period may be a pre-charging stage in any PWM period of the brushed DC motor system. When the first current signal is used to switch the driving switch from the on state to the off state, the first adjustment period may be a pre-discharging stage in any PWM period.

[0081] The first adjustment cycle includes multiple clock cycles.

[0082] The DAC signal is used to indicate the number of unit charges input to the drive switch in multiple clock cycles included in the first adjustment cycle, and the first clock cycle in which the input unit charge needs to be increased in the multiple clock cycles.

[0083] The DAC signal represents a series of coding sequences obtained after encoding the total charge input to the driving switch; wherein the coding sequence consists of a first part and a second part; wherein the first part of the coding sequence indicates the number of unit charge input to the driving switch in multiple clock cycles, and the second part of the coding sequence indicates the first clock cycle in the multiple clock cycles where the input unit charge needs to be increased. wherein the number of unit charge corresponding to each clock cycle is the same.

[0084] The coding sequence may be a binary coding sequence, which is composed of a plurality of "0" and "1" bits.

[0085] The number of bits in the second part of the coding sequence is related to the time length of the first adjustment cycle and the time length of the clock cycle; specifically, the maximum value that can be represented by the number of bits in the second part of the coding sequence = the time length of the first adjustment cycle / the time length of the clock cycle. The maximum value that can be represented by the number of bits in the second part of the coding sequence is the number of multiple clock cycles.

[0086] For example, the first adjustment period is 1us, the clock period is 62.5ns, then the number of multiple clock periods is 1us / 62.5ns=16, and the number of bits in the second part is log2 16 =4.

[0087] The number of bits in the first part of the coding sequence is related to the input bit width of the digital-to-analog conversion circuit. The maximum coding value corresponding to the first part of the coding sequence can represent the maximum input current of the driving switch. The maximum input current and the maximum coding value of the first part represent the current resolution.

[0088] For example, the input bit width of the digital-to-analog conversion circuit is 5 bits, and the maximum input current that can be represented is 100 mA; the current resolution is: 100 mA / (25)≈3 mA. The unit charge is: the charge input to the drive switch with a current of 3 mA in one clock cycle.

[0089] Exemplarily, as described above, the coding sequence includes 9 bits, the number of bits in the first part is 5, and the number of bits in the second part is 4; wherein the first 5 bits are used to represent the number of unit charges input to the drive switch in multiple clock cycles, and the last 4 bits represent the first clock cycle in which the input unit charge needs to be increased.

[0090] The following takes the coding sequence 000110101 as an example to illustrate how the coding sequence corresponding to the DAC signal indicates the number of unit charges and the first clock cycle.

[0091] Figure 4B A schematic diagram of the total charge amount of each clock cycle corresponding to the coding sequence 000110101 provided in the embodiment of the present application; Figure 4B As shown, the horizontal axis represents time and the vertical axis represents current. The unit charge is T CLK *I LSB , where T CLK For one clock cycle, I LSB is the unit current.

[0092] Among them, the encoding value corresponding to the first 5 bits 00011 is 3; this indicates that the number of unit charges input to the drive switch in 16 clock cycles is 3, that is, the basic charge input to the drive switch in each clock cycle is: 3*unit charge.

[0093] The encoding value corresponding to the last 4 bits 0101 is 5, indicating that the number of first clock cycles in multiple clock cycles is 5. Specifically, the first clock cycle to the fifth clock cycle in the first adjustment cycle are determined as the first clock cycle.

[0094] The code value of the code sequence is the decimal value corresponding to the code sequence. The code value of the code sequence can represent the sum of the total charge corresponding to multiple clock cycles. The larger the code value of the code sequence, the larger the sum of the total charge.

[0095] As described above, the digital-to-analog conversion circuit can generate the first current signal in the following manner: the digital-to-analog conversion circuit determines the total amount of charge input to the drive switch in each clock cycle within the first adjustment cycle based on the DAC signal; the digital-to-analog conversion circuit generates the first current signal based on the total amount of charge corresponding to the multiple clock cycles.

[0096] The total charge corresponding to the first clock cycle is the sum of the basic charge and the unit charge; the basic charge is the product of the number of unit charges and the unit charge. For each second clock cycle different from the first clock cycle in the first adjustment cycle, the total charge of the second clock cycle is the basic charge.

[0097] S402: The brushed DC motor system obtains a target DAC signal based on a state switching delay of a driving switch in a first adjustment period and a preset condition. The target DAC signal is a DAC signal in the first adjustment period or an adjusted DAC signal.

[0098] In some embodiments, the brushed DC motor system determines whether to adjust the DAC signal based on a state switching delay of the drive switch in a first adjustment cycle.

[0099] If the brushed DC motor system determines to adjust the DAC signal, the target DAC signal is the adjusted DAC signal.

[0100] If the brushed DC motor system determines not to adjust the current signal, the target DAC signal is the DAC signal of the first adjustment cycle.

[0101] When the brushed DC motor system determines to adjust the current signal, the brushed DC motor system determines a manner of adjusting the DAC signal based on a preset condition.

[0102] S403: The brushed DC motor system generates a target current signal based on the target DAC signal in the second regulation period, and sends the target current signal to the drive switch to switch the state of the drive switch.

[0103] Wherein, the second adjustment cycle is the cycle after the DAC signal is adjusted. In the second adjustment cycle and at least one adjustment cycle after the second adjustment cycle, the absolute value of the difference between the state switching delay of the drive switch and the preset delay is less than or equal to the second preset threshold value, so as to reduce the state switching loss of the drive switch. Wherein, the preset delay is the state switching delay corresponding to the drive switch when the state switching loss is minimized. The preset delay can also be called the ideal switching delay. The second preset threshold value is the maximum difference between the allowable state switching delay and the preset delay.

[0104] The way in which the brushed DC motor system generates the target current signal based on the target DAC signal in the second adjustment period is the same as the way in which the brushed DC motor system generates the first current signal in the first adjustment period, which will not be elaborated here.

[0105] The present application provides an input current regulation method for a driving switch, wherein a DAC signal indicates the number of unit charges respectively input to the driving switch in a plurality of clock cycles, and the first clock cycle in which the input unit charge needs to be increased in a plurality of clock cycles; when the present application adjusts the first current signal so that the switching delay of the driving switch meets the requirements, by adjusting the DAC signal once, on the one hand, it is possible to adjust the basic charge (number*unit charge) that needs to be input to the driving switch in a plurality of clock cycles, thereby achieving coarse-grained regulation of the first current signal; on the other hand, it is also possible to increase the unit charge in the first clock cycle in a plurality of clock cycles, thereby achieving fine-grained regulation of the first current signal; that is, the present application achieves coarse-grained and fine-grained regulation of the first current signal by adjusting the DAC signal once, thereby reducing the regulation resource overhead of the input current of the driving switch.

[0106] As described above, the brushed DC motor system determines whether to adjust the DAC signal based on the state switching delay of the driving switch in the first adjustment cycle.

[0107] Specifically, if the absolute value of the delay difference between the switching state switching delay corresponding to the DAC signal of the first adjustment period and the preset delay is less than or equal to the second preset threshold, the brushed DC motor system does not adjust the DAC signal.

[0108] If the absolute value of the delay difference between the switching state switching delay corresponding to the DAC signal of the first adjustment period and the preset delay is greater than the second preset threshold, the brushed DC motor system adjusts the DAC signal.

[0109] When the absolute value of the delay difference is greater than the second preset threshold, the DAC signal of the first adjustment period meets the preset condition.

[0110] The preset conditions include a first condition and a second condition.

[0111] The first condition is that the state switching delay of the driving switch is greater than the preset delay, and the absolute value of the delay difference between the state switching delay and the preset delay is greater than or equal to a first preset threshold, wherein the first preset threshold is greater than the second preset threshold.

[0112] In some embodiments, when the brushed DC motor system is initially started, the first current signal is small and the state switching delay is large, thus satisfying the first condition.

[0113] The second condition is that the state switching delay of the driving switch is less than the preset delay, and the delay difference between the state switching delay and the preset delay is greater than the second preset threshold and less than the first preset threshold.

[0114] In some embodiments, after the brushed DC motor system has been running stably for a period of time when the delay difference is less than the second preset threshold, the state switching delay is reduced under the influence of the external environment. However, the reduction is small. At this time, the state switching delay of the drive switch meets the second condition.

[0115] The brushed DC motor system adjusts the DAC signal in different ways depending on the preset conditions.

[0116] Next, through Figure 5 The manner in which the brushed DC motor system adjusts the DAC signal is exemplified when the state switching delay of the first adjustment period meets the first condition or the second condition.

[0117] Figure 5 This is a flowchart of the implementation of the input current regulation method of the drive switch provided in the embodiment of the present application. Figure 5As shown, the method includes S501 to S505; wherein S503 describes the way in which the brushed DC motor adjusts the DAC signal when the state switching delay meets the first condition; S504 describes the way in which the brushed DC motor adjusts the DAC signal when the state switching delay meets the second condition.

[0118] S501: The brushed DC motor system generates a first current signal based on a DAC signal of a first adjustment cycle, and sends the first current signal to a drive switch to switch a state of the drive switch.

[0119] Among them, the relevant explanation of S501 is the same as that of S401 and will not be repeated here.

[0120] S502: The brushed DC motor system determines whether the state switching delay of the first adjustment cycle satisfies a first condition or a second condition; if the first condition is satisfied, execute S503; if the second condition is satisfied, execute S504.

[0121] As described above, the first condition is that the state switching delay of the driving switch is greater than the preset delay, and the absolute value of the delay difference is greater than or equal to the first preset threshold.

[0122] In this case, the state switching delay is much longer than the ideal switching delay of the driving switch.

[0123] The second condition is that the state switching delay of the driving switch is less than the preset delay, and the delay difference is greater than the second preset threshold and less than the first preset threshold.

[0124] In this case, the difference between the state switching delay and the ideal switching delay is small.

[0125] S503: The brushed DC motor system adjusts the DAC signal according to the first mapping relationship until the absolute value of the delay difference is less than or equal to the second preset threshold, thereby obtaining a target DAC signal.

[0126] The first mapping relationship includes a plurality of corresponding relationships between the number of adjustment times and the adjustment step length, and the number of adjustment times is negatively correlated with the adjustment step length.

[0127] In some embodiments, the DAC signal may be adjusted by a digital control logic circuit. Adjusting the DAC signal means adjusting the code value of the code sequence corresponding to the DAC signal.

[0128] The code value of the DAC signal represents the sum of the total charge corresponding to each clock cycle; the code value is positively correlated with the sum of the total charge, and the sum of the total charge is negatively correlated with the state switching delay.

[0129] Specifically, the larger the coding value and the larger the sum of the total charge, the smaller the first delay; the smaller the coding value and the smaller the sum of the total charge, the larger the first delay.

[0130] The adjustment step length is the adjustment amount of the code value corresponding to the code sequence. In the first mapping relationship, the adjustment step length is negatively correlated with the number of adjustments.

[0131] S504: The brushed DC motor system adjusts the DAC signal according to the first mapping relationship and the second mapping relationship until the absolute value of the delay difference is less than or equal to the second preset threshold, thereby obtaining the target DAC signal.

[0132] The second mapping relationship includes a plurality of corresponding relationships between adjustment times and adjustment steps, and the plurality of adjustment times of the first mapping relationship and the second mapping relationship are the same.

[0133] In the second mapping relationship, the number of adjustments is positively correlated with the adjustment step length.

[0134] In some embodiments, the DAC signal is adjusted under the second condition, specifically, it can be adjusted based on the second mapping relationship first, and then based on the first mapping relationship.

[0135] S505 : The brushed DC motor system generates a target current signal based on the target DAC signal in the second regulation period, and sends the target current signal to the drive switch to switch the state of the drive switch.

[0136] The relevant description of S505 is the same as that of S403 and is not repeated here.

[0137] In this embodiment, the brushed DC motor system adjusts the DAC signal in different ways according to different preset conditions satisfied by the state switching delay of the driving switch.

[0138] Specifically, when the state switching delay of the first adjustment cycle is much greater than the preset delay, the brushed DC motor system adjusts the DAC signal based on the first mapping relationship, adjusts the DAC signal in the order of adjustment steps from large to small, and adjusts the granularity from coarse to fine to adjust the first current signal input to the drive switch, thereby reducing the state switching delay. While making the state switching delay quickly approach the preset delay, the fine adjustment of the first current signal is improved.

[0139] When the state switching delay of the first adjustment cycle is not much different from the preset delay, the brushed DC motor system first adjusts the DAC signal based on the second mapping relationship, and adjusts the DAC signal in order from small to large adjustment steps, so as to avoid the state switching delay being adjusted too large, and then adjusts the DAC signal based on the first mapping relationship, so that the state switching delay quickly approaches the preset delay.

[0140] Next, through Figure 6 The embodiment specifically describes the specific process of the brushed DC motor system using the first method to adjust the DAC signal. Figure 8The embodiment specifically describes the specific process of adjusting the DAC signal in the brushed DC motor system using the second method.

[0141] Figure 6 The implementation flow chart of the input current regulation method of the driving switch provided in the embodiment of the present application is as follows: Figure 6 As shown in S503, the brushless DC motor system uses the first method to adjust the DAC signal through S5031 to S5034:

[0142] S5031. The brushed DC motor system determines a current adjustment number, and determines a first step length corresponding to a current DAC signal according to the current adjustment number and a first mapping relationship.

[0143] In the first mapping relationship, the greater the number of adjustments, the smaller the adjustment step. In the first mapping relationship, the number of adjustments increases by 1, and the adjustment step decreases by half.

[0144] S5032: The brushed DC motor system generates an updated DAC signal according to the encoding value of the current DAC signal and the result of the first step of addition, and updates the current adjustment times.

[0145] Update the current adjustment number, specifically, increase the adjustment number by 1.

[0146] Exemplarily, the coding sequence corresponding to the current DAC signal is 000110101 (corresponding to a coding value of 53), the current adjustment number is the first time, and the first step length is 256. After the DAC signal is updated based on the first step length, the coding sequence corresponding to the updated DAC signal is 100110101 (corresponding to a coding value of 309).

[0147] In the next adjustment, the first step length is 128. After the DAC signal is updated again based on the first step length, the coding sequence corresponding to the DAC signal is 110110101 (the corresponding coding value is 437).

[0148] As the DAC signal code value increases, the first current signal increases, and the increase amplitude of the first current signal is reduced by half.

[0149] S5033. The brushed DC motor system determines whether the absolute value of the delay difference corresponding to the current DAC signal is less than or equal to the second preset threshold; if so, execute S5034 to determine the current DAC signal as the target DAC signal; otherwise, return to S5031.

[0150] Specifically, the digital control logic circuit inputs the current DAC signal to the digital-to-analog conversion circuit, so that the digital-to-analog conversion circuit controls the switching of the driving switch state according to the current DAC signal.

[0151] In some embodiments, the brushed DC motor system is further provided with a detection module to detect the state switching delay corresponding to the current DAC signal. Then the brushed DC motor system determines whether the absolute value of the delay difference corresponding to the current DAC signal is less than or equal to the second preset threshold.

[0152] If the absolute value of the delay difference corresponding to the current DAC signal is less than or equal to the second preset threshold, it means that the adjustment is completed. The DAC signal of the current adjustment period is the target DAC signal, and the current adjustment period is the second adjustment period.

[0153] If the absolute value of the delay difference corresponding to the current DAC signal is greater than the second preset threshold, S5031 to S5033 are executed to continue increasing the first current signal to reduce the state switching delay.

[0154] In this embodiment, when adjusting the first current signal, the number of adjustments is increased by 1 and the adjustment step is reduced by half. The first current signal can be controlled more accurately while the step is reduced quickly. This avoids the situation where the adjusted first current signal is too large or the target current signal cannot be accurately reached due to the step being too large.

[0155] To better understand the adjustment process, Figure 7 Example Figure 6 adjustment process. Figure 7 Schematic diagram of the adjustment process of the first current signal provided in the embodiment of the present application. Figure 7 As shown, the point coordinate IPCHG on the curve represents the sum of the total charge corresponding to the target current signal, and TDON is the preset delay. IPCHGINIT is the sum of the total charge corresponding to the first current signal during the first adjustment in the first adjustment cycle. Among them, the first adjustment cycle is the first adjustment cycle.

[0156] In the first adjustment cycle, it is detected that the state switching delay TDON_EFF0 is greater than TDON, the first step length is determined to be Step, and the DAC signal is increased based on Step to increase the first current signal. Figure 7 Where IPCHG1 is the sum of the total charge amounts corresponding to the first current signal after the first current signal is increased based on Step.

[0157] In the second adjustment cycle, it is detected that the state switching delay TDON_EFF1 is greater than TDON, and the first step length is determined to be Step / 2. The DAC signal is increased based on Step / 2 to increase the first current signal. IPCHG2 is the sum of the total charge corresponding to the first current signal after the first current signal is increased based on Step / 2.

[0158] In the third adjustment cycle, it is detected that the state switching delay TDON_EFF2 is greater than TDON, and the first step length is determined to be Step / 4. The DAC signal is increased based on Step / 4 to increase the first current signal. After IPCHG3 increases the first current signal based on Step / 4, the sum of the total charge corresponding to the first current signal.

[0159] The DAC signal and the first current signal are updated and the state switching delay is detected in the above manner until the absolute value of the delay difference is less than the second preset threshold.

[0160] Figure 8 The implementation flow chart of the input current regulation method of the driving switch provided in the embodiment of the present application is as follows: Figure 8 As shown in S504, the brushless DC motor system uses the second method to adjust the DAC signal through S5041 to S5045:

[0161] S5041. The brushed DC motor system determines a current adjustment number, and determines a second step length corresponding to a current DAC signal according to the current adjustment number and a second mapping relationship.

[0162] In the second mapping relationship, the number of adjustments increases by 1, and the adjustment step length doubles.

[0163] S5042: The brushed DC motor system generates an updated DAC signal according to the result of subtracting the encoding value of the DAC signal from the second step length, and updates the current adjustment times.

[0164] Exemplarily, the coding sequence corresponding to the current DAC signal is 111111011 (corresponding to a coding value of 507), the current adjustment number is the first time, and the second step length is 1. After the DAC signal is updated based on the first step length, the coding sequence corresponding to the updated DAC signal is 111111010 (corresponding to a coding value of 506).

[0165] In the next adjustment, the second step length is 2. After the DAC signal is updated again based on the first step length, the coding sequence corresponding to the DAC signal is 111111000 (the corresponding coding value is 504).

[0166] As the code value of the DAC signal increases, the first current signal decreases exponentially.

[0167] Updating the adjustment times means adding 1 to the adjustment times.

[0168] S5043. The brushed DC motor system determines whether the state switching delay corresponding to the current DAC signal satisfies the third condition or the fourth condition; if the fourth condition is met, execute S5044 to obtain the target DAC signal; if the third condition is met, obtain the intermediate DAC signal and execute S5045.

[0169] The third condition is that the current state switching delay of the driving switch is greater than the preset delay and the absolute value of the delay difference is greater than the second preset threshold.

[0170] If the third condition is met, it means that the magnitude relationship between the state switching delay of the current driving switch and the preset delay has changed. At this time, if the coding value of the middle DAC continues to be reduced, the gap between the state switching delay of the subsequent driving switch and the preset delay becomes larger and larger. At this time, the coding value of the middle DAC should be gradually increased through S5045.

[0171] The fourth condition is: the absolute value of the delay difference is less than or equal to the second preset threshold. The fourth condition includes two cases, namely, case 1: the state switching delay of the current driving switch is greater than the preset delay, and the absolute value of the delay difference is less than or equal to the second preset threshold; case 2: the state switching delay of the current driving switch is less than or equal to the preset delay, and the absolute value of the delay difference is less than or equal to the second preset threshold.

[0172] If any of the fourth conditions is met, it means that the current state switching delay of the driving switch is close to the ideal switching delay. The current DAC signal can be determined as the target DAC signal.

[0173] S5045. The brushed DC motor system increases the encoding value of the intermediate DAC signal based on the second step length used last time and the first mapping relationship until the absolute value of the delay difference is less than or equal to the second preset threshold, thereby obtaining a target DAC signal.

[0174] Based on the first mapping relationship, the brushed DC motor system can increase the intermediate DAC signal encoding value in the following manner: the brushed DC motor system searches for the target adjustment number corresponding to the second step length from the first mapping relationship based on the second step length used last time, and re-updates the current adjustment number to the next adjustment number of the target adjustment number.

[0175] Next, the brushed DC motor uses the same adjustment method as S5031 to S5034 to increase the coding value of the intermediate DAC signal in the order of adjustment steps from large to small to increase the first current signal until the absolute value of the delay difference is less than or equal to the second preset threshold.

[0176] In order to more clearly understand the solution of the present application, the process of adjusting the DAC signal based on the second mapping relationship and the first mapping relationship is described below by example.

[0177] Exemplarily, the adjustment times of the first mapping relationship include 1, 2, 3, ..., 8; the corresponding adjustment step sizes are: 128, 64, 32, 16, 8, 4, 2, 1, respectively.

[0178] The adjustment times of the second mapping relationship include 1, 2, 3, ..., 8; the corresponding adjustment steps are 1, 2, 4, ..., 128 respectively.

[0179] The brushed DC motor system first reduces the DAC signal of the first adjustment cycle in the order of the second step length of 1, 2, 3, ..., 128. Assume that the second step length is 32 when the intermediate DAC signal is obtained.

[0180] In the first mapping relationship, the target adjustment number corresponding to the second step size 32 is 5. Therefore, the brushed DC motor system updates the current adjustment number to 4. In the first mapping relationship, the adjustment step size corresponding to 4 is 16. Based on the first mapping relationship, the brushed DC motor system increases the intermediate DAC signal in the order of step sizes 16, 8, 4, 2, and 1 to increase the first current signal until the absolute value of the delay difference is less than or equal to the second preset threshold.

[0181] In this embodiment, if the state switching delay of the first adjustment cycle is less than the ideal switching delay, and the delay difference is small, the brushed DC motor can first roughly adjust the state switching delay to be greater than the ideal switching delay in the order of adjusting the step size from small to large; then, based on the current adjustment step size, the state switching delay is finely adjusted again in the order of step size from large to small, so that the state switching delay of the drive switch can quickly and accurately converge to the preset delay.

[0182] The adjustment of the DAC signal step size in the present application can be specifically implemented by a state machine in a digital control logic circuit. In the present application, the state of the state machine includes an idle (IDLE) state, a step size reduction (STEP_DOWN) state, a step size increase (STEP_UP) state, and a locked (LOCK) state.

[0183] Fig. 9 The schematic diagram of the state machine step size adjustment provided in the embodiment of the present application is as follows: Fig. 9 The four states of the state machine are described below:

[0184] IDLE: When the drive switch input current regulation function is not enabled, the state machine is in the IDLE state.

[0185] STEP_DOWN (adjustment step size is reduced by half): When the input current regulation function of the drive switch is started (corresponding to S5031 to S5033), or when the current switching delay increases from the STEP_UP state so that the size relationship between the current switching delay and the preset delay changes, it will jump to the STEP_DOWN state and gradually reduce the step size according to the binary method (corresponding to S5044) until the delay difference is reached or the step size is reduced to 0.

[0186] STEP_UP (adjustment step size doubled): When the state switching delay changes when the system is in the LOCK state, it needs to be readjusted. At this time, it will jump to the STEP_UP state and gradually increase the step size until the relationship between the state switching delay and the preset delay changes, and the stop step size will be increased (corresponding to S5041 to S5043).

[0187] LOCK (adjustment completed, state delay is near the preset delay): When the absolute value of the delay difference is smaller than the second preset threshold value, or the step size is reduced to 0, the binary search is considered to be completed, so the DAC signal is locked. Unless the absolute value of the delay difference is greater than the second preset threshold value, it is necessary to re-enter STEP_UP for adjustment again.

[0188] Based on the above embodiments, the present application provides a motor drive circuit. The structure of the motor drive circuit 101 is as follows: Figure 1 As shown. It includes: a digital control logic circuit 20, a digital-to-analog conversion circuit 21 and a half-bridge circuit 103; wherein the output end of the digital control logic circuit 20 is connected to the input end of the digital-to-analog conversion circuit 21, and the two output ends of the digital-to-analog conversion circuit 21 are correspondingly connected to the control ends of the two driving switches on the half-bridge circuit 103.

[0189] For any driving switch, the digital control logic circuit 20 is used to generate a digital-to-analog converter DAC signal of a first adjustment cycle.

[0190] The digital-to-analog conversion circuit 21 is used to generate a first current signal based on a DAC signal, and send the first current signal to a driving switch to switch the state of the driving switch; wherein the DAC signal is used to indicate the number of unit charges input to the driving switch in a plurality of clock cycles included in a first adjustment cycle, and the first clock cycle in which a plurality of clock cycles are required to increase the input unit charge.

[0191] The digital control logic circuit 20 is also used to obtain the target DAC signal based on the state switching delay of the driving switch in the first adjustment cycle and the preset conditions, and send the target DAC signal to the digital-to-analog conversion circuit 21; the target DAC signal is the DAC signal of the first adjustment cycle or the adjusted DAC signal.

[0192] The digital-to-analog conversion circuit 21 is also used to generate a target current signal based on the target DAC signal in the second adjustment cycle, and send the target current signal to the drive switch to switch the state of the drive switch; in the second adjustment cycle and at least one adjustment cycle after the second adjustment cycle, the absolute value of the delay difference between the state switching delay of the drive switch and the preset delay is less than a preset threshold.

[0193] In the motor drive circuit 101 provided in the present application, the DAC signal indicates the number of unit charges input to the drive switch in multiple clock cycles, and the first clock cycle in which the input unit charge needs to be increased in multiple clock cycles; when the brushed DC motor system adjusts the first current signal to make the switching delay of the drive switch meet the requirements, by adjusting the DAC signal once, on the one hand, it is possible to adjust the basic charge (number * unit charge) that needs to be input to the drive switch in multiple clock cycles, thereby achieving coarse-grained adjustment of the first current signal; on the other hand, it is also possible to increase the unit charge in the first clock cycle in multiple clock cycles, thereby achieving fine-grained adjustment of the first current signal; that is, the present application can achieve coarse-grained and fine-grained adjustment of the first current signal by adjusting the DAC signal once, thereby reducing the adjustment resource overhead of the input current of the drive switch.

[0194] The present application provides a motor driving chip including: a motor driving circuit 101 .

[0195] The present application provides a brushed DC motor system, including: a brushed DC motor body Mm and a motor drive circuit 101, wherein the output end of the motor drive circuit is connected to the drive end of the brushed DC motor body Mm; the motor drive circuit 101 is used to provide a pulse voltage signal to the brushed DC motor body Mm to drive the brushed DC motor body Mm to work.

[0196] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for adjusting input current of a driving switch, characterized in that: include: A first current signal is generated based on a digital-to-analog converter DAC signal of a first adjustment cycle, and the first current signal is sent to a drive switch to switch the state of the drive switch; wherein the DAC signal is used to indicate the number of unit charges input to the drive switch in a plurality of clock cycles included in the first adjustment cycle, and the first clock cycle in the plurality of clock cycles in which the input unit charge needs to be increased; A target DAC signal is obtained based on the state switching delay of the driving switch in the first adjustment period and a preset condition; the target DAC signal is the DAC signal of the first adjustment period or the adjusted DAC signal; In a second adjustment cycle, a target current signal is generated based on the target DAC signal, and the target current signal is sent to the drive switch to switch the state of the drive switch; in the second adjustment cycle and at least one adjustment cycle after the second adjustment cycle, the absolute value of the delay difference between the state switching delay of the drive switch and the preset delay is less than the preset threshold.

2. The method according to claim 1, characterized in that The generating of the first current signal based on the DAC signal of the first adjustment cycle comprises: Based on the DAC signal, determine the total charge amount input to the driving switch in each clock cycle within the first adjustment cycle; wherein the total charge amount corresponding to the first clock cycle is the sum of the basic charge amount and the unit charge amount; the basic charge amount is the product of the number of unit charges and the unit charge amount; for each second clock cycle different from the first clock cycle within the first adjustment cycle, the total charge amount of the second clock cycle is the basic charge amount; The first current signal is generated based on total charge amounts corresponding to the multiple clock cycles respectively.

3. The method according to claim 1, characterized in that The preset condition includes a first condition and a second condition; the target DAC signal is obtained based on the state switching delay of the driving switch in the first adjustment cycle and the preset condition, including: If the state switching delay of the driving switch in the first adjustment period meets the first condition, the DAC signal is adjusted; the first condition is that the state switching delay of the driving switch is greater than the preset delay, and the absolute value of the delay difference between the state switching delay and the preset delay is greater than or equal to a first preset threshold; If the state switching delay of the driving switch in the first adjustment period meets the second condition, the DAC signal is adjusted; the second condition is that the state switching delay of the driving switch is less than the preset delay, and the absolute value of the delay difference between the state switching delay and the preset delay is greater than the second preset threshold and less than or equal to the first preset threshold; wherein the first preset threshold is greater than the second preset threshold.

4. The method according to claim 3, characterized in that When the state switching delay of the driving switch in the first adjustment period satisfies the first condition, adjusting the DAC signal comprises: The DAC signal is adjusted according to a first mapping relationship until the absolute value of the delay difference is less than or equal to the second preset threshold; wherein the first mapping relationship includes a plurality of sets of corresponding relationships between adjustment times and adjustment steps, and the adjustment times are negatively correlated with the adjustment step.

5. The method according to claim 4, characterized in that The step of adjusting the DAC signal according to the first mapping relationship until the absolute value of the delay difference is less than or equal to the second preset threshold value to obtain a target DAC signal includes: Determine a current adjustment number, and determine a first step length corresponding to a current DAC signal according to the current adjustment number and a first mapping relationship; Generate an updated DAC signal according to the result of adding the encoding value of the current DAC signal to the first step, and update the current adjustment number; The process is repeated until the absolute value of the delay difference is less than or equal to the second preset threshold, thereby obtaining the target DAC signal.

6. The method according to claim 3, characterized in that When the state switching delay of the driving switch in the first adjustment period satisfies the second condition, adjusting the DAC signal comprises: According to the first mapping relationship and the second mapping relationship, the DAC signal is adjusted until the absolute value of the delay difference is less than or equal to the second preset threshold value, so as to obtain the target DAC signal; wherein, the first mapping relationship and the second mapping relationship respectively include a plurality of sets of corresponding relationships between the number of adjustments and the adjustment step length; in the first mapping relationship, the number of adjustments is negatively correlated with the adjustment step length; in the second mapping relationship, the number of adjustments is positively correlated with the adjustment step length.

7. The method according to claim 6, characterized in that The step of adjusting the DAC signal according to the first mapping relationship and the second mapping relationship until the absolute value of the delay difference is less than or equal to the second preset threshold value to obtain the target DAC signal includes: Determine a current adjustment number, and determine a second step length corresponding to the current DAC signal according to the current adjustment number and the second mapping relationship; Generate an updated DAC signal according to a result of subtracting the encoding value of the current DAC signal from the second step length, and update the current adjustment times; Repeat the process until the state switching delay of the driving switch is greater than the preset delay and the absolute value of the delay difference is greater than the second preset threshold, thereby obtaining an intermediate DAC signal; According to the second step length used last time and the first mapping relationship, increase the encoding value of the intermediate DAC signal until the absolute value of the delay difference is less than the preset threshold value, so as to obtain the target DAC signal; Alternatively, the target DAC signal is obtained until the absolute value of the delay difference is less than or equal to the second preset threshold.

8. The method according to any one of claims 4 to 7, characterized in that: In the first mapping relationship, the adjustment times are increased by 1 and the adjustment step is reduced by half.

9. The method according to claim 6 or 7, characterized in that: In the second mapping relationship, the adjustment times are reduced or increased by 1, and the adjustment step is doubled.

10. A motor drive circuit, characterized in that: include: A digital control logic circuit, a digital-to-analog conversion circuit and a half-bridge circuit; wherein the output end of the digital control logic circuit is connected to the input end of the digital-to-analog conversion circuit, and the two output ends of the digital-to-analog conversion circuit are correspondingly connected to the control ends of the two drive switches on the half-bridge circuit; For any of the driving switches, the digital control logic circuit is used to generate a digital-to-analog converter DAC signal of a first adjustment cycle; The digital-to-analog conversion circuit is used to generate a first current signal based on the DAC signal, and send the first current signal to the drive switch to switch the state of the drive switch; wherein the DAC signal is used to indicate the number of unit charges input to the drive switch in a plurality of clock cycles included in the first adjustment cycle, and the first clock cycle in which the input unit charge needs to be increased in the plurality of clock cycles; The digital control logic circuit is further used to obtain a target DAC signal based on the state switching delay of the driving switch in the first adjustment period and a preset condition, and send the target DAC signal to the digital-to-analog conversion circuit; the target DAC signal is the DAC signal of the first adjustment period or the adjusted DAC signal; The digital-to-analog conversion circuit is also used to generate a target current signal based on the target DAC signal in a second adjustment cycle, and send the target current signal to the drive switch to switch the state of the drive switch; in the second adjustment cycle and at least one adjustment cycle after the second adjustment cycle, the absolute value of the delay difference between the state switching delay of the drive switch and the preset delay is less than the preset threshold.

11. A motor driver chip, characterized in that: include: The motor drive circuit according to claim 10.

12. A brushed DC motor system, characterized in that: include: A brushed DC motor body and the motor drive circuit according to claim 10, wherein the output end of the motor drive circuit is connected to the drive end of the brushed DC motor body; The motor driving circuit is used to provide a pulse voltage signal to the brushed DC motor body to drive the brushed DC motor body to operate.

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