High-efficiency high-transformation-ratio non-isolated hybrid step-down conversion circuit

Abstract

The invention relates to a high-efficiency high-transformation-ratio non-isolated hybrid voltage-reduction conversion circuit. The circuit comprises an input filtering unit, an auxiliary power supply unit, a voltage definite-proportion conversion unit, an intermediate filtering unit, a power conversion unit, an energy storage inductor, an output filtering unit, an output sampling unit, a feedback compensation unit and a PWM control unit. According to the invention, the problems of low duty ratio, short conduction time and unstable operation of the single-stage BUCK under the condition of high transformation ratio are solved, and through front-stage open-loop voltage reduction, the duty ratio of the rear-stage BUCK is improved, the conduction time is increased, and the circuit efficiency is improved. According to the invention, the circuit is mainly designed based on the actual application requirements of a user, the bus voltage can be directly converted into the input voltage of a low-voltage controller, and large-current output can be realized in a small-size package.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply and power drive, and in particular to a high-efficiency and high-transformation-ratio non-isolated hybrid buck conversion circuit. Background Art

[0002] With the improvement of information integration and intelligence in my country, the requirements of the whole system for the power supply system are getting higher and higher. At the same time, the application of digital chips such as widely used high-computing power FPGA has made the system's requirements for low-voltage and high-current output DC / DC regulated power supplies higher and higher. Low operating voltage can reduce the internal power loss of integrated chips, and high current output can meet the power requirements of high-computing power digital chips and improve system performance. However, the increasing chip functions and integration require the power supply to provide more and more current.

[0003] In the traditional power supply architecture, the low-voltage and high-current power supply requirements of controllers such as FPGAs and DSPs usually use a combined power supply architecture of secondary power supply + tertiary power supply. The two-stage architecture requires two power converters, and the efficiency of the power supply system will decrease with each conversion. At the same time, the size of the power supply system will be larger and the price will be higher. The existing power supply architecture can no longer meet the needs of system performance improvement and miniaturization. Therefore, it is urgent to realize a low-voltage output power supply solution with better performance. Summary of the invention

[0004] In order to solve the deficiencies in the prior art, an object of the present invention is to provide a high-efficiency, high-transformation-ratio, non-isolated hybrid buck converter circuit.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A high-efficiency, high-ratio non-isolated hybrid step-down conversion circuit comprises: an input filter unit, a voltage ratio conversion unit, an intermediate filter unit, a power conversion unit, an energy storage inductor, an output filter unit, an auxiliary power supply unit, a PWM control unit, an output sampling unit and a feedback compensation unit. The output end of the input filter unit is respectively connected to the input end of the voltage ratio conversion unit and the input end of the auxiliary power supply unit; the output end of the auxiliary power supply unit is connected to the input end of the voltage ratio conversion unit; the output end of the voltage ratio conversion unit is respectively connected to the input end of the intermediate filter unit and the input end of the PWM control unit; the output end of the intermediate filter unit is connected to the input end of the power conversion unit, the output end of the power conversion unit is connected to the input end of the energy storage inductor, the output end of the energy storage inductor is connected to the input end of the output filter unit and the input end of the output sampling unit, the output end of the output filter unit is connected to the input end of the output sampling unit, the output end of the output sampling unit is connected to the input end of the PWM control unit, the output end of the PWM control unit is connected to the control end of the power conversion unit, and the PWM control unit is interactively connected to the feedback compensation unit.

[0007] As a further improvement of the above technical solution, the voltage ratio conversion unit includes a voltage conversion module N1, a voltage conversion module N2, a resistor R1, a resistor R2 and a resistor R3.

[0008] The voltage conversion module N1 has an input power supply terminal Vin leading to a circuit input terminal Vin, a power ground GND leading to a circuit ground terminal GND, and an enable terminal EN leading to a circuit disable terminal INH via the resistor R1; the voltage conversion module N1 is connected to the input power supply terminal Vin of the voltage conversion module N2, the voltage conversion module N1 is connected to the power ground GND of the voltage conversion module N2, the voltage conversion module N1 is connected to the output terminal Vo of the voltage conversion module N2, the voltage conversion module N1 is connected to the enable terminal EN of the voltage conversion module N2, the voltage conversion module N1 is connected to the synchronization terminal SYNC of the voltage conversion module N2, and the voltage conversion module N1 is connected to the indication pin PGOOD of the voltage conversion module N2.

[0009] As a further improvement of the above technical solution, the input filter unit includes a capacitor C1; the intermediate filter unit includes a capacitor C2; one end of the capacitor C1 is connected to the input power supply terminal Vin of the voltage conversion module N1, and the other end is connected to GND; one end of the capacitor C2 is connected to the output terminal Vo of the voltage conversion module N1, and the other end is connected to GND; one end of the resistor R2 is connected to the enable terminal EN of the voltage conversion module N1, and the other end is connected to the network VCC; one end of the resistor R3 is connected to the indication pin PGOOD of the voltage conversion module N1, and the other end is connected to the network VCC; the output terminal Vo of the voltage conversion module N1 is connected to the input power supply terminal Vin of the synchronous BUCK chip N3.

[0010] As a further improvement of the above technical solution, the auxiliary power supply unit includes a resistor R19, a voltage regulator D5, a transistor Q9 and a capacitor C18; the PWM control unit includes a synchronous BUCK chip N3, a synchronous BUCK chip N4, a resistor R7, a resistor R10, a capacitor C6, a diode D1, a capacitor C7, a diode D2, a resistor R15, a resistor R17, a capacitor C13, a diode D3, a capacitor C15 and a diode D4.

[0011] The feedback terminal FB of the synchronous buck chip N3 is led out as the circuit adjustment terminal Trim, and the ground terminal GND is led out as the circuit ground terminal GND; the synchronous buck chip N3 is connected to the input power supply terminal Vin of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the ground terminal GND of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the soft start input pin 1TK / SS1 of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the soft start input pin 2TK / SS2 of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the error amplifier compensation pin 1ITH1 of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the error amplifier compensation pin 2ITH2 of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the synchronous buck chip N4 The error feedback input pin 1VFB1 of the UCK chip N4 is connected, the synchronous buck chip N3 is connected to the error feedback input pin 2VFB2 of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the enable control pin 1RUN1 of the synchronous buck chip N4, and the synchronous buck chip N3 is connected to the enable control pin 2RUN2 of the synchronous buck chip N4; the error amplifier compensation pin 1ITH1 of the synchronous buck chip N3 is connected to the error amplifier compensation pin 2ITH2, the soft start input pin 1TK / SS1 of the synchronous buck chip N3 is connected to the soft start input pin 2TK / SS2, the error feedback input pin 1VFB1 of the synchronous buck chip N3 is connected to the error feedback input pin 2VFB2, and the enable control pin 1RUN1 of the synchronous buck chip N3 is connected to the enable control pin 2RUN2.

[0012] The anode of the diode D1 is connected to the internal regulator output pin INTVcc of the synchronous BUCK chip N3; the cathode of the diode D1 is connected to the bootstrap power supply 1BOOST1 of the synchronous BUCK chip N3; the cathode of the diode D2 is connected to the bootstrap power supply 2BOOST2 of the synchronous BUCK chip N3; the anode of the diode D2 is connected to the internal regulator output pin INTVcc of the synchronous BUCK chip N3; the cathode of the diode D3 is connected to the bootstrap power supply 1BOOST1 of the synchronous BUCK chip N4; the anode of the diode D3 is connected to the internal regulator output pin INTVcc of the synchronous BUCK chip N4; the anode of the diode D4 is connected to the internal regulator output pin INTVcc of the synchronous BUCK chip N4; the cathode of the diode D4 is connected to the bootstrap power supply 2BOOST2 of the synchronous BUCK chip N4.

[0013] As a further improvement of the above technical solution, the energy storage inductor unit includes inductor L1, inductor L2, inductor L3 and inductor L4; the output filter unit includes capacitor C9, capacitor C11, capacitor C14 and capacitor C17; the output sampling unit includes resistor R8, resistor R9, capacitor C8, resistor R13, resistor R14, capacitor C12, resistor R5 and resistor R6.

[0014] One end of the resistor R5 is connected to the error feedback input pin 1VFB1 of the synchronous buck chip N3, and the other end is connected to the differential telemetry amplifier output pin DIFFOUT of the synchronous buck chip N3; one end of the resistor R5 is connected to the error feedback input pin 1VFB1 of the synchronous buck chip N3, and the other end is connected to GND.

[0015] The differential telemetry amplifier positive input pin DIFFP of the synchronous BUCK chip N3 is connected to the second end of the inductor L1; the differential telemetry amplifier negative input pin DIFFN of the synchronous BUCK chip N3 is connected to GND; the enable control pin 1RUN1 of the synchronous BUCK chip N3 is connected to the indication pin PGOOD of the voltage conversion module N1.

[0016] One end of the resistor R10 is connected to the indication pin PGOOD of the synchronous buck chip N3 , and the other end is connected to the output pin INTVcc of the internal voltage regulator of the synchronous buck chip N3 .

[0017] The clock output pin CLKOUT of the synchronous buck chip N3 is connected to the mode selection pin MODE / PLLIN of the synchronous buck chip N4; the mode selection pin MODE / PLLIN of the synchronous buck chip N3 is connected to GND; the differential telemetry amplifier positive input pin DIFFP of the synchronous buck chip N4 is connected to GND; and the differential telemetry amplifier negative input pin DIFFN of the synchronous buck chip N4 is connected to GND.

[0018] One end of the resistor R7 is connected to the frequency pin FREQ of the synchronous BUCK chip N3, and the other end is connected to GND.

[0019] One end of the resistor C8 is connected to the second end of the inductor L1, and the other end is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronous buck chip N3; the resistor R9 is connected in parallel with the capacitor C8; one end of the capacitor C9 is connected to the second end of the inductor L1, and the other end is connected to GND; the negative input pin sense1- of the current sensing comparator 1 of the synchronous buck chip N3 is connected to the second end of the inductor L1; the second end of the inductor L1 is connected to the lead-out circuit input terminal Vo.

[0020] One end of the capacitor C10 is connected to the second end of the inductor L1, and the other end is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronous BUCK chip N3; the resistor R11 is connected in parallel with the capacitor C10; one end of the capacitor C11 is connected to the second end of the inductor L1, and the other end is connected to GND; the negative input pin sense2- of the current sensing comparator 2 of the synchronous BUCK chip N3 is connected to the second end of the inductor L2; the second end of the inductor L2 is connected to the lead-out circuit input terminal Vo.

[0021] One end of the resistor R15 is connected to the indication pin PGOOD of the synchronous buck chip N4, and the other end is connected to the internal regulator output pin INTVcc of the synchronous buck chip N4; one end of the resistor R17 is connected to the frequency pin FREQ of the synchronous buck chip N4, and the other end is connected to GND.

[0022] One end of the resistor C12 is connected to the second end of the inductor L3, and the other end is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronous BUCK chip N4; the resistor R14 is connected in parallel with the capacitor C12; one end of the capacitor C14 is connected to the second end of the inductor L3, and the other end is connected to GND; the negative input pin sense2- of the current sensing comparator 2 of the synchronous BUCK chip N4 is connected to the second end of the inductor L3; the second end of the inductor L3 is connected to the lead-out circuit input terminal Vo.

[0023] One end of the resistor C16 is connected to the second end of the inductor L3, and the other end is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronous BUCK chip N4; the resistor R14 is connected in parallel with the capacitor C16; one end of the capacitor C17 is connected to the second end of the inductor L3, and the other end is connected to GND; the negative input pin sense2- of the current sensing comparator 2 of the synchronous BUCK chip N4 is connected to the second end of the inductor L4; the second end of the inductor L4 is connected to the lead-out circuit input terminal Vo.

[0024] One end of the resistor R19 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4, and the other end is connected to the cathode of the voltage regulator D5 and the B pole of the transistor Q9; the anode of the voltage regulator D5 is connected to GND; the C pole of the transistor Q9 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4, and the E pole is connected to the network Vcc; one end of the capacitor C18 is connected to the network Vcc, and the other end is connected to GND.

[0025] As a further improvement of the above technical solution, the power conversion unit includes a MOS tube Q1, a MOS tube Q2, a MOS tube Q3, a MOS tube Q4, a MOS tube Q5, a MOS tube Q6, a MOS tube Q7 and a MOS tube Q8.

[0026] The source of the MOS tube Q1 is connected to the input power supply terminal Vin of the synchronous BUCK chip N3; the gate of the MOS tube Q1 is connected to the high-end gate drive output pin 1TG1 of the synchronous BUCK chip N3; the source of the MOS tube Q1 is connected to the switch node SW1 of the synchronous BUCK chip N3, the first end of the capacitor C6, the drain of the MOS tube Q2, the first end of the inductor L1, and the first end of the resistor R8; the second end of the capacitor C6 is connected to the bootstrap power supply 1BOOST1 of the synchronous BUCK chip N3; the second end of the resistor R8 is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronous BUCK chip N3; the gate of the MOS tube Q2 is connected to the low-end gate drive output pin 1BG1 of the synchronous BUCK chip N3; the source of the MOS tube Q2 is connected to GND.

[0027] The source of the MOS tube Q3 is connected to the input power supply terminal Vin of the synchronous BUCK chip N3; the gate of the MOS tube Q3 is connected to the high-end gate drive output pin 2TG2 of the synchronous BUCK chip N3; the source of the MOS tube Q3 is connected to the switch node SW2 of the synchronous BUCK chip N3, the first end of the capacitor C7, the drain of the MOS tube Q4, the first end of the inductor L2, and the first end of the resistor R12; the second end of the capacitor C7 is connected to the bootstrap power supply 2BOOST2 of the synchronous BUCK chip N3; the second end of the resistor R12 is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronous BUCK chip N3; the gate of the MOS tube Q4 is connected to the low-end gate drive output pin 2BG2 of the synchronous BUCK chip N3; the source of the MOS tube Q4 is connected to GND.

[0028] The source of the MOS tube Q5 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4; the gate of the MOS tube Q5 is connected to the high-end gate drive output pin 1TG1 of the synchronous BUCK chip N4; the source of the MOS tube Q5 is connected to the switch node SW1 of the synchronous BUCK chip N4, the first end of the capacitor C13, the drain of the MOS tube Q6, the first end of the inductor L3, and the first end of the resistor R13; the second end of the capacitor C13 is connected to the bootstrap power supply 1BOOST1 of the synchronous BUCK chip N4; the second end of the resistor R13 is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronous BUCK chip N4; the gate of the MOS tube Q6 is connected to the low-end gate drive output pin 1BG1 of the synchronous BUCK chip N4; the source of the MOS tube Q6 is connected to GND; The source of the MOS tube Q7 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4; the gate of the MOS tube Q7 is connected to the high-end gate drive output pin 2TG2 of the synchronous BUCK chip N4; the source of the MOS tube Q7 is connected to the switch node SW2 of the synchronous BUCK chip N4, the first end of the capacitor C15, the drain of the MOS tube Q8, the first end of the inductor L4, and the first end of the resistor R18; the second end of the capacitor C15 is connected to the bootstrap power supply 2BOOST2 of the synchronous BUCK chip N4; the second end of the resistor R18 is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronous BUCK chip N4; the gate of the MOS tube Q8 is connected to the low-end gate drive output pin 2BG2 of the synchronous BUCK chip N4; the source of the MOS tube Q8 is connected to GND.

[0029] As a further improvement of the above technical solution, the feedback compensation unit includes a capacitor C3, a capacitor C4, a capacitor C5 and a resistor R4.

[0030] One end of the capacitor C3 is connected to the soft start input pin 1TK / SS1 of the synchronous BUCK chip N3, and the other end is connected to GND; one end of the capacitor C4 is connected to GND, and the other end is connected to the second end of the resistor R4; the first end of the resistor R4 is connected to the error amplifier compensation pin 1ITH1 of the voltage conversion module N1; one end of the capacitor C5 is connected to the error amplifier compensation pin 1ITH1 of the synchronous BUCK chip N3, and the other end is connected to GND.

[0031] As a further improvement of the above technical solution, the circuit also includes an adjustable resistor RSET; the two ends of the adjustable resistor RSET are respectively connected to the circuit Trim terminal and the ground terminal GND; different output voltages are determined by adjusting the resistance value of the adjustable resistor RSET to form an adjustment circuit closed loop.

[0032] Compared with the prior art, the advantages of the present invention are:

[0033] (1) The present invention solves the problem of low duty cycle, short conduction time and unstable operation of a single-stage BUCK under high transformation ratio conditions. By reducing the voltage in the front-stage open loop, the duty cycle of the rear-stage BUCK is increased, the conduction time is increased, and the circuit efficiency is improved. The present invention is mainly designed based on the actual application needs of users. The bus voltage can be directly converted into the input voltage of the low-voltage controller, and a large current output can be achieved in a small-size package.

[0034] (2) The main control chips N3 and N4 used in the present invention are the same synchronous BUCK controller, which is typically applied in a step-down circuit and can only achieve stable output and output voltage adjustment functions under low voltage input. The present invention can increase the circuit input voltage range by adding a voltage ratio conversion unit.

[0035] (3) The circuit structure adopted by the present invention is easy to implement circuit expansion, thereby increasing circuit power and improving circuit output current capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a principle block diagram of a high-efficiency, high-ratio non-isolated hybrid buck converter circuit in the present invention;

[0037] Figure 2 It is a circuit schematic diagram of a high-efficiency, high-ratio non-isolated hybrid buck converter circuit in the present invention;

[0038] Figure 3 It is a principle diagram of the adjustment function of the high-efficiency, high-ratio non-isolated hybrid buck conversion circuit in the present invention;

[0039] Figure 4 It is an application diagram of the high-efficiency, high-ratio non-isolated hybrid buck conversion circuit in the present invention.

[0040] in:

[0041] 1. Input filter unit, 2. Voltage ratio conversion unit, 3. Intermediate filter unit, 4. Power conversion unit, 5. Energy storage inductor, 6. Output filter unit, 7. Auxiliary power supply unit, 8. PWM control unit, 9. Output sampling unit, 10. Feedback compensation unit. DETAILED DESCRIPTION

[0042] The present invention will be further described below in conjunction with the accompanying drawings:

[0043] like Figure 1A high-efficiency, high-ratio non-isolated hybrid buck conversion circuit is shown, which includes: an input filter unit 1, a voltage ratio conversion unit 2, a secondary filter unit 3, a power conversion unit 4, an energy storage inductor unit 5, an output filter unit 6, an auxiliary power supply unit 7, a PWM control unit 8, an output sampling unit 9 and a feedback compensation unit 10. The output end of the input filter unit 1 is connected to the input end of the voltage ratio conversion unit 2 and the auxiliary power supply unit 7, the output end of the auxiliary power supply unit 7 is connected to the input end of the voltage ratio conversion unit 2, the output end of the voltage ratio conversion unit 2 is connected to the input end of the intermediate filter unit 3 and the PWM control unit 8, the output end of the intermediate filter unit 3 is connected to the input end of the power conversion unit 4, the output end of the power conversion unit 4 is connected to the input end of the energy storage inductor unit 5, the output end of the energy storage inductor unit 5 is connected to the input end of the output filter unit 6 and the output sampling unit 9, the output end of the output filter unit 6 is connected to the input end of the output sampling unit 9, the output end of the output sampling unit 9 is connected to the input end of the PWM control unit 8, the output end of the PWM control unit 8 is connected to the control end of the power conversion unit 4, and the PWM control unit 8 is connected to the feedback compensation unit 10.

[0044] Specifically, the input filter unit 1 is used for filtering the circuit input signal, reducing the AC component in the input signal, and obtaining the DC input signal; the auxiliary power supply unit 7 is used for providing the Vcc level inside the circuit and providing a low-voltage input for the internal circuit; the voltage ratio conversion unit 2 is used for converting the input voltage into an intermediate voltage at a ratio of 4:1, and providing the input voltage for the power conversion unit 4; the intermediate filter unit 3 is used for filtering the intermediate voltage signal and reducing its AC signal; the power conversion unit 4 is used for converting the stable DC intermediate voltage into the required AC voltage by changing the switch duty cycle; the energy storage inductor unit 5 is used for energy conversion and storage; the output filter unit 6 is used for output signal filtering and rectification to obtain a stable DC output; the output sampling unit 9 is used to detect the circuit output signal and feed back the PWM control chip; the feedback compensation unit 10 is used for circuit loop compensation to make the circuit work stably; the PWM control unit 8 is used for output signal feedback adjustment to provide a control signal for the power conversion unit 4. The voltage ratio conversion unit 2 adopts a switch capacitor structure, which can achieve a 4:1 input-output conversion, greatly reduce the input voltage, that is, reduce the input-output voltage difference of the power conversion unit 4, and improve efficiency. In order to solve the problem that the voltage ratio conversion unit 2 cannot be started with load, the present invention uses the power indication function signal of the voltage ratio conversion unit 2 as the enable control signal of the PWM control unit 8, thereby realizing the direct load startup of the entire circuit, without the need to start the circuit without load before connecting the load.

[0045] like Figure 2 As shown, the input filter unit 1 includes a capacitor C1; the voltage ratio conversion unit 2 includes a voltage conversion module N1, a voltage conversion module N2, a resistor R1, a resistor R2 and a resistor R3; the intermediate filter unit 3 includes a capacitor C2; the power conversion unit 4 includes a MOS transistor Q1, a MOS transistor Q2, a MOS transistor Q3, a MOS transistor Q4, a MOS transistor Q5, a MOS transistor Q6, a MOS transistor Q7 and a MOS transistor Q8; the energy storage inductor unit 5 includes an inductor L1, an inductor L2, an inductor L3 and an inductor L4; the output filter unit 6 includes a capacitor C9, a capacitor C11, a capacitor C14 and a capacitor C17; the auxiliary The auxiliary power supply unit 7 includes a resistor R19, a voltage regulator D5, a transistor Q9 and a capacitor C18; the PWM control unit 8 includes a synchronous BUCK chip N3, a synchronous BUCK chip N4, a resistor R7, a resistor R10, a capacitor C6, a diode D1, a capacitor C7, a diode D2, a resistor R15, a resistor R17, a capacitor C13, a diode D3, a capacitor C15 and a diode D4; the output sampling unit 9 includes a resistor R8, a resistor R9, a capacitor C8, a resistor R13, a resistor R14, a capacitor C12, a resistor R5 and a resistor R6; the feedback compensation unit 10 includes a capacitor C3, a capacitor C4 and a capacitor C5.

[0046] Figure 1 for Figure 2 Simplified diagram of the functional modules, Figure 1 The input filter unit in is Figure 2 Capacitor C1 in Figure 1 The auxiliary power supply unit 7 is Figure 2 The resistor R19, the voltage regulator D5, the transistor Q9 and the capacitor C18; Figure 1 The voltage ratio conversion unit 2 in the Figure 2 The voltage conversion module N1, the voltage conversion module N2, the resistor R1, the resistor R2, and the resistor R3; Figure 1 The intermediate filter unit 3 in is Figure 2 C2 in Figure 1 The power conversion unit 4 in the Figure 2 MOS tube Q1, MOS tube Q2, MOS tube Q3, MOS tube Q4, MOS tube Q5, MOS tube Q6, MOS tube Q7, MOS tube Q8; Figure 1 The energy storage inductor unit 5 is Figure 2 Inductor L1, inductor L2, inductor L3, inductor L4; Figure 1 The output filter unit 6 in is Figure 2 Capacitor C9, capacitor C11, capacitor C14, capacitor C17; Figure 1 The output sampling unit 9 in is Figure 2Resistor R8, resistor R9, capacitor C8, resistor R13, resistor R14, capacitor C12, resistor R5, resistor R6; Figure 1 The feedback compensation unit 10 in the Figure 2 Capacitor C3, capacitor C4, capacitor C5; Figure 1 The PWM control unit 8 in Figure 2 The synchronous buck chip N3, the synchronous buck chip N4, the resistor R7, the resistor R10, the capacitor C6, the diode D1, the capacitor C7, the diode D2, the resistor R15, the resistor R17, the capacitor C13, the diode D3, the capacitor C15, and the diode D4.

[0047] exist Figure 2In the high-efficiency, high-ratio non-isolated hybrid buck converter circuit shown, the capacitor C1 functions as input filtering, which is used to filter out the pulsating current at the input end and provide a stable voltage for the input end of the voltage conversion module N1 and the voltage conversion module N2. N1 and N2 are voltage conversion modules, which output a DC voltage with an input-output voltage conversion ratio of 4:1. The DC voltage provides input voltage for the synchronous buck chip N3 and the synchronous buck chip N4, and provides an enable control signal for the synchronous buck chip N3 and the synchronous buck chip N4; the capacitor C2 functions as filtering, which is used to filter out the pulsating current at the input end of the synchronous buck chip N3 and N4 and provide a stable voltage for them; the resistor R19, the capacitor C5, the voltage regulator D5, and the three-stage regulator Q9 constitute an auxiliary power supply circuit, which realizes the voltage conversion from the input voltage to Vcc, and is used to provide power supply for some internal circuits or as an internal TTL high level; the resistor R3 is used for the status indication setting of the voltage conversion module, and the status will be transmitted to the synchronous buck chip at the same time. When the status indication is good, the synchronous buck chip starts working. Capacitor C6, capacitor C7, capacitor C13, capacitor C15, diode D1, diode D2, diode D3, and diode D4 constitute a bootstrap circuit to provide a driving voltage for the MOSFET inside the synchronous BUCK chip. Inductor L1, inductor L2, inductor L3, and inductor L4 are output filter inductors, which have the function of storing energy and generating a back electromotive force to stabilize the output voltage. At the same time, they have a filtering function and can reduce current ripple. Capacitor C9, capacitor C11, capacitor C14, and capacitor C17 are output capacitors, which are used to withstand the pulsation of the inductor current, reduce the output voltage ripple, and adjust the steady-state characteristics and dynamic characteristics of the output voltage. Resistors R1 and R2 have a current limiting function. When the voltage at the circuit prohibition terminal INH is low, resistors R1 and R2 are used to limit the current to avoid a direct short circuit in the voltage conversion module, which causes the device to burn out. Resistor R4, capacitor C4, and capacitor C5 constitute a loop compensation circuit to make the circuit work stably as a whole. Resistor R8, resistor R9, resistor R11, resistor R12, resistor R13, resistor R14, resistor R16, resistor R18, capacitor C8, capacitor C10, capacitor C12, and capacitor C16 constitute a current sampling circuit for transmitting the current signal of the inductor to the synchronous BUCK chip. Resistor R7 and resistor R17 are used to adjust the frequency of the synchronous BUCK chip. Resistor R10 and resistor R15 are used to indicate the working status of the synchronous BUCK chip.

[0048] Figure 3 For Figure 2 Based on the circuit shown, an external adjustable resistor RSET is connected to the circuit Trim terminal and the circuit output ground terminal GNDO, and different output voltages are determined by adjusting the resistance value of RSET to form an adjustment circuit closed loop.

[0049] In order to achieve adjustable output voltage, resistors R5, R6 and RSET form an output voltage adjustment circuit to output a constant voltage and adjust the output voltage value through RSET. Figure 3 The adjustment circuit is inside the box.

[0050] Depend on Figure 3 From the circuit shown, it can be seen that the output voltage Vo is obtained using the following formula:

[0051]

[0052] Output voltage V O With resistance

[0053] R SET The calculation formula is:

[0054] From the above formula, we can see that by setting different RSET, the output voltage V can be adjusted. O , realize the output adjustable function.

[0055] The working principle of the high-efficiency, high-ratio non-isolated hybrid buck converter circuit described in the present invention is:

[0056] The input voltage VIN provides the power supply voltage for the voltage conversion module N1, and the output of the voltage conversion module N1 provides the power supply voltage for the synchronous BUCK chips N3 and N4. When the main power switch tube MOSFET is turned on, the input power supply supplies power to the output load through the main power switch tube MOSFET and the inductor, and the inductor stores energy at the same time. When the main power switch tube MOSFET is turned off, the energy stored in the inductor is released to the output load, and forms a freewheeling loop through the internal synchronous rectification MOSFET to continue to supply power to the output load, and then rectified and filtered by the output filter unit to ensure that the output end obtains continuous current and voltage output, and at the same time to keep the output signal stable. The output sampling unit feeds the output signal back to the synchronous BUCK chip N3 and the synchronous BUCK chip N4, and adjusts the chip working duty cycle through the PWM control unit to achieve stable output voltage and output current.

[0057] Typical applications of the high efficiency and high transformation ratio non-isolated hybrid buck converter circuit described in the present invention are as follows: Figure 4 As shown, the external Trim terminal is connected to ground through the resistor R SET The setting affects the synchronous BUCK chip feedback loop and controls the output voltage. The working state is controlled by the circuit inhibit terminal INH. When the inhibit terminal is low, the circuit does not work by default. When the inhibit terminal INHINH is empty or the voltage is high, the circuit works.

[0058] The above-described embodiments are merely descriptions of preferred implementations of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the scope of protection determined by the claims of the present invention.

Claims

1. A high-efficiency, high-ratio non-isolated hybrid buck converter circuit, characterized in that: The circuit comprises: an input filter unit (1), a voltage ratio conversion unit (2), an intermediate filter unit (3), a power conversion unit (4), an energy storage inductor unit (5), an output filter unit (6), an auxiliary power supply unit (7), a PWM control unit (8), an output sampling unit (9) and a feedback compensation unit (10); The output end of the input filter unit (1) is respectively connected to the input end of the voltage ratio conversion unit (2) and the input end of the auxiliary power supply unit (7); the output end of the auxiliary power supply unit (7) is connected to the input end of the voltage ratio conversion unit (2); the output end of the voltage ratio conversion unit (2) is respectively connected to the input end of the intermediate filter unit (3) and the input end of the PWM control unit (8); the output end of the intermediate filter unit (3) is connected to the input end of the power conversion unit (4), and the output end of the power conversion unit (4) is connected to the storage The energy storage inductor unit (5) is connected to the input end of the energy storage inductor unit (5), the output end of the energy storage inductor unit (5) is connected to the input end of the output filter unit (6) and the input end of the output sampling unit (9), the output end of the output filter unit (6) is connected to the input end of the output sampling unit (9), the output end of the output sampling unit (9) is connected to the input end of the PWM control unit (8), the output end of the PWM control unit (8) is connected to the control end of the power conversion unit (4), and the PWM control unit (8) is interactively connected to the feedback compensation unit (10).

2. The high-efficiency, high-transformation-ratio, non-isolated hybrid buck converter circuit according to claim 1, characterized in that: The voltage ratio conversion unit (2) comprises a voltage conversion module N1, a voltage conversion module N2, a resistor R1, a resistor R2 and a resistor R3; The voltage conversion module N1 has an input power supply terminal Vin leading to a circuit input terminal Vin, a power ground GND leading to a circuit ground terminal GND, and an enable terminal EN leading to a circuit disable terminal INH via the resistor R1; the voltage conversion module N1 is connected to the input power supply terminal Vin of the voltage conversion module N2, the voltage conversion module N1 is connected to the power ground GND of the voltage conversion module N2, the voltage conversion module N1 is connected to the output terminal Vo of the voltage conversion module N2, the voltage conversion module N1 is connected to the enable terminal EN of the voltage conversion module N2, the voltage conversion module N1 is connected to the synchronization terminal SYNC of the voltage conversion module N2, and the voltage conversion module N1 is connected to the indication pin PGOOD of the voltage conversion module N2.

3. The high-efficiency, high-transformation-ratio, non-isolated hybrid buck converter circuit according to claim 2, characterized in that: The input filter unit (1) comprises a capacitor C1; the intermediate filter unit (3) comprises a capacitor C2; one end of the capacitor C1 is connected to the input power supply terminal Vin of the voltage conversion module N1, and the other end is connected to GND; one end of the capacitor C2 is connected to the output terminal Vo of the voltage conversion module N1, and the other end is connected to GND; one end of the resistor R2 is connected to the enable terminal EN of the voltage conversion module N1, and the other end is connected to the network VCC; one end of the resistor R3 is connected to the indication pin PGOOD of the voltage conversion module N1, and the other end is connected to the network VCC; the output terminal Vo of the voltage conversion module N1 is connected to the input power supply terminal Vin of the synchronous BUCK chip N3.

4. The high-efficiency, high-transformation-ratio non-isolated hybrid buck converter circuit according to claim 3, characterized in that: The auxiliary power supply unit (7) comprises a resistor R19, a voltage regulator D5, a transistor Q9 and a capacitor C18; the PWM control unit (8) comprises a synchronous BUCK chip N3, a synchronous BUCK chip N4, a resistor R7, a resistor R10, a capacitor C6, a diode D1, a capacitor C7, a diode D2, a resistor R15, a resistor R17, a capacitor C13, a diode D3, a capacitor C15 and a diode D4; The feedback terminal FB of the synchronous buck chip N3 is led out as the circuit adjustment terminal Trim, and the ground terminal GND is led out as the circuit ground terminal GND; the synchronous buck chip N3 is connected to the input power supply terminal Vin of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the ground terminal GND of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the soft start input pin 1TK / SS1 of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the soft start input pin 2TK / SS2 of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the error amplifier compensation pin 1ITH1 of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the error amplifier compensation pin 2ITH2 of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the synchronous buck chip N4 The error feedback input pin 1VFB1 of the UCK chip N4 is connected, the synchronous buck chip N3 is connected to the error feedback input pin 2VFB2 of the synchronous buck chip N4, the synchronous buck chip N3 is connected to the enable control pin 1RUN1 of the synchronous buck chip N4, and the synchronous buck chip N3 is connected to the enable control pin 2RUN2 of the synchronous buck chip N4; the error amplifier compensation pin 1ITH1 of the synchronous buck chip N3 is connected to the error amplifier compensation pin 2ITH2, the soft start input pin 1TK / SS1 of the synchronous buck chip N3 is connected to the soft start input pin 2TK / SS2, the error feedback input pin 1VFB1 of the synchronous buck chip N3 is connected to the error feedback input pin 2VFB2, and the enable control pin 1RUN1 of the synchronous buck chip N3 is connected to the enable control pin 2RUN2; The anode of the diode D1 is connected to the internal regulator output pin INTVcc of the synchronous BUCK chip N3; the cathode of the diode D1 is connected to the bootstrap power supply 1BOOST1 of the synchronous BUCK chip N3; the cathode of the diode D2 is connected to the bootstrap power supply 2BOOST2 of the synchronous BUCK chip N3; the anode of the diode D2 is connected to the internal regulator output pin INTVcc of the synchronous BUCK chip N3; the cathode of the diode D3 is connected to the bootstrap power supply 1BOOST1 of the synchronous BUCK chip N4; the anode of the diode D3 is connected to the internal regulator output pin INTVcc of the synchronous BUCK chip N4; the anode of the diode D4 is connected to the internal regulator output pin INTVcc of the synchronous BUCK chip N4; the cathode of the diode D4 is connected to the bootstrap power supply 2BOOST2 of the synchronous BUCK chip N4.

5. The high-efficiency, high-transformation-ratio non-isolated hybrid buck converter circuit according to claim 4, characterized in that: The energy storage inductor unit (5) includes an inductor L1, an inductor L2, an inductor L3 and an inductor L4; the output filter unit (6) includes a capacitor C9, a capacitor C11, a capacitor C14 and a capacitor C17; the output sampling unit (9) includes a resistor R8, a resistor R9, a capacitor C8, a resistor R13, a resistor R14, a capacitor C12, a resistor R5 and a resistor R6; One end of the resistor R5 is connected to the error feedback input pin 1VFB1 of the synchronous buck chip N3, and the other end is connected to the differential telemetry amplifier output pin DIFFOUT of the synchronous buck chip N3; one end of the resistor R5 is connected to the error feedback input pin 1VFB1 of the synchronous buck chip N3, and the other end is connected to GND; The differential telemetry amplifier positive input pin DIFFP of the synchronous BUCK chip N3 is connected to the second end of the inductor L1; the differential telemetry amplifier negative input pin DIFFN of the synchronous BUCK chip N3 is connected to GND; the enable control pin 1RUN1 of the synchronous BUCK chip N3 is connected to the indication pin PGOOD of the voltage conversion module N1; One end of the resistor R10 is connected to the indication pin PGOOD of the synchronous buck chip N3, and the other end is connected to the output pin INTVcc of the internal voltage regulator of the synchronous buck chip N3; The clock output pin CLKOUT of the synchronous buck chip N3 is connected to the mode selection pin MODE / PLLIN of the synchronous buck chip N4; the mode selection pin MODE / PLLIN of the synchronous buck chip N3 is connected to GND; the differential telemetry amplifier positive input pin DIFFP of the synchronous buck chip N4 is connected to GND; the differential telemetry amplifier negative input pin DIFFN of the synchronous buck chip N4 is connected to GND; One end of the resistor R7 is connected to the frequency pin FREQ of the synchronous BUCK chip N3, and the other end is connected to GND; One end of the resistor C8 is connected to the second end of the inductor L1, and the other end is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronous buck chip N3; the resistor R9 is connected in parallel with the capacitor C8; one end of the capacitor C9 is connected to the second end of the inductor L1, and the other end is connected to GND; the negative input pin sense1- of the current sensing comparator 1 of the synchronous buck chip N3 is connected to the second end of the inductor L1; the second end of the inductor L1 is connected to the lead-out circuit input terminal Vo; One end of the capacitor C10 is connected to the second end of the inductor L1, and the other end is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronous BUCK chip N3; the resistor R11 is connected in parallel with the capacitor C10; one end of the capacitor C11 is connected to the second end of the inductor L1, and the other end is connected to GND; the negative input pin sense2- of the current sensing comparator 2 of the synchronous BUCK chip N3 is connected to the second end of the inductor L2; the second end of the inductor L2 is connected to the lead-out circuit input terminal Vo; One end of the resistor R15 is connected to the indication pin PGOOD of the synchronous buck chip N4, and one end is connected to the internal regulator output pin INTVcc of the synchronous buck chip N4; one end of the resistor R17 is connected to the frequency pin FREQ of the synchronous buck chip N4, and the other end is connected to GND; One end of the resistor C12 is connected to the second end of the inductor L3, and the other end is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronous BUCK chip N4; the resistor R14 is connected in parallel with the capacitor C12; one end of the capacitor C14 is connected to the second end of the inductor L3, and the other end is connected to GND; the negative input pin sense2- of the current sensing comparator 2 of the synchronous BUCK chip N4 is connected to the second end of the inductor L3; the second end of the inductor L3 is connected to the lead-out circuit input terminal Vo; One end of the resistor C16 is connected to the second end of the inductor L3, and the other end is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronous BUCK chip N4; the resistor R14 is connected in parallel with the capacitor C16; one end of the capacitor C17 is connected to the second end of the inductor L3, and the other end is connected to GND; the negative input pin sense2- of the current sensing comparator 2 of the synchronous BUCK chip N4 is connected to the second end of the inductor L4; the second end of the inductor L4 is connected to the lead-out circuit input terminal Vo; One end of the resistor R19 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4, and the other end is connected to the cathode of the voltage regulator D5 and the B pole of the transistor Q9; the anode of the voltage regulator D5 is connected to GND; the C pole of the transistor Q9 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4, and the E pole is connected to the network Vcc; one end of the capacitor C18 is connected to the network Vcc, and the other end is connected to GND.

6. The high-efficiency, high-transformation-ratio non-isolated hybrid buck converter circuit according to claim 5, characterized in that: The power conversion unit (4) comprises a MOS tube Q1, a MOS tube Q2, a MOS tube Q3, a MOS tube Q4, a MOS tube Q5, a MOS tube Q6, a MOS tube Q7 and a MOS tube Q8; The source of the MOS tube Q1 is connected to the input power supply terminal Vin of the synchronous BUCK chip N3; the gate of the MOS tube Q1 is connected to the high-end gate drive output pin 1TG1 of the synchronous BUCK chip N3; the source of the MOS tube Q1 is connected to the switch node SW1 of the synchronous BUCK chip N3, the first end of the capacitor C6, the drain of the MOS tube Q2, the first end of the inductor L1, and the first end of the resistor R8; the second end of the capacitor C6 is connected to the bootstrap power supply 1BOOST1 of the synchronous BUCK chip N3; the second end of the resistor R8 is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronous BUCK chip N3; the gate of the MOS tube Q2 is connected to the low-end gate drive output pin 1BG1 of the synchronous BUCK chip N3; the source of the MOS tube Q2 is connected to GND; The source of the MOS tube Q3 is connected to the input power supply terminal Vin of the synchronous BUCK chip N3; the gate of the MOS tube Q3 is connected to the high-end gate drive output pin 2TG2 of the synchronous BUCK chip N3; the source of the MOS tube Q3 is connected to the switch node SW2 of the synchronous BUCK chip N3, the first end of the capacitor C7, the drain of the MOS tube Q4, the first end of the inductor L2, and the first end of the resistor R12; the second end of the capacitor C7 is connected to the bootstrap power supply 2BOOST2 of the synchronous BUCK chip N3; the second end of the resistor R12 is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronous BUCK chip N3; the gate of the MOS tube Q4 is connected to the low-end gate drive output pin 2BG2 of the synchronous BUCK chip N3; the source of the MOS tube Q4 is connected to GND; The source of the MOS tube Q5 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4; the gate of the MOS tube Q5 is connected to the high-end gate drive output pin 1TG1 of the synchronous BUCK chip N4; the source of the MOS tube Q5 is connected to the switch node SW1 of the synchronous BUCK chip N4, the first end of the capacitor C13, the drain of the MOS tube Q6, the first end of the inductor L3, and the first end of the resistor R13; the second end of the capacitor C13 is connected to the bootstrap power supply 1BOOST1 of the synchronous BUCK chip N4; the second end of the resistor R13 is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronous BUCK chip N4; the gate of the MOS tube Q6 is connected to the low-end gate drive output pin 1BG1 of the synchronous BUCK chip N4; the source of the MOS tube Q6 is connected to GND; The source of the MOS tube Q7 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4; the gate of the MOS tube Q7 is connected to the high-end gate drive output pin 2TG2 of the synchronous BUCK chip N4; the source of the MOS tube Q7 is connected to the switch node SW2 of the synchronous BUCK chip N4, the first end of the capacitor C15, the drain of the MOS tube Q8, the first end of the inductor L4, and the first end of the resistor R18; the second end of the capacitor C15 is connected to the bootstrap power supply 2BOOST2 of the synchronous BUCK chip N4; the second end of the resistor R18 is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronous BUCK chip N4; the gate of the MOS tube Q8 is connected to the low-end gate drive output pin 2BG2 of the synchronous BUCK chip N4; the source of the MOS tube Q8 is connected to GND.

7. The high-efficiency, high-transformation-ratio non-isolated hybrid buck converter circuit according to claim 6, characterized in that: The feedback compensation unit (10) comprises a capacitor C3, a capacitor C4, a capacitor C5 and a resistor R4; One end of the capacitor C3 is connected to the soft start input pin 1TK / SS1 of the synchronous BUCK chip N3, and the other end is connected to GND; one end of the capacitor C4 is connected to GND, and the other end is connected to the second end of the resistor R4; the first end of the resistor R4 is connected to the error amplifier compensation pin 1ITH1 of the voltage conversion module N1; one end of the capacitor C5 is connected to the error amplifier compensation pin 1ITH1 of the synchronous BUCK chip N3, and the other end is connected to GND.

8. The high-efficiency, high-transformation-ratio non-isolated hybrid buck converter circuit according to claim 7, characterized in that: The circuit also includes an adjustable resistor RSET; two ends of the adjustable resistor RSET are respectively connected to the circuit Trim terminal and the ground terminal GND; different output voltages are determined by adjusting the resistance value of the adjustable resistor RSET to form an adjustment circuit closed loop.

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