Large dynamic range cross-group amplifier

Abstract

The invention relates to a large-dynamic-range cross-group amplifier, which belongs to the technical field of cross-group amplifiers and comprises a main trans-impedance amplifier, a second trans-impedance amplifier and a feedback resistance module, the main trans-impedance amplifier comprises a first common-emitter common-base amplifier, a first emitter follower and a feedback resistance module, the first common-emitter common-base amplifier is connected with the first emitter follower and a first common-base amplifier in a voltage boosting branch, and the feedback resistance module is connected with a second common-emitter follower and a second common-base amplifier in a voltage boosting branch; the feedback resistor module is connected with the first emitter follower; the load resistance reduction branch comprises a triode and a load resistor, and the triode is connected with the first common-emitter common-base amplifier and the load resistor; the compensation capacitor introduction branch comprises a second emitter follower connected with the first emitter follower, a second transmission gate switch and a feedback capacitor connected with the second emitter follower; the decision circuit comprises a low-pass filter and a latch comparator, and the low-pass filter is connected with the first emitter follower and the latch comparator; and the bias voltage control circuit comprises an inverter which is connected with the latch comparator. According to the invention, the overload capacity and the loop stability when the transimpedance is reduced are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of cross-group amplifiers, and in particular to a cross-group amplifier with a large dynamic range. Background Art

[0002] In the optical fiber communication system, the transimpedance amplifier (TIA) is located at the front end of the receiving link. Its core function is to convert the weak current signal generated by the photodiode into a voltage signal and amplify it for further processing by the subsequent circuit. The performance of the TIA is crucial to the performance of the entire receiving link. However, the TIA in the prior art will encounter the problem of insufficient overload capacity when processing high-intensity input signals, resulting in signal distortion and performance degradation.

[0003] A key performance indicator closely related to this issue is the input dynamic range, which defines the difference between the maximum and minimum input optical powers that the TIA can handle within a specific bit error rate range, usually expressed in dBm units. This range is determined by the saturated input optical power and the received optical sensitivity. The received optical sensitivity is mainly affected by the noise performance. The lower the equivalent input noise of the TIA, the higher its sensitivity. Generally speaking, a larger transimpedance gain helps to reduce the equivalent input noise, but at the same time, a larger transimpedance gain is more likely to cause saturation when processing large signals. In order to balance this contradiction, the TIA in the prior art integrates an automatic gain control (AGC) circuit.

[0004] Although the AGC can automatically adjust the gain to adapt to changes in the input signal, its adjustment mechanism may also bring limitations to system performance. Figure 1 As shown, the dominant pole of the TIA is usually formed by the feedback resistor R f and the total input capacitance C in The calculation formula is p1 = (1 + β0R L / r π ) / (2πR f C in ), where β0 represents the small signal current gain of transistor Q1, r π is the small signal input resistance of transistor Q1. The secondary main pole of TIA is determined by the forward amplifier, which is usually a common emitter / common source amplifier with a resistive load, and its pole is determined by the load resistance R L and the output node capacitance C L The calculation formula is p2 = 1 / (2πR L C L ). When the input optical power is large, due to the effect of AGC, the transresistance R fThe main pole is reduced, which causes the main pole to move closer to the secondary main pole, which will reduce the phase margin and affect the stability of the loop. In this case, the step response of the TIA will show ringing, which will reduce the quality of the output eye diagram and further affect the bit error rate of the system. Summary of the invention

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the insufficient overload capacity in the prior art and the high bit error rate caused by the reduction of loop stability and the deterioration of output eye diagram quality when the transimpedance is reduced.

[0006] In a first aspect, in order to solve the above technical problems, the present invention provides a large dynamic range cross-group amplifier, comprising:

[0007] A main transimpedance amplifier, comprising a first cascode amplifier, a first emitter follower and a feedback resistor module; the first cascode amplifier is connected to the first emitter follower; the feedback resistor module is connected to the first emitter follower;

[0008] A voltage boosting branch, comprising a first cascode amplifier, connected to the first cascode amplifier;

[0009] A load resistance reduction branch comprises a triode and a load resistor; one end of the triode is connected to the first cascode amplifier, and the other end is connected to the load resistor;

[0010] A compensation capacitor introduction branch includes a second emitter follower, a second transmission gate switch and a feedback capacitor; the second emitter follower and the second transmission gate switch are both connected to the first emitter follower; one end of the feedback capacitor is connected to the second emitter follower, and the other end is connected to the input end of the main transimpedance amplifier;

[0011] A decision circuit, comprising a low-pass filter and a latch comparator; one end of the low-pass filter is connected to the first emitter follower, and the other end is connected to the positive input end of the latch comparator;

[0012] The bias voltage control circuit includes an inverter connected to the latch comparator.

[0013] In one embodiment of the present invention, the first common-emitter common-base amplifier includes a first transistor, a second transistor and a first load resistor; the base of the first transistor is set as the input end of the main transimpedance amplifier; the collector of the first transistor is connected to the emitter of the second transistor; the base of the second transistor is connected to a first bias voltage; the collector of the second transistor is connected to one end of the first load resistor; and the other end of the first load resistor is connected to a power supply.

[0014] In one embodiment of the present invention, the first emitter follower includes a third transistor and a fourth transistor; the base of the third transistor is connected to the collector of the second transistor in the first common-emitter amplifier; the collector of the third transistor is connected to a power supply; the emitter of the third transistor is connected to the collector of the fourth transistor and serves as the output end of the main transimpedance amplifier; the base of the fourth transistor is connected to a second bias voltage; and the emitter of the fourth transistor is grounded.

[0015] In one embodiment of the present invention, the feedback resistor module includes a first transmission gate switch, a second MOS tube and a feedback resistor; the input end of the first transmission gate switch is connected to the input end of the main transimpedance amplifier; the output end of the first transmission gate switch is connected to the drain of the second MOS tube; the source of the second MOS tube is connected to the output end of the main transimpedance amplifier; the gate of the second MOS tube is connected to the bias voltage; one end of the feedback resistor is connected to the input end of the main transimpedance amplifier, and the other end is connected to the output end of the main transimpedance amplifier.

[0016] In one embodiment of the present invention, the first common-base amplifier includes a first MOS tube, a seventh transistor and an eighth transistor; the drain of the first MOS tube is connected to the emitter of the first transistor in the first common-emitter common-base amplifier; the gate of the first MOS tube is connected to a fourth bias voltage; the source of the first MOS tube is grounded; the emitter of the seventh transistor is connected to the drain of the first MOS tube; the base of the seventh transistor is connected to the third bias voltage; the collector of the seventh transistor is connected to the emitter of the eighth transistor; the base of the eighth transistor is connected to the collector of the eighth transistor and is connected to a power supply.

[0017] In one embodiment of the present invention, the emitter of the transistor is connected to the emitter of the second transistor in the first common-emitter amplifier, the base of the transistor is connected to a fifth bias voltage, and the collector of the transistor is connected to one end of the load resistor; the other end of the load resistor is connected to a power supply.

[0018] In one embodiment of the present invention, the second emitter follower includes a fifth transistor and a sixth transistor; the base of the fifth transistor is connected to the base of the third transistor in the first emitter follower; the collector of the fifth transistor is connected to a power supply; the emitter of the fifth transistor is connected to the collector of the sixth transistor, the base of the sixth transistor is connected to the output end of the second transmission gate switch, and the emitter of the sixth transistor is grounded; the input end of the second transmission gate switch is connected to the base of the fourth transistor in the first emitter follower; one end of the feedback capacitor is connected to the collector of the sixth transistor.

[0019] In one embodiment of the present invention, the low-pass filter includes a filter resistor and a filter capacitor; one end of the filter resistor is connected to the output end of the main transimpedance amplifier, and the other end is connected to one end of the filter capacitor and connected to the positive input end of the latch comparator, the other end of the filter capacitor is grounded, the reverse input end of the latch comparator is connected to a reference voltage, and the output of the latch comparator is set to a voltage signal.

[0020] In one embodiment of the present invention, the bias voltage control circuit also includes a third transmission gate switch and a fourth transmission gate switch; the input end of the third transmission gate switch is connected to the first bias voltage, and the output end of the third transmission gate switch is connected to the fifth bias voltage; the input end of the inverter receives the voltage signal in the decision circuit, the output end of the inverter controls the shutdown of the fourth transmission gate switch, the output end of the fourth transmission gate switch is connected to the fifth bias voltage, and the input end of the fourth transmission gate switch is grounded.

[0021] In a second aspect, in order to solve the above technical problem, the present invention provides a fiber optic communication system, including the above large dynamic range cross-group amplifier.

[0022] The above technical solution of the present invention has the following beneficial effects compared with the prior art:

[0023] A large dynamic range cross-group amplifier described in the present invention increases the input voltage through a voltage lifting branch, enhances the overload capacity, and thus realizes effective processing of a large dynamic range input signal. When the input optical power increases, the present invention can intelligently reduce the feedback resistance, reduce the equivalent load resistance of the main transimpedance amplifier, and introduce a compensation capacitor through the coordinated work of the load resistance reduction branch, the compensation capacitor introduction branch, the decision circuit, and the bias voltage control circuit. These measures not only reduce the gain of the amplifier, but also effectively slow down the trend of the main pole of the transimpedance feedback loop moving to high frequency, thereby improving the stability of the loop and improving the quality of the output eye diagram. These improvements ultimately significantly reduce the bit error rate of the system and enhance the reliability of signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein

[0025] Figure 1 It is a circuit schematic diagram of an existing transimpedance amplifier;

[0026] Figure 2 The schematic diagram of a circuit of a transimpedance amplifier with a large dynamic range in a preferred embodiment of the present invention.

[0027] Explanation of the reference numerals in the specification: 1. Main transimpedance amplifier; 2. Voltage raising branch; 3. Load resistance lowering branch; 4. Compensation capacitor introduction branch; 5. Decision circuit; 6. Bias voltage control circuit. DETAILED DESCRIPTION

[0028] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0029] Embodiment 1

[0030] Reference Figure 2 As shown, the present invention provides a large dynamic range transimpedance amplifier, comprising:

[0031] The main transimpedance amplifier 1 comprises a first cascode amplifier, a first emitter follower and a feedback resistor module; the first cascode amplifier is connected to the first emitter follower; the feedback resistor module is connected to the first emitter follower;

[0032] The voltage boosting branch 2 includes a first common-base amplifier and is connected to the first common-emitter-cascode amplifier;

[0033] The load resistance reduction branch 3 comprises a transistor and a load resistor; one end of the transistor is connected to the first cascode amplifier, and the other end is connected to the load resistor;

[0034] The compensation capacitor is introduced into branch 4, which includes a second emitter follower, a second transmission gate switch and a feedback capacitor; the second emitter follower and the second transmission gate switch are both connected to the first emitter follower; one end of the feedback capacitor is connected to the second emitter follower, and the other end is connected to the input end of the main transimpedance amplifier 1;

[0035] The decision circuit 5 comprises a low-pass filter and a latch comparator; one end of the low-pass filter is connected to the first emitter follower, and the other end is connected to the positive input end of the latch comparator;

[0036] The bias voltage control circuit 6 includes an inverter connected to the latch comparator.

[0037] A large dynamic range transimpedance amplifier provided by an embodiment of the present invention uses a voltage raising branch 2 to raise the input voltage, thereby improving the overload capacity and realizing a large dynamic range input. When the input optical power increases, through the synergistic effect of the load resistance reduction branch 3, the compensation capacitor introduction branch 4, the decision circuit 5 and the bias voltage control circuit 6, the amplifier can reduce the feedback resistance by controlling the switch, reduce the equivalent load resistance of the main transimpedance amplifier 1, and introduce a compensation capacitor. These measures effectively slow down the trend of the main pole of the transimpedance feedback loop moving to high frequency while reducing the amplifier gain, thereby improving the stability of the loop. In addition, the embodiment of the present invention ensures that the feedback loop has a sufficiently large phase margin, improves the quality of the output eye diagram, and greatly reduces the bit error rate of the system.

[0038] Specifically, the main transimpedance amplifier 1 includes a first cascode amplifier, a first emitter follower and a feedback resistor module. The first cascode amplifier includes a first transistor Q1, a second transistor Q2 and a first load resistor R L1 Specifically, the base of the first transistor Q1 is set as the input terminal I of the main transimpedance amplifier 1. in The collector of the first transistor Q1 is connected to the emitter of the second transistor Q2, and a voltage node V2 is formed between the collector of the first transistor Q1 and the emitter of the second transistor Q2. The base of the second transistor Q2 is connected to the first bias voltage V b1 , the collector of the second transistor Q2 is connected to the first load resistor R L1 One end of the second transistor Q2 collector and the first load resistor R L1 A voltage node V3 is formed between the first load resistor R L1 The other end is connected to the power supply V CC .

[0039] Furthermore, the first emitter follower includes a third transistor Q3 and a fourth transistor Q4. The base of the third transistor Q3 is connected to the collector of the second transistor Q2, and the collector of the third transistor Q3 is connected to the power supply V CC The emitter of the third transistor Q3 is connected to the collector of the fourth transistor Q4 and serves as the output terminal V of the main transimpedance amplifier 1. out The base of the fourth transistor Q4 is connected to the second bias voltage V b2 , the emitter of the fourth transistor Q4 is grounded.

[0040] Furthermore, the feedback resistor module includes a first transmission gate switch T1, a second MOS tube M2 and a feedback resistor R f0 The input end of the first transmission gate switch T1 is connected to the input end I of the main transimpedance amplifier 1. inThe output end of the first transmission gate switch T1 is connected to the drain of the second MOS tube M2, and the first transmission gate switch T1 is turned off by the voltage signal SW_ON. The source of the second MOS tube M2 is connected to the output end V out , the gate of the second MOS tube M2 is connected to the bias voltage V g_nm . Feedback resistor R f0 One end is connected to the input terminal I of the main transimpedance amplifier 1 in The other end is connected to the output terminal V of the main transimpedance amplifier 1 out .

[0041] The first common-emitter amplifier and the first emitter follower of the above design achieve a large dynamic range and low noise performance, while utilizing dynamic control elements in the bias voltage and feedback resistor modules to ensure signal integrity and stability, thereby improving the overall performance and reliability of the transimpedance amplifier.

[0042] Specifically, the voltage raising branch 2 includes a first common base amplifier, which includes a first MOS tube M1, a seventh transistor Q7 and an eighth transistor Q8. The drain of the first MOS tube M1 is connected to the emitter of the first transistor Q1, a voltage node V1 is formed between the drain of the first MOS tube M1 and the emitter of the first transistor Q1, and the gate of the first MOS tube M1 is connected to the fourth bias voltage V b4 The source of the first MOS transistor M1 is grounded. The emitter of the seventh transistor Q7 is connected to the drain of the first MOS transistor M1, and the base of the seventh transistor Q7 is connected to the third bias voltage V b3 The collector of the seventh transistor Q7 is connected to the emitter of the eighth transistor Q8. The base of the eighth transistor Q8 is connected to the collector of the eighth transistor Q8 and is connected to the power supply V CC .

[0043] The introduction of the first MOS transistor M1 and the seventh transistor Q7 in the voltage raising branch 2 optimizes the performance of the transimpedance amplifier in the prior art. Specifically, the addition of these components increases the emitter voltage of the first transistor Q1 in the transimpedance amplifier from 0 to a fixed potential. This design change results in the input terminal I in The voltage is increased, thereby increasing the output voltage of the main transimpedance amplifier 1, V out When the input optical power is too high, the output signal distortion problem is usually caused by the output terminal V out The voltage is insufficient, causing the fourth transistor Q4 to fail to work properly. Therefore, the voltage raising branch 2 can effectively increase the carrying capacity of the transimpedance amplifier for the saturated input optical power, thereby realizing effective processing of input signals with a large dynamic range. This improvement not only improves the performance of the amplifier, but also enhances its ability to process signals under different optical power conditions.

[0044] Specifically, the load resistance reduction branch 3 includes a transistor Q9 (also referred to as the ninth transistor Q9) and a load resistor R L2 (Also called the second load resistor R L2 The emitter of the ninth transistor Q9 is connected to the emitter of the second transistor Q2, and the base of the ninth transistor Q9 is connected to the fifth bias voltage V b5 , the collector of the ninth transistor Q9 is connected to the second load resistor R L2 one end, and the second load resistor R L2 The other end is connected to the power supply V CC The ninth transistor Q9 and the second load resistor R L2 The introduction and design of the MOSFET realizes the dynamic adjustment of the load resistance, optimizes the linearity and stability of signal processing, and improves the power efficiency, circuit flexibility and protection capability.

[0045] Specifically, the compensation capacitor introduction branch 4 includes a second emitter follower, a feedback capacitor C C and the second transmission gate switch T2. The second emitter follower includes a fifth transistor Q5 and a sixth transistor Q6. Specifically, the base of the fifth transistor Q5 is connected to the base of the third transistor Q3 to ensure signal continuity. The collector of the fifth transistor Q5 is connected to the power supply V CC , its emitter is connected to the collector of the sixth transistor Q6, so a voltage node V4 is formed between the emitter of the fifth transistor Q5 and the collector of the sixth transistor Q6. The base of the sixth transistor Q6 is connected to the output end of the second transmission gate switch T2, and the emitter of the sixth transistor Q6 is grounded. For the second transmission gate switch T2, its input end is connected to the base of the fourth transistor Q4, and the second transmission gate switch T2 is turned off by the voltage signal SW_ON. For the feedback capacitor C c One end of which is connected to the collector of the sixth transistor Q6, and the other end is connected to the input terminal I of the main transimpedance amplifier 1. in In this design, dynamic adjustment and phase compensation are used to improve the stability and dynamic response capability of the transimpedance amplifier, reduce noise, and optimize signal processing performance.

[0046] Specifically, the decision circuit 5 includes a low-pass filter and a latch comparator. The low-pass filter includes a filter resistor R f And filter capacitor C f For the filter resistor R f , one end of which is connected to the output terminal V of the main transimpedance amplifier 1 out , the other end is connected to the filter capacitor C f One end is connected to the positive input of the latch comparator, so this end and the filter capacitor C fA voltage node V5 is formed between one end of the filter capacitor C f The other end of the latch comparator is connected to the reference voltage V ref , the output of the latched comparator is set to the voltage signal SW_ON.

[0047] Furthermore, when the input optical power is close to zero or very low, the reference voltage V ref will be lower than the output terminal V out The time domain average voltage V5 after low-pass filter processing causes the voltage signal SW_ON output by the latch comparator to remain at a low level. As the input optical power gradually increases, more current will flow through the feedback resistor R of the transimpedance amplifier. f0 , which will cause the output of the main transimpedance amplifier 1 to be V out The time domain average voltage V5 is reduced, and the time domain average voltage V5 is also reduced. When V5 is reduced to a value lower than the reference voltage V ref When the threshold is reached, the output voltage signal SW_ON of the latch comparator will switch to a high level state.

[0048] Specifically, the bias voltage control circuit 6 includes an inverter, a third transmission gate switch T3 and a fourth transmission gate switch T4. The input end of the third transmission gate switch T3 is connected to the first bias voltage V b1 The output end of the third transmission gate switch T3 is connected to the fifth bias voltage V b5 , the third transmission gate switch T3 is turned off by the voltage signal SW_ON. The input end of the inverter is connected to the voltage signal SW_ON to receive the voltage signal, and the output end of the inverter controls the turn-off of the fourth transmission gate switch T4. The output end of the fourth transmission gate switch T4 is connected to the fifth bias voltage V b5 , the input end of the fourth transmission gate switch T4 is grounded.

[0049] Furthermore, when the input optical power is 0 or very small, the output voltage signal SW_ON is in a low level state. At this time, the first transmission gate switch T1 is closed, and the feedback resistor module only has the feedback resistor R f0 Valid; the second transmission gate switch T2 is closed, the compensation capacitor introduced into branch 4 is disconnected, and the feedback capacitor C c The third transmission gate switch T3 is closed, and the fourth transmission gate switch T4 is opened, and the fifth bias voltage V b5 Grounding, load resistance reduction branch 3 is disconnected and does not work. Relatively speaking, under the condition of large input optical power, the output voltage signal SW_ON is at a high level. At this time, the first transmission gate switch T1 is turned on, and the second MOS tube M2 and the feedback resistor R f0 In parallel, the transimpedance gain is reduced; the second transmission gate switch T2 is turned on, the compensation capacitor is introduced into branch 4 and connected to the main transimpedance amplifier 1, and the feedback capacitor Cc is connected in parallel with the feedback resistor module to introduce a zero point to increase the phase margin; the third transmission gate switch T3 is turned on, while the fourth transmission gate switch T4 is turned off, and the fifth bias voltage V b5 Connect the first bias voltage V b1 , the load resistance reduction branch 3 is connected to the main transimpedance amplifier 1 to reduce its equivalent load. The above adjustment slows down the trend of the main pole of the transimpedance feedback loop moving to high frequency, and at the same time makes the secondary main pole move to high frequency. The two work together to separate the main pole and the secondary main pole, ensuring that the feedback loop has a sufficiently large phase margin. This design improves the loop stability, improves the output eye diagram quality, and significantly reduces the bit error rate of the system.

[0050] Embodiment 2

[0051] This embodiment provides an optical fiber communication system, including a large dynamic range cross-group amplifier provided in the first embodiment.

[0052] It should be noted that the terms "first" and "second" mentioned in the embodiments of the present invention are only used to distinguish different components or steps, and they do not represent any difference in priority or importance. This numbering method is intended to clearly identify and describe the various parts of the present invention so as to better understand and implement the technical solution.

[0053] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0054] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0055] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0056] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0057] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A large dynamic range cross-group amplifier, characterized in that: include: A main transimpedance amplifier, comprising a first cascode amplifier, a first emitter follower and a feedback resistor module; The first cascode amplifier is connected to the first emitter follower; the feedback resistor module is connected to the first emitter follower; A voltage boosting branch, comprising a first cascode amplifier, connected to the first cascode amplifier; A load resistance reduction branch comprises a triode and a load resistor; one end of the triode is connected to the first cascode amplifier, and the other end is connected to the load resistor; A compensation capacitor introduction branch includes a second emitter follower, a second transmission gate switch and a feedback capacitor; the second emitter follower and the second transmission gate switch are both connected to the first emitter follower; one end of the feedback capacitor is connected to the second emitter follower, and the other end is connected to the input end of the main transimpedance amplifier; A decision circuit, including a low-pass filter and a latch comparator; One end of the low-pass filter is connected to the first emitter follower, and the other end is connected to the positive input end of the latch comparator; The bias voltage control circuit includes an inverter connected to the latch comparator.

2. The large dynamic range cross-group amplifier according to claim 1, characterized in that: The first common-emitter common-base amplifier includes a first transistor, a second transistor and a first load resistor; the base of the first transistor is set as the input end of the main transimpedance amplifier; the collector of the first transistor is connected to the emitter of the second transistor; the base of the second transistor is connected to a first bias voltage; the collector of the second transistor is connected to one end of the first load resistor; and the other end of the first load resistor is connected to a power supply.

3. The large dynamic range cross-group amplifier according to claim 1, characterized in that: The first emitter follower includes a third transistor and a fourth transistor; the base of the third transistor is connected to the collector of the second transistor in the first common-emitter amplifier; the collector of the third transistor is connected to a power supply; the emitter of the third transistor is connected to the collector of the fourth transistor and serves as the output end of the main transimpedance amplifier; the base of the fourth transistor is connected to a second bias voltage; and the emitter of the fourth transistor is grounded.

4. The large dynamic range cross-group amplifier according to claim 1, characterized in that: The feedback resistor module includes a first transmission gate switch, a second MOS tube and a feedback resistor; the input end of the first transmission gate switch is connected to the input end of the main transimpedance amplifier; the output end of the first transmission gate switch is connected to the drain of the second MOS tube; the source of the second MOS tube is connected to the output end of the main transimpedance amplifier; the gate of the second MOS tube is connected to the bias voltage; one end of the feedback resistor is connected to the input end of the main transimpedance amplifier, and the other end is connected to the output end of the main transimpedance amplifier.

5. The large dynamic range cross-group amplifier according to claim 1, characterized in that: The first common-base amplifier includes a first MOS tube, a seventh transistor and an eighth transistor; the drain of the first MOS tube is connected to the emitter of the first transistor in the first common-emitter common-base amplifier; the gate of the first MOS tube is connected to a fourth bias voltage; the source of the first MOS tube is grounded; the emitter of the seventh transistor is connected to the drain of the first MOS tube; the base of the seventh transistor is connected to the third bias voltage; the collector of the seventh transistor is connected to the emitter of the eighth transistor; the base of the eighth transistor is connected to the collector of the eighth transistor and is connected to a power supply.

6. The large dynamic range cross-group amplifier according to claim 1, characterized in that: The emitter of the transistor is connected to the emitter of the second transistor in the first cascode amplifier, the base of the transistor is connected to the fifth bias voltage, the collector of the transistor is connected to one end of the load resistor; the other end of the load resistor is connected to a power supply.

7. The large dynamic range cross-group amplifier according to claim 1, characterized in that: The second emitter follower includes a fifth transistor and a sixth transistor; the base of the fifth transistor is connected to the base of the third transistor in the first emitter follower; the collector of the fifth transistor is connected to a power supply; the emitter of the fifth transistor is connected to the collector of the sixth transistor, the base of the sixth transistor is connected to the output end of the second transmission gate switch, and the emitter of the sixth transistor is grounded; the input end of the second transmission gate switch is connected to the base of the fourth transistor in the first emitter follower; one end of the feedback capacitor is connected to the collector of the sixth transistor.

8. The large dynamic range cross-group amplifier according to claim 1, characterized in that: The low-pass filter includes a filter resistor and a filter capacitor; one end of the filter resistor is connected to the output end of the main transimpedance amplifier, and the other end is connected to one end of the filter capacitor and connected to the positive input end of the latch comparator, the other end of the filter capacitor is grounded, the reverse input end of the latch comparator is connected to a reference voltage, and the output of the latch comparator is set to a voltage signal.

9. The large dynamic range cross-group amplifier according to claim 1, characterized in that: The bias voltage control circuit also includes a third transmission gate switch and a fourth transmission gate switch; the input end of the third transmission gate switch is connected to the first bias voltage, and the output end of the third transmission gate switch is connected to the fifth bias voltage; the input end of the inverter receives the voltage signal in the decision circuit, the output end of the inverter controls the shutdown of the fourth transmission gate switch, the output end of the fourth transmission gate switch is connected to the fifth bias voltage, and the input end of the fourth transmission gate switch is grounded.

10. An optical fiber communication system, characterized in that: A large dynamic range cross-group amplifier comprising any one of claims 1-9.

Images