Power amplifier circuit

Abstract

Provided is a power amplifier circuit capable of suppressing gain fluctuations associated with switching of operation modes. A power amplifier circuit, which has a two-stage structure in which a driving stage amplifier and a power stage amplifier are connected in series, is provided with: a first switching circuit that switches between conduction and non-conduction between a node between the driving stage amplifier and the power stage amplifier and an output terminal; and a second switching circuit that switches between conduction and non-conduction between the power stage amplifier and the output terminal. The power amplifier circuit has: a first mode in which the first switching circuit is turned on and the second switching circuit is turned off; and a second mode in which the first switching circuit is turned off and the second switching circuit is turned on. When transitioning from the first mode to the second mode, the second switching circuit is turned on, and then the first switching circuit is turned off. When transitioning from the second mode to the first mode, the first switching circuit is turned on, and then the second switching circuit is turned off.

Description

Technical Field

[0001] The invention relates to a power amplifier circuit. Background Art

[0002] Conventionally, a technology for switching an operation mode according to the magnitude of output power in a power amplifier circuit used for wireless communication or the like has been disclosed (for example, Patent Document 1). Patent Document 1 illustrates, as an example of a method for switching an operation mode, a structure in which a bypass switch circuit is provided for bypassing a power stage amplifier when low output power is required.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application No. 2006-512847

[0006] In a structure that uses a bypass switch circuit to switch the high-frequency signal path, the high-frequency signal path is cut off according to the switch timing, which sometimes causes a decrease in gain. In addition, sometimes an overshoot occurs when switching from a low-power mode to a high-power mode, and it takes time for the gain to stabilize after the mode switching. This gain change associated with the switching of the operation mode may become the main cause of communication errors. Summary of the invention

[0007] Problem that the invention aims to solve

[0008] The present invention has been made in view of the above circumstances, and an object of the present invention is to realize a power amplifier circuit capable of suppressing gain fluctuations associated with switching of operation modes.

[0009] Technical solutions to solve problems

[0010] A power amplifier circuit according to one aspect of the present invention is a two-stage power amplifier circuit in which a driver stage amplifier and a power stage amplifier are connected in series, and comprises: a first switch circuit for switching between the conduction and non-conduction of a node between the driver stage amplifier and the power stage amplifier and an output terminal; and a second switch circuit for switching between the conduction and non-conduction of the power stage amplifier and the output terminal, the power amplifier circuit having: a first mode in which the first switch circuit is turned on and the second switch circuit is set to non-conduction; and a second mode in which the first switch circuit is set to non-conduction and the second switch circuit is turned on, and when transitioning from the first mode to the second mode, the second switch circuit is turned on and then the first switch circuit is set to non-conduction, and when transitioning from the second mode to the first mode, the first switch circuit is turned on and then the second switch circuit is set to non-conduction.

[0011] With this configuration, it is possible to suppress gain fluctuations associated with switching of the operation mode.

[0012] Effects of the Invention

[0013] According to the present invention, it is possible to realize a power amplifier circuit capable of suppressing gain fluctuations associated with switching of operation modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a diagram showing the structure of a power amplifier circuit according to an embodiment.

[0015] Figure 2 : is a timing chart showing an example of control timing in a conventional example.

[0016] Figure 3A It is a diagram showing the control state of the switching element in LPM.

[0017] Figure 3B It is a diagram showing the control state of the switching element in HPM.

[0018] Figure 4 It is a diagram showing a configuration example of a switching element.

[0019] Figure 5A This is a diagram showing an example of the operation of a switching element when switching from LPM to HPM in a conventional example.

[0020] Figure 5B This is a diagram showing an operation example of a switching element when transitioning from HPM to LPM in a conventional example.

[0021] Figure 6 This is a conceptual diagram showing an example of gain change when switching from LPM to HPM in a conventional example.

[0022] Figure 7 : is a timing chart showing an example of control timing of the power amplifier circuit according to the embodiment.

[0023] Figure 8 This is a block diagram showing an example of the internal structure of the control circuit.

[0024] Fig.9A FIG. 1 is a first diagram showing an operation example of a switching element during mode transition in the power amplifier circuit according to the embodiment.

[0025] Fig. 9B FIG. 2 is a second diagram showing an operation example of a switching element during mode transition in the power amplifier circuit according to the embodiment.

[0026] Fig.10: is a timing chart showing an example of control timing of the power amplifier circuit according to the comparative example.

[0027] Fig.11A It is a diagram showing an operation example of the switching element when the LPM is changed to the HPM in the comparative example.

[0028] Fig. 11B 1 is a diagram showing a loop path during mode transition in the power amplifier circuit according to the embodiment.

[0029] Fig.12 : is a timing chart showing an example of control timing of the power amplifier circuit according to the modification of the embodiment.

[0030] Description of Reference Numerals

[0031] 1: Power amplifier circuit;

[0032] 2: Si (silicon) substrate;

[0033] 3: GaAs (gallium arsenide) substrate;

[0034] 21: 1st switch circuit;

[0035] 22: 2nd switch circuit;

[0036] 23: Control circuit;

[0037] DRV: driver stage amplifier;

[0038] PA: power stage amplifier;

[0039] RFin: input terminal;

[0040] RFout: output terminal;

[0041] SW1_1, SW1_2: first switch element;

[0042] SW2: the second switch element;

[0043] SW3: The third switch element. DETAILED DESCRIPTION

[0044] Hereinafter, the power amplifier circuit involved in the embodiment and its variant examples will be described in detail based on the accompanying drawings. In addition, the present invention is not limited to the embodiment and its variant examples. The embodiment and its variant examples are for illustration only, and it is self-evident that partial replacement or combination of the structures shown in the embodiment and its variant examples can be performed. In the variant examples of the embodiment, the description of the matters common to the embodiment is omitted, and only the differences are described. In particular, the same effects based on the same structure will not be mentioned repeatedly in the variant examples of the embodiment.

[0045] Figure 1 It is a diagram showing the structure of a power amplifier circuit according to an embodiment. Figure 1 The power amplifier circuit 1 shown is a two-stage RF power amplifier in which a driver stage amplifier DRV and a power stage amplifier PA are connected in series. The power amplifier circuit 1 amplifies a high-frequency signal input from an input terminal RFin and outputs it from an output terminal RFout. In addition, although not shown in the figure, matching circuits are provided at the input end and output end of the power amplifier circuit, and between the driver stage amplifier DRV and the power stage amplifier PA.

[0046] The power amplifier circuit 1 according to the embodiment has, as operation modes, a low power mode (Low Power Mode, hereinafter also referred to as "LPM") for operating at a relatively low output power, and a high power mode (High Power Mode, hereinafter also referred to as "HPM") for operating at a relatively high output power. In the present disclosure, the low power mode (LPM) corresponds to the first mode. In addition, in the present disclosure, the high power mode (HPM) corresponds to the second mode.

[0047] The power amplifier circuit 1 includes a first switch circuit 21 , a second switch circuit 22 , and a control circuit 23 as components for switching an operation mode.

[0048] The first switch circuit 21 switches between conduction and non-conduction between a node between the driver stage amplifier DRV and the power stage amplifier PA and the output terminal RFout.

[0049] The first switch circuit 21 includes first switch elements SW1_1, SW1_2 and a third switch element SW3. The first switch elements SW1_1 and SW1_2 are connected in series between a node between the driver stage amplifier DRV and the power stage amplifier PA and an output terminal RFout. The third switch element SW3 is connected in a branch connection between a node between the first switch elements SW1_1 and SW1_2 and a ground potential.

[0050] The second switch circuit 22 switches between conduction and non-conduction between the power stage amplifier PA and the output terminal RFout.

[0051] The second switch circuit 22 includes a second switch element SW2. The second switch element SW2 is connected in series between the power stage amplifier PA and the output terminal RFout.

[0052] In the present disclosure, the control circuit 23 performs ON / OFF control of the first switch elements SW1_1 and SW1_2 , the second switch element SW2 , and the third switch element SW3 . In the present disclosure, the control circuit 23 performs bias control of the power stage amplifier PA.

[0053] exist Figure 1 In the structure shown, the driver stage amplifier DRV, the first switch circuit 21, the second switch circuit 22, and the control circuit 23 are composed of, for example, a silicon device (integrated circuit; IC) including a field effect transistor (FET) formed on a Si (silicon) substrate 2. In addition, the power stage amplifier PA is composed of, for example, a HBT device (integrated circuit; IC) including a heterojunction bipolar transistor (HBT) formed on a GaAs (gallium arsenide) substrate 3.

[0054] Figure 2 : is a timing chart showing an example of control timing in a conventional example. Figure 3A It is a diagram showing the control state of the switching element in LPM. Figure 3B It is a diagram showing the control state of the switching element in HPM.

[0055] In the present disclosure, an operation mode control signal MODE_CTRL is input from a higher-level control system (not shown) to the control circuit 23. The control circuit 23 performs switching control between LPM and HPM based on the operation mode control signal MODE_CTRL.

[0056] Specifically, under LPM, if Figure 3A As shown, the control circuit 23 controls the first switch elements SW1_1 and SW1_2 to be turned on (ON), the second switch element SW2 and the third switch element SW3 to be turned off (OFF), and the bias of the power stage amplifier PA to be turned off. Thus, a high-frequency signal path shown by a dotted arrow is formed, and the high-frequency signal amplified by the driver stage amplifier DRV is output from the output terminal RFout.

[0057] In addition, under HPM, if Figure 3B As shown, the control circuit 23 controls the first switch elements SW1_1 and SW1_2 to be turned off, controls the second switch element SW2 and the third switch element SW3 to be turned on, and controls the bias of the power stage amplifier PA to be turned on. As a result, a high-frequency signal path shown by a single-dot chain line arrow is formed, and the high-frequency signal amplified by the driver stage amplifier DRV is further amplified by the power stage amplifier PA and output from the output terminal RFout.

[0058] Figure 4 It is a diagram showing a configuration example of a switching element. Figure 5A This is a diagram showing an example of the operation of a switching element when switching from LPM to HPM in a conventional example. Figure 5B This is a diagram showing an operation example of a switching element when transitioning from HPM to LPM in a conventional example. Figure 6 This is a conceptual diagram showing an example of gain change when switching from LPM to HPM in a conventional example.

[0059] like Figure 4 As shown, the first switching elements SW1_1 and SW1_2, the second switching element SW2, and the third switching element SW3 are each configured by connecting a plurality of FETs in series.

[0060] Figure 4 The timing of the actual on-control of the switching element in the manner shown is delayed relative to the on-control timing. The amount of delay is determined by the gate capacitance and gate resistance corresponding to the size of the FET. Figure 4 The switching element in the manner shown is controlled to be off, and the delay amount of the timing of actual turning off becomes smaller than the delay amount of the timing of turning on control.

[0061] Therefore, in Figure 2 In the timing diagram of the conventional example shown in FIG. Figure 5A As shown in FIG. 1 , when the LPM is changed to the HPM, the turn-on timing of the second switch element SW2 is delayed relative to the turn-off timing of the first switch elements SW1_1 and SW1_2, and the high-frequency signal path may be cut off. Figure 5B As shown, when the mode changes from HPM to LPM, the turning-on timing of the first switching elements SW1_1 and SW1_2 is delayed relative to the turning-off timing of the second switching element SW2 , and the high-frequency signal path may be cut off.

[0062] The gain change period Gain_Change accompanying the switching of the operation mode is defined within a range of, for example, 500 ns to 2 μs. Figure 6 , the following example is schematically shown, that is, when changing from LPM to HPM, the high-frequency signal path is cut off due to the delay of the turn-on timing of the second switch element SW2 relative to the turn-off timing of the first switch elements SW1_1 and SW1_2, resulting in a drop in gain. Figure 6 , an example is schematically shown in which an overshoot occurs when the second switch element SW2 is actually turned on, and the gain is unstable during the gain change period Gain_Change associated with the switching of the operation mode. Such gain changes associated with the switching of the operation mode may become a major cause of communication errors.

[0063] Hereinafter, the switching timing of each switching element that can suppress the gain fluctuation accompanying the switching of the operation mode and the configuration that can realize the switching timing will be described.

[0064] Figure 7 : is a timing chart showing an example of control timing of the power amplifier circuit according to the embodiment. Figure 8 This is a block diagram showing an example of the internal structure of the control circuit. Fig.9A FIG. 1 is a first diagram showing an operation example of a switching element during mode transition in the power amplifier circuit according to the embodiment. Fig. 9B FIG. 2 is a second diagram showing an operation example of a switching element during mode transition in the power amplifier circuit according to the embodiment.

[0065] like Figure 3A As shown in FIG. 1 , in LPM, the first switch elements SW1_1 and SW1_2 are turned on, and the second switch element SW2 and the third switch element SW3 are turned off. When transitioning from LPM to HPM, as shown in FIG. Figure 7 As shown, the control circuit 23 controls the second switch element SW2 to be turned on before the first switch elements SW1_1 and SW1_2 are turned off, and the bias of the power stage amplifier PA is turned on. In other words, when transitioning from LPM to HPM, the control circuit 23 delays the timing of controlling the first switch elements SW1_1 and SW1_2 to be turned off relative to the timing of controlling the second switch element SW2 to be turned on. Figure 8 In the structure shown in the figure, the turn-off control timing delay of the first switch elements SW1_1 and SW1_2 can be controlled by Figure 8 The R1C1 circuit is set with respect to the switching timing from LPM to HPM of the operation mode control signal MODE_CTRL.

[0066] If the second switch element SW2 is turned on, Fig.9A As shown in FIG. 1 , both a high-frequency signal path (dashed line) based on LPM and a high-frequency signal path (single-dot chain line) based on HPM are formed. Then, the first switch elements SW1_1 and SW1_2 are turned off, thereby Fig. 9B As shown, the LPM-based high-frequency signal path (dashed line) is cut off.

[0067] exist Fig. 9B In the state shown, a loop path (two-dot chain line) of the high-frequency signal of the HPM is formed by the capacitance components of the first switch elements SW1_1 and SW1_2 , and good reverse isolation may not be obtained.

[0068] Therefore, the control circuit 23 controls the third switch element SW3 to turn on after controlling the first switch elements SW1_1 and SW1_2 to turn off. That is, the control circuit 23 delays the timing of the third switch element SW3 to turn on relative to the timing of the first switch elements SW1_1 and SW1_2 to turn off. Thus, the reverse isolation under HPM can be well maintained. Figure 8 In the structure shown in FIG. 1 , the turn-on control timing delay amount of the third switch element SW3 can be controlled by Figure 8 The R3C3 circuit is set with respect to the switching timing from LPM to HPM of the operation mode control signal MODE_CTRL.

[0069] By turning on the third switch element SW3, the capacitance components of the first switch elements SW1_1 and SW1_2 are grounded, and the control state of the switch elements becomes Figure 3B The control state of the switch element under HPM shown in the figure is that the high frequency signal amplified by the driver stage amplifier DRV is further amplified by the power stage amplifier PA and output from the output terminal RFout.

[0070] like Figure 3B As shown in FIG. 1 , in HPM, the first switch elements SW1_1 and SW1_2 are turned off, and the second switch element SW2 and the third switch element SW3 are turned on. When transitioning from HPM to LPM, as shown in FIG. Figure 7 As shown, the control circuit 23 controls the first switch elements SW1_1 and SW1_2 to turn on, and controls the third switch element SW3 to turn off, before controlling the second switch element SW2 to turn off. In other words, when transitioning from HPM to LPM, the control circuit 23 delays the timing of controlling the second switch element SW2 to turn off relative to the timing of controlling the first switch elements SW1_1 and SW1_2 to turn on. Figure 8 In the structure shown in FIG. 1 , the turn-off control timing delay amount of the second switch element SW2 can be controlled by Figure 8 The R2C2 circuit is set with respect to the switching timing from HPM to LPM of the operation mode control signal MODE_CTRL.

[0071] If the first switch elements SW1_1 and SW1_2 are controlled to be on, and the third switch element SW3 is controlled to be off, then Fig.9A As shown in FIG. 1 , both a high-frequency signal path (dashed line) based on LPM and a high-frequency signal path (single-dot chain line) based on HPM are formed. Then, the second switch element SW2 is controlled to be off, and the control state of the switch element becomes Figure 3AThe control state of the switch element under LPM shown in FIG. Then, the control circuit 23 performs a bias-off control on the power stage amplifier PA. As a result, the high-frequency signal amplified by the driver stage amplifier DRV is output from the output terminal RFout. Figure 8 In the structure shown in FIG. 1 , the bias disconnection control timing delay amount of the power stage amplifier PA can be controlled by Figure 8 The RPCP circuit sets the switching timing from HPM to LPM relative to the action mode control signal MODE_CTRL.

[0072] Fig.10 : is a timing chart showing an example of control timing of the power amplifier circuit according to the comparative example. Fig.11A It is a diagram showing an operation example of the switching element when the LPM is changed to the HPM in the comparative example.

[0073] exist Fig.10 In the comparative example shown, the following example is shown, that is, when the LPM is changed to the HPM, the third switch element SW3 is controlled to be turned on before the first switch elements SW1_1 and SW1_2 are controlled to be turned off. Fig.11A As shown, a short-circuit path to the ground potential is formed in both the high-frequency signal path (dashed line) by the LPM and the high-frequency signal path (single-dot chain line) by the HPM.

[0074] Fig. 11B FIG. 1 is a diagram showing a loop path during mode transition in a power amplifier circuit according to an embodiment of the present invention. Fig.9A When both the high-frequency signal path (dashed line) based on LPM and the high-frequency signal path (single-dot chain line) based on HPM are formed as shown, Fig. 11B The loop path is shown by the double-dashed arrow in FIG. In this loop path, the phase changes due to the impedance of the circuit, which may form a positive feedback loop and cause the power stage amplifier PA to oscillate.

[0075] Fig.12 : is a timing chart showing an example of control timing of the power amplifier circuit according to the modification of the embodiment.

[0076] exist Fig.12In the timing diagram shown, during the period from the on-control timing of the bias of the power stage amplifier PA when transitioning from LPM to HPM to the off-control timing of the first switch elements SW1_1 and SW1_2, and during the period from the on-control timing of the first switch elements SW1_1 and SW1_2 when transitioning from HPM to LPM to the off-control timing of the bias of the power stage amplifier PA, the bias of the power stage amplifier PA is set to a low bias (LOW) lower than the normal bias (HIGH) under HPM. This can prevent the power stage amplifier PA from oscillating when forming a loop path.

[0077] The above-mentioned embodiments and their modifications are intended to facilitate understanding of the present invention and are not intended to limit the present invention. The present invention can be modified / improved without departing from the gist of the present invention, and equivalents thereof are also included in the present invention.

[0078] In addition, the present disclosure can take the following structures as described above or in place of the above structures.

[0079] (1) A power amplifier circuit according to one aspect of the present invention is a two-stage power amplifier circuit in which a driver stage amplifier and a power stage amplifier are connected in series, and comprises: a first switch circuit for switching between conduction and non-conduction between a node between the driver stage amplifier and the power stage amplifier and an output terminal; and a second switch circuit for switching between conduction and non-conduction between the power stage amplifier and the output terminal, the power amplifier circuit having: a first mode in which the first switch circuit is turned on and the second switch circuit is set to non-conduction; and a second mode in which the first switch circuit is set to non-conduction and the second switch circuit is turned on, and when transitioning from the first mode to the second mode, the second switch circuit is turned on and then the first switch circuit is set to non-conduction, and when transitioning from the second mode to the first mode, the first switch circuit is turned on and then the second switch circuit is set to non-conduction.

[0080] With this structure, it is possible to prevent the first switch circuit and the second switch circuit from being non-conductive when transitioning from the first mode to the second mode. In addition, it is possible to prevent the first switch circuit and the second switch circuit from being non-conductive when transitioning from the second mode to the first mode. Thus, it is possible to suppress gain fluctuations associated with switching of the operation mode.

[0081] (2) Preferably, in the power amplifier circuit of (1) above, the first switch circuit at least includes: a first switch element connected in series between a node between the driver stage amplifier and the power stage amplifier and an output terminal; the second switch circuit includes: a second switch element connected in series between the power stage amplifier and the output terminal; and the power amplifier circuit at least further includes: a control circuit for controlling on and off the first switch element and the second switch element; when transitioning from the first mode to the second mode, the control circuit controls on the second switch element and then controls off the first switch element; when transitioning from the second mode to the first mode, the control circuit controls on the first switch element and then controls off the second switch element.

[0082] With this structure, it is possible to prevent the first switch element and the second switch element from being disconnected when transitioning from the first mode to the second mode. In addition, it is possible to prevent the first switch element and the second switch element from being disconnected when transitioning from the second mode to the first mode. Thus, gain fluctuations associated with switching of the operation mode can be suppressed.

[0083] (3) In the power amplifier circuit of (2) above, in the first switching circuit, a plurality of first switching elements are connected in series between a node between the driver stage amplifier and the power stage amplifier and an output terminal, and the first switching circuit further comprises: a third switching element, which is branch-connected between a node between the plurality of first switching elements and a ground potential, and when transitioning from the first mode to the second mode, the control circuit controls the first switching element to be turned off and then controls the third switching element to be turned on, and when transitioning from the second mode to the first mode, the control circuit controls the first switching element to be turned on and controls the third switching element to be turned off.

[0084] With this configuration, it is possible to prevent the third switching element from being turned on while the plurality of first switching elements are turned on, thereby preventing a short-circuit path from being formed between the high-frequency signal path and the ground potential.

[0085] (4) Preferably, in the power amplifier circuit of (3) above, when transitioning from the first mode to the second mode, the control circuit controls the second switch element to be turned on, and controls the bias of the power stage amplifier to be turned on, and when transitioning from the second mode to the first mode, the control circuit controls the second switch element to be turned off, and then controls the bias of the power stage amplifier to be turned off.

[0086] (5) In the power amplifier circuit of (4) above, when transitioning from the first mode to the second mode, the control circuit controls the second switch element to be turned on, and sets the bias of the power stage amplifier to a low bias lower than the bias of the power stage amplifier in the second mode during a period from the turn-on control timing of the bias of the power stage amplifier to the turn-off control timing of the first switch element, and when transitioning from the second mode to the first mode, the control circuit sets the bias of the power stage amplifier to the low bias during a period from the turn-on control timing of the first switch element to the turn-off control timing of the bias of the power stage amplifier.

[0087] With this configuration, when both the first switching element and the second switching element are turned on, the phase changes according to the impedance to form a positive feedback loop, and thus the oscillation of the power stage amplifier can be suppressed.

[0088] (6) In any one of the power amplifier circuits described in (1) to (5) above, the driver stage amplifier is a silicon device formed on a Si substrate, and the power stage amplifier is a HBT device formed on a GaAs substrate.

[0089] With this structure, the driver stage amplifier, the first bias circuit, and the second bias circuit can be formed integrally on the Si substrate. In addition, the influence of heat generated by the power stage amplifier on the driver stage amplifier can be suppressed.

[0090] According to the present disclosure, it is possible to realize a power amplifier circuit capable of suppressing gain fluctuations associated with switching of operation modes.

Claims

1. A power amplifier circuit is a two-stage power amplifier circuit in which a driver stage amplifier and a power stage amplifier are connected in series, and has: a first switch circuit for switching between conduction and non-conduction of a node between the driver stage amplifier and the power stage amplifier and an output terminal; and The second switch circuit switches between the conduction and non-conduction of the power stage amplifier and the output terminal. The power amplifier circuit has: a first mode, making the first switch circuit conductive and setting the second switch circuit non-conductive; and In the second mode, the first switch circuit is set to non-conductive state and the second switch circuit is made conductive. When the first mode is changed to the second mode, the second switch circuit is turned on and then the first switch circuit is turned off. When the second mode is shifted to the first mode, the first switch circuit is turned on and then the second switch circuit is turned off.

2. The power amplifier circuit according to claim 1, wherein: The first switch circuit at least includes: a first switch element connected in series between a node between the driver stage amplifier and the power stage amplifier and an output terminal; The second switch circuit includes: a second switch element connected in series between the power stage amplifier and the output terminal; The power amplifier circuit further includes at least: a control circuit for controlling the on / off of the first switching element and the second switching element. When the first mode is changed to the second mode, the control circuit controls the second switching element to be turned on and then controls the first switching element to be turned off. When transitioning from the second mode to the first mode, the control circuit performs on-control of the first switching element and then performs off-control of the second switching element.

3. The power amplifier circuit according to claim 2, wherein: In the first switch circuit, a plurality of first switch elements are connected in series between a node between the driver stage amplifier and the power stage amplifier and an output terminal. The first switch circuit further includes: a third switch element connected in a branched manner between a node between the plurality of first switch elements and a ground potential; When the first mode is changed to the second mode, the control circuit controls the first switching element to be turned off and then controls the third switching element to be turned on. When the second mode is shifted to the first mode, the control circuit controls the first switching element to be turned on and controls the third switching element to be turned off.

4. The power amplifier circuit according to claim 3, wherein: When the first mode is changed to the second mode, the control circuit controls the second switch element to be turned on and controls the bias of the power stage amplifier to be turned on. When transitioning from the second mode to the first mode, the control circuit performs off-control of the second switching element and then performs off-control of the bias of the power stage amplifier.

5. The power amplifier circuit according to claim 4, wherein: When transitioning from the first mode to the second mode, the control circuit controls the second switch element to be turned on, and sets the bias of the power stage amplifier to a low bias lower than the bias of the power stage amplifier in the second mode during a period from the turn-on control timing of the bias of the power stage amplifier to the turn-off control timing of the first switch element. When transitioning from the second mode to the first mode, the control circuit sets the bias of the power stage amplifier to the low bias during a period from an on control timing of the first switching element to an off control timing of the bias of the power stage amplifier.

6. The power amplifier circuit according to any one of claims 1 to 5, wherein: The driver stage amplifier is a silicon device formed on a Si substrate. The power stage amplifier is a HBT device formed on a GaAs substrate.

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