Synchronous processing system integrating multi-chip multi-channel radio frequency receiving and transmitting direct sampling

Abstract

The invention discloses a synchronous processing system integrating multi-chip multi-path radio frequency receiving and transmitting direct sampling. According to the disclosed scheme, a plurality of radio frequency integrated transceivers are adopted to directly complete multi-channel radio frequency transceiving and direct sampling synchronization processing, a transceiving intermediate frequency secondary frequency conversion and processing scheme in traditional millimeter wave communication is replaced, and a full-digital DDS method is adopted to precisely realize a multi-channel radio frequency transceiving clock synchronization method of any variable clock in a certain frequency band. Clock phase adjustment is carried out on input synchronous reference signals of the multiple radio frequency transceivers, it is guaranteed that link data transmitted and received by the multiple radio frequency transceivers are transmitted and received to the system processing module through the synchronous interface, and multi-channel radio frequency transmitting and receiving synchronous collection is achieved. According to the invention, the requirements of a high-speed ADC, a DAC and a clock generation circuit can be effectively reduced, the integration level is extremely high, the application scene is more flexible, and the generalization degree is higher.

Description

Technical Field

[0001] The present application relates to the technical field of millimeter wave communication ranging, and in particular to a synchronous processing system integrating multi-chip multi-channel radio frequency transceiver direct sampling. Background Art

[0002] Millimeter wave signals have a high frequency band and a large bandwidth. After passing through the millimeter wave frequency conversion channel, it is usually difficult to directly convert them into zero intermediate frequency baseband analog signals. Secondary frequency conversion is required, and the selection of secondary frequency conversion scheme is particularly important for the realization of the entire system.

[0003] Compared with traditional intermediate frequency transceiver sampling or baseband sampling, the designed secondary frequency conversion microwave channel is complex, the transceiver frequency is fixed and cannot be flexibly changed within a wideband range, which makes the overall weight, power consumption and volume of the system relatively large, and it is not easy to realize the miniaturization, integration and intelligence of the RF transceiver acquisition channels. Summary of the invention

[0004] In view of the defects or shortcomings of the prior art, the present invention provides a synchronous processing system integrating multiple chips and multiple-channel radio frequency transceivers for direct sampling.

[0005] To this end, the present invention provides an integrated multi-chip multi-channel RF transceiver direct sampling synchronous processing system comprising: a transceiver matching and RF transceiver sampling module, a system processing module and a synchronous clock DDS generation module;

[0006] The transceiver matching and RF transceiver sampling module includes N RF transceivers, each RF transceiver is provided with M signal receiving ports and M signal transmitting ports, each signal receiving port is connected to a receiving matcher, and each signal transmitting port is connected to a transmitting matcher; wherein N is a natural number greater than or equal to 2, and M is 1 or 2;

[0007] The system processing module includes a central processing module and N data interface processing units;

[0008] The synchronous clock DDS generation module includes a clock driver, an NCO accumulator, a DAC converter, a low-pass filter and a clock regulator;

[0009] in:

[0010] The clock driver performs multi-channel homologous clock driving processing on the input external clock CLKIN to obtain two output clocks CLKOUT1 and CLKOUT2;

[0011] The NCO accumulator accumulates phase data based on the phase quantization truncation enable generated by the system processing module and uses the output clock CLKOUT2 as a reference clock, and then outputs the accumulated phase data through a digital lookup table;

[0012] The DAC converter uses CLKOUT1 as a reference clock, performs DAC conversion processing on the data output by the NCO accumulator, and generates a sine wave mapping clock signal;

[0013] The low-pass filter performs low-pass filtering on the sine wave mapping clock signal, and then outputs the clock CLKOUT3 after clock shaping;

[0014] The clock regulator multiplies the clock CLKOUT3 and outputs 2N+1 co-source and co-phase clock signals and N+1 co-source low-speed reference signals; the 2N+1 co-source and co-phase clock signals are respectively transmitted to each RF transceiver, the central processing module and each data interface processing unit, and serve as the reference clock input of the corresponding RF transceiver, the global clock input of the system and the reference clock input of the corresponding data interface processing unit; the N+1 co-source reference signals are respectively transmitted to each RF transceiver and the central processing module, and serve as the reference signal input of the corresponding RF transceiver and the global reference input of the system;

[0015] The central processing module generates a synchronization pulse for controlling N radio frequency transceivers to work under the synchronization pulse condition; the central processing module generates a phase quantization truncation enable using an externally input second pulse;

[0016] The receiving matcher adjusts the amplitude and impedance of the input signal and converts the single-ended signal into a differential signal through a radio frequency transformer to obtain a corresponding differential input signal;

[0017] The RF transceiver performs frequency multiplication, phase locking and frequency division processing on the reference clock input and the reference signal input to obtain the sampling clock, transmission clock and system reference clock required for the operation of the RF transceiver;

[0018] And the RF transceiver performs receiving ADC link processing on each input differential input signal according to the sampling clock, system reference clock and synchronization pulse signal, obtains corresponding sampling data and inputs it to the data interface processing unit;

[0019] The RF transceiver performs transmit DAC link processing on the sampled data from the data interface processing unit according to the transmit clock, the system reference clock and the synchronization pulse signal to obtain a differential RF signal;

[0020] The transmitting matcher converts the corresponding differential RF signal into a single-ended signal and then adjusts the amplitude and impedance to obtain the transmitting signal of the corresponding transmitting port.

[0021] An optional solution is that the system processing module adopts an FPGA processing module. That is, the NCO accumulator and its related functions "accumulate phase data based on the phase quantization truncation enable generated by the system processing module, use the output clock CLKOUT2 as the reference clock, and then output the phase data accumulation data through a digital lookup table" are implemented in the FPGA processing module using software.

[0022] An optional solution is that the data interface processing unit adopts a GTH physical interface unit of the JESD204C protocol; each RF transceiver is connected to the corresponding GTH physical interface unit of the JESD204C protocol via a Serdes data interface of the JESD204C protocol.

[0023] An optional solution is that each channel of received and transmitted data between the RF transceiver and the GTH physical interface unit corresponds to two Serdes data lanes.

[0024] An optional solution is that the NCO accumulator is integrated into the FPGA processing module.

[0025] An optional solution is that the receiving ADC link processing includes signal energy adjustment, ADC sampling, AGC amplification and down-conversion processing performed in sequence.

[0026] An optional solution is that the transmit DAC link processes interpolation filtering, up-conversion, DAC conversion and signal amplification in sequence.

[0027] Compared with the prior art, this application has the following beneficial effects:

[0028] (1) The present invention adopts a radio frequency transceiver chip to construct a fully digital, universal, flexible, integrated, multi-channel radio frequency transceiver direct acquisition, processing and synchronization system, and configures a digital, flexible and variable clock scheme and a transceiver analog front end, which can more flexibly and easily realize a fully digital, intelligent secondary frequency conversion transceiver front end, thereby realizing the integration of the secondary frequency conversion channel and the digital transceiver acquisition, making the system more conducive to integration, miniaturization, intelligence and large-scale development, and more conducive to realizing the complex functions of software radio and flexible and variable applications in multiple scenarios.

[0029] (2) The present invention adopts a fully digital DDS method to realize a multi-channel RF transceiver clock synchronization method with any variable clock within a certain frequency band. By adjusting the clock phase synchronization of the input references of multiple RF transceivers, the link data received and sent by the multiple RF transceivers are ensured to be transmitted and received by the system processing module through a synchronous interface (such as a JESD204C synchronous interface), thereby realizing multi-channel RF transceiver synchronous collection.

[0030] In the preferred solution, a high-bit NCO can be used in the digital domain to improve frequency accuracy and reduce time-frequency errors, which has little impact on practical applications such as ranging. At the same time, the ranging value will not drift due to deviation within 1PPS, which far exceeds the error requirements of frequency accuracy and ranging zero value.

[0031] The present invention is applicable to different millimeter wave communication ranging (including phased array reception processing and MIMO system) and other scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The present invention is a block diagram of the structural principle of a synchronous processing system solution integrating multiple chips and multiple channels of RF transceivers for direct sampling.

[0033] Figure 2 A spectrum diagram showing a plurality of different frequency points output by a radio frequency transceiver transmitting DAC link in a system according to an embodiment of the present invention; Figure 2 A is the spectrum when outputting 2.294GHz intermediate frequency. In the figure, Scale / Div 10dB means that each grid of the vertical axis is 10dB, RefLevel 23.00dBm means that the maximum reference of the vertical axis is 23dBm, Genter 2.29400GHz is the center frequency of the signal, ResBW 180kHz is the set resolution bandwidth, #Video BW 10kHz is the set video bandwidth, Span 20.00MHz is the signal bandwidth range of the horizontal axis analysis, and Sweep 8.73ms (1001pts) is the sweep time of the test signal; Figure 2 B is the integrated power when outputting 2.294GHz intermediate frequency; Figure 2 C is the spectrum of the 4.8GHz intermediate frequency output with a shaping factor of 0.35; Figure 2 D is the integrated power of the 4.8 GHz intermediate frequency output with a forming factor of 0.35.

[0034] Figure 3 This is a waveform diagram of the signal collection received by the ADC link and the JESD204C link establishment status of the system heavy radio frequency transceiver in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] Unless otherwise specified, the scientific and technical terms used herein are understood according to the knowledge of ordinary technicians in the relevant fields.

[0036] The present invention adopts multiple RF integrated transceivers for direct sampling (internal integrated ADC, DAC, clock phase-locked PLL, digital up and down conversion, filtering and other functions), which can directly receive and transmit intermediate frequency band (S band, L band, C band or X band) signals, replacing the secondary frequency conversion scheme in the existing scheme, and synchronously configuring a digital flexible and variable clock scheme, which can effectively reduce the requirements for high-speed ADC, DAC and clock generation circuits. The RF transceiver direct sampling scheme has extremely high integration, more flexible application scenarios, and higher degree of generalization, which can adapt to future development.

[0037] In the system of the present invention, the synchronous clock DDS generation module provides a synchronous reference clock DCLK / reference signal SYSREF as input to multiple RF transceivers, thereby ensuring that the multiple RF transceivers can generate the same and accurate internal synchronization signal to synchronize the internal clock of the chip.

[0038] The present invention ensures that the output of multiple clocks is synchronized between chips on the basis of completing the synchronization of a single RF transceiver. The present invention adopts the synchronization function of the synchronous clock DDS generation module, that is, an externally provided synchronous clock input CLK_IN generates multiple high-performance clocks and a synchronous pulse input SYNC_IN generated inside the system processing module is given to each RF transceiver. During the process, it is necessary to ensure that the synchronous clock DCLK generated by each RF transceiver has the same phase (in phase) and SYNC_IN arrives at the same time. At the same time, the synchronous synchronous clock DDS generation module provides the required reference signal SYSREF to multiple RF transceivers and the system processing model to ensure data synchronization between each RF transceiver and the system processing module.

[0039] It should be noted that, depending on the application scenarios of the system, the RF transceiver of the system of the present invention receives and transmits different signals. Taking the communication ranging application scenario as an example, the RF transceiver performs synchronous reception or transmission processing on the RF signal carrying ranging information, and after being processed by the system of the present invention, the signal transmission and reception realizes synchronous collection and reception. In addition to the field of communication ranging, the system of the present invention is also applicable to phased array transceiver systems, in which multiple RF transceiver components transmit and receive signals of the same frequency and phase, which can be used for synchronous processing such as improving signal sensitivity and controlling beam direction. It can also be used in traditional mobile communication MIMO systems to realize synchronous transmission and reception of signals in different frequency bands.

[0040] In addition, for specific usage scenarios, the N RF transceivers in the system of the present invention, the receiving and transmitting signals of different RF transceivers can be the same or different. Taking the communication ranging application scenario as an example, when N=2, the receiving and transmitting signals of the two RF transceivers are different, and the receiving signal of one of the RF transceivers can be an S-band signal, and the transmitting signal can be a C-band signal; the receiving signal of the other RF transceiver can be an S-band signal, and the transmitting signal can be a C-band signal. In some schemes, for the M transceiver paths of the RF transceiver, the receiving and transmitting signals between different paths can be the same or different. Taking the communication ranging application scenario as an example, when M=2, the two transceiver paths of the RF transceiver are different, and the receiving signal of one of the RF transceivers can be an S-band signal, and the transmitting signal can be a C-band signal; the receiving signal of the other RF transceiver can be a C-band signal, and the transmitting signal can be an X-band signal.

[0041] The exemplary embodiments of the present application will be described below in conjunction with the accompanying drawings. For the sake of clarity and conciseness, not all features of the actual embodiments are described in the specification. However, it should be understood that many implementation-specific decisions can be made in the process of developing any such actual embodiments in order to achieve the specific goals of the developer, and these decisions may vary from embodiment to embodiment.

[0042] It is also necessary to explain here that, in order to avoid obscuring the present application due to unnecessary details, only the device structure closely related to the scheme according to the present application is shown in the drawings, while other details that are not closely related to the present application are omitted.

[0043] It should be understood that the present application is not limited to the described implementation forms due to the following description with reference to the accompanying drawings. In this article, where feasible, the embodiments can be combined with each other, features between different embodiments can be replaced or borrowed, and one or more features can be omitted in one embodiment.

[0044] Example:

[0045] See also Figure 1 As shown, based on the solution of the present invention, the transceiver matching and RF transceiver sampling module in the synchronous processing system of this embodiment includes two RF transceivers, each of which supports the transceiver of two signals;

[0046] The system processing module of this embodiment adopts an FPGA processing module, and the FPGA processing module is provided with a central processing module and two data interface processing units, wherein the data interface processing unit adopts a GTH physical interface unit of the JESD204C protocol; each RF transceiver is connected to the corresponding GTH physical interface unit of the JESD204C protocol through a Serdes data interface of the JESD204C protocol, and each channel of transceiver data between the RF transceiver and the GTH physical interface unit corresponds to two Serdes data lanes;

[0047] The input clock of the clock regulator in the synchronous clock DDS generation module of the embodiment system is CLKOUT3, and the frequency multiplication outputs 5 same-source and same-phase clock signals DCLK1, DCLK2, DCLK, DCLK_GTH1, DCLK_GTH2 and 3 same-source low-speed reference signals SYSREF1, SYSREF2, SYSREF;

[0048] 5 channels of same-source and same-phase clock signals DCLK1, DCLK2, DCLK, DCLK_GTH1, and DCLK_GTH2 are respectively sent to the reference clock input of RF transceiver 1, the reference clock input of RF transceiver 2, the global clock input of FPGA, the reference clock input of GTH1 physical interface data, and the reference clock input of GTH2 physical interface data;

[0049] Three homologous low-speed reference signals SYSREF1, SYSREF2, and SYSREF are respectively sent to RF transceiver 1 as reference signal input, RF transceiver 2 as reference signal input, and FPGA as global reference input;

[0050] Two channels of synchronous clock / reference signals DCLK1 / SYSREF1 and DCLK2 / SYSREF2 of the same source are used as the reference clock and reference signal input of the two RF transceivers respectively. The reference clock / reference signal input enters the RF transceiver 1 and RF transceiver 2 and undergoes frequency multiplication, phase-locked and frequency division processing to obtain the sampling clock ADC_CLK1 / ADC_CLK2 required by the receiving ADC link, the transmitting DAC link DAC_CLK1 / DAC_CLK2, and the system reference clock SYSCLK1 / SYSCLK2 required by the RF transceiver.

[0051] The central processing module outputs the synchronization pulse SYNC_IN to the two RF transceivers, and simultaneously receives the synchronization pulse indication output signal SYNC_OUT1 of RF transceiver 1 and the synchronization pulse indication output signal SYNC_OUT2 of RF transceiver 2;

[0052] The central processing module of this embodiment uses the external input second pulse 1PPS to synchronously generate a phase quantization truncation enable for each 1PPS and transmit it to the NCO phase accumulator after receiving it through the FPGA;

[0053] The devices involved in the system of the present invention can adopt existing commercially available related devices. The transceiver RF transceiver of this embodiment adopts CX8242KAN produced by Hangzhou Chengxin Technology Co., Ltd. (AD9371 produced by ADI or BMRA9009 of Aerospace 772 Institute are also applicable to the present invention); the receiving matcher performs corresponding resistance π attenuation adjustment to a suitable dynamic range and meet the input signal sensitivity according to different frequency bands and input signal sizes when single-ended, and performs impedance matching, and converts it to a differential signal after single-ended. The receiving RF transformer adopts the broadband 1:1 RF transformer TK19-002 of Chengdu Yaguang Technology; the transmitting matcher converts the transmitted differential signal into a single-ended signal. The transmitting RF transformer used in this embodiment is the broadband 1:2 RF transformer BAL-2-0006GB produced by Guiyang Sunlord Xunda. After converting to single-ended, the resistance π attenuation adjustment and impedance matching are performed according to the power size and frequency band of the output signal;

[0054] The clock driver adopts JSCLK954 produced by China Electronics 58 Institute; the DAC converter adopts DAC5675 produced by TI; the low-pass filter adopts 9th-order LC filter; the clock shaping adopts JSCLK905 produced by China Electronics 58 Institute; the clock regulator adopts LMK04832 produced by TI (hmc7044 produced by AD or CX3E04 produced by Hangzhou Chengxin Technology Co., Ltd. is also applicable to the present invention); the NCO accumulator and its related phase data accumulation and digital lookup table functions of this embodiment are implemented in FPGA by software;

[0055] The FPGA processing module uses the XCVU9P hardware platform produced by Xilinx and implements software processing in VIVADO2019.3.

[0056] The system of this embodiment is implemented in VIVADO software, FPGA is used to control the RF transceiver and its peripherals and perform data processing, and a spectrum analyzer is used to measure the DAC link output frequency, bandwidth, power size, etc. of the transceiver RF Figure 2 The results shown, Figure 2 The frequency spectrum diagram of some different frequency points of the RF transceiver transmit DAC link output is shown; Figure 2 A is the spectrum when outputting 2.294GHz intermediate frequency, Figure 2 B is the integrated power when outputting 2.294GHz intermediate frequency. Figure 2 C is the spectrum of the 4.8GHz intermediate frequency output with a shaping coefficient of 0.35. Figure 2D is the integrated power of the 4.8 GHz intermediate frequency output with a forming factor of 0.35.

[0057] The system of this embodiment is implemented in VIVADO software, and FPGA is used to control and process the RF transceiver and its peripherals. By collecting and analyzing the input 4.8GHZ intermediate frequency signal, Figure 3 The waveform diagram of the signal acquisition received by the RF transceiver receiving ADC link and the JESD204C link establishment is shown. Figure 3 The results show that the JESD204C link in the ADC link is successfully established and the received signals are collected synchronously.

[0058] The above are only various implementations of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A synchronous processing system integrating multi-chip multi-channel RF transceiver direct sampling, characterized in that: The system includes: transceiver matching and RF transceiver sampling module, system processing module and synchronous clock DDS generation module; The transceiver matching and RF transceiver sampling module includes N RF transceivers, each RF transceiver is provided with M signal receiving ports and M signal transmitting ports, each signal receiving port is connected to a receiving matcher, and each signal transmitting port is connected to a transmitting matcher; wherein N is a natural number greater than or equal to 2, and M is 1 or 2; The system processing module includes a central processing module and N data interface processing units; The synchronous clock DDS generation module includes a clock driver, an NCO accumulator, a DAC converter, a low-pass filter and a clock regulator; in: The clock driver performs multi-channel homologous clock driving processing on the input external clock CLKIN to obtain two output clocks CLKOUT1 and CLKOUT2; The NCO accumulator accumulates phase data based on the phase quantization truncation enable generated by the system processing module and uses the output clock CLKOUT2 as a reference clock, and then outputs the accumulated phase data through a digital lookup table; The DAC converter uses CLKOUT1 as a reference clock, performs DAC conversion processing on the data output by the NCO accumulator, and generates a sine wave mapping clock signal; The low-pass filter performs low-pass filtering on the sine wave mapping clock signal, and then outputs the clock CLKOUT3 after clock shaping; The clock regulator multiplies the clock CLKOUT3 and outputs 2N+1 co-source and co-phase clock signals and N+1 co-source low-speed reference signals; the 2N+1 co-source and co-phase clock signals are respectively transmitted to each RF transceiver, the central processing module and each data interface processing unit, and serve as the reference clock input of the corresponding RF transceiver, the global clock input of the system and the reference clock input of the corresponding data interface processing unit; the N+1 co-source reference signals are respectively transmitted to each RF transceiver and the central processing module, and serve as the reference signal input of the corresponding RF transceiver and the global reference input of the system; The central processing module generates a synchronization pulse for controlling N radio frequency transceivers to work under the synchronization pulse condition; the central processing module generates a phase quantization truncation enable using an externally input second pulse; The receiving matcher adjusts the amplitude and impedance of the input signal and converts the single-ended signal into a differential signal through a radio frequency transformer to obtain a corresponding differential input signal; The RF transceiver performs frequency multiplication, phase locking and frequency division processing on the reference clock input and the reference signal input to obtain the sampling clock, transmission clock and system reference clock required for the operation of the RF transceiver; And the RF transceiver performs receiving ADC link processing on each input differential input signal according to the sampling clock, system reference clock and synchronization pulse signal, obtains corresponding sampling data and inputs it to the data interface processing unit; The RF transceiver performs transmit DAC link processing on the sampled data from the data interface processing unit according to the transmit clock, the system reference clock and the synchronization pulse signal to obtain a differential RF signal; The transmitting matcher converts the corresponding differential RF signal into a single-ended signal and then adjusts the amplitude and impedance to obtain the transmitting signal of the corresponding transmitting port.

2. The synchronous processing system for integrated multi-chip multi-channel RF transceiver direct sampling according to claim 1, characterized in that: The system processing module adopts an FPGA processing module.

3. The integrated multi-chip multi-channel RF transceiver direct sampling synchronous processing system according to claim 2, characterized in that: The data interface processing unit adopts a GTH physical interface unit of the JESD204C protocol; each radio frequency transceiver is connected to the corresponding GTH physical interface unit of the JESD204C protocol through a Serdes data interface of the JESD204C protocol.

4. The synchronous processing system for integrated multi-chip multi-channel RF transceiver direct sampling according to claim 3, characterized in that: Each channel of received and transmitted data between the RF transceiver and the GTH physical interface unit corresponds to two Serdes data lanes.

5. The integrated multi-chip multi-channel RF transceiver direct sampling synchronous processing system according to claim 2, characterized in that: The NCO accumulator is integrated into the FPGA processing module.

6. The integrated multi-chip multi-channel RF transceiver direct sampling synchronous processing system according to claim 1, characterized in that: The receiving ADC link processing includes signal energy adjustment, ADC sampling, AGC amplification and down-conversion processing performed in sequence.

7. The integrated multi-chip multi-channel RF transceiver direct sampling synchronous processing system according to claim 1, characterized in that: The transmit DAC link processes interpolation filtering, up-conversion, DAC conversion and signal amplification in sequence.

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