Manchester Encoding Communication Check System

Abstract

The present application discloses a Manchester coding communication verification system, which relates to the field of coding. It includes a core ECU and several edge ECUs. An SPI controller is provided inside the edge ECU and is connected to a voltage conversion circuit at the MOSI end and a current conversion circuit at the MISO end. The edge ECU translates the Manchester data to be sent into SPI byte data for caching through the CPU core, performs matching verification on the external level signal, and determines the fault source according to the result. The SPI controller takes over the SPI byte data according to the request and sends and receives data according to the preset coding frequency. When sending, the DMA controller reads the cached SPI byte data and sends it to the SPI controller. When receiving, the SPI controller inputs the external level signal and retrieves and caches it through the DMA controller. This solution utilizes the characteristics of data transmission without CPU intervention of SPI and DMA technologies to improve the processing efficiency of Manchester coding and enhance the flexibility and scalability of system coding verification.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of encoding, and particularly to a Manchester encoding communication verification system. Background Art

[0002] In modern communication technologies, Manchester encoding, as an important data transmission method, is widely used in multiple fields due to its unique advantages, including but not limited to Ethernet, vehicle bus systems, and various industrial buses. The core feature of Manchester encoding is that the transmitted signal does not contain a DC component. This characteristic enables the signal to effectively resist the DC offset problem during long-distance transmission. At the same time, the built-in clock information simplifies the clock recovery process at the receiving end, enhancing the stability and reliability of the system.

[0003] In the automotive fieldbus PSI5, the Manchester current encoding technology is utilized. When this bus is applied among multiple ECUs or sensor networks, the edge ECUs 1 and ECUx are mounted on the PSI5 bus. The ECU determines the vehicle state, such as collision detection, by detecting sensor data on the bus. However, self-verification cannot determine the reasons for ECU and circuit failures, making it difficult to ensure vehicle safety in the case of abnormal external sensor data. Although some Manchester codec chips have emerged on the market to solve this problem, their data processing speed is difficult to maintain, and the external encoding chips will increase the cost. If the edge ECU is used for self-verification, it is necessary to comprehensively consider the CPU response resource utilization problem. The edge ECU not only needs to complete the communication requirements of the PSI5 bus but also needs to complete edge computing control, obtain other sensing data, and communicate with other chips such as the core ECU. In addition, although it costs less to implement Manchester encoding using the timer and general-purpose input / output (GPIO) ports of the ECU core, the efficiency of this method is greatly reduced, and it may also introduce additional delays and uncertainties, affecting the real-time performance and reliability of communication. In application scenarios that require processing a large amount of data or high-frequency communication, the limitations of this method are particularly obvious. Summary of the Invention

[0004] The embodiments of the present application provide a Manchester encoding communication verification system to solve the problems of encoding efficiency and resource utilization rate during system verification by the ECU chip. The system includes a core ECU and several edge ECUs. The edge ECUs are communicatively connected to the core ECU through the PSI5 bus; an SPI controller is provided inside the edge ECU, and the SPI controller is respectively connected to a voltage conversion circuit at the peripheral output MOSI end and a current conversion circuit at the peripheral input MISO end through hardware interfaces; the voltage conversion circuit and the current conversion circuit are connected to the PSI5 bus;

[0005] The edge ECU responds to the encoding request, translates the obtained Manchester data to be translated into SPI byte data through the CPU core and caches it, and performs matching verification on the externally input level signal and the Manchester data to be translated, and determines the fault source according to the matching result;

[0006] The CPU core is connected to the DMA controller and sets a transfer task for the DMA controller according to the encoding request; the SPI controller is connected to the DMA controller, takes over the SPI byte data according to the encoding request, and sends and receives data according to a preset encoding frequency;

[0007] In the sending stage, the cached SPI byte data is read through the DMA controller and sent to the SPI controller. In the receiving stage, the external level signal is input through the SPI controller and retrieved and cached through the DMA controller.

[0008] Specifically, the working frequency of the SPI controller is set to 8 times the Manchester encoding frequency. When translating, according to the order of the Manchester data, each single-bit Manchester data to be translated is converted into 8-bit SPI byte data.

[0009] Specifically, the Manchester data includes bit idle, bit 0, and bit 1; the SPI byte data after translating bit idle, bit 0, and bit 1 are represented as 0x00, 0x0F, and 0xF0 respectively.

[0010] Specifically, the translated SPI bytes and the input data are stored in a buffer. The buffer is divided into a first buffer area, a second buffer area, and a third buffer area; the SPI data translated by the CPU core in response to the encoding request is alternately stored in the first buffer area and the second buffer area, and the buffer area read by the DMA controller at the same moment is different from the buffer area executed by the CPU core;

[0011] The external level signal input by the SPI controller is stored in the third buffer area through the DMA controller, and the CPU core reads the third buffer area and performs matching verification with the original Manchester data.

[0012] Specifically, two FIFO registers are also set between the DMA controller and the SPI controller. The first FIFO register stores the SPI byte data carried outwards by the DMA controller, and the second FIFO register stores the level data carried inwards by the SPI controller.

[0013] Specifically, the voltage conversion circuit includes an operational amplifier U1. The MOSI terminal is connected to one of the input terminals of U1, and the output terminal of U1 is feedback-connected to the other input terminal of U1 through a resistor R2;

[0014] The output terminal of U1 is connected to the gate of the MOS transistor through the resistor R1. The drain of the MOS transistor is connected to the PSI5 bus, and the source of the MOS transistor outputs a reference current.

[0015] Specifically, the current conversion circuit includes an amplification circuit and a comparator. The amplification circuit includes an operational amplifier U2 and a sampling resistor R4. The source of the MOS transistor is grounded after passing through the sampling resistor R4. U2 is connected across both ends of the sampling resistor R4 for current sampling, and a feedback resistor R5 is connected across one input terminal and the output terminal.

[0016] The output terminal of U2 is connected to one input terminal of the comparator U3. The other input terminal of U3 inputs the comparison current modulated by the edge ECU. The output of U3 is sent to the edge ECU through the MISO terminal.

[0017] Specifically, the CPU core obtains the periodic level signal for comparison. When the received level signal matches the translated SPI byte data, it is determined that the verification is consistent.

[0018] When the received level signal does not match the translated SPI byte data, obtain the duty cycle of the level signal and the number of edge ECUs, adjust the comparison current in the current conversion circuit according to the duty cycle and the number of sensors in the PSI5 bus, and re-encode the Manchester data for verification. When the verification result does not match, it is determined that the current edge ECU or the peripheral bus circuit fails. When the verification result matches, it is determined that the sensor on the PSI5 bus fails.

[0019] Specifically, when the level signal output by the current conversion circuit is higher than the comparison current, the converted Manchester code outputs a high level. When the level signal is lower than the comparison current, the converted Manchester code outputs a low level.

[0020] The reference current value output by the voltage conversion circuit is positively correlated with the number of sensors mounted on the PSI5 bus. The CPU core determines the reference current value according to the duty cycle of the input high and low levels and adjusts the comparison current.

[0021] Specifically, the DMA controller is provided with at least two DMA channels, which are respectively used for data output and data input. When the DMA controller receives the corresponding transmission task, it determines the target DMA channel according to the usage status of the DMA channel, and reads data from or stores data into the buffer.

[0022] The beneficial effects brought by the technical solution provided by the embodiments of the present application at least include:

[0023] This application integrates the verification coding process into the edge ECU. Instead of directly outputting Manchester level signals, it first translates them into SPI byte data and combines DMA transfer technology to reduce CPU interrupt response, reduce CPU resource occupancy, and improve the flexibility and scalability of the system. To further improve synchronization efficiency and accuracy, the ratio of the coding baud rate to the SPI transfer baud rate is kept consistent with the byte length. The Manchester coding is protocol-converted bit by bit to achieve conversion for any bit length. Utilizing the full-duplex feature of SPI hardware, the Manchester coding current modulation signal sent from the MOSI port to the bus is received back at the MISO port through a current signal extraction circuit, implementing a closed-loop self-check function for the transmitted signal to ensure the correctness and reliability of the modulation signal sent to the bus. Brief Description of the Drawings

[0024] Figure 1 is a schematic structural diagram of the Manchester coding communication verification system provided by an embodiment of this application;

[0025] Figure 2 is a schematic structural diagram of the edge ECU and the peripheral circuit provided by an embodiment of this application;

[0026] Figure 3 is a schematic diagram of the Manchester coding signal;

[0027] Figure 4 lists the working timing diagram of the buffer;

[0028] Figure 5 is a schematic circuit diagram of the peripheral circuit of the edge processor provided by an embodiment of this application. Detailed Embodiment

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the following will further describe the embodiments of this application in detail with reference to the drawings.

[0030] Figure 1 is a simplified schematic diagram of the Manchester coding communication verification system provided by an embodiment of this application. The system includes a core ECU and several edge ECUs, where at least one edge ECU manages several sensor devices, and the sensor devices are mounted on the PSI5 bus. The edge ECU is connected to the PSI5 bus through a peripheral circuit to achieve data communication with the core ECU and other edge ECUs. For a determined edge ECU, this application mainly performs circuit and sensor coding verification through this edge ECU to evaluate the system stability.

[0031] Figure 2 is a schematic structural diagram of the edge ECU and the peripheral circuit provided by an embodiment of this application. This application takes any edge ECU (corresponding to Figure 2Taking the SOC hardware architecture as an example, it is internally equipped with an SPI controller. The SPI controller is respectively connected to the voltage conversion circuit at the peripheral output MOSI terminal and the current conversion circuit at the peripheral input MISO terminal through hardware interfaces. The voltage conversion circuit and the current conversion circuit are connected to the PSI5 bus. The voltage conversion circuit therein converts the Manchester voltage signal into a current signal and sends it to the external PSI5 bus. The current conversion circuit is connected to the output of the voltage conversion circuit and samples the Manchester current on the external PSI5 bus, converts it into a voltage signal and then sends it back to the edge ECU. Strictly speaking, sampling the external Manchester current includes the superposition of two parts. One part is the directly encoded output current value, and the other part is the current value on the PSI5 bus.

[0032] Request instructions such as encoding and verification are sent down by the core ECU, or the ECU is triggered according to set conditions. When the edge ECU responds to the encoding request, it will translate the acquired Manchester data to be translated into SPI byte data through the CPU core (Core) and cache it. In this process, the Manchester data to be translated can be sent by the core ECU to the edge ECU through the PSI5 bus, and after being sent into the Core, it is translated and encoded according to the rules. In the verification stage, the Core will perform matching verification on the externally input level signal and the Manchester data to be translated, and determine the fault source according to the matching result.

[0033] Manchester data is different from ordinary level signal values. Ordinary level signals represent bit data through high and low levels, but due to interference factors, it is extremely easy to cause mutations, resulting in inaccurate data. Therefore, it is more accurate to use Manchester encoding.

[0034] Figure 3 is a schematic diagram of the Manchester encoding signal. Manchester encoding is an automatically synchronized encoding method, that is, the clock synchronization signal is hidden in the data waveform. In Manchester encoding, there is a transition in the middle of each bit. The transition in the middle of the bit serves as both the clock signal and the data signal. Each symbol is represented by two level signals with different phases. Compared with the non-return-to-zero binary code represented by high and low levels, it is easier to extract the synchronous clock information in the case of consecutive "0" or consecutive "1". And when Manchester code is transmitted, there is no DC component, which can reduce the power consumption of the system and has strong anti-interference ability. When the transmitted signal is "1", the Manchester encoding jumps from high level to low level; if the transmitted information is "0", the Manchester encoding jumps from low level to high level, and keeping the low level without transition within a data cycle CS signal indicates idle.

[0035] In the traditional solution, during verification, an additional FPGA or corresponding chip can be used. For ECU verification, a timer and GPIO ports are usually used to implement Manchester encoding, that is, the ECU directly outputs Manchester level signals. This form has serious problems in terms of encoding efficiency and CPU resource occupancy. Since the CPU also has to execute data interaction processing between the core ECU and other peripheral ECUs, such frequent interrupt responses will cause system delays. In this application, to avoid using level signals and frequent interrupts, the Manchester data to be translated is first converted into bit data (SPI byte data) internally and stored in a buffer, rather than directly outputting. The transported converted data is taken over by the DMA controller, which can reduce CPU interrupt responses.

[0036] The CPU core is connected to the DMA controller. During the translation process, the transmission task can be set for the DMA controller according to the encoding request, allowing the DMA controller to be responsible for external data transmission, and transferring the data from the buffer to the SPI controller. The SPI controller is connected to the DMA controller. It takes over the SPI byte data according to the encoding request and sends and receives data according to the preset encoding frequency.

[0037] In the sending stage, the peripheral ECU reads the SPI byte data in the buffer through the DMA controller and sends it to the SPI controller, and then the SPI controller sends the data out to the voltage conversion circuit. In the receiving stage, the peripheral ECU inputs the level signal output by the external current conversion circuit through the SPI controller, and then retrieves and caches it through the DMA controller.

[0038] This solution aims to overcome the rate limitation of traditional chips, reduce system costs, reduce CPU resource occupancy, and simplify the hardware design complexity. By cleverly utilizing the high-efficiency data transmission ability of the SPI interface and the CPU-free data transmission characteristics of the DMA, it can not only significantly improve the real-time processing efficiency of Manchester encoding, but also greatly enhance the flexibility and scalability of the system while ensuring communication quality, opening up a new path for the application of Manchester encoding technology in a wider range of fields.

[0039] The most important purpose of translating the Manchester encoding data in this application is to adapt to the data transfer of the DMA controller. Since the DMA controller takes over the CPU tasks and executes byte data, for the sake of improving efficiency and being compatible with sensor data types, this application takes the most common 8-bit encoding as an example for illustration.

[0040] Set the encoding order of the SPI controller to the MSB from high to low mode, and configure the working frequency of the SPI controller to 8 times the baud rate of the Manchester code to be sent. That is, if the Manchester code baud rate is 1 Mbps, configure the SPI hardware clock frequency to 8 MHz. Then, in the translation process, according to the order of the Manchester data, each single-bit Manchester data to be translated is converted into an 8-bit SPI byte data. This transcoding process is bit-by-bit encoding. That is, the Manchester data includes bit idle, bit 0, and bit 1, and the SPI byte data after translating bit idle, bit 0, and bit 1 are represented as 0x00, 0x0F, and 0xF0 respectively. This process does not use 8-bit to Manchester code translation to 8-bit SPI byte data. Theoretically, it is feasible, but this parameter is specifically determined according to the sensor data type. When the sensor data is 8-bit or 16-bit data, this can strictly translate 8-bit to Manchester code to 8-bit SPI byte data. However, when the sensor data is not 8-bit (such as 12-bit), it is impossible to transfer the complete sensor data. Therefore, this application uses 8-bit as the basis for translation. It realizes the encoding translation of any form of sensor, reduces the CPU resource occupancy while realizing verification. The translation verification process can be simplified into the following steps:

[0041] (1) First, the system completes initialization, configures the SPI working frequency and DMA channel according to the Manchester code baud rate;

[0042] (2) Then, determine whether there is a Manchester code sequence that needs to be encoded and sent. If not, loop and wait. If so, go to the next step;

[0043] (3) Send the bit data and bit length of the Manchester code sequence to be sent into the translation encoding algorithm, and store the translated SPI byte data in the specified buffer for DMA to perform buffer transfer;

[0044] (4) Start DMA transfer and SPI data sending;

[0045] (5) After sending, perform self-check on the signals on the bus to confirm the correctness of the bus signals;

[0046] To ensure the synchronous progress of encoding transfer and verification matching, this application also makes a fine-grained division of the buffer for storing data, specifically dividing it into a first buffer, a second buffer, and a third buffer. The SPI data after the CPU core responds to the encoding request is alternately stored in the first buffer and the second buffer, and the buffer read by the DMA controller at the same moment is different from the buffer executed by the CPU core. The external level signal input by the SPI controller is stored in the third buffer through the DMA controller, and the CPU core reads the third buffer and performs matching verification with the original Manchester data.

[0047] Figure 4 The working timing diagram of the buffer is listed. After the Core executes the translation encoding work, it preferentially stores it in the first buffer (step 1). When the first buffer is full or reaches the set threshold, it further stores the SPI byte data in the second buffer (step 2). As a DMA controller, after receiving the instruction from the Core, it will take over the data transfer task, that is, extract the SPI data from the first buffer (step 3) and transfer it to the SPI controller. Assuming that all system input and output operations are running normally, the DMA controller will also receive the level signal data for internal storage (since it is operated by the DMA controller, it is stored in the form of bit data), and this data will be stored in the third buffer (step 4). For the Core, when a complete loopback logic is completed, it can extract the data from the third buffer and execute the matching verification step (step 5). Assuming that the Manchester encoded data is cyclically translated and step 6 continues to store it in the first buffer, then after the DMA controller extracts the data from the first buffer in the previous round, in step 7, it preferentially extracts the SPI byte data from the second buffer. In addition, the DMA controller is at least provided with two DMA channels, which are respectively used for data output and data input. When the DMA controller receives the corresponding transfer task, it determines the target DMA channel according to the usage status of the DMA channel, and reads data from or stores data in the buffer. During the above process, it is always ensured that the DMA controller extracts data from a buffer different from the Core's core buffer, which can not only ensure that the data is extracted strictly in sequence, but also avoid DMA channel busy and data errors.

[0048] In some embodiments, two FIFO registers are further provided between the DMA controller and the SPI controller. The first FIFO register stores the SPI byte data transported outward by the DMA controller, and the second FIFO register stores the level data transported inward by the SPI controller. The two FIFOs are respectively used for outward and inward data transfer. The bit depth of the FIFO can be determined according to the sensor data. For example, if the sensor data is 16-bit long, then the bit depth of the FIFO is set to 16 bits. In this way, the SPI controller can determine the complete sensor data according to the first-in-first-out principle, which is convenient for subsequent data analysis processing and data decoding operations.

[0049] Figure 5It is a circuit schematic diagram of the peripheral circuit of the edge processor provided by an embodiment of the present application, specifically including a voltage conversion circuit and a current conversion circuit. The voltage conversion circuit therein includes an operational amplifier U1, the MOSI terminal is connected to one input terminal of U1, and the output terminal of U1 is feedback-connected to the other input terminal of U1 through a resistor R2. A resistor R1 is cascaded at the output of U1, the gate of the MOS transistor is connected through the resistor R1, the drain of the MOS transistor is connected to the PSI5 bus, and the source of the MOS transistor outputs a reference current. In some embodiments, a resistor R3 can also be connected in parallel between the source of Q1 and the output terminal of U1 for feedback.

[0050] In the above structure, the operational amplifier U1 and the MOS transistor Q1 implement a voltage-to-current conversion circuit. The operational amplifier feedback circuit can generate a fixed current when MOSI is at a high level, and this current is the key to the self-loop and is connected to the input of the current conversion circuit.

[0051] The current conversion circuit includes an amplifier circuit and a comparator. The amplifier circuit includes an operational amplifier U2 and a sampling resistor R4. The source of the MOS transistor is grounded after passing through the sampling resistor R4. U2 is connected across both ends of the sampling resistor R4 for current sampling, and a feedback resistor R5 is connected across one input terminal and the output terminal. Of course, in some embodiments, a resistor R6 can also be provided between the ground terminal and the other input terminal of U2 to stabilize the circuit and perform proportional amplification of the current.

[0052] The output terminal of U2 is connected to one input terminal of the comparator U3. A comparison current modulated by the edge ECU is input to the other input terminal of U3, which can be specifically realized by accessing voltage-dividing resistors R7, R8, and a voltage source modulation to generate a stable comparison current. The output of U3 is used as a comparison result (level signal) and is sent to the edge ECU through the MISO terminal. What is sent to the MISO terminal is a high level 1 or a low level 0, that is, the converted voltage signal. And the comparison current modulation in this circuit can be modulated by the voltage output by the CPU.

[0053] In a possible implementation manner, when the level signal output by the current conversion circuit is higher than the comparison current, the converted Manchester code outputs a high level 1; when the output level signal is lower than the comparison current, the converted Manchester code outputs a low level 0. This comparison current is an ideal current value under normal quantity and normal circuit structure conditions, and can be used for verification and diagnosis when the circuit is abnormal or the PSI5 bus is abnormal.

[0054] Specifically, the CPU core obtains the periodic level signal for comparison. When the received level signal matches the translated SPI byte data, it is determined that the verification is consistent.

[0055] When the received level signal does not match the translated SPI byte data, the fault source cannot be directly determined. It is also necessary to further obtain the duty cycle of the level signal and the number of edge ECUs, adjust the comparison current in the current conversion circuit according to the duty cycle and the number of sensors in the PSI5 bus, and re-encode the Manchester data for verification. When the secondary verification result still does not match, it is determined that the current edge ECU or the peripheral bus circuit is faulty, and when the secondary verification result matches, it is determined that the sensor on the PSI5 bus is faulty (i.e., the sensor is offline).

[0056] Since it is considered that the reference current value output by the voltage conversion circuit also includes the current value of the PSI5 bus, and this value is positively correlated with the number of sensors mounted on the PSI5 bus, the process of secondary adjustment of the comparison current is to adapt to the PSI5 bus signal to determine whether there is a sensor offline. The CPU core can determine the reference current value according to the duty cycle of the input high and low levels and adjust the comparison current. Specifically, a voltage / current modulation look-up table can be generated in advance during the production stage according to the number of sensors mounted on the vehicle bus and the circuit structure, listing the comparison voltage / current values output by the ECU under different numbers of mounted sensors. This look-up table can be stored in the ECU and modulated and output according to the duty cycle difference during the verification stage to further diagnose and analyze possible results.

[0057] In summary, this application integrates the verification and encoding process into the edge ECU. Instead of directly outputting the Manchester level signal, it first translates it into SPI byte data, and combines the DMA transmission technology to reduce the CPU interrupt response, reduce the occupation of CPU resources, and improve the flexibility and scalability of the system. To further improve the synchronization efficiency and accuracy, the ratio of the encoding baud rate to the SPI transmission baud rate is kept consistent with the byte length. The Manchester encoding is converted bit by bit according to the protocol to achieve the conversion of any bit length. Utilizing the full-duplex characteristic of the SPI hardware, the Manchester encoding current modulation signal sent from the MOSI port to the bus is received back at the MISO port through the current signal extraction circuit, realizing a closed-loop self-check function for the transmitted signal to ensure the correctness and reliability of the modulation signal sent to the bus.

[0058] This specific embodiment is only an explanation of the present invention and does not limit the present invention. Those skilled in the art can make modifications without creative contributions to this embodiment after reading this specification, but as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A Manchester coding communication verification system, comprising a core ECU and a plurality of edge ECUs, wherein the edge ECUs are connected to the core ECU via a PSI5 bus; characterized in that: The edge ECU is equipped with an SPI controller, which is connected to the voltage conversion circuit of the peripheral output MOSI end and the current conversion circuit of the peripheral input MISO end through a hardware interface; the voltage conversion circuit and the current conversion circuit are connected to the PSI5 bus, the voltage conversion circuit converts the Manchester voltage signal into a current signal and sends it to the external PSI5 bus, and the current conversion circuit connects the voltage conversion circuit output and samples the Manchester current on the external PSI5 bus, converts it into a voltage signal and sends it back to the edge ECU; The edge ECU responds to the encoding request, translates the acquired Manchester data to be translated into SPI byte data and caches it through the CPU core, and performs a matching check on the external input level signal and the Manchester data to be translated, and determines the fault source according to the matching result; The CPU core is connected to the DMA controller and sets the transmission task to the DMA controller according to the encoding request; the SPI controller is connected to the DMA controller and takes over the SPI byte data according to the encoding request, and sends and receives data according to the preset encoding frequency; In the sending phase, the cached SPI byte data is read through the DMA controller and sent to the SPI controller. In the receiving phase, the external level signal is input through the SPI controller and called and cached through the DMA controller.

2. The Manchester coding communication verification system according to claim 1, characterized in that: The operating frequency of the SPI controller is set to 8 times the Manchester encoding frequency. During translation, each single-bit Manchester data to be translated is converted into 8-bit SPI byte data according to the order of the Manchester data.

3. The Manchester coding communication verification system according to claim 2, characterized in that: Manchester data includes bit idle, bit 0 and bit 1; the SPI byte data after translating bit idle, bit 0 and bit 1 are expressed as 0x00, 0x0F and 0xF0 respectively.

4. The Manchester coding communication verification system according to claim 1, characterized in that: The translated SPI bytes and the input data are stored in a buffer, which is divided into a first buffer area, a second buffer area and a third buffer area; the SPI data translated by the CPU core in response to the encoding request is alternately stored in the first buffer area and the second buffer area, and the buffer area read by the DMA controller and the buffer area executed by the CPU core at the same time are different; The SPI controller inputs an external level signal which is stored in the third buffer area through the DMA controller, and the CPU core reads the third buffer area and performs a matching check with the original Manchester data.

5. The Manchester coding communication verification system according to claim 1, characterized in that: Two FIFO registers are also arranged between the DMA controller and the SPI controller. The first FIFO register stores the SPI byte data transferred outward by the DMA controller, and the second FIFO register stores the level data transferred inward by the SPI controller.

6. The Manchester coding communication verification system according to claim 1, characterized in that: The voltage conversion circuit comprises an operational amplifier U1, a MOSI terminal is connected to one of the input terminals of U1, and an output terminal of U1 is connected to another input terminal of U1 through a resistor R2 for feedback; The output end of U1 is connected to the gate of the MOS tube through the resistor R1, the drain of the MOS tube is connected to the PSI5 bus, and the source of the MOS tube outputs a reference current.

7. The Manchester coding communication verification system according to claim 6, characterized in that: The current conversion circuit includes an amplifier circuit and a comparator. The amplifier circuit includes an operational amplifier U2 and a sampling resistor R4. The source of the MOS tube is grounded after passing through the sampling resistor R4. U2 is connected to both ends of the sampling resistor R4 for current sampling. A feedback resistor R5 is connected between one input terminal and an output terminal. The output end of U2 is connected to one input end of the comparator U3, and the other input end of U3 inputs the comparison current modulated by the edge ECU. The output of U3 is sent to the edge ECU through the MISO end.

8. The Manchester coding communication verification system according to any one of claims 1 to 7, characterized in that: The CPU core obtains the periodic level signal for comparison. When the received level signal matches the translated SPI byte data, the verification is confirmed to be consistent; When the received level signal does not match the translated SPI byte data, the duty cycle of the level signal and the number of edge ECUs are obtained, the comparison current in the current conversion circuit is adjusted according to the duty cycle size and the number of sensors in the PSI5 bus, and the Manchester data is re-encoded for verification; When the verification results do not match, it is determined that the current edge ECU or peripheral bus circuit is faulty, and when the verification results match, it is determined that the sensor on the PSI5 bus is faulty.

9. The Manchester coding communication verification system according to claim 8, characterized in that: When the level signal output by the current conversion circuit is higher than the comparison current, the converted Manchester code outputs a high level, and when the level signal is lower than the comparison current, the converted Manchester code outputs a low level; The reference current value output by the voltage conversion circuit is positively correlated with the number of sensors mounted on the PSI5 bus. The CPU core determines the reference current value and adjusts the comparison current according to the high and low level duty ratios of the inputs.

10. The Manchester coding communication verification system according to claim 8, characterized in that: The DMA controller is provided with at least two DMA channels, which are used for data output and data input respectively. When the DMA controller receives a corresponding transmission task, it determines the target DMA channel according to the usage status of the DMA channel, and reads data from the buffer or stores it in the buffer.

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