Substrate structure and electronic device

Abstract

The invention provides a substrate structure and an electronic device.The substrate structure comprises a master device, a first slave device and a second slave device which are arranged on the same substrate, the length of the electrical connection between the master device and the first slave device is greater than the length of the electrical connection between the master device and the second slave device. The communication rate between the master device and the first slave device is greater than the communication rate between the master device and the second slave device. The length of the electrical connection between the master device and the first slave device is set to be greater than the length of the electrical connection between the master device and the second slave device, so that the quality of the overall communication signal in the substrate structure can be improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of circuit boards, and in particular to a substrate structure and an electronic device. Background Art

[0002] The stub effect refers to the signal reflection and impedance discontinuity caused by branch structures in the transmission line, such as broken wire ends, test points, and redundant traces. These branch structures are usually called "stubs", which cause signal reflection during transmission, affecting signal integrity and transmission quality.

[0003] When the master device communicates with the proximal load but not with the remote load, the redundant SPI traces between the proximal load and the remote load will produce a Stub effect, which will not only cause spatial radiation within the PCB board, but more importantly, will cause distortion of the signal waveform, affecting the communication quality of the SPI signal, such as packet loss, garbled characters, etc., posing a great threat to product quality. Summary of the invention

[0004] The technical problem to be solved by the present disclosure is to overcome the above-mentioned defects in the prior art and to provide a substrate structure and an electronic device.

[0005] The present invention solves the above technical problems through the following technical solutions:

[0006] A first aspect of the present disclosure provides a substrate structure, comprising a master device, a first slave device, and a second slave device, which are arranged on the same substrate, wherein the length of the electrical connection between the master device and the first slave device is greater than the length of the electrical connection between the master device and the second slave device, and the communication rate between the master device and the first slave device is greater than the communication rate between the master device and the second slave device.

[0007] Optionally, a length of a wire between the master device and the first slave device is greater than a length of a wire between the master device and the second slave device.

[0008] Optionally, a length of a metal lead from the master device to the first slave device is greater than a length of a metal lead from the master device to the second slave device.

[0009] Optionally, a wiring length between the master device and the first slave device is greater than a wiring length between the master device and the second slave device.

[0010] Optionally, a first solder pad, a second solder pad and a third solder pad are also provided on the substrate, the communication pin of the master device component is electrically connected to the first solder pad, the communication pin of the first slave device component is electrically connected to the second solder pad, and the first solder pad and the second solder pad as well as the first solder pad and the third solder pad are connected by wiring.

[0011] Optionally, a local ground copper foil is provided in a projection area in a layer adjacent to the layer where a first routing line is located, wherein the first routing line is a routing line between the master device and the first slave device.

[0012] Optionally, in the layer where the first routing line is located, ground wires are respectively provided at both ends of the first routing line, and ground holes are provided on the ground wires, and the ground holes are electrically connected to the ground copper foil in a direction perpendicular to the substrate.

[0013] Optionally, the first routing line includes a clock routing line and a data routing line, and the impedance of the clock routing line and the impedance of the data routing line are both within a preset impedance range.

[0014] Optionally, the length of the clock line and the length of the data line are within the same length range.

[0015] Optionally, the master device, the first slave device and the second slave device are arranged on the same layer.

[0016] Optionally, the master device and the first slave device are arranged at the same layer, and the master device and the second slave device are arranged at different layers.

[0017] Optionally, the master device and the second slave device are arranged at the same layer, and the master device and the first slave device are arranged at different layers.

[0018] Optionally, the number of the second slave device devices is at least two.

[0019] A second aspect of the present disclosure provides an electronic device, comprising the substrate structure described in the first aspect.

[0020] Based on the common sense in the art, the above optional conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0021] The positive progressive effect of the present disclosure is that by setting the length of the electrical connection between the master device and the first slave device to be greater than the length of the electrical connection between the master device and the second slave device, the quality of the overall communication signal in the substrate structure can be improved. Specifically, when the master device communicates with the first slave device at the far end, the second slave device at the near end does not work. Since the length of the electrical connection between the master device and the second slave device is shorter, the Stub effect it produces is smaller, and therefore the impact on the high-speed communication signal between the master device and the first slave device is smaller; when the master device communicates with the second slave device at the near end, the first slave device at the far end does not work. Since the length of the electrical connection between the master device and the first slave device is longer, the Stub effect it produces is larger, but since the communication rate between the master device and the second slave device is lower, the impact on its communication signal is relatively small. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the topological structure of an SPI signal routing provided in Example 1 of the present disclosure.

[0023] Figure 2 A schematic diagram of another topological structure of SPI signal routing provided in Example 1 of the present disclosure.

[0024] Figure 3 A schematic diagram of the topological structure of another SPI signal routing provided in Embodiment 1 of the present disclosure.

[0025] Figure 4 A cross-sectional view of the wiring topology of a PCB board.

[0026] Figure 5 This is a schematic diagram of the test waveform in the SCK routing of SPI.

[0027] Figure 6 A cross-sectional view of the routing topology structure of a PCB board provided in Example 1 of the present disclosure.

[0028] Figure 7 A cross-sectional view of the routing topology structure of another PCB board provided in Example 1 of the present disclosure.

[0029] Figure 8 A cross-sectional view of the routing topology structure of another PCB board provided in Embodiment 1 of the present disclosure.

[0030] Fig. 9 A top view of the SPI signal provided in Example 1 of the present disclosure using the 3W routing principle.

[0031] Fig.10 A cross-sectional view of an SPI signal disposed on the surface layer using the 3W routing principle provided in Embodiment 1 of the present disclosure.

[0032] Fig.11 Schematic diagram of the mutual inductance effect between two closed-loop circuits provided in Example 1 of the present disclosure.

[0033] Fig.12 A top view of an SPI routing on the surface or inner layer provided in Example 1 of the present disclosure.

[0034] Fig.13 A top view of another SPI routing on the surface or inner layer provided in Example 1 of the present disclosure.

[0035] Fig.14 A cross-sectional view of a SPI routing on the surface or inner layer provided in Example 1 of the present disclosure.

[0036] Fig.15 This is a curve chart of the radiation values ​​emitted by the wireless vehicle-mounted device provided in Example 1 of the present disclosure in the 0-1 GHz test frequency band.

[0037] Fig.16 This is a schematic diagram of the results of a static test of the GPS antenna of the wireless vehicle-mounted device provided in Example 1 of the present disclosure in an open location. DETAILED DESCRIPTION

[0038] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0039] It should be noted that the terms "first", "second", etc. in the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0040] The substrate structure provided in the embodiments of the present disclosure is suitable for electronic devices such as electric bicycles, scooters, driving recorders, routers, mobile phones, switches, medical equipment, etc.

[0041] SPI (Serial Peripheral interface) was first defined by Motorola on its MC68HCXX series processors. SPI is a high-speed, full-duplex, synchronous communication bus that only occupies four wires on the chip pins, saving the chip pins and saving space on the PCB layout, providing convenience. It is mainly used in EEPROM, FLASH, sensors, real-time clocks, AD converters, and between digital signal processors and digital signal decoders.

[0042] SPI is divided into two modes: master and slave. An SPI communication system needs to include one (and only one) master device and one or more slave devices. The device that provides the clock is the master device (Master), and the device that receives the clock is the slave device (Slave). The read and write operations of the SPI interface are initiated by the master device. When there are multiple slave devices, they are managed through their respective chip select signals. SPI is full-duplex and SPI has no defined speed limit. The general implementation can usually reach or even exceed 10Mbps.

[0043] The SPI interface generally uses the following four signal lines for communication: SDI (data input), SDO (data output), SCK (clock), and CS (chip select). The SPI interface includes the MISO pin, MOSI pin, SCK pin, and CS / SS pin. MISO is the master input / slave output pin, which sends data in slave mode and receives data in master mode. MOSI is the master output / slave input pin, which sends data in master mode and receives data in slave mode. SCK is the clock pin, and the serial clock signal generated by the master device is output through this pin. CS / SS is the chip select pin, and the master device selects the specified slave device by controlling this pin, allowing the master device to communicate with a specific slave device individually to avoid conflicts on the data line.

[0044] When the master device has a slave device, the topology of the SPI signal routing is as follows: Figure 1 shown.

[0045] When the master device has multiple slave devices, the topology of the SPI signal routing can be as follows: Figure 2As shown, this situation mainly occurs when the I / O pin resources of the master device are insufficient. For example, due to cost considerations or the PCB board density is very high, it is impossible to place a large-size host. A set of SPI (including SCK, SIMO, SOMI) and multiple sets of CS / SS are used to achieve communication. Among them, when a master device corresponds to multiple slave devices, a pin is separately led out from the master device as CS / SS to correspond to each slave device, that is, the number of CS / SS pins is led out on the master device as many as the number of slave devices, and SCK, SIMO, and SOMI are shared. Each slave device needs to have a CS / SS pin connected to the CS / SS pin on the master device. When the master device wants to communicate with a specific slave device, it pulls the corresponding CS / SS pin low and keeps other CS / SS pins high. At the same time, because the MISO pin of the slave device is on the same signal, the SOMI pin of the unselected slave device is required to be configured as a high configuration output.

[0046] When the master device has multiple slave devices, the topology of the SPI signal routing can also be as follows: Figure 3 As shown. Generally, the signal line is transmitted from one device to the next in a serial manner until the data reaches the target device. This data transmission method is called daisy chain. The disadvantage of daisy chain is that if a single point failure occurs in the slave device, the slave devices with a lower priority than the slave device will be disconnected. The farther the slave device is from the master device, the lower the priority of the service. Therefore, it is necessary to set up a bus detector and arrange the priority of the slave devices. If a slave device times out, it should be handled in time to prevent a single point failure from causing the collapse of the entire link. The daisy chain makes full use of the function of the SPI shift register. Each slave device copies the input data to the output in the next clock cycle.

[0047] Figure 4 A cross-sectional view of the wiring topology of a PCB board is given. Figure 4 In the example shown, the PCB board is provided with a master device and a slave device, the master device is an MCU, and the slave devices include FLASH, an acceleration sensor Gsensor, and a Bluetooth chip. A section of SPI routing is led out from the MCU, including SCK, SIMO, SOMI, CS / SS1, CS / SS2, and CS / SS3. Via 1 is punched and the layer is changed to the inner layer to via 2. SCK, SIMO, SOMI, and CS / SS1 are changed to the TOP layer and routed to the pad of FLASH; and SCK, SIMO, SOMI, and CS / SS2 in the inner layer are continued to be led to via 3, and SCK, SIMO, SOMI, and CS / SS2 are changed to the TOP layer and routed to the pad of Gsensor; and SCK, SIMO, SOMI, and CS / SS3 in the inner layer are continued to be led to via 4, and SCK, SIMO, SOMI, and CS / SS4 are changed to the TOP layer and routed to the pad of the Bluetooth chip.

[0048] The length of the trace from MCU to via 2 is L1, the length of the trace from via 2 to FLASH is L4, and the length of the trace from MCU to FLASH is L1+L4. The length of the trace from via 2 to Gsensor is L5, and the length of the trace from MCU to Gsensor is L1+L5. The length of the trace from via 2 to the Bluetooth chip is L6, and the length of the trace from MCU to the Bluetooth chip is L1+L6. Among them, L6> L5> L4.

[0049] When MCU communicates with FLASH, SCK, SIMO, and SOMI from MCU to FLASH work, while Gsensor and Bluetooth chip do not work, so the routing of SCK, SIMO, and SOMI from via 2 to Gsensor does not work, but there is a Stub, and the Stub is a useless extra wire end. It is not involved in the transmission of SCK, SIMO, and SOMI signals. The Stub will form a changing electric field toward the surrounding ground plane, generate displacement current, and the changing electric field will generate a changing magnetic field, thereby forming an antenna effect, radiating to the outside, affecting the quality of high-speed signals or high-frequency signals, such as causing reflection and overshoot of high-speed signals, causing distortion of high-speed signals, and packet loss and garbled characters when transmitting high-speed signals. The presence of stubs during high-speed signal transmission not only has a negative impact on the signal itself, but also causes the product's EMI radiation indicators (for example, China's 3C, the EU's CE, North America's FCC, etc. have strict regulations on EMI radiation in EMC) to fail to meet the requirements, resulting in interference with sensitive devices in the substrate (such as audio devices, RF devices, onboard antennas, etc.) and sensitive traces (such as audio traces, RF traces, RF traces, etc.), affecting the normal function of the product.

[0050] When MCU communicates with Gsensor, SCK, SIMO, and SOMI from MCU to Gsensor work, while FLASH and Bluetooth chip do not work, so the SCK, SIMO, and SOMI routing from via 3 to Bluetooth chip does not work, but there is a Stub, which is redundant and does not participate in the transmission of SCK, SIMO, and SOMI signals. The Stub will form a changing electric field toward the surrounding ground plane, generate displacement current, and the changing electric field will generate a changing magnetic field, thereby forming an antenna effect, radiating to the outside, affecting the quality of high-speed signals or high-frequency signals, such as causing signal reflection and overshoot, causing high-speed signal distortion, and packet loss and garbled code when transmitting high-speed signals. There is a section of TOP layer routing from FLASH to via 2 that does not work, and this section is also a Stub. As long as there is a section of TOP layer routing from FLASH to via 2 that is less than 5mm, the impact on SCK, SIMO, and SOMI routing is small, and the main focus is on the SCK, SIMO, and SOMI routing from via 3 to the Bluetooth chip.

[0051] Figure 5 The test waveform of the SCK routing in SPI is given. For the clock routing in SPI, namely the SCK routing, take the SCK routing in 10MHz SPI as an example. Figure 5 , the period of 10MHz SCK routing is 100ns, the peak-to-peak value of 10MHz SCK routing is 3.4V, the maximum amplitude is 2.56V, and the minimum amplitude is -640mV. The maximum amplitude of the overshoot of the clock signal in the 10MHz SCK routing is 2.56V, and the minimum amplitude of the return groove of the clock signal in the 10MHz SCK routing is -640mV. After the maximum value of the overshoot of the clock signal, there is a ringing of the clock signal. Although the clock signal of the SCK routing is only 10MHz, its rising edge is very steep, so it is best to design it according to the requirements of high-speed signals. The higher the clock signal transmission rate, that is, the operating frequency, in the SCK trace, the faster its signal mutation speed is, the stronger the EMI radiation generated outside the PCB board is, and the stronger the interference to sensitive devices (such as audio devices, RF devices, onboard antennas, etc.) and sensitive traces (such as audio traces, RF traces, RF traces, etc.) in the circuit board is, which can easily cause abnormal operation of sensitive devices (such as audio devices, RF devices, onboard antennas, etc.) and sensitive traces (such as audio traces, RF traces, RF traces, etc.) in the board.

[0052] The steeper the rising edge of the clock signal in the SCK trace, the higher the overshoot generated in the SCK trace, the faster its signal mutation speed, the stronger the EMI radiation generated outside the PCB board, and the stronger the interference to the sensitive circuits in the PCB board, which can easily cause abnormal operation of the sensitive circuits. The ringing in the clock signal in the SCK trace is equivalent to multiple harmonics of the clock signal's frequency multiples. The size of the ringing swing will also cause strong interference to the sensitive circuits in the PCB board, which can easily cause abnormal operation of the sensitive circuits. The clock signal in the SCK trace needs to pay attention to its rising edge. The quality of the clock signal waveform in the SCK trace will not only affect the external EMI radiation and the interference to the sensitive circuits in the PCB board, but also affect the signal quality of the SIMO and SOMI traces in the SPI trace (the signals of the SIMO and SOMI traces are all based on the SCK trace signal as the reference clock), avoiding packet loss, garbled characters and other phenomena in the SIMO and SOMI traces.

[0053] Example 1

[0054] This embodiment provides a substrate structure, including a master device, a first slave device, and a second slave device, which are arranged on the same substrate, wherein the length of the electrical connection between the master device and the first slave device is greater than the length of the electrical connection between the master device and the second slave device, and the communication rate between the master device and the first slave device is greater than the communication rate between the master device and the second slave device.

[0055] The number of the second slave device components may be at least two.

[0056] In a specific example, the master device and the first slave device, and the master device and the second slave device are both electrically connected via wires. In this example, the length of the wire from the master device to the first slave device is greater than the length of the wire from the master device to the second slave device.

[0057] In another specific example, the substrate structure provided in this embodiment is also applicable to an integrated circuit, and specifically, the master device and the first slave device, as well as the master device and the second slave device are electrically connected via metal leads. In this example, the length of the metal lead from the master device to the first slave device is greater than the length of the metal lead from the master device to the second slave device.

[0058] In another specific example, the master device and the first slave device, as well as the master device and the second slave device, are electrically connected via wiring on a substrate. In this example, the wiring length from the master device to the first slave device is greater than the wiring length from the master device to the second slave device.

[0059] In a specific implementation, the communication mode between the master device and the first slave device and between the master device and the second slave device may be SPI communication, UART (Universal Asynchronous Receiver / Transmitter) communication, RS-232 communication or RS-485 communication, etc. In the example of realizing electrical connection through routing, the routing corresponding to the above communication modes may be SPI routing, UART routing, clock routing, RS-232 routing, RS-485 routing, 1-Wire routing, I 2 C routing, I 2S routing, differential routing (such as SATA routing, HDMI routing, USB routing, QPI routing, PCIE routing, etc.). Among them, SPI routing includes clock routing, namely SCK routing, data routing, namely SIMO and SOMI routing, chip select routing, namely SS / CS routing, etc.

[0060] In this embodiment, the substrate includes a printed circuit board, SIP, integrated circuit board, etc. Among them, SIP (System In a Package) is a packaging concept, which is a packaging method in which all or most of the electronic functions of a system or subsystem are configured in an integrated substrate, and the chip is connected to the integrated substrate in a 2D or 3D manner. The printed circuit board can be called a PCB (Printed Circuit Board) or a printed circuit board.

[0061] In this embodiment, by setting the length of the electrical connection between the master device and the first slave device to be greater than the length of the electrical connection between the master device and the second slave device, the quality of the overall communication signal in the substrate structure can be improved. Specifically: when the master device communicates with the first slave device at the far end, the second slave device at the near end does not work. Since the length of the electrical connection between the master device and the second slave device is shorter, the Stub effect it produces is smaller, and therefore the impact on the high-speed communication signal between the master device and the first slave device is smaller; when the master device communicates with the second slave device at the near end, the first slave device at the far end does not work. Since the length of the electrical connection between the master device and the first slave device is longer, the Stub effect it produces is larger, but since the communication rate between the master device and the second slave device is lower, the impact on its communication signal is relatively small.

[0062] In an optional embodiment, a first solder pad, a second solder pad and a third solder pad are further provided on the substrate, the communication pin of the master device component is electrically connected to the first solder pad, the communication pin of the first slave device component is electrically connected to the second solder pad, the communication pin of the second slave device component is electrically connected to the third solder pad, and the first solder pad and the second solder pad as well as the first solder pad and the third solder pad are all connected by wiring.

[0063] In an optional embodiment, a local ground copper foil is provided in a projection area in a layer adjacent to the layer where the first routing line is located, wherein the first routing line is a routing line between the master device and the first slave device. In this embodiment, the local ground copper foil is provided in a projection area in a layer adjacent to the layer where the first routing line is located, i.e., the routing line between the master device and the first slave device, so as to provide a return path for the first routing line, thereby reducing noise and interference, so as to improve the quality of the signal transmitted in the first routing line.

[0064] In an optional implementation manner, the master device component, the first slave device component and the second slave device component are arranged on the same layer.

[0065] In another optional implementation manner, the master device component and the first slave device component are arranged at the same layer, and the master device component and the second slave device component are arranged at different layers.

[0066] In yet another optional implementation, the master device component and the second slave device component are arranged at the same layer, and the master device component and the first slave device component are arranged at different layers.

[0067] Figure 6 A cross-sectional view of the wiring topology of a PCB board is given. Figure 6 In the example shown, a master device and a slave device are provided on the PCB board, the master device is an MCU, and the slave devices include FLASH and an acceleration sensor Gsensor, wherein FLASH corresponds to the first slave device, Gsensor corresponds to the second slave device, and the SPI trace between the MCU and FLASH corresponds to the first trace. The MCU is arranged on the TOP layer of the PCB board, while the FLASH is arranged on the TOP layer of the PCB board, and the Gsensor is arranged on the BOTTOM layer of the PCB board, and the FLASH and the Gsensor are pasted on the front and back. The SPI trace is led out from the MCU pad, and the SPI trace is led from the TOP layer to the position of the Gsensor pad near the BOTTOM layer, wherein the trace length from the MCU pad to the via 1 is L1, that is, the SCK, SIMO, and SOMI traces are divided into two parts at the via 1: one end leads a small section of the TOP layer trace from the via 1 to the FLASH pad, and its length is L4, and the other end leads a small section of the trace from the BOTTOM layer of the via 1 to the Gsensor pad, and its length is L5.

[0068] Among them, the routing length L1 from the MCU pad to via 1 is the shared length of the SCK, SIMO, SOMI, SS / CS routing of Gsensor and the SCK, SIMO, SOMI, SS / CS routing of FLASH, while the branch length L4 from via 1 to the TOP layer routing of FLASH pad, and the branch length L5 from via 1 to the BOTTOM layer routing of Gsensor pad, L4 and L5 are required to be as short as possible, preferably less than 5mm.

[0069] The Gsensor of the TOP layer and the FLASH of the BOTTOM layer overlap or coincide as much as possible in the vertical direction, so that the branch length L5 of the BOTTOM layer routing from via 1 to the Gsensor pad and the branch length L4 of the TOP layer routing from via 1 to the FLASH pad are as short as possible, reducing the Stub effect in the SCK, SIMO, SOMI, and SS / CS routing.

[0070] If the layout density is high and the space on the front and back of the PCB is limited, the FLASH on the TOP layer and the Gsensor on the BOTTOM layer cannot be completely overlapped in the vertical direction. It is recommended that via 1 be close to Gsensor and slightly away from FLASH, so that the branch length L5 of the BOTTOM layer routing from via 1 to the Gsensor pad is much smaller than the branch length L4 of the TOP layer routing from via 1 to the FLASH pad. When the SPI routing from MCU to FLASH communicates, since Gsensor does not work and the branch length L5 of the BOTTOM layer routing from via 1 to the Gsensor pad is short, the Stub effect it produces is small. However, when the SPI routing from MCU to Gsensor communicates, since FLASH does not work and the branch length L4 of the TOP layer routing from via 1 to the FLASH pad is long, the Stub effect it produces is large. Since the data transmitted between Gsensor and MCU is usually a small-capacity digital signal, the Stub effect generated by the SPI routing from MCU to FLASH has a relatively small impact on the MCU to Gsensor. The SPI routing from MCU to Gsensor has a small amount of data and a low transmission rate (for example, 400kHz), and is not very sensitive to the Stub effect. The data volume required for the SPI routing from MCU to Gsensor is far less than that from MCU to FLASH, and FLASH will store some important data, programs, etc. The signal data volume transmitted between the SPI routing from MCU to FLASH is very large and the rate is high (for example, 10MHz). The SPI signal from MCU to FLASH is related to the system stability of the entire MCU, so it is necessary to give priority to protecting the quality of the SPI routing from MCU to FLASH.

[0071] exist Figure 6 Based on this, the SPI routing from MCU to via 1 is changed to the inner layer routing, and the following can be obtained: Figure 7 A cross-sectional view of the routing topology of the PCB board is shown.

[0072] Figure 8 Another cross-sectional view of the wiring topology of a PCB is given. Figure 8In the example shown, a master device and a slave device are provided on the PCB board, the master device is an MCU, and the slave devices include FLASH and an acceleration sensor Gsensor, wherein FLASH corresponds to the first slave device, Gsensor corresponds to the second slave device, and the SPI trace between the MCU and FLASH corresponds to the first trace. The MCU, FLASH, and Gsensor are all arranged on the TOP layer of the PCB board. The SPI trace from the MCU first changes layers to the inner layer through via 1, and then to via 2, and changes SCK, SIMO, SOMI, and CS / SS1 to the TOP layer and traces to the pad of Gsensor; and the SCK, SIMO, SOMI, and CS / SS2 on the inner layer continue to be led to via 3, and changes SCK, SIMO, SOMI, and CS / SS2 to the TOP layer and traces to the pad of FLASH. The routing from via 2 to the Gsensor pad is required to be as short-circuited as possible. The best solution is to set via 2 at the edge of the Gsensor pad. It is acceptable for the Gsensor pad to be tangent to via 2. Via 2 cannot be designed to be set on the Gsensor pad, which will cause tin leakage. If it is a resin-filled through hole, via 2 can be considered to be set on the Gsensor pad to shorten the Stub effect caused by the routing length between the Gsensor pad and via 2 as much as possible on the signal quality.

[0073] When MCU and FLASH communicate at a higher transmission rate of 10MHz, Gsensor does not work. Since the routing between the Gsensor pad and via 2 can be ignored, the Stub effect generated by the routing between the Gsensor pad and via 2 can be ignored, and the impact on the 10MHz signal transmission between MCU and FLASH is very small.

[0074] When the MCU and Gsensor communicate at a lower transmission rate of 400kHz, the Stub effect is larger due to the longer wiring between the FLASH pad and via 2. However, since the FLASH is not working at this time, the 400kHz rate is only 1 / 25 of the 10MHz rate. For the 400kHz rate, the Stub effect is acceptable and has little impact on the communication between the MCU and Gsensor. At the same time, the amount of data transmitted by the MCU and Gsensor is small. Therefore, Figure 8 The topology shown is acceptable for communication between MCU and Gsensor and meets the design requirements.

[0075] In order to reduce the crosstalk between the first traces in PCB design, the line spacing should be large enough. When the line center spacing of the first trace is not less than 3 times the line width, most of the electric fields can be kept from interfering with each other. This is the 3W principle. Fig. 9The top view of the SPI signal using the 3W routing principle is given. Fig. 9 As shown, when the line widths of SCK, SIMO, SOMI, and SS / CS are all W, the line center distance between them is 3W, and the edge spacing between them is 2W.

[0076] For the first routing above, Fig.10 The cross-sectional view of the SPI signal set on the surface layer using the 3W routing principle is given. Fig.10 The SCK routing and SIMO routing are used as examples for analysis and explanation. The SCK routing and the GND copper foil of the adjacent layer generate a pulse electric field (displacement current), and the SIMO routing and the GND copper foil of the adjacent layer generate a pulse electric field. If the 3W routing principle is adopted, 70%~80% of the pulse electric field generated by the SCK routing falls on the GND copper foil of the adjacent layer, and only 20%~30% falls on the SIMO routing on the same layer. The probability that the SIMO routing is affected by the pulse electric field generated by the SCK routing is only 20%~30%; by the same token, 70%~80% of the pulse electric field generated by the SIMO routing falls on the GND copper foil of the adjacent layer, and only 20%~30% falls on the SCK routing on the same layer. The probability that the SCK routing is affected by the pulse electric field generated by the SIMO routing is only 20%~30%.

[0077] Fig.11 A schematic diagram of the mutual inductance effect between two closed loops is given. During the transmission of the SCK line, the pulse current in the SCK line will generate a pulse magnetic field B1; during the transmission of the SIMO line, the pulse current in the SIMO line will generate a pulse magnetic field B2; since the SCK line and the SIMO line are adjacent, the pulse magnetic field B1 and the pulse magnetic field B2 are fully coupled to each other. For the two loops C1 and C2 that are close to each other, the magnetic field generated by the current I1 in loop C1 and the magnetic flux interlinked with loop C2 is , then the mutual inductance coefficient of loop C1 to C2 is defined as: ;

[0078] Similarly, the magnetic field generated by the current I2 in loop C2 and the magnetic flux interlinked with loop C1 is , define the mutual inductance coefficient of loop C2 to C1 as: .

[0079] In order to reduce the crosstalk between the above-mentioned first routing lines, another optional implementation is provided. Specifically, in the layer where the first routing line is located, ground wires are respectively provided at both ends of the first routing line, and ground holes are provided on the ground wires, and the ground holes are electrically connected to the ground copper foil in a direction perpendicular to the substrate. In this implementation, the ground wires provided at both ends of the first routing line and the ground holes provided on the ground wires can further provide a return path for the first routing line, and the grounding can play a shielding role, which can further improve the quality of the signal transmitted in the first routing line.

[0080] In an optional implementation, in order to avoid signal loss and further improve the quality of the communication signal between the master device and the first slave device, impedance control is performed on the clock line and the data line in the first line. Specifically, the impedance of the clock line and the impedance of the data line are both within a preset impedance range. The preset impedance range can be set according to actual conditions. In a specific example, the preset impedance range is 50Ω±10%, i.e. [45Ω, 55Ω]. In a specific implementation, the impedance of the clock line and the data line can be controlled by controlling the line width and / or spacing of the clock line and the data line so that the impedance of the two is within the same impedance range.

[0081] In an optional implementation, in order to ensure signal synchronization and further improve the quality of the communication signal between the master device and the first slave device, the clock line and the data line in the first line are made equal in length, specifically, the length of the clock line and the length of the data line are within the same length range. The length range can be set according to actual conditions.

[0082] For the first routing above, Fig.12 A top view of the SPI trace on the surface or inner layer is given. Fig.13 Another top view of SPI routing on the surface or inner layer is given. For the SCK, SIMO, SOMI, and SS / CS routing in SPI, the SCK routing has the highest requirements. It is best to require grounding at both ends. If it is not possible to do so, grounding on one side must be done to provide a return path for the SCK routing. At the same time, grounding can play a shielding role. SS / CS is a chip select signal, and the requirements are not high. Fig.12 As shown in the figure, ground wires are set at both ends of the SCK, SIMO, and SOMI lines, and ground holes are evenly drilled on the ground wires to provide return paths for the SCK, SIMO, and SOMI lines. At the same time, the ground wires can play a shielding role. If the line density is high and the space is limited, such as Fig.13 As shown in the figure, at least both ends of the SCK line need to be grounded.

[0083] For the first routing above, Fig.14 A cross-sectional view of the SPI trace on the surface or inner layer is given. Fig.14As shown, the pulse electric field generated on the left side of the SCK trace on the surface basically falls on the ground line on the same layer, and the pulse electric field generated on the right side of the SCK trace on the surface basically falls on the ground line on the same layer, while the pulse electric field falling on the SIMO trace can be ignored, that is, the pulse electric field generated by the SCK trace can be ignored for the SIMO trace. Similarly, the pulse electric field generated on the left side of the SIMO trace on the surface basically falls on the ground line on the same layer, while the pulse electric field falling on the SCK trace can be ignored, that is, the pulse electric field generated by the SIMO trace can be ignored for the SCK trace.

[0084] During the transmission process of SCK routing, the SCK routing, the GND copper foil of the adjacent layer, and the ground wire of the same layer form a return path. Since the spacing between the SCK routing and the ground wire of the same layer is very small (0.1mm), the loop formed is almost zero, and the pulse current of the SCK routing will generate a pulse magnetic field B1 confined to a very small space; during the transmission process of SIMO routing, the SIMO routing, the GND copper foil of the adjacent layer, and the ground wire of the same layer form a return path, and the loop formed is almost zero, and the pulse current of the SIMO routing will generate a pulse magnetic field B2 confined to a very small space; that is, the coupling between the pulse magnetic field B1 generated by the pulse current of the SCK routing and the pulse magnetic field B2 generated by the pulse current of the SIMO routing is very small, and the influence between them is very small.

[0085] from Fig.10 and 14 It can be seen that the method of wrapping the ground wire between the SPI traces will have less crosstalk impact than the method of using the 3W principle. Therefore, the quality of the communication signal can be improved by wrapping the ground wire between the SPI traces.

[0086] The following is the test process of the present embodiment:

[0087] In order to prove the rationality and practicality of the design of the device and wiring structure in the substrate structure provided in this embodiment, Figure 8 and Fig.12 Taking the application in substrate structure as an example, EMI radiation test and GPS antenna static test were carried out on wireless vehicle-mounted equipment.

[0088] 1. EMI radiation test and analysis process

[0089] EMI radiation is an important test indicator in the EMC test items of the EU CE certification, China 3C certification, and North American FCC certification. The EMI radiation test mainly takes the performance test of the wireless vehicle-mounted equipment as an example. Both the RE radiation test standard and the CE conducted emission test standard adopt the EN55022-2008 / GB9254-2008 standard, and conduct the test on the 0.15MHz~0.5MHz, 0.5MHz~30MHz, 30MHz~1GHz, and 1GHz~6GHz frequency bands of the wireless vehicle-mounted equipment. These frequency bands meet the Class B test requirements of the EN55022-2008 / GB9254-2008 standard. Figure 15 shows the radiation value emitted by the wireless vehicle-mounted equipment in the 0~1GHz test frequency band. Fig.15 A refers to the safety limit of the 3C certification standard. Products below this safety limit are qualified. B refers to the fluctuation curve of the radiation data of the tested product. Fig.15 It can be seen that line B is far away from line A, that is, it is much smaller than the safety standard value, which shows that the EMI radiation index is well controlled, that is, the device and routing structure in the substrate structure provided in this embodiment does not have a serious impact on the radiation of the entire product.

[0090] 2. Static test of GPS antenna

[0091] Fig.16 The results of the static test of the GPS antenna of the wireless vehicle device in an open space are given, including the conditions of the satellites that the wireless vehicle device can search in the sky at a certain point in time. Fig.16 It can be concluded that there are 9 satellites that meet the C / No value ≧40, while the specification requires that 4 or more satellites meet the C / No value ≧40 for accurate positioning, which far exceeds this requirement. It should be noted that the GPS module and GPS antenna are extremely sensitive devices, and the GPS RF routing is an extremely sensitive routing. This shows that the sensitive devices and routing structure in the substrate structure provided in this embodiment do not interfere with the GPS module, the GPS RF routing, and the GPS antenna.

[0092] in, Fig.16The "PRN" in the figure is the specific GPS satellite number that the wireless vehicle-mounted device can search for in a certain open location and at a certain point in time, which are: GPS satellite 1, GPS satellite 2, GPS satellite 3, GPS satellite 6, GPS satellite 11, GPS satellite 14, GPS satellite 17, GPS satellite 19, GPS satellite 30, GPS satellite 28, GPS satellite 199, GPS satellite 50, GPS satellite 40, GPS satellite 41; there are 9 satellites that meet the C / No value ≧40, which are: GPS satellite 2 (C / No value = 40), GPS satellite 11 (C / No value = 42), GPS satellite 14 (C / No value = 42), GPS satellite 17 (C / No value = 43), GPS satellite 19 (C / No value = 40), GPS satellite 30 (C / No value = 40), GPS satellite 28 (C / No value = 42), GPS satellite 50 (C / No value = 48), GPS satellite 41 (C / No value = 40); "BAND" is the corresponding bandwidth; "AZI" is the corresponding satellite's downward angle of view: 43°, 249°, 52°, 271°, 244°, 157°, 5°, 329°, 195°, none, 148°, 148°, 257°, ​​237°; "ELE" is the corresponding satellite's elevation angle: 8°, 11°, 34°, 48°, 16°, 75°, 48°, 38°, 16°, none, 59°, 59°, 20°, 46°.

[0093] Example 2

[0094] This embodiment provides an electronic device, including the substrate structure in Embodiment 1.

[0095] The electronic device provided in this embodiment may be an electric bicycle, a scooter, a driving recorder, a router, a mobile phone, a switch, a medical device, etc.

[0096] In this embodiment, by setting the length of the electrical connection between the master device and the first slave device in the substrate structure to be greater than the length of the electrical connection between the master device and the second slave device, the quality of the overall communication signal in the electronic device can be improved.

[0097] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A substrate structure, characterized in that: It includes a master device, a first slave device and a second slave device arranged on the same substrate, wherein the length of the electrical connection between the master device and the first slave device is greater than the length of the electrical connection between the master device and the second slave device, and the communication rate between the master device and the first slave device is greater than the communication rate between the master device and the second slave device.

2. The substrate structure according to claim 1, characterized in that: The length of the wire between the master device and the first slave device is greater than the length of the wire between the master device and the second slave device; Alternatively, a length of a metal lead from the master device to the first slave device is greater than a length of a metal lead from the master device to the second slave device.

3. The substrate structure according to claim 1, characterized in that: A routing length between the master device and the first slave device is greater than a routing length between the master device and the second slave device.

4. The substrate structure according to claim 3, characterized in that: The substrate is also provided with a first solder pad, a second solder pad and a third solder pad, the communication pin of the master device is electrically connected to the first solder pad, the communication pin of the first slave device is electrically connected to the second solder pad, the communication pin of the second slave device is electrically connected to the third solder pad, and the first solder pad and the second solder pad as well as the first solder pad and the third solder pad are all connected by wiring.

5. The substrate structure according to claim 3, characterized in that: A local ground copper foil is provided in a projection area in a layer adjacent to a layer where a first routing line is located, wherein the first routing line is a routing line between the master device and the first slave device.

6. The substrate structure according to claim 5, characterized in that: In the layer where the first routing line is located, ground wires are respectively provided at both ends of the first routing line, and ground holes are provided on the ground wires, and the ground holes are electrically connected to the ground copper foil in a direction perpendicular to the substrate.

7. The substrate structure according to claim 5 or 6, characterized in that: The first routing line includes a clock routing line and a data routing line, and the impedance of the clock routing line and the impedance of the data routing line are both within a preset impedance range.

8. The substrate structure according to claim 7, characterized in that: The length of the clock line and the length of the data line are within the same length range.

9. The substrate structure according to any one of claims 1 to 6, characterized in that: The master device, the first slave device and the second slave device are arranged on the same layer; Alternatively, the master device and the first slave device are arranged at the same layer, and the master device and the second slave device are arranged at different layers; Alternatively, the master device and the second slave device are arranged at the same layer, and the master device and the first slave device are arranged at different layers.

10. The substrate structure according to any one of claims 1 to 6, characterized in that: The number of the second slave devices is at least two.

11. An electronic device, characterized in that: The invention comprises the substrate structure according to any one of claims 1 to 10.

Images