Circuit board, manufacturing method thereof, and superconducting quantum computer

Abstract

The present invention provides a circuit board, a manufacturing method thereof, and a superconducting quantum computer, belonging to the technical fields of quantum information and circuit boards. The circuit board is used for carrying a superconducting quantum chip and includes: a signal sub-board including a superconducting circuit layer configured to transmit electrical signals of the superconducting quantum chip, and two dielectric layers provided on both sides of the superconducting circuit layer; and two shielding layers and two heat-conducting layers sequentially provided on both sides of the signal sub-board. Metallized vias are formed in the shielding layer, the dielectric layer, and the superconducting circuit layer to electrically connect the shielding layer to the superconducting circuit layer, so that the shielding layer performs electromagnetic shielding on the superconducting circuit layer, and the heat-conducting layer conducts the heat generated by the superconducting circuit layer to the outside through the metallized vias, the dielectric layer, and the shielding layer. The circuit board provided by the present invention has good anti-interference performance and good heat dissipation effect.

Description

Technical Field

[0001] The present invention belongs to the fields of quantum information and circuit boards, especially in the field of manufacturing and packaging of superconducting quantum chips. In particular, at least one embodiment of the present invention relates to a circuit board, a manufacturing method thereof, and a superconducting quantum computer. Background Art

[0002] Due to the sensitivity of superconducting quantum chips to environmental noise, superconducting quantum chips need to be physically protected and shielded from noise through encapsulation in an encapsulation box. As the number of superconducting qubits in the superconducting quantum chip increases, the number of signal lines required for the encapsulation box also increases accordingly.

[0003] Generally, a common copper-clad printed circuit board (Printed Circuit Board, abbreviated as PCB) is used inside the encapsulation box to transmit signals. When an electrical signal passes through the copper lines inside the encapsulation box, heat is generated, and as the number of lines increases, the problem of heat accumulation becomes more and more serious.

[0004] At the same time, if the heat dissipation capacity of the encapsulation box is insufficient and the heat generated inside the encapsulation box cannot be dissipated in time, the temperature of the encapsulation box will rise.

[0005] If the total heat generation inside the encapsulation box is too high and the refrigeration capacity of the refrigerator is not sufficient to completely offset this heat, the temperatures of all components in the MC (Mixing Chamber) layer of the refrigerator will also rise accordingly.

[0006] The above situations will cause the temperature of the superconducting quantum chip to rise, thereby reducing the fidelity of the 0 state (|0>) of the superconducting qubit. Summary of the Invention

[0007] In view of this, in order to at least partially solve the above-mentioned technical problems, the present invention provides a circuit board, a manufacturing method thereof, and a superconducting quantum computer. The circuit board can transmit the electrical signals of the superconducting quantum chip while ensuring sufficient heat dissipation and having strong anti-interference performance.

[0008] According to an embodiment of one aspect of the present invention, there is provided a circuit board for carrying a superconducting quantum chip, including: a signal sub-board, including a superconducting line layer configured to transmit electrical signals of the superconducting quantum chip, and two dielectric layers disposed on both sides of the superconducting line layer; and two shielding layers and two heat-conducting layers disposed on both sides of the signal sub-board in sequence. Metallized vias are formed in the shielding layer, the dielectric layer, and the superconducting line layer to electrically connect the shielding layer to the superconducting line layer, so that the shielding layer performs electromagnetic shielding on the superconducting line layer, and the heat-conducting layer conducts the heat generated by the superconducting line layer to the outside through the metallized vias, the dielectric layer, and the shielding layer.

[0009] According to an embodiment of another aspect of the present invention, there is provided a method for manufacturing the above-mentioned circuit board, including: providing a first circuit sub-board, wherein the first circuit sub-board includes a first dielectric layer, and a first superconducting plate layer and a first shielding layer respectively located on both sides of the first dielectric layer, and a first heat-conducting layer is provided on the surface of the first shielding layer, and the first shielding layer is electrically connected to the first superconducting plate layer through a first metallized via, wherein the first superconducting plate layer includes at least one signal line, and a first ground plane symmetrically arranged on both sides of the signal line along the first direction of the signal line; providing a second circuit sub-board, wherein the second circuit sub-board includes a second dielectric layer, and a second superconducting plate layer and a second shielding layer respectively located on both sides of the second dielectric layer, and a second heat-conducting layer is provided on the surface of the second shielding layer, and the second shielding layer is electrically connected to the second superconducting plate layer through a second metallized via, wherein the second superconducting plate layer includes at least one strip-shaped groove arranged through, and a second ground plane symmetrically arranged on both sides of the strip-shaped groove along the first direction of the strip-shaped groove; and aligning and welding the first circuit sub-board and the second circuit sub-board so that the signal line is embedded in the strip-shaped groove, and the first ground plane and the second ground plane are electrically connected.

[0010] According to an embodiment of still another aspect of the present invention, there is provided a superconducting quantum computer, including the above-mentioned circuit board; and a superconducting quantum chip, and the superconducting quantum chip is mounted on the above-mentioned circuit board.

[0011] For the circuit board for mounting a superconducting quantum chip provided by the above embodiment of the present invention, a superconducting circuit layer made of a superconducting material is used for transmitting electrical signals. Since the superconducting material has a small resistance and less heat generation in the superconducting state, the heat generation of the superconducting circuit layer can be reduced.

[0012] For the circuit board for mounting a superconducting quantum chip provided by the above embodiment of the present invention, a shielding layer located on both sides of the superconducting circuit layer is used to perform electromagnetic shielding on the superconducting circuit layer to shield interference signals, so that the circuit board has good anti-interference performance and can transmit electrical signals with high quality.

[0013] For the circuit board for mounting a superconducting quantum chip provided by the above embodiment of the present invention, the use of metallized vias and shielding layers is beneficial to enhancing the heat dissipation of the superconducting circuit layer to achieve a better heat dissipation effect, thereby being able to prevent problems such as a reduction in bit fidelity and chip failure caused by heat accumulation.

[0014] For the circuit board for mounting a superconducting quantum chip provided by the above embodiment of the present invention, the use of shielding layers and metallized vias increases the isolation degree between signal lines, and further reduces the crosstalk between signal lines.

[0015] According to the circuit board for carrying a superconducting quantum chip provided in the above embodiments of the present invention, the circuit board uses a ceramic material to make the dielectric layer. Since the ceramic material has a high thermal conductivity, it is beneficial to conduct the heat generated by the superconducting circuit layer, and thus beneficial to the heat dissipation of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention and do not limit the present invention.

[0017] Figure 1 Isometric structural schematic diagram of the circuit board provided by the embodiment of the present invention;

[0018] Figure 2 Cross-sectional schematic diagram of the circuit board provided by the embodiment of the present invention;

[0019] Figure 3 Flow schematic diagram of the manufacturing method of the circuit board provided by the embodiment of the present invention;

[0020] Figure 4 Isometric structural schematic diagram of the first circuit sub-board provided by the embodiment of the present invention;

[0021] Figure 5 Is Figure 4 Cross-sectional schematic diagram of the first circuit sub-board shown;

[0022] Figure 6 Isometric structural schematic diagram of the second circuit sub-board provided by the embodiment of the present invention;

[0023] Figure 7 Is Figure 6 Cross-sectional schematic diagram of the second circuit sub-board shown;

[0024] Figure 8 Process flow schematic diagram of manufacturing the first metallized via provided by the embodiment of the present invention;

[0025] Figure 9 Isometric structural schematic diagram of the first dielectric layer formed with the first metallized via provided by the embodiment of the present invention;

[0026] Figure 10 Is Figure 9 Cross-sectional schematic diagram of the first dielectric layer formed with the first metallized via shown;

[0027] Figure 11 Isometric structural schematic diagram of the signal lines and the first ground plane etched on the first superconducting plate layer on the first dielectric layer provided by the embodiment of the present invention;

[0028] Figure 12 IsFigure 11 Schematic cross-sectional view of the component shown;

[0029] Figure 13 Isometric structural schematic diagram of the first thermal conductive layer provided on the first shielding layer in the embodiment of the present invention;

[0030] Figure 14 Isometric structural schematic diagram of the first solder joint manufactured on the surface of the first metallized via in the embodiment of the present invention;

[0031] Figure 15 Isometric structural schematic diagram of the second solder joint manufactured on the surface of the second metallized via in the embodiment of the present invention;

[0032] Figure 16 Isometric structural schematic diagram of the alignment and welding of the first circuit sub-board and the second circuit sub-board provided in the embodiment of the present invention;

[0033] Figure 17 Cross-sectional schematic diagram of the alignment and welding of the first circuit sub-board and the second circuit sub-board provided in the embodiment of the present invention; and

[0034] Figure 18 Is a comparison diagram of the crosstalk simulation calculation results between the signal lines of the circuit boards provided in Comparative Example 1 and Embodiment 1 of the present invention.

[0035] Description of reference numerals:

[0036] 100 - Circuit board;

[0037] 1011 - First thermal conductive layer;

[0038] 1012 - First shielding layer;

[0039] 1021 - Second thermal conductive layer;

[0040] 1022 - Second shielding layer;

[0041] 200 - Signal sub-board;

[0042] 201 - First dielectric layer;

[0043] 202 - Second dielectric layer;

[0044] 203 - Superconducting circuit layer;

[0045] 2031 - First superconducting plate layer;

[0046] 2032 - Second superconducting plate layer;

[0047] 2033 - Signal line;

[0048] 2034 - First ground plane;

[0049] 2035 - Strip groove;

[0050] 2036 - Second ground plane;

[0051] 204 - First solder mask layer;

[0052] 205 - Second solder mask layer;

[0053] 11 - First circuit sub - board;

[0054] 111 - First metallized via;

[0055] 22 - Second circuit sub - board;

[0056] 112 - Second metallized via;

[0057] 113 - First solder joint;

[0058] 114 - Second solder joint. Detailed implementation manners

[0059] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the following further elaborates on the present invention in detail with reference to specific embodiments and the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the invention complete and thorough, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals throughout the drawings denote the same elements.

[0060] The terms used herein are merely for describing specific embodiments and are not intended to limit the present invention. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0061] A printed circuit board (PCB), abbreviated as such, is an important component in electronic devices. Functionally speaking, a PCB mainly realizes functions such as electrical connection, mechanical support, signal transmission, and heat dissipation.

[0062] Among them, electrical connection means connecting various electronic components together according to design requirements to form a complete circuit, thereby ensuring that current can flow smoothly between each component and realizing various functions of the electronic device.

[0063] Among them, mechanical support provides a fixing foundation and support for electronic components, enabling various electronic components to maintain the correct position, orientation, and attitude on the circuit board to ensure the stability and reliability of the electronic device.

[0064] Among them, signal transmission refers to the transmission and processing of signals to ensure signal integrity and accuracy, reduce signal interference and attenuation. Heat dissipation can dissipate the heat generated by electronic components to ensure the normal operation of electronic devices.

[0065] In related technologies, the basic structure of a PCB generally mainly includes an insulating substrate, conductive traces, pads, etc.

[0066] Among them, the insulating substrate is usually made of materials such as glass fiber and epoxy resin, and thus has good insulation performance and mechanical strength, thereby providing physical support for the circuit.

[0067] Among them, the conductive traces can be formed on the insulating substrate through micro-nano processing technologies such as coating and etching, and are usually implemented in the form of copper foil traces. The conductive traces are used to connect various electronic components to achieve the transmission of current or signals.

[0068] Among them, the pads are metal areas for soldering the pins of electronic components, providing electrical connection points for the components.

[0069] As an electronic device, a superconducting quantum chip also uses a PCB. Due to the particularity of the superconducting quantum chip (sensitivity to environmental noise, physical implementation, etc.), higher requirements are imposed on the PCB. For example, the superconducting quantum chip is sensitive to temperature. Too high a temperature will cause the superconducting circuit to quench, resulting in a significant decrease in the fidelity of superconducting qubits, and may even cause the superconducting quantum chip to malfunction. Moreover, various noise signals will interfere with the normal reading, control, etc. of superconducting qubits, thus affecting normal quantum computing.

[0070] Therefore, when mounting the superconducting quantum chip on the PCB, it is desired that the circuit board has good performance in the above aspects. However, there are various problems in the current use of the PCB, such as large heat generation, weak heat dissipation, poor anti-interference, etc.

[0071] In view of this, through research, the present invention proposes a circuit board, its manufacturing method, and a superconducting quantum computer. This circuit board uses superconducting materials to transmit signals and is also configured with materials for enhancing heat conduction, thereby taking into account the thermal design and electromagnetic design required during the packaging process of the superconducting quantum chip. It should be noted that the circuit board provided by the present invention is not limited to being applied to superconducting quantum chips, and can also be applied to conventional chips, classical chips, or semiconductor chips, or other electronic devices.

[0072] Figure 1 Isometric structural schematic diagram of the circuit board provided by the embodiment of the present invention.

[0073] Figure 2 Cross-sectional schematic diagram of the circuit board provided by the embodiment of the present invention.

[0074] According to an exemplary embodiment of the present invention, the present invention provides a circuit board for carrying a superconducting quantum chip, referring to Figure 1 , Figure 2 As shown, the circuit board 100 includes:

[0075] A signal sub-board 200, including a superconducting circuit layer 203 configured to transmit electrical signals of the superconducting quantum chip, and two dielectric layers provided on both sides of the superconducting circuit layer 203; and

[0076] Two shielding layers and two heat-conducting layers are sequentially provided on both sides of the signal sub-board 200. Metallized vias are formed in the shielding layer, the dielectric layer, and the superconducting circuit layer to electrically connect the shielding layer to the superconducting circuit layer 203, so that the shielding layer performs electromagnetic shielding on the superconducting circuit layer 203, and the heat-conducting layer conducts the heat generated by the superconducting circuit layer 203 to the outside through the metallized vias, the dielectric layer, and the shielding layer.

[0077] In an embodiment of the present invention, the signal sub-board 200 includes a first dielectric layer 201, a second dielectric layer 202, and a superconducting circuit layer 203 located between the first dielectric layer 201 and the second dielectric layer 202. The first dielectric layer 201 and the second dielectric layer 202 sandwich the superconducting circuit layer 203 inside, and can provide physical protection for the superconducting circuit layer 203.

[0078] In an embodiment of the present invention, the circuit board 100 includes a first shielding layer 1012 and a first heat-conducting layer 1011 that are sequentially stacked on the first side of the signal sub-board 200, and the first shielding layer 1012 covers the first dielectric layer 201, and the first shielding layer 1012 is electrically connected to the superconducting circuit layer 203 through a first metallized via penetrating the first dielectric layer 201.

[0079] In an embodiment of the present invention, the circuit board 100 includes a second shielding layer 1022 and a second heat-conducting layer 1021 that are sequentially stacked on the second side of the signal sub-board 200, and the second shielding layer 1022 covers the second dielectric layer 202, and the second shielding layer 1022 is electrically connected to the superconducting circuit layer 203 through a second metallized via penetrating the second dielectric layer 202.

[0080] In an embodiment of the present invention, the first shielding layer 1012 and the second shielding layer 1022 perform electromagnetic shielding on the superconducting circuit layer 203, that is, the shielding of interfering electrical signals can be realized, the signal transmission quality can be improved, and interference can be reduced. And the first shielding layer 1012 and the second shielding layer 1022 can also be used as a path for signal return, playing a role in signal return.

[0081] In an embodiment of the present invention, the first shielding layer 1012 and the second shielding layer 1022 can be made of superconducting materials, which is conducive to achieving a better electromagnetic shielding effect. The shielding layers made of superconducting materials on both sides of the superconducting circuit layer 203 perform electromagnetic shielding on the superconducting circuit layer 203, which can shield external interference signals, enabling the circuit board to have better anti-interference performance, and thus improving the transmission quality of electrical signals.

[0082] In some embodiments, the first shielding layer 1012, the second shielding layer 1022 and the superconducting circuit layer 203 can be made of the same material.

[0083] It should be noted that the material of the first dielectric layer 201 and the material of the second dielectric layer 202 can be the same or different.

[0084] In some embodiments, the materials of the first dielectric layer 201 and the second dielectric layer 202 can be organic materials, such as organic resins. The organic resins can be, for example, epoxy resins, polyimides or polytetrafluoroethylene. The thicknesses of the first dielectric layer 201 and the second dielectric layer 202 are not specifically limited herein and can be adjusted according to the actual usage scenarios and requirements of the circuit board 100.

[0085] In some embodiments, the first dielectric layer 201 and the second dielectric layer 202 can be ceramic layers independently. The first dielectric layer 201 and the second dielectric layer 202 are preferably made of ceramic materials. Since ceramic materials have a high thermal conductivity, they are more conducive to conducting the heat generated by the superconducting circuit layer 203, and thus are beneficial to the heat dissipation of the circuit board 100. Moreover, compared with the first dielectric layer 201 and the second dielectric layer 202 made of organic resins, the dielectric losses of the first dielectric layer 202 and the second dielectric layer 203 made of ceramic materials are low, so it is also beneficial to reduce signal insertion loss.

[0086] In an embodiment of the present invention, the ceramic materials include but are not limited to alumina, silica, silicon nitride, zirconia, aluminum nitride, beryllium oxide, silicon carbide, magnesia, Al2O3 doped with zirconium. Based on some classifications, the ceramic materials used can be High Temperature Co-fired Ceramic (HTCC) or Low Temperature Co-fired Ceramic (LTCC).

[0087] In some embodiments, the superconducting circuit layer 203 is made of a superconducting material with a high melting point (melting point greater than 600 °C). The superconducting materials include aluminum, tantalum, tantalum nitride, titanium nitride or niobium. Using a superconducting material with a high melting point is more conducive to manufacturing a circuit board with higher line accuracy and better flatness.

[0088] In some embodiments, the signal lines 2033 in the superconducting line layer 203 may have different structural forms. For example, the superconducting line layer 203 includes at least one signal line 2033 and a ground plane ( Figure 1 and Figure 2 not labeled). In some examples, the superconducting line layer may be implemented in the form of a coplanar waveguide transmission line. Therefore, the signal line 2033 can be the center conductor of the coplanar waveguide, and ground planes are symmetrically distributed along the first direction (the length direction of the center conductor) of the center conductor, and there is a gap between the center conductor and the ground planes, for example, it can be a spacer region of vacuum or air medium.

[0089] In some embodiments, the superconducting line layer 203 may include a single-layer superconducting plate layer. The single-layer superconducting plate layer includes at least one signal line 2033 and ground planes symmetrically disposed on both sides of the signal line 2033 along the first direction (the first direction is the length direction of the signal line 2033), wherein the signal line 2033 and the ground planes are in the same plane. That is to say, the signal line 2033 is formed by the single-layer superconducting plate layer, and the ground planes are also formed by the single-layer superconducting plate layer.

[0090] In some embodiments, the superconducting line layer 203 may be composed of multiple superconducting plate layers. For example, the number of superconducting plate layers can be 2, 3, 4, 5, but is not limited to the listed values.

[0091] In some embodiments, referring to Figure 2 as shown, the superconducting line layer 203 may include a first superconducting plate layer 2031 and a second superconducting plate layer 2032 that are stacked and welded together.

[0092] In the embodiments of the present invention, the signal line 2033 is formed by the first superconducting plate layer 2031, and the ground plane is jointly formed by the first superconducting plate layer 2031 and the second superconducting plate layer 2032.

[0093] In some embodiments, the first superconducting plate layer 2031 is used to form the signal line 2033 and first ground planes symmetrically disposed on both sides of the signal line 2033 along the first direction (the first direction is the length direction of the signal line 2033), wherein the signal line 2033 and the first ground planes are in the same plane.

[0094] In the embodiments of the present invention, the second superconducting plate layer 2032 has at least one strip-shaped groove penetrating therethrough and second ground planes symmetrically disposed on both sides of the strip-shaped groove along the first direction of the strip-shaped groove, and the second ground planes are welded to the first ground planes to form the ground plane.

[0095] In an embodiment of the present invention, the shape of the orthographic projection of the signal line 2033 on the first dielectric layer 201 is rectangular, and the shape of the orthographic projection of the strip-shaped groove on the first dielectric layer 201 is rectangular. The orthographic projection of the signal line 2033 on the first dielectric layer 201 is located within the orthographic projection area of the strip-shaped groove on the first dielectric layer 201.

[0096] That is to say, the width of the strip-shaped groove 404 along the second direction perpendicular to the first direction is greater than the width of the signal line 2033 along the second direction, and the projection of the center line of the signal line 2033 along the first direction on the first dielectric layer 201 is aligned with the projection of the center line of the strip-shaped groove 404 along the first direction on the first dielectric layer 201, so as to embed the signal line 2033 into the strip-shaped groove.

[0097] In some embodiments, the signal line 2033 may be jointly formed by the first superconducting plate layer 2031 and the second superconducting plate layer 2032, and the ground plane may be jointly formed by the first superconducting plate layer 2031 and the second superconducting plate layer 2032.

[0098] In an embodiment of the present invention, the ground planes provided by the multi-layer superconducting plate layers can be connected by welding. Considering heat transfer, a material with a relatively high thermal conductivity can be selected as the welding material. And considering signal return, in some examples, the welding material is conductive or can transmit electrical signals, so that the ground planes of each layer are conductively connected.

[0099] In some embodiments, the welding material can be selected as tin.

[0100] In some embodiments, the welding material can be a metal or alloy with a low melting point, such as a metal or alloy with a melting point below 300°C. Exemplarily, the welding material can be indium metal, tin-lead alloy or tin-bismuth alloy.

[0101] In some embodiments, when the first dielectric layer 201 and the second dielectric layer 202 are ceramic materials, due to the strong high-temperature resistance of the ceramic materials, a metal with a higher temperature such as aluminum (melting point 660°C) can be used as the welding material.

[0102] In some embodiments, the first heat-conducting layer 1011 and the second heat-conducting layer 1021 are configured with the same material or different materials. The first heat-conducting layer 1011 and / or the second heat-conducting layer 1021 can be non-metallic materials. In some embodiments, both the first heat-conducting layer 1011 and the second heat-conducting layer 1021 are preferably copper layers to achieve better heat-conducting effects.

[0103] In some embodiments, the first metallized via 111 and the second metallized via 112 can be non-metal columns or metal columns (such as copper columns). Considering the manufacturing of the metallized vias, they can be further configured as multi-layer structures, such as multiple concentric columns. In the example, the copper column is selected for implementation because its process is relatively easier to achieve.

[0104] In an embodiment of the present invention, the first shielding layer 1012 and the first heat-conducting layer 1011 being in contact with each other can achieve heat transfer. At the same time, the first metallized via 111 can also transfer the heat generated by the superconducting circuit layer 203 to the first heat-conducting layer 1011, and then conduct the heat out through the first heat-conducting layer 1011. The second shielding layer 1022 and the second heat-conducting layer 1021 being in contact with each other can achieve heat transfer. At the same time, the second metallized via 112 can also transfer the heat generated by the superconducting circuit layer 203 to the second heat-conducting layer 1021, and then conduct the heat out through the second heat-conducting layer 1021. In addition to being able to connect to the ground plane for signal return and heat dissipation, the first metallized via 111 and the second metallized via 112 can also play a positive role in the isolation between lines. Specifically, the metal vias between signal lines weaken the electromagnetic interaction between adjacent signal lines, and the weaker the interaction, the higher the isolation. By using shielding layers and metallized vias, the isolation between signal lines is increased, and thus crosstalk between signal lines can be reduced.

[0105] In an embodiment of the present invention, the superconducting quantum chip can be encapsulated in an encapsulation box, and the first heat-conducting layer 1011 and the second heat-conducting layer 1021 of the circuit board carrying the superconducting quantum chip can be respectively connected to the heat sink in the encapsulation box (used to absorb and dissipate heat; conduct the heat away from heat sources such as electronic components, and dissipate the heat to the surrounding environment by increasing the surface area, etc.) for heat dissipation.

[0106] According to an exemplary embodiment of the present invention, the present invention provides a superconducting quantum computer, including the above-mentioned circuit board; and a superconducting quantum chip, where the superconducting quantum chip is mounted on the above-mentioned circuit board.

[0107] Figure 3 It is a schematic flow chart of the manufacturing method of the circuit board provided by the embodiment of the present invention.

[0108] According to an exemplary embodiment of the present invention, the present invention provides a manufacturing method of a circuit board, as shown in reference Figure 3 and includes: operations S1 to S3.

[0109] Operation S1, providing the first circuit sub-board 11.

[0110] Figure 4Isometric structural schematic diagram of the first circuit sub-board provided by an embodiment of the present invention.

[0111] Figure 5 Is Figure 4 Cross-sectional schematic diagram of the first circuit sub-board shown in the figure.

[0112] In some embodiments, referring to Figure 4 , Figure 5 As shown, the first circuit sub-board 11 includes a first dielectric layer 201, and a first superconducting plate layer 2031 and a first shielding layer 1012 respectively located on both sides of the first dielectric layer 201. The first shielding layer 1012 is electrically connected to the first superconducting plate layer 2031 through a first metallized via 111. A first heat-conducting layer 1011 is provided on the surface of the first shielding layer 1012. The first superconducting plate layer 2031 includes at least one signal line 2033 and first ground planes 2034 symmetrically arranged on both sides of the signal line 2033 along the first direction of the signal line 2033.

[0113] Referring to Figure 5 As shown, both ends of the first metallized via 111 are electrically connected to the first shielding layer 1012 and the first ground plane 2034 of the first superconducting plate layer 2031 respectively.

[0114] Operation S2, provide the second circuit sub-board 22.

[0115] Figure 6 Isometric structural schematic diagram of the second circuit sub-board provided by an embodiment of the present invention.

[0116] Figure 7 Is Figure 6 Cross-sectional schematic diagram of the second circuit sub-board shown in the figure.

[0117] In some embodiments, referring to Figure 6 , Figure 7 As shown, the second circuit sub-board 22 includes a second dielectric layer 202 and a second superconducting plate layer 2032 and a second shielding layer 1022 respectively located on both sides of the second dielectric layer 202. The second shielding layer 1022 is electrically connected to the second superconducting plate layer 2032 through a second metallized via 112. A second heat-conducting layer 1021 is covered on the second shielding layer 1022. The second superconducting plate layer 2032 includes at least one strip groove 2035 and second ground planes 2036 symmetrically arranged on both sides of the strip groove 2035 along the first direction of the strip groove 2035.

[0118] Referring to Figure 7 As shown, both ends of the second metallized via 112 are electrically connected to the second shielding layer 1022 and the second ground plane 2036 of the second superconducting plate layer 2032 respectively.

[0119] It should be noted that operations S1 and S2 can be implemented simultaneously or successively, and the specific order is not particularly limited.

[0120] Operation S3: Align and weld the first circuit sub-board 11 and the second circuit sub-board 22 so that the signal line 2033 is embedded in the strip-shaped groove 2035, and the first ground plane 2034 and the second ground plane 2036 are electrically connected.

[0121] In an embodiment of the present invention, the orthographic projection of the signal line 2033 on the first dielectric layer 201 is located within the orthographic projection area of the strip-shaped groove 2035 on the first dielectric layer 201, so that the signal line 2033 is embedded in the strip-shaped groove 2035. Moreover, the first ground plane 2034 and the second ground plane 2036 are electrically connected to form a ground plane.

[0122] In an embodiment of the present invention, by separately manufacturing the first circuit sub-board and the second circuit sub-board and aligning and welding the first circuit sub-board and the second circuit sub-board, the manufacturing difficulty of the circuit board can be reduced. And it can solve the problem of the mismatch of the interlayer positions caused by the accumulation of interlayer alignment errors or deviations during the layer-by-layer manufacturing of the circuit board.

[0123] Figure 8 It is a schematic process flow diagram for manufacturing the first metallized via provided by an embodiment of the present invention.

[0124] Figure 9 It is an isometric structural schematic diagram of the first dielectric layer formed with the first metallized via provided by an embodiment of the present invention.

[0125] Figure 10 It is Figure 9 a schematic cross-sectional diagram of the first dielectric layer formed with the first metallized via as shown.

[0126] In an embodiment of the present invention, referring to Figure 8 、 Figure 9 、 Figure 10 as shown, the process flow for manufacturing the first metallized via 111 on the first dielectric layer 201 includes steps S10 to S40.

[0127] Step S10: Form metal layers on the first surface and the second surface opposite to the first surface of the first dielectric layer 201 respectively.

[0128] In some embodiments, the metal layer can be, for example, a copper layer.

[0129] In some embodiments, the method of electron beam evaporation or magnetron sputtering is used to deposit copper metal layers on the first surface and the second surface opposite to the first surface of the first dielectric layer 201 respectively. The thickness of the copper metal layer can be, for example, 30 μm.

[0130] Step S20, form a plurality of first vias penetrating through the first dielectric layer 201.

[0131] In an embodiment of the present invention, a laser is used to punch holes at preset positions of the first dielectric layer 201 to form a plurality of first vias penetrating through the first dielectric layer 201. The aperture of the first via can be, for example, 0.1 mm.

[0132] Step S30, deposit metal on the sidewalls of the first vias so that the metal in the first vias is flush with the metal layer.

[0133] In an embodiment of the present invention, electrolytic copper plating is used to deposit copper metal on the sidewalls of the first vias, so that the copper metal in the first vias is connected to the metal layers on both sides of the first dielectric layer 201 and is flush with the metal layer.

[0134] Step S40, etch the metal layer on the first dielectric layer 201 so that the area of the metal layer corresponding to the first vias is retained, and the remaining area of the metal layer is removed to form a first metallized via 111 penetrating through the first dielectric layer 201.

[0135] In an embodiment of the present invention, a photosensitive ink or photoresist is coated on one of the metal layers on the first dielectric layer 201, the designed area is exposed by using a photomask and ultraviolet exposure, and then the metal layer is etched, leaving only the area of the metal layer corresponding to the first vias. The area of the metal layer corresponding to the first vias is circular, and the diameter of the circle is greater than the aperture of the first via. The diameter of the circle is, for example, 0.3 mm.

[0136] In some embodiments, the preparation process of the first metallized via 111 may be the same as that of the second metallized via 112.

[0137] Figure 11 Isometric structural schematic diagram of a signal line and a first ground plane etched on a first superconducting plate layer on a first dielectric layer provided by an embodiment of the present invention.

[0138] Figure 12 Is Figure 11 Schematic cross-sectional view of the component shown.

[0139] Refer to Figure 11 、 Figure 12 As shown, a first superconducting plate layer 2031 and a first shielding layer 1012 are respectively formed on both sides of the first dielectric layer 201. Then, the first superconducting plate layer 2031 is etched to form at least one signal line 2033 and a first ground plane 2034.

[0140] In some embodiments, an atomic layer deposition method, a magnetron sputtering method, or an electron beam evaporation method is used to deposit superconducting materials on both sides of the first dielectric layer 201 to form a first superconducting plate layer 2031 and a first shielding layer 1012.

[0141] In an embodiment of the present invention, before depositing the first superconducting plate layer 2031 and the first shielding layer 1012, an argon ion cleaning can be used to in-situ remove the oxide layer on the surface of the first metallized via 111, so as to reduce the contact resistance between the superconducting material and the first metallized via 111.

[0142] In some embodiments, a photosensitive ink or photoresist is coated on the first superconducting plate layer 2031, and the designed circuit area is exposed by using a photomask and ultraviolet exposure, and then the first superconducting plate layer 2031 is etched to form at least one signal line 2033 and a first ground plane 2034.

[0143] In some embodiments, the first superconducting plate layer 2031 is etched by wet etching, and the selectivity ratio of the etching solution to the first metallized via 111 is controlled to avoid etching away the metal of the first metallized via 111. Exemplarily, when the superconducting material is aluminum, an alkaline etching solution that does not react with the metal of the first metallized via 111 (such as copper metal) can be used for etching, such as sodium hydroxide, potassium hydroxide, or tetramethylammonium hydroxide (TMAH).

[0144] In some embodiments, the first superconducting plate layer 2031 is etched by dry etching. In addition to improving the selectivity ratio, the etching depth can also be controlled by the process until the etching stops when reaching the first metallized via 111.

[0145] Figure 13 An isometric structural schematic diagram of setting a first heat conducting layer on the first shielding layer provided by an embodiment of the present invention.

[0146] Reference Figure 13 As shown, a first heat conducting layer 1011 is deposited on the first shielding layer 1012 by a magnetron sputtering method or an electron beam coating method. The first heat conducting layer 1011 can be a copper metal layer, and the first heat conducting layer 1011 is directly connected to the first metallized via 111, which can enhance the heat dissipation capacity of the circuit board.

[0147] Figure 14 A structural schematic diagram of manufacturing a first tin solder joint on the surface of the first metallized via provided by an embodiment of the present invention.

[0148] Figure 15 A structural schematic diagram of manufacturing a second tin solder joint on the surface of the second metallized via provided by an embodiment of the present invention.

[0149] Figure 16Schematic diagram of the alignment and welding of the first circuit sub-board and the second circuit sub-board provided by the embodiment of the present invention.

[0150] Figure 17 Cross-sectional schematic diagram of the alignment and welding of the first circuit sub-board and the second circuit sub-board provided by the embodiment of the present invention.

[0151] In the embodiment of the present invention, referring to Figure 14 As shown, a first solder joint 113 is provided at one end of the first metallized via 111 close to the first superconducting plate layer 2031.

[0152] In some embodiments, a fixed-point laser ball placement or a stencil ball placement method can be used to fabricate the first solder joint 113 on the surface of the first metallized via 111.

[0153] In some embodiments, a method of applying solder paste on a stencil or spraying tin on a stencil can be used to fabricate the first solder joint 113 on the surface of the first metallized via 111.

[0154] In the embodiment of the present invention, referring to Figure 15 As shown, a second solder joint 114 is provided at one end of the second metallized via 112 close to the second superconducting plate layer 2032.

[0155] In the embodiment of the present invention, the alignment welding of the first circuit sub-board 11 and the second circuit sub-board 22 includes welding the first solder joint 113 and the second solder joint 114.

[0156] In some embodiments, before aligning and welding the first circuit sub-board 11 and the second circuit sub-board 22, a first solder mask layer 204 is provided on the non-solder joint area of the surface of the first superconducting plate layer 2031 away from the first dielectric layer 201, so that the first solder joint 113 located on the first metallized via 111 is more likely to be formed.

[0157] In some embodiments, before aligning and welding the first circuit sub-board 11 and the second circuit sub-board 22, a second solder mask layer 205 is provided on the non-solder joint area of the surface of the second superconducting plate layer 2032 away from the second dielectric layer 202, so that the second solder joint 114 located on the second metallized via 112 is more likely to be formed.

[0158] In some embodiments, the first solder mask layer 204 and / or the second solder mask layer 205 can be selected to be composed of a solder resist. In some examples, the first solder mask layer 204 and / or the second solder mask layer 205 can be solder resist ink (also known as green oil).

[0159] In some embodiments, the main components of the solder resist may include various chemical substances such as resin, solvent, filler, and pigment.

[0160] Among them, the resin is one of the main components of the solder mask, and usually various types such as epoxy resin, polyimide resin, acrylic resin, carboxylated epoxy acrylate, etc. are adopted. The resin has excellent heat resistance and electrical insulation properties, and can effectively protect the areas on the circuit board that do not need to be soldered.

[0161] The solvent evenly mixes substances such as resin and filler, so as to be evenly coated (in thickness) on the circuit board. The solvent can be low-boiling organic compounds such as acetone, toluene, ethanol, etc.

[0162] The filler is used to adjust the viscosity and fluidity of the solder mask, and increase the impact resistance and wear resistance. The filler materials include but are not limited to silica, alumina, glass fiber, etc.

[0163] For some superconducting metals that are not wetted by tin, since they can naturally act as a solder mask layer, there is no need to form a solder mask layer on the surface of the first superconducting plate layer 2031 and / or the second superconducting plate layer 2032.

[0164] In some embodiments, the material of the first superconducting plate layer 2031 and / or the second superconducting plate layer 2032 is, for example, metal aluminum. Since an aluminum oxide layer is formed on the surface of the metal aluminum and the aluminum oxide layer is not wetted by tin, the aluminum oxide layer can serve as a natural solder mask layer, and at this time, there is no need to form a solder mask layer on the first superconducting plate layer 2031 and / or the second superconducting plate layer 2032.

[0165] In the embodiments of the present invention, the solder mask layer can conduct the first shielding layer 1012 and the second shielding layer 1022 at the electronics level, so as to reduce the grounding impedance of the superconducting line layer 203, enhance the shielding of the signal line 2033, and reduce the crosstalk between adjacent lines.

[0166] Reference Figure 16 、 Figure 17 As shown in, after the first circuit sub-board 11 and the second circuit sub-board 22 are respectively manufactured, the second circuit sub-board 22 is placed upside down on the first circuit sub-board 11, and after alignment, welding is performed.

[0167] In some embodiments, a flip-chip bonder is used to control the temperature to make the solder joints (solder balls) in a molten state, and forced alignment is performed to complete the assembly process.

[0168] In some embodiments, a method similar to the self-alignment welding of BGA (Ball Grid Array) chips is used to completely melt the solder joints (solder balls) into a liquid state, and the self-alignment welding is completed by using the surface tension of the solder balls. This method saves costs and does not require expensive flip-chip bonding equipment.

[0169] The following schematically illustrates the designed circuit board. It should be noted that this illustrative example is only a specific embodiment of the present invention and does not limit the protection scope of the present invention.

[0170] Example 1

[0171] Refer to Figure 17 As shown, a circuit board is manufactured. Specifically, the circuit board includes: a signal sub-board, including a superconducting line layer 203 configured to transmit electrical signals of a superconducting quantum chip, and two dielectric layers provided on both sides of the superconducting line layer 203; and two shielding layers and two heat-conducting layers sequentially provided on both sides of the signal sub-board. Metallized vias are formed through the shielding layer, the dielectric layer, and the superconducting line layer, and the distance between adjacent two metallized vias is 300 μm. The superconducting line layer 203 includes two signal lines 2033, and ground planes symmetrically provided on both sides of the signal lines 2033 along the first direction of the signal lines 2033. The two ends of the metallized via are respectively electrically connected to the shielding layer and the ground plane.

[0172] The superconducting quantum chip is mounted on the circuit board manufactured in Example 1 through a connecting wire, and the crosstalk (isolation) between the signal lines of the circuit board is simulated and calculated.

[0173] Comparative Example 1

[0174] A circuit board is manufactured by the same method as in Example 1, except that the circuit board does not have metallized vias.

[0175] The superconducting quantum chip is mounted on the circuit board manufactured in Comparative Example 1 through a connecting wire, and the crosstalk (isolation) between the signal lines of the circuit board is simulated and calculated.

[0176] Figure 18 It is a comparative diagram of the crosstalk simulation calculation results between the signal lines of the circuit boards provided in Comparative Example 1 and Example 1 of the present invention.

[0177] Refer to Figure 18 As shown, the simulation calculation results show that the isolation of Example 1 is higher than that of Comparative Example 1. The shielding layer, the dielectric layer, and the superconducting line layer of the circuit board provided in Example 1 are formed with through metallized vias, and the isolation between the signal lines of the circuit board is calculated to be 38.8875 db at 7 GHz through simulation. The circuit board provided in Comparative Example 1 does not have metallized vias, and the isolation between the signal lines of the circuit board is calculated to be 36.4344 db at 7 GHz through simulation. Compared with Comparative Example 1, in Example 1 of the present invention, by forming through metallized vias in the shielding layer, the dielectric layer, and the superconducting line layer, the isolation between the signal lines is increased by approximately 2.45 db, which shows that the metallized vias have a certain effect on suppressing microwave crosstalk.

[0178] The ordinal terms used in the description and claims, such as "first", "second", "third", etc., are used to modify the corresponding elements. They do not themselves imply any ordinal number for the element, nor do they represent the order of one element relative to another or the order in the manufacturing method. The use of these ordinal terms is only to clearly distinguish an element with a certain name from another element with the same name.

[0179] The specific embodiments described above further elaborate on the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A circuit board for carrying a superconducting quantum chip, characterized in that, Comprising: A signal sub-board, including a superconducting circuit layer configured to transmit electrical signals of a superconducting quantum chip, and two dielectric layers disposed on both sides of the superconducting circuit layer; And Two shielding layers and two heat-conducting layers sequentially disposed on both sides of the signal sub-board, and a through metallized via is formed in the shielding layer, dielectric layer, and superconducting circuit layer to electrically connect the shielding layer to the superconducting circuit layer, so that the shielding layer performs electromagnetic shielding on the superconducting circuit layer, and the heat-conducting layer conducts the heat generated by the superconducting circuit layer to the outside through the metallized via, the dielectric layer, and the shielding layer; The dielectric layer is a ceramic layer; The shielding layer is a superconducting layer.

2. The circuit board according to claim 1, wherein The heat-conducting layer is a copper layer; And / or, the metallized via is a copper pillar.

3. The circuit board according to claim 1, characterized in that, The superconducting circuit layer includes at least one signal line, and ground planes symmetrically disposed on both sides of the signal line along a first direction of the signal line; Wherein, two ends of the metallized via are respectively electrically connected to the shielding layer and the ground plane; And / or, the superconducting circuit layer includes a first superconducting plate layer and a second superconducting plate layer that are stacked and welded.

4. The circuit board according to claim 3, characterized in that The signal line of the superconducting circuit layer is made of the first superconducting plate layer, and the ground plane of the superconducting circuit layer is made of the first superconducting plate layer and the second superconducting plate layer.

5. The circuit board according to claim 4, characterized in that, The second superconducting plate layer has at least one strip-shaped groove penetrating therethrough; The orthographic projection of the signal line on the dielectric layer is located within the orthographic projection area of the strip-shaped groove on the dielectric layer.

6. A manufacturing method of a circuit board according to any one of claims 1 to 5, characterized in that, Comprising: Providing a first circuit sub-board, wherein the first circuit sub-board includes a first dielectric layer, and a first superconducting plate layer and a first shielding layer respectively disposed on both sides of the first dielectric layer, and a first heat-conducting layer is disposed on the surface of the first shielding layer, and the first shielding layer is electrically connected to the first superconducting plate layer through a first metallized via, wherein the first superconducting plate layer includes at least one signal line, and a first ground plane symmetrically disposed on both sides of the signal line along a first direction of the signal line; Providing a second circuit sub-board, wherein the second circuit sub-board includes a second dielectric layer, and a second superconducting plate layer and a second shielding layer respectively disposed on both sides of the second dielectric layer, and a second heat-conducting layer is disposed on the surface of the second shielding layer, and the second shielding layer is electrically connected to the second superconducting plate layer through a second metallized via, wherein the second superconducting plate layer includes at least one strip-shaped groove penetrating therethrough, and a second ground plane symmetrically disposed on both sides of the strip-shaped groove along a first direction of the strip-shaped groove; And Aligning and welding the first circuit sub-board and the second circuit sub-board so that the signal line is embedded in the strip-shaped groove, and the first ground plane and the second ground plane are electrically connected.

7. The manufacturing method according to claim 6, characterized in that, Further comprising: Providing a first solder joint at one end of the first metallized via close to the first superconducting plate layer, and providing a second solder joint at one end of the second metallized via close to the second superconducting plate layer; Aligning and welding the first circuit sub-board and the second circuit sub-board includes welding the first solder joint and the second solder joint.

8. The manufacturing method according to claim 7, characterized in that, Before aligning and welding the first circuit sub-board and the second circuit sub-board, further comprising: A first solder mask layer is provided on a non-soldering point area of a surface of the first superconducting plate layer away from the first dielectric layer; and / or, a second solder mask layer is provided on a non-soldering point area of a surface of the second superconducting plate layer away from the second dielectric layer.

9. The manufacturing method according to claim 6, characterized in that, The formation process of the first metallized via includes: forming metal layers on a first surface and a second surface opposite to the first surface of the first dielectric layer respectively; forming a plurality of first through holes penetrating through the first dielectric layer; depositing metal on side walls of the first through holes so that the metal in the first through holes is flush with the metal layers; and etching the metal layers on the first dielectric layer so that areas of the metal layers corresponding to the first through holes are reserved and remaining areas of the metal layers are removed.

10. A superconducting quantum computer, characterized in that, including a circuit board according to any one of claims 1 to 5; and a superconducting quantum chip, the superconducting quantum chip being mounted on the circuit board.

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