Embedded substrate, power supply device and electronic equipment

Abstract

The embodiment of the invention discloses an embedded substrate, a power supply device and electronic equipment. The embedded substrate comprises a front surface first adding layer jointed with the first surface of the core part maintaining body, a conduction structure electrically connected with a circuit layer of the dielectric layer is arranged in the dielectric layer of the front surface first adding layer, and the conduction structure comprises a first conduction structure electrically connected with a bonding pad on the chip; the dielectric layer of the first additional layer on the front side is made of an exposable and developable material, an open pore for constructing the conduction structure is formed through exposure and development, the open window of the outer protection layer has a first projection on the first surface, the first open pore for constructing the first conduction structure has a second projection on the first surface, and the second projection covers the first projection. Through the arrangement, the first conduction structure with a larger through-flow cross section is constructed and formed by utilizing the windowing size of the chip side, so that the through-flow capability is effectively improved, and the heat conduction capability is high. In addition, the bonding stress between the circuit layer and the front surface of the chip can be reduced, the layering risk is reduced, and the reliability is better.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of electronic component packaging, and in particular to an embedded substrate, a power supply device, and an electronic device. Background Art

[0002] Embedded substrate technology can embed electronic components in the substrate, such as but not limited to chips, resistors, capacitors, inductors and other components, and interconnect them through peripheral lines to form highly integrated, high-density functional modules. Embedded substrate technology can be used in a variety of different application scenarios. With the continuous evolution of product functions, achieving high current, high heat dissipation and high reliability has become the core requirement of embedded substrates.

[0003] A typical power chip packaging module, in which the chip and other components are buried in the core board structure, and the core board surface is stacked with a build-up layer to achieve a highly integrated circuit for interconnection. Usually, the pad on the front of the chip is exposed to the window of the PI layer, and a blind hole is formed in the build-up layer adjacent to the chip through a Laser process to establish an electrical connection between the chip side and the build-up layer side. However, due to the position accuracy of the chip layout and the position accuracy of the blind hole processing, a ring width needs to be reserved between the blind hole and the window of the PI layer, and the diameter of the blind hole is smaller than the window size of the chip PI layer. The window size of the chip material is fixed, which limits the flow and thermal conductivity of the blind hole to the design bottleneck, which directly affects the flow and thermal conductivity of the front of the chip. Summary of the invention

[0004] The embodiments of the present application provide an embedded substrate, a power supply device and an electronic device, which achieve high current, high heat dissipation and high reliability by optimizing the structure of the embedded substrate.

[0005] According to a first aspect of an embodiment of the present application, there is provided an embedded substrate, which includes a core retaining body, a build-up layer and a chip embedded in the core retaining body; wherein the core retaining body includes a first surface and a second surface, and the front side of the chip is arranged toward the first surface of the core retaining body; an outer protective layer is arranged outside the solder pad of the chip, and the outer protective layer has a window arranged corresponding to the solder pad on the chip; wherein the build-up layer includes a front build-up layer covering the first surface of the core retaining body, the front build-up layer includes a front first build-up layer bonded to the first surface of the core retaining body and the front side of the chip, and the front first build-up layer includes The present invention comprises a dielectric layer and a circuit layer which are stacked, and a conductive structure electrically connected to the circuit layer is arranged in the dielectric layer of the first build-up layer on the front side, and the conductive structure comprises a first conductive structure electrically connected to the pad on the chip; wherein the dielectric layer of the first build-up layer on the front side is made of an exposeable and developable material, and an opening for constructing the conductive structure is formed by exposure and development, and the opening for constructing the first conductive structure is a first opening; the window of the outer protective layer has a first projection on the first surface, and the first opening corresponding to the window has a second projection on the first surface, and the second projection covers the first projection.

[0006] Such a configuration, on the one hand, can maximize the use of the window size on the chip side to construct a first conductive structure, the first conductive structure can have a larger flow cross-section, can effectively improve the flow capacity, and at the same time have good thermal conductivity. On the other hand, the first opening of the first conductive structure is formed by exposure and development process, which can avoid the process difficulty of traditional laser opening, and has better processability.

[0007] In addition, compared with the solution of improving the thermal conductivity of the substrate by plating a copper layer on the outer protective layer on the front side of the chip, in the embodiment of the present application, the dielectric layer of the first build-up layer on the front side and the outer protective layer on the chip side are both organic materials, and the dielectric layer of the first build-up layer on the front side can reduce the bonding stress between the circuit layer and the front side of the chip, and reduce the risk of interlayer interface delamination. Overall, it has better reliability.

[0008] Exemplarily, the light-exposure-developable material may be a dry film, which may be formed by lamination; in other exemplary embodiments, the light-exposure-developable material may also be a liquid photosensitive adhesive, which may be coated or spin-coated on the core retainer.

[0009] Based on the first aspect, the embodiment of the present application further provides a first implementation of the first aspect: the embedded substrate further includes an electronic component embedded in the core retainer, the conductive structure further includes a second conductive structure electrically connected to the pin of the electronic component, and the opening for constructing the second conductive structure is a second opening. In this way, it can be flexibly configured according to the functional requirements of the product.

[0010] In practical applications, the electronic components are provided in plurality, and at least one of the plurality of electronic components is a capacitor or a resistor.

[0011] Based on the first aspect, or the first implementation of the first aspect, the embodiment of the present application also provides a second implementation of the first aspect: the embedded substrate also includes a flow-through structure built into the core retaining body, the conduction structure also includes a third conduction structure electrically connected to the flow-through structure, and the opening for constructing the third conduction structure is a third opening. In this way, the external connection relationship on the first side of the core retaining body can be opened by the exposure and development process, and the overall processability is good.

[0012] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, the embodiment of the present application also provides a third embodiment of the first aspect: the core retaining body is a core plate made of organic material.

[0013] For example, the substrate of the core board may be made of FR4 (Flame Resistant 4, glass cloth reinforced epoxy phenolic resin), BT (Bismaleimide Triazine resins, bismaleimide triazine resin) or BT-like organic materials.

[0014] Based on the third implementation of the first aspect, the embodiment of the present application also provides a fourth implementation of the first aspect: the flow-through structure in the core board is a PTH (Plating Through Hole) or a copper column arranged through the core board substrate, or the flow-through structure in the core board is a multi-layer hole structure in the core board substrate.

[0015] In practical applications, the opening of the PTH through hole has a flat morphology, good processability, and controllable cost. In this way, based on the PTH through hole, a blind hole stacking hole with reliable connection can be realized, which is conducive to the rapid transmission of signals, heat, and current.

[0016] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, the embodiment of the present application further provides a fifth embodiment of the first aspect: the core retainer is a core plate made of glass material. In this way, based on the glass substrate frame, the overall strength of the substrate is improved, and based on the adjustability of the CTE (coefficient of thermal expansion) of the glass material, in a specific implementation, a glass with a CTE close to that of the chip substrate can be selected, which can effectively reduce structural stress.

[0017] Based on the fifth implementation of the first aspect, the embodiment of the present application also provides a sixth implementation of the first aspect: the flow structure in the core plate is TGV. Here, based on the good TGV (through Glass vias) hole density and hole filling capacity, the Z-direction heat transfer conduction and flow capacity can also be improved.

[0018] Based on the third implementation of the first aspect, or the fourth implementation of the first aspect, or the fifth implementation of the first aspect, or the sixth implementation of the first aspect, the embodiment of the present application also provides a seventh implementation of the first aspect: the chip and the electronic components embedded in the core board are aligned with the first surface of the core board, or aligned with the second surface of the core board. In a specific implementation, for the case of being aligned with the first surface of the core board, the specific implementation of the exposure and development process can be facilitated; for the case of being aligned with the second surface of the core board, it is beneficial to the high thermal conductivity of the product architecture without a back-side build-up layer.

[0019] Based on the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, or the seventh embodiment of the first aspect, the embodiment of the present application also provides an eighth embodiment of the first aspect: the embedded material of the chip and the periphery of the electronic component is ABF. It has the characteristic of controllable cost. Alternatively, the embedded material of the chip and the periphery of the electronic component is an exposable and developable material. The overall processability is better.

[0020] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, or the seventh embodiment of the first aspect, or the eighth embodiment of the first aspect, the embodiment of the present application also provides a ninth embodiment of the first aspect: the build-up layer also includes a back build-up layer covering the second surface of the core retaining body. The path for realizing flow and heat conduction between the buried substrate and the outside can be flexibly arranged.

[0021] Based on the ninth implementation of the first aspect, the embodiment of the present application further provides a tenth implementation of the first aspect: a heat conducting portion is provided in the back build-up layer, the inner end side of the heat conducting portion is in contact with the back side of the chip, and the outer end side of the heat conducting portion extends to the surface layer of the back build-up layer. In this way, the heat conducting portion can effectively reduce the thermal resistance of the back side of the chip, quickly conduct the heat of the chip, and has good high thermal conductivity.

[0022] Exemplarily, the heat conducting part may be a copper block, or may also be a blind hole or a copper bar arranged in an array.

[0023] In practical applications, the back of the chip may have a back copper layer to achieve contact between the inner end of the heat conducting part and the back copper layer. The back copper layer can provide good heat dissipation, further improve the back heat conduction capacity, and reduce the operating temperature of the chip; for example, when applied to a power module, it can improve power efficiency.

[0024] Based on the ninth implementation of the first aspect, or the tenth implementation of the first aspect, the embodiment of the present application also provides an eleventh implementation of the first aspect: the back side build-up layer includes a first back side build-up layer, and the first back side build-up layer is bonded to the second side of the core retaining body; wherein the first back side build-up layer includes a dielectric layer and a circuit layer arranged in a stacked manner, and a conductive structure electrically connected to its circuit layer is arranged in the dielectric layer of the first back side build-up layer.

[0025] In practical applications, the dielectric layer of the first back build-up layer can also be made of an exposable and developable material, and openings for constructing a conductive structure are formed by exposure and development. For the manufacturing process of the embedded substrate, the process route can be simplified.

[0026] Based on the eleventh implementation of the first aspect, the embodiment of the present application also provides the twelfth implementation of the first aspect: the dielectric layer of the first back-side build-up layer is made of PP material. With this arrangement, on the one hand, the PP material has good strength and high temperature resistance, and the overall strength of the substrate is enhanced; on the other hand, the inner end side of the heat conductive part abuts against the chip, and the outer end side of the heat conductive part extends to the surface layer of the back-side build-up layer; that is, taking the embedded material as ABF as an example, the heat conductive part passes through the ABF filling layer and the PP build-up layer in turn, generating a pinning effect at the bonding interface between the two, reducing the risk of delamination between the ABF embedded material and the PP build-up layer material, and further improving reliability.

[0027] Based on the eleventh embodiment of the first aspect, or the twelfth embodiment of the first aspect, the embodiment of the present application also provides a thirteenth embodiment of the first aspect: the back side build-up layer includes at least one back side second build-up layer, and the back side second build-up layer is stacked on the back side first build-up layer. The back side second build-up layer includes a stacked dielectric layer and a circuit layer, and the dielectric layer of the back side second build-up layer is made of ABF, PP or an exposeable and developable material.

[0028] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, or the seventh embodiment of the first aspect, or the eighth embodiment of the first aspect, or the ninth embodiment of the first aspect, or the tenth embodiment of the first aspect, or the eleventh embodiment of the first aspect, or the twelfth embodiment of the first aspect, or the thirteenth embodiment of the first aspect, the embodiment of the present application also provides a fourteenth embodiment of the first aspect: the front build-up layer includes at least one front second build-up layer, the front second build-up layer is sequentially stacked on the front first build-up layer, the front second build-up layer includes a dielectric layer and a circuit layer stacked, and the dielectric layer of the front second build-up layer is made of ABF, PP or an exposable and developable material.

[0029] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, the embodiment of the present application further provides a fifteenth embodiment of the first aspect: the core retainer is a filling medium layer made of a filling medium material. With such a configuration, the process is simple and the manufacturing cost can be reasonably controlled.

[0030] For example, the filling dielectric material may be an exposable and developable material, so that the dielectric layer of the first front build-up layer can be formed simultaneously while the core retainer is formed, which has good processability.

[0031] In practical applications, the flow-through structure in the filling medium layer can be a copper column, which has good thermal conductivity and flow-through capacity.

[0032] Based on the fifteenth implementation of the first aspect, the embodiment of the present application further provides a sixteenth implementation of the first aspect: the chip and the electronic components embedded in the core board are aligned with the second surface of the filling medium layer.

[0033] A second aspect of an embodiment of the present application provides a power supply device, which includes a chip, an inductor element and multiple electronic components. The chip and some of the multiple electronic components use the embedded substrate as described above to form a first package body, and the inductor element and another part of the multiple electronic components form a second package body, and the second package body is arranged to overlap with the first package body.

[0034] A third aspect of an embodiment of the present application provides an electronic device, which includes a system board and a power supply device, wherein the power supply device is arranged on the system board, and the power supply device is the power supply device as described above.

[0035] A fourth aspect of an embodiment of the present application provides an electronic device, which includes a mainboard and an embedded component. The embedded component is arranged on the mainboard, and the embedded component is made of the embedded substrate as described above.

[0036] In practical applications, the electronic device can be a server, a computer or a high-performance computing cluster, for high-power, high-integration, ultra-large-scale data center servers; in addition, the electronic device can also be a switch, a router or an edge device, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A cross-sectional view of the structure of an embedded substrate provided in an embodiment of the present application;

[0038] Figure 2 for Figure 1 A schematic diagram of the projection relationship between the first opening and the corresponding window shown in ;

[0039] Figure 3 for Figure 1 A schematic diagram of the process of embedding the substrate shown in FIG.

[0040] Figure 4 A cross-sectional view of another embedded substrate structure provided in an embodiment of the present application;

[0041] Figure 5 A schematic diagram of the arrangement of an array heat conduction structure provided in an embodiment of the present application;

[0042] Figure 6 A schematic diagram of the arrangement of an array heat conduction structure provided in an embodiment of the present application;

[0043] Figure 7 for Figure 4A schematic diagram of the process of embedding the substrate shown in FIG.

[0044] Figure 8 A cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0045] Fig. 9 for Figure 8 A schematic diagram of the process of embedding the substrate shown in FIG.

[0046] Fig.10 A cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0047] Fig.11 for Fig.10 A schematic diagram of the process of embedding the substrate shown in FIG.

[0048] Fig.12 A cross-sectional view of another embedded substrate structure provided in an embodiment of the present application;

[0049] Fig.13 for Fig.12 A schematic diagram of the process of embedding the substrate shown in FIG.

[0050] Fig.14 A cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0051] Fig.15 for Fig.14 The process diagram of the embedded substrate is shown in

[0052] Fig.16 A cross-sectional view of another embedded substrate structure provided in an embodiment of the present application;

[0053] Fig.17 for Fig.16 A schematic diagram of the process of embedding the substrate shown in FIG.

[0054] Fig.18 A cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0055] Fig.19 for Fig.18 A schematic diagram of the process of embedding the substrate shown in FIG.

[0056] Fig. 20 A cross-sectional view of another embedded substrate structure provided in an embodiment of the present application;

[0057] Fig.21 for Fig. 20 A schematic diagram of the process of embedding the substrate shown in FIG.

[0058] Fig. 22A cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0059] Fig.23 for Fig. 22 A schematic diagram of the process of embedding the substrate shown in FIG.

[0060] Fig.24 A cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0061] Fig.25 for Fig.24 A schematic diagram of the process of embedding the substrate shown in FIG.

[0062] Fig.26 A cross-sectional view of the structure of another embedded substrate provided in an embodiment of the present application;

[0063] Fig. 27 for Fig.26 A schematic diagram of the process of embedding the substrate shown in FIG.

[0064] Fig.28 A schematic diagram of an application scenario of a power module provided in an embodiment of the present application;

[0065] Fig.29 A schematic diagram of another application scenario of a power module provided in an embodiment of the present application;

[0066] Fig.30 A schematic diagram of an electronic configuration provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0067] The embodiments of the present application provide an embedded substrate implementation solution that can achieve high current, high heat dissipation and high reliability, so as to be applied to different high-integration and high-density application scenarios.

[0068] Embedded substrate technology is used to embed electronic components into the substrate, which can shorten the connection path between components, reduce transmission loss, improve product integration, and reduce module size. Embedded substrate technology can be used in a variety of different application scenarios. With the continuous evolution of product functions, achieving high current, high heat dissipation and high reliability has become the core requirement of embedded substrates.

[0069] Take the embedded substrate used in the power chip packaging module as an example. A typical embedded substrate architecture, in which the chip and components such as capacitors and / or resistors can be buried in the core board, and the surface of the core board is stacked with a build-up layer to achieve interconnection between components and connection to the external circuit. Usually, the pads on the front side (welding surface) of the chip are exposed to the window opening of the PI layer (outer protective layer). Accordingly, a laser process is used to open holes on the build-up layer, and blind holes corresponding to the pads are formed to establish an electrical connection between the chip side and the build-up layer side. Usually, a ring width needs to be reserved between the blind hole and the window opening of the PI layer, and the window opening size of the chip material is fixed. The diameter of the blind hole formed thereby is smaller than the window opening size of the chip PI layer, which limits the improvement of the flow capacity and thermal conductivity of the blind hole.

[0070] Based on this, an embodiment of the present application provides an embedded substrate, which includes a core retaining body, a build-up layer and a chip embedded in the core retaining body. The core retaining body includes a first surface and a second surface, and the front of the chip is arranged toward the first surface of the core retaining body. The front of the chip includes an outer protective layer located outside its solder pad, and the outer protective layer has a window arranged corresponding to the solder pad on the chip. The build-up layer includes a front build-up layer covering the first surface of the core retaining body, and the front build-up layer includes a front first build-up layer joined to the first surface of the core retaining body, and the front first build-up layer is joined to the front of the chip; the front first build-up layer includes a dielectric layer and a circuit layer arranged in a stacked manner, and a first conductive structure electrically connected to the circuit layer is arranged in the dielectric layer, and the first conductive structure is arranged corresponding to and electrically connected to the solder pad on the chip. In the embodiment of the present application, the dielectric layer of the first build-up layer on the front side is made of an exposable and developable material, and a first opening for constructing a first conductive structure is formed by exposure and development, the opening on the outer protective layer has a first projection on the first surface, and the first opening corresponding to the opening has a second projection on the first surface, and the second projection covers the first projection. In this way, a first opening of a larger size can be formed by the exposure and development process, and the size of the first opening can be larger than the size of the opening on the outer protective layer of the chip, and the opening on the chip side can be fully utilized to form a first conductive structure for flow. For example, but not limited to, the first conductive structure can be a blind hole formed by copper plating or electroplating. In this way, on the one hand, the size of the opening on the chip side can be maximized to construct the first conductive structure, and the first conductive structure can have a larger flow cross-section, which can effectively improve the flow capacity and have good thermal conductivity. On the other hand, the first opening of the first conductive structure is formed by exposure and development processes, which can avoid the process difficulties of traditional laser opening, and has better processability.

[0071] In addition, compared with the solution of improving the thermal conductivity of the substrate by plating a copper layer on the outer protective layer (PI layer) on the front side of the chip, in the embodiment of the present application, the dielectric layer of the first build-up layer on the front side and the outer protective layer on the chip side are both organic materials, and the dielectric layer of the first build-up layer on the front side can reduce the bonding stress between the circuit layer and the front side of the chip, and reduce the risk of interlayer interface delamination. Overall, it has better reliability.

[0072] In order to better understand the technical solution and technical effects of the present application, without losing generality, the specific embodiments will be described in detail below in conjunction with the accompanying drawings. Figure 1 , which is a cross-sectional view of the structure of an embedded substrate provided in an embodiment of the present application.

[0073] like Figure 1 As shown, the embedded substrate 100 uses a core plate 1 as a core retaining body, and a chip 2 and an electronic component 5 are embedded in the core plate 1. In order to clearly illustrate the basic architectural relationship of the embedded substrate, two chips 2 and two electronic components 5 are illustrated in the figure by way of example. In a specific implementation, the number of chips 2 and electronic components 5 can be determined according to the overall design requirements of the product. In addition, in the case of providing multiple electronic components 5, at least one electronic component 5 is a capacitor element or a resistor element. This is not limited to the embodiments of the present application.

[0074] In a specific implementation, the substrate of the core board 1 can be made of organic materials, such as but not limited to FR4, BT or BT-like materials, etc. The chips 2 and electronic components 5 built into the embedded grooves on the core board 1 can be filled with ABF (Ajinomoto Build-up Film) to realize the assembly and fixation of the corresponding devices.

[0075] In the present embodiment, the front side of the chip 2 is arranged toward the first side 1A of the core board 1, and the outer protective layer on the front side is the PI layer 21, and the PI layer 21 is aligned with the first side 1A of the core board 1. The "aligned arrangement" here includes the situation that the first side 1A of the core board 1 is completely flush with the surface of the PI layer 21, and also includes the situation that the first side 1A of the core board 1 and the surface of the PI layer 21 are close to flush within the tolerance range. Correspondingly, the back side of the chip 2 is arranged toward the first side 1A of the core board 1. There is a window 211 on the PI layer 21, and the window 211 is arranged corresponding to the pad 22 located in the inner layer, and the pad 22 is exposed to the corresponding window 211 to achieve electrical connection with the external circuit.

[0076] In other possible implementations, the outer protective layer may also be made of other organic materials, as long as it can provide physical isolation to prevent oxidation of the chip substrate and meet the functional requirements of the chip's external electrical performance. This application embodiment will not be described in detail.

[0077] Both sides of the core board 1 of the embedded substrate 100 are covered with build-up layers, and the circuit layer of the build-up layers is connected to the embedded devices in the core board 1 to achieve more complex circuit connections and functions. In this embodiment, the first side 1A of the core board 1 is covered with a front build-up layer T, and the second side 1B of the core board 1 is covered with a back build-up layer B, which can achieve double-sided interconnection and heat dissipation.

[0078] Figure 1 As shown, the front build-up layer T includes three layers stacked in sequence, namely, a first front build-up layer 3 and two second front build-up layers 4. The first front build-up layer 3 is located in the inner layer of the front build-up layer T, and is bonded to the PI layer 21 on the front of the core board 1 and the chip 2, respectively. Relative to the first front build-up layer 3, the second front build-up layer 4 is located in the outer layer of the front build-up layer T. In a specific implementation, the number of layers of the second front build-up layer 4 can be set as needed, rather than being limited to the two layers shown in the figure.

[0079] Each build-up layer includes a dielectric layer and a circuit layer that are stacked together. The circuit layer 32 of the first front build-up layer 3 is stacked on the dielectric layer 31 , and the circuit layer 42 of the second front build-up layer 4 is stacked on the dielectric layer 41 .

[0080] The dielectric layer 31 of the front first build-up layer 3 is made of an exposable and developable material, and the dielectric layer 41 of the front second build-up layer 4 can be made of ABF or PP (Prepreg).

[0081] In a specific implementation, the exposable and developable material can be a dry film, which can be selected according to the overall design of the embedded substrate architecture. Based on the exposure and development characteristics of the material, corresponding openings can be formed in the dielectric layer 31 to form a conductive structure that can realize the corresponding connectivity function; in other words, openings for constructing a conductive structure can be formed in the dielectric layer 31 of the first build-up layer 3 on the front side through exposure and development processes. Here, the layout position of the conductive structure is determined according to the electrical connection requirements between the build-up layer side and the core board 1 side, thereby realizing the electrical connection and conduction of the corresponding device or circuit.

[0082] In other possible implementations, the exposable and developable material may also be a liquid photoresist, which may be coated or spin-coated on the core board 1 .

[0083] In the present embodiment, for the chip 2 embedded in the core board 1, its pad 22 is connected to the circuit layer 32 of the front build-up layer T through the first conductive structure 33. The pin side of the electronic component 5 is also aligned with the first surface 1A of the core board 1. For the electronic component 5 embedded in the core board 1, its pin can be connected to the circuit layer 32 of the front build-up layer T through the second conductive structure 34. For other interfaces on the first surface of the core board 1, such as but not limited to, the interface pad 111 shown in the figure, it can be connected to the circuit layer 32 of the front build-up layer T through the third conductive structure 35. It can be understood that for the conductive structure of each configuration function, corresponding openings can be formed at the location of the conductive structure through exposure and development processes. In a specific implementation, it can be a blind hole or a copper column. This embodiment is specifically described with a conductive structure in the form of a blind hole.

[0084] Among them, on the dielectric layer 31 of the first front build-up layer 3, the opening for constructing the first conductive structure 33 is the first opening 311, and the second projection of the first opening 311 on the first surface 1A covers the first projection of the corresponding window 211 of the PI layer 21 on the first surface 1A.

[0085] The "first surface" here is a reference plane used to illustrate the comparison relationship between the first opening and the corresponding window size. The reference plane can also be other reference planes parallel to the first surface. It should be understood that the first surface as a reference plane does not constitute a substantial limitation on the core panel described in this embodiment.

[0086] The “coverage” here includes the situation where the first projected outline d of the window 211 on the first surface 1A is completely within the second projected outline D of the first opening 311 on the first surface 1A, and also includes the situation where the first projected outline d of the window 211 on the first surface 1A partially overlaps with the second projected outline D of the first opening 311 on the first surface 1A, for example but not limited to, the two projected outlines have locally overlapping points, or the two projected outlines have locally overlapping line segments.

[0087] Please also see Figure 2 , which shows a schematic diagram of the projection relationship between the first opening 311 and the corresponding window 211 of the PI layer. Figure 2 Taking a group of correspondingly arranged first openings 311 and windows 211 as an example, the projection relationship between the two is shown. For ease of description, the cross-sections of the first openings 311 and windows 211 shown in the figure are both circular cross-sections.

[0088] In a possible implementation, the cross-sectional shape of the first opening 311 and the window 211 may be an ellipse, a rectangle or other polygon, or may be set to an irregular shape according to the actual situation of the board surface space arrangement. This embodiment of the application is not limited.

[0089] in addition, Figure 2As shown in , the second projection of the first opening 311 coincides with the center of the first projection of the window 211. In other possible implementations, on the basis of satisfying that the second projection of the first opening 311 on the dielectric layer 31 of the first front build-up layer 3 covers the first projection of the corresponding window 211 on the PI layer 21, the relative position relationship between the second projection of the first opening 311 and the first projection of the window 211 in the reference plane may also be non-centrally coincident. This is not limited to the embodiments of the present application.

[0090] For example Figure 1 As shown, the back build-up layer B in this embodiment includes three build-up layers, wherein the back first build-up layer 7 is located in the inner layer of the back build-up layer B and is bonded to the second surface of the core board 1, and the other two build-up layers are sequentially superimposed on the back first build-up layer 7, and each build-up layer includes a dielectric layer and a circuit layer that are superimposed. Here, the dielectric layer of each build-up layer of the back build-up layer B can be made of ABF. That is, the dielectric layer of each build-up layer of the back build-up layer B can be configured with the same material as the front second build-up layer 4 on the side of the front build-up layer T.

[0091] In a specific implementation, the specific number of layers of the front build-up layer T and the back build-up layer B can be determined according to product design requirements, and is not limited to the three layers shown in the figure.

[0092] In other possible implementations, the backside build-up layer B may be selectively provided as required.

[0093] In this embodiment, a PTH through hole 11 is provided on the substrate of the core board 1 to achieve conduction between the first surface 1A and the second surface 1B of the core board 1, and has the functions of power supply, signal transmission and heat conduction. The PTH through hole 11 can be formed by a plug brush and electroplating process, and the hole mouth has a flat morphology. The processability is good and the cost is controllable. In this way, based on the PTH through hole 11, a blind hole stacking hole with reliable connection can be achieved, which is conducive to the rapid transmission of signals, heat and current.

[0094] Combine the following Figure 3 Brief Description Figure 1 The process flow of the buried substrate 100 is described in FIG.

[0095] Step S301, preparing a core board 1.

[0096] First, after the organic core board is received, holes are drilled at the position of the molded PTH through hole 11, and the glue removal process is performed. Next, the PTH through hole 11 is electroplated based on the copper deposition process, and the hole is plugged and brushed; in the specific implementation, the hole can be plugged with resin or conductive copper paste. Then, after the seed layer is formed on the board surface, the surface copper is electroplated; in the specific implementation, the seed layer can be formed by copper deposition process or sputtering process. Finally, the surface copper layer is patterned to form the interface pad 111.

[0097] Step S302: preparation for embedding and mounting.

[0098] An embedding groove 1-1 is formed on the core board 1 and the glue is removed. In a specific implementation, the groove can be formed by UV Laser (ultraviolet laser), CO2 laser (carbon dioxide laser) or other mechanical processing. Then, a tape 1-2 is attached to the first surface 1A of the core board 1.

[0099] Step S303: mounting chips and electronic components, and pressing and filling.

[0100] Specifically, the chip 2 and the electronic component 5 are built into the embedding groove 1-1, and the front side is mounted on the adhesive film 1-2; here, the electronic component 5 can be a capacitor, a resistor or an inductor. Next, a filling and pressing operation is performed, and the embedding filling material 1-3 can be ABF, or can be selected according to actual process conditions.

[0101] Here, while the gaps between the devices and between the devices and the embedded grooves are filled by pressing, the embedded filling material 1-3 also forms a dielectric layer 71 of the back first build-up layer 7 bonded to the second surface 1B side of the core board 1. The back first build-up layer 7 here, that is, the build-up layer structure of the back build-up layer B bonded to the second surface of the core board 1.

[0102] Step S304 , laminating the dielectric layer 31 of the front first build-up layer 3 .

[0103] The adhesive film 1 - 2 is removed, and the exposable and developable material is pressed onto the core board 1 to form a dielectric layer 31 , which is then bonded to the front side of the chip 2 and the electronic component 5 .

[0104] Step S305, forming holes on the front side and forming holes on the back side by using exposure and development processes.

[0105] Specifically, on the dielectric layer 31 of the first front build-up layer 3, a first opening 311 is formed corresponding to the pad 22 of the chip 2, a second opening 312 is formed corresponding to the pin of the electronic component 5, and a third opening 313 is formed corresponding to the interface pad 111 of the PTH through hole 11. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings to construct a conductive structure.

[0106] Based on the laser hole forming process, a third opening 313 is formed on the embedded filling material 1-3 layers on the back side of the chip 2 corresponding to the interface pad 111 of the PTH through hole 11.

[0107] Step S306 , forming each conductive structure, and the surface copper of the first front build-up layer and the first back build-up layer.

[0108] First, the debonding process is performed, and then a seed layer can be formed first; in the specific implementation, the seed layer can be formed by copper plating or sputtering process. Then, the walls of the first opening 311, the second opening 312 and the third opening 313 are electroplated to form conductive blind holes, forming the first conductive structure 33, the second conductive structure 34 and the third conductive structure 35 respectively.

[0109] At the same time, copper is formed by electroplating on the front and back surfaces. The copper layer on the front surface is used to form the circuit layer 32 of the first build-up layer on the front surface, and the copper layer on the back surface is used to form the circuit layer 72 of the first build-up layer on the back surface.

[0110] Step S307, patterning the front copper layer and the back copper layer.

[0111] After the surface treatment, lamination, exposure, development, etching and stripping processes may be performed in sequence to form corresponding circuit layers, thereby completing the front first build-up layer 3 and the back first build-up layer 7 .

[0112] Step S308, forming the outer layers of the front build-up layer T and the back build-up layer B, forming the outer solder resist layer 6, and processing the surface of the outer metal layer.

[0113] In a specific implementation, the number of layers of each outer layer can be determined according to the overall design requirements of the product, and a corresponding manufacturing process can be formulated. This embodiment of the present application is not limited.

[0114] For the chip, in order to further improve its backside heat conduction capability, a corresponding heat conduction part can be provided on the backside of the chip in other specific implementations. Figure 4 , which is a cross-sectional view of another embedded substrate structure provided in an embodiment of the present application. Figure 1 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0115] like Figure 4 As shown, a chip 2a and an electronic component 5 are embedded in the core board 1 of the embedded substrate 100a, wherein the front side of the chip 2a is arranged toward the first side 1A of the core board 1, and the PI layer 21 on the front side is aligned with the first side 1A of the core board 1. The first side 1A of the core board 1 is covered with a front build-up layer T, and the second side 1B of the core board 1 is covered with a back build-up layer B.

[0116] The dielectric layer 31 of the front first build-up layer 3 is made of an exposable and developable material, and the dielectric layer 41 of the front second build-up layer 4 can be made of ABF; similarly, the dielectric layers of each build-up layer of the back build-up layer B can also be made of ABF.

[0117] The pad 22 of the chip 2a is connected to the circuit layer 32 of the front build-up layer T through the first conductive structure 33. On the dielectric layer 31 of the first front build-up layer 3, the opening for constructing the first conductive structure 33 is the first opening 311, and the second projection of the first opening 311 on the first surface 1A covers the first projection of the corresponding window 211 of the PI layer 21 on the first surface 1A.

[0118] In this way, the size of the first opening 311 on the chip 2a side can be used to the maximum extent to construct the first conductive structure 33, and the first conductive structure 33 with a larger flow cross section has good thermal conductivity. In addition, based on the fact that the dielectric layer 31 of the first front build-up layer 3 and the PI layer 21 on the chip 2a side have material thermal expansion coefficients that tend to be close, the bonding stress between the circuit layer and the front of the chip 2a can be reduced.

[0119] In this embodiment, the pins of the electronic components 5 embedded in the core board 1 can be connected to the circuit layer 32 of the front build-up layer T through the second conductive structure 34. The substrate of the core board 1 is provided with a PTH through hole 11, which is connected to the circuit layers of the front build-up layer T and the back build-up layer B through the pads at both ends thereof.

[0120] As shown in the figure, the back of the chip 2a is in contact with the heat-conducting structure 8 arranged in the array. In this embodiment, the inner end side of each heat-conducting structure 8 is in contact with the back copper layer 23 of the chip 2a, and the outer end side of each heat-conducting structure 8 extends to the surface layer of the back build-up layer B. Therefore, the heat-conducting part formed by the array heat-conducting structure 8 can effectively reduce the Z-direction thermal resistance of the back of the chip 2a, quickly conduct the heat generated by the chip, and has good high thermal conductivity.

[0121] In a specific implementation, the back copper layer 23 of the chip 2a can be the back copper that has been set when the chip leaves the factory, or the back copper layer of the chip can be formed in the memory module manufacturing process, and the chip can be selected more preferably. It can be determined according to the specific product design and process conditions, and the embodiment of the present application is not limited.

[0122] Of course, the back copper layer 23 is a structural layer that can be set selectively. In other words, even if there is no back copper layer on the back of the chip 2a, the heat generated by the chip can still be quickly conducted out through the heat conduction part. In comparison, for the chip 2a with the back copper layer 23, the back copper layer 23 can provide good heat dissipation ability, which can further improve the back heat conduction ability and reduce the working temperature of the chip; for example, when applied to a power module, it can improve the power efficiency.

[0123] For the heat conducting structure 8 arranged in an array, different structural forms can be adopted in specific implementation. Figure 4 The perspective of the AA section position in the middle illustrates two structural forms of array heat conduction structures.

[0124] See also Figure 5, the figure is a schematic diagram of the arrangement of array thermal conductive blind holes. Figure 5 For example, relative to the back copper layer 23 of the chip, the thermally conductive blind vias 8a are arranged in an array in the form of four rows and four columns. In other possible implementations, the thermally conductive blind vias 8a arranged in the array can be determined as needed, for example but not limited to, within the width range of the back side of the chip, the proportion of the array thermally conductive blind vias (Cu) can be 10%, rather than limited to Figure 5 The configuration shown.

[0125] See also Figure 6 , which is a schematic diagram of the arrangement of array thermal conductive copper strips. Figure 6 For example, relative to the back copper layer 23 of the chip, the thermal conductive copper strips 8b are arranged in an array in the form of five rows and a single column. In other possible implementation schemes, the thermal conductive copper strips 8b arranged in the array can also be determined as needed, for example but not limited to, within the width range of the back side of the chip, the proportion of the array thermal conductive copper strips (Cu) can be 30%, rather than limited to Figure 6 The configuration shown.

[0126] Combine the following Figure 7 Brief Description Figure 4 The process flow of the buried substrate 100a is described in FIG.

[0127] Step S701, preparing a core board.

[0128] Step S702: Preparation for embedding and mounting.

[0129] Step S703: mounting chips and electronic components, and pressing and filling.

[0130] Step S704: Laminating the dielectric layer of the first front build-up layer.

[0131] For the above steps S701 to S704, please refer to Figure 3 Schematic diagram of the process of steps S301 to S304.

[0132] Step S705, forming holes on the front side by using exposure and development processes; and forming holes on the back side.

[0133] Based on the exposure and development process, on the dielectric layer 31 of the first front build-up layer 3, a first opening 311 is formed corresponding to the pad 22 of the chip 2a, a second opening 312 is formed corresponding to the pin of the electronic component 5, and a third opening 313 is formed corresponding to the interface pad 111 of the PTH through hole 11. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings to construct the corresponding conductive structure.

[0134] Based on the laser hole forming process, a fourth opening 314 is formed on the embedded filling material 1-3 layers on the back of the chip 2a corresponding to the array heat conducting structure, so as to construct the corresponding heat conducting structure 8. In a specific implementation, a fourth opening with a size and shape matching the heat conducting blind hole or the heat conducting copper strip can be formed respectively.

[0135] Step S706 , forming each conductive structure and the heat-conducting structure arranged in the array, as well as the surface copper of the front first build-up layer and the back first build-up layer.

[0136] First, the debonding process is performed, and then a seed layer can be formed first; in the specific implementation, the seed layer can be formed by copper plating or sputtering. Then, the walls of the first opening 311, the second opening 312, and the third opening 313 are electroplated to form conductive blind holes, respectively forming the first conductive structure 33, the second conductive structure 34, and the third conductive structure 35; and the fourth opening 314 is electroplated to form an array-arranged thermal conductive structure 8.

[0137] At the same time, copper is formed by electroplating on the front and back surfaces. The copper layer on the front surface is used to form the circuit layer 32 of the first build-up layer on the front surface, and the copper layer on the back surface is used to form the circuit layer 72 of the first build-up layer on the back surface.

[0138] Step S707, the front copper layer and the back copper layer are patterned. Figure 3 The process diagram of step S307 is shown in FIG. 1 , in which the corresponding circuit layers are formed, and the front first build-up layer 3 and the back first build-up layer 7 are completed.

[0139] Step S708, forming the outer layers of the front build-up layer T and the back build-up layer B, forming the outer solder resist layer 6, and processing the surface of the outer metal layer.

[0140] In a specific implementation, the number of layers of each outer layer can be determined according to the overall design requirements of the product, and a corresponding manufacturing process can be formulated.

[0141] The foregoing Figure 4 In the embedded substrate architecture described above, the array of heat-conducting structures is used as the heat-conducting part to reduce the thermal resistance in the Z direction. In other specific implementations, a heat-conducting part in the form of a copper block structure can be set on the back of the chip. Figure 8 , a cross-sectional view of another embedded substrate provided in the embodiment of the present application. Figure 4 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0142] like Figure 8As shown, the core board 1b of the embedded substrate 100b is embedded with a chip 2a and an electronic component 5. The front side of the chip 2a is arranged toward the first side 1A of the core board 1b, and the PI layer 21 on the front side is aligned with the first side 1A of the core board 1b. The first side 1A of the core board 1b is covered with a front build-up layer T, and the second side 1B of the core board 1b is covered with a back build-up layer B.

[0143] Similarly, the dielectric layer 31 of the front first build-up layer 3 is made of an exposable and developable material, the dielectric layer 41 of the front second build-up layer 4 can be made of ABF; the dielectric layers of each build-up layer of the back build-up layer B can also be made of ABF.

[0144] The pad 22 of the chip 2a is connected to the circuit layer 32 of the front build-up layer T through the first conductive structure 33. On the dielectric layer 31 of the first front build-up layer 3, the opening for constructing the first conductive structure 33 is the first opening 311, and the second projection of the first opening 311 on the first surface 1A covers the first projection of the corresponding window 211 of the PI layer 21 on the first surface 1A. In this way, the size of the first opening 311 on the chip 2a side can be used to the maximum extent to construct the first conductive structure 33, and the first conductive structure 33 with a larger flow cross section has good thermal conductivity. In addition, the bonding stress between the circuit layer and the front of the chip 2a can be reduced.

[0145] Compared to Figure 4 The difference of the embedded substrate described in this embodiment is that the heat conducting part on the back of the chip 2a is a heat conducting copper block 8c, and the base of the core board 1b includes a multi-layer circuit layer 11b to have a large current flow capacity and high thermal conductivity.

[0146] As shown in the figure, the back side of the chip 2a is in contact with the heat-conducting copper block 8c, the inner end side of the heat-conducting copper block 8c is in contact with the back copper layer 23 of the chip 2a, and the outer end side extends to the surface layer of the back build-up layer B. Therefore, the heat generated by the chip is quickly conducted out through the heat-conducting copper block 8c.

[0147] In this embodiment, the pins of the electronic components 5 embedded in the core board 1b can be connected to the circuit layer 32 of the front build-up layer T through the second conductive structure 34. For the multi-layer circuit layer 11b set on the substrate of the core board 1b, for example but not limited to, the layers can be connected by copper filling through blind holes 111b and X holes 112b. On the basis of large through-current and high thermal conductivity, layer-changing routing can be realized in the substrate of the core board 1b as needed, and the architecture design is more flexible.

[0148] Combine the following Fig. 9 Brief Description Figure 8 The process flow of the buried substrate 100b is described in FIG.

[0149] Step S901, preparing a core board 1b.

[0150] First, after the core board middle layer has an organic core board material, an X-shaped hole is processed at the position of the formed X hole 112b, and the hole is filled with electroplating to form the surface copper, and then the surface of the middle layer is patterned. For example, the lamination, exposure, development, etching and stripping processes can be performed in sequence to obtain the corresponding circuit layer. Then, on the basis of the core board middle layer, the layer addition is completed, and the blind hole is processed at the position of the formed blind hole 111b, and the hole is filled with electroplating to form the surface copper, and then the patterning is performed. Finally, until the layer addition is completed, the surface copper layer is patterned to form the interface pad 111.

[0151] It should be noted that the substrates of the various layers of the core board 1b can be made of organic materials, such as but not limited to FR4, BT or BT-like materials. The specific implementation of the above-mentioned processes can be achieved by using existing technologies, which will not be described here.

[0152] Step S902: Preparation for embedding and mounting.

[0153] The core board 1b is embedded with a groove 1-1 and subjected to a debonding process. In a specific implementation, the grooves can be cut using UV laser, CO2 laser or other mechanical processing techniques. Then, an adhesive film 1-2 is attached to the first surface 1A of the core board 1b.

[0154] Step S903, mounting chips and electronic components, and pressing and filling.

[0155] The chip 2a and the electronic component 5 are built into the embedding groove 1-1, and the front side is mounted on the adhesive film 1-2, and then the filling and pressing operation is performed. The embedding filling material 1-3 can be ABF, and while filling the gaps between the devices and between the devices and the embedding grooves, the embedding filling material 1-3 also forms a dielectric layer 71 of the back first build-up layer 7 bonded to the second surface 1B side of the core board 1b.

[0156] Step S904 , laminating the dielectric layer 31 of the front first build-up layer 3 .

[0157] The adhesive film 1 - 2 is removed, and the dielectric layer 31 made of an exposable and developable material is pressed onto the core board 1 b and bonded to the front side of the chip 2 a and the electronic component 5 .

[0158] Step S905, forming holes on the front side by using exposure and development processes.

[0159] Based on the exposure and development process, on the dielectric layer 31 of the first front build-up layer 3, a first opening 311 is formed corresponding to the pad 22 of the chip 2a, a second opening 312 is formed corresponding to the pin of the electronic component 5, and a third opening 313 is formed corresponding to the interface pad 111 of the multi-layer circuit layer 11b. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings to construct the corresponding conductive structure.

[0160] Based on the laser hole forming process, a fourth opening 314b is formed on the embedded filling material 1-3 layers on the back side of the chip 2a, corresponding to the thermal conductive copper block 8c, so as to construct the corresponding thermal conductive copper block 8c.

[0161] Step S906 , forming each conductive structure, and the surface copper of the first front build-up layer and the first back build-up layer.

[0162] First, a debonding process is performed to form a seed layer, and then the walls of the first opening 311, the second opening 312 and the third opening 313 are electroplated to form conductive blind holes, thereby forming the first conductive structure 33, the second conductive structure 34 and the third conductive structure 35 respectively.

[0163] At the same time, copper is formed by electroplating on the front and back surfaces. The copper layer on the front surface is used to form the circuit layer 32 of the first build-up layer on the front surface, and the copper layer on the back surface is formed on the wall surface of the fourth opening 314b by electroplating.

[0164] Step S907, filling the fourth opening on the back side by electroplating.

[0165] Based on the electroplating blind slot filling process, a thermal conductive copper block 8c is formed in the fourth opening 314b.

[0166] Step S908, patterning the front copper layer and the back copper layer.

[0167] After the surface treatment, lamination, exposure, development, etching and stripping processes may be performed in sequence to form a corresponding circuit layer.

[0168] Step S908, forming the outer layer of the front build-up layer and the back build-up layer, forming the outer solder resist layer, and processing the surface of the outer metal layer.

[0169] The number of layers of each outer layer can be determined according to the overall design requirements of the product, and the corresponding process steps can be formulated.

[0170] The foregoing Figure 4 and Figure 8 In the embedded substrate architecture described above, the heat conducting part is in contact with the back copper layer of the chip. In other possible implementations, the heat conducting part can be directly in contact with the back of the chip. Fig.10 , which is a cross-sectional view of another embedded substrate provided in the embodiment of the present application. Figure 8 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0171] like Fig.10 As shown, the core board 1b of the embedded substrate 100c is embedded with a chip 2 and an electronic component 5. Figure 8 The difference of the embedded substrate described in this embodiment is that there is no back copper layer on the back side of the chip 2, and the heat-conducting copper block 8c serving as the heat-conducting part is in contact with the back side of the substrate of the chip 2.

[0172] The other structures and connections of the embedded substrate 100c can be Figure 8 The embedded substrate is the same as that shown in FIG.

[0173] Combine the following Fig.11 Brief Description Fig.10 The process flow of the buried substrate 100c is described in FIG.

[0174] Step S1101, preparing a core board.

[0175] Step S1102, preparation for embedding and mounting.

[0176] For the above steps S1101 to S1102, please refer to Fig. 9 Schematic diagram of the process of step S901 to step S902.

[0177] Step S1103, mounting chips and electronic components, and pressing and filling.

[0178] The front side of the chip 2 and the electronic component 5 are mounted on the adhesive film 1-2, and then the filling and pressing operation is performed. The embedded filling material 1-3 can be ABF. While filling the gaps between the devices and between the devices and the embedded grooves, the embedded filling material 1-3 also forms a dielectric layer 81 of the back first build-up layer 7 that is bonded to the second surface 1B side of the core board 1b. Next, a surface copper layer is electroplated on the dielectric layer 81 to form a circuit layer 82 of the back first build-up layer 7.

[0179] Step S1104 , laminating the dielectric layer 31 of the front first build-up layer 3 .

[0180] The adhesive film 1 - 2 is removed, and the dielectric layer 31 made of an exposable and developable material is pressed onto the core board 1 b and bonded to the front side of the chip 2 and the electronic component 5 .

[0181] Step S1105, forming holes on the front side by using exposure and development processes.

[0182] Based on the exposure and development process, on the dielectric layer 31 of the first front build-up layer 3, a first opening 311 is formed corresponding to the pad 22 of the chip 2, a second opening 312 is formed corresponding to the pin of the electronic component 5, and a third opening 313 is formed corresponding to the interface pad 111 of the PTH through hole 11. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings to construct the corresponding conductive structure.

[0183] Step S1106, forming each conductive structure and the surface copper of the first build-up layer on the front side.

[0184] First, the debonding process is performed to form a seed layer. Then, the walls of the first opening 311, the second opening 312, and the third opening 313 are electroplated to form conductive blind holes, respectively forming the first conductive structure 33, the second conductive structure 34, and the third conductive structure 35. At the same time, the front surface is electroplated to form surface copper, and the surface copper layer on the front surface is used to form the circuit layer 32 of the first build-up layer on the front surface.

[0185] Step S1107, forming a hole on the back side.

[0186] Based on the plasma process, holes are formed in the embedded filling material 1-3 layers on the back side and the copper layer on the back side of the core board 1b. In other specific implementations, laser hole forming or mechanical hole forming process can also be used.

[0187] A fourth opening 314b is formed corresponding to the thermally conductive copper block 8c to construct the corresponding thermally conductive copper block 8c; a third opening 313 is formed corresponding to the interface pad 111 of the multi-layer circuit layer 11b to construct the third conductive structure 35.

[0188] Step S1108, filling the third opening and the fourth opening on the back side by electroplating.

[0189] Based on the blind slot filling process, a three-conducting structure 35 is formed in the third opening 313, and a heat-conducting copper block 8c is formed in the fourth opening 314b. The blind hole is filled with electroplating, and the blind slot is filled with electroplating.

[0190] Step S1109, patterning the front copper layer and the back copper layer.

[0191] After the surface treatment, lamination, exposure, development, etching and stripping processes may be performed in sequence to form a corresponding circuit layer.

[0192] Step S1110, forming the outer layer of the front build-up layer and the back build-up layer, forming the outer solder resist layer, and processing the surface of the outer metal layer.

[0193] The number of layers of each outer layer can be determined according to the overall design requirements of the product, and the corresponding process steps can be formulated.

[0194] The foregoing Figure 1 , Figure 4 , Figure 8 and Fig.10 In the embedded substrate architecture described, the front PI layer 21 of the chip and the pin side of the electronic component 5 are both aligned with the first surface of the core board. In other specific implementations, the chip and electronic component embedded in the core board can also be arranged in a manner that the back surface is aligned with the second surface of the core board. Fig.12 , which is a cross-sectional view of another embedded substrate provided in the embodiment of the present application. Figure 8 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0195] like Fig.12 As shown, the core board 1b of the embedded substrate 100d is embedded with a chip 2 and an electronic component 5. Figure 8 The difference of the embedded substrate described in this embodiment is that the back surfaces of the chip 2 and the electronic component 5 are aligned with the second surface 1B of the core board 1b.

[0196] For the heat-conducting copper block 8c as the heat-conducting part, the chip 2 is sunken, and the back copper layer 23 on the back of the chip 2 is used as a direct receiving layer for blind hole formation. In a specific implementation, the gaps between the devices (chip 2 and electronic components 5) and between the devices and the embedded grooves of the core board 1b can be filled with an exposable and developable material or an ABF material.

[0197] The other structures and connections of the embedded substrate 100d can be Figure 8 The embedded substrate is the same as that shown in FIG.

[0198] Combine the following Fig.13 Taking the exposed and developable material as the embedded filling material 1-3 as an example, a brief description is given. Fig.12 The process flow of the buried substrate 100d is described in FIG.

[0199] Step S1301, preparing a core board.

[0200] Step S1302, preparing for embedded mounting, the adhesive film is attached to the second side of the core board.

[0201] For the above steps S1301 to S1302, please refer to Fig. 9 Schematic diagram of the process of step S901 to step S902.

[0202] Step S1303, mounting chips and electronic components.

[0203] The chip 2 and the electronic component 5 are built into the embedding groove 1-1 of the core board 1b, and the back side is mounted on the adhesive film 1-2.

[0204] Step S1304, pressing and filling.

[0205] An exposed and developable material is used as the embedded filling material 1-3 to form the dielectric layer 31 of the front first build-up layer 3 while filling the gaps between the devices and between the devices and the embedded grooves.

[0206] Step S1305, forming holes on the front side by using exposure and development processes.

[0207] Based on the exposure and development process, on the dielectric layer 31 of the first front build-up layer 3, a first opening 311 is formed corresponding to the pad 22 of the chip 2, a second opening 312 is formed corresponding to the pin of the electronic component 5, and a third opening 313 is formed corresponding to the interface pad 111 of the PTH through hole 11. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings to construct the corresponding conductive structure.

[0208] Step S1306, forming each conductive structure and the surface copper of the first build-up layer on the front side.

[0209] After removing the adhesive film 1-2, a seed layer is first formed. Then, the walls of the first opening 311, the second opening 312, and the third opening 313 are electroplated to form conductive blind holes, respectively forming the first conductive structure 33, the second conductive structure 34, and the third conductive structure 35. At the same time, copper is electroplated on the front side, and the copper layer on the front side is used to form the circuit layer 32 of the first build-up layer on the front side.

[0210] Step S1307: a back copper layer is formed on the back side of the chip.

[0211] The back side is sputtered or electroplated to form a copper layer on the chip 2, and then patterned to form a back copper layer 23.

[0212] Step S1308, forming a hole on the back side.

[0213] Holes are formed based on a laser process to form holes in the embedded filling material layers 1-3 on the back and the copper layer on the back of the core board 1b. In other specific implementations, plasma hole forming or mechanical hole forming processes may also be used.

[0214] A fourth opening 314b is formed corresponding to the thermally conductive copper block 8c to construct the corresponding thermally conductive copper block 8c; a third opening 313 is formed corresponding to the interface pad 111 of the multi-layer circuit layer 11b to construct the third conductive structure 35.

[0215] Step S1309, forming a third conductive structure and a thermal conductive copper block on the back side, and a surface copper of the first build-up layer on the back side.

[0216] Specifically, a seed layer may be formed first; in a specific implementation, the seed layer may be formed by copper plating or sputtering. Then, the walls of the third opening 313 and the fourth opening 314b are electroplated to form the third conductive structure 35 and the heat-conducting copper block 314c.

[0217] At the same time, copper is formed on the back side by electroplating, and the copper layer on the back side is used to form the circuit layer 72 of the first build-up layer on the back side.

[0218] Step S1310, patterning the front copper layer and the back copper layer.

[0219] After the surface treatment, lamination, exposure, development, etching and stripping processes may be used to form corresponding circuit layers, thereby completing the front first build-up layer 3 and the back first build-up layer 7 .

[0220] Step S1311, forming the outer layer of the front build-up layer and the back build-up layer, forming the outer solder resist layer, and processing the surface of the outer metal layer.

[0221] The number of layers of each outer layer can be determined according to the overall design requirements of the product, and the corresponding process steps can be formulated.

[0222] The foregoing Fig.12 In the embedded substrate architecture described above, the gaps between the devices and between the devices and the embedded grooves of the core board can be made of an exposed and developable material as the embedded material. In other possible implementations, the dielectric layer of the back first build-up layer on the back of the core board can also be made of an exposed and developable material. Fig.14 , which is a cross-sectional view of another embedded substrate structure provided in an embodiment of the present application. Fig.12 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0223] like Fig.14 As shown, the core board 1b of the embedded substrate 100e is embedded with a chip 2 and an electronic component 5. Both sides of the core board 1b include three layers of build-up layers, wherein the front build-up layer T includes three layers stacked in sequence, namely, a first front build-up layer 3 and two second front build-up layers 4. The back build-up layer B includes three layers stacked in sequence, namely, a first back build-up layer 7 and two second back build-up layers 9. Relative to the first back build-up layer 7, the second back build-up layer 9 is located in the outer layer of the back build-up layer B. In a specific implementation, the number of layers of the second back build-up layer 9 can be set as needed, rather than being limited to the two layers shown in the figure.

[0224] Compared to Fig.12 The difference of the embedded substrate described in this embodiment is that the front sides of the chip 2 and the electronic component 5 are aligned with the first side 1A of the core board 1b, and at the same time, the dielectric layer 71 of the first build-up layer 7 on the back side is made of an exposable and developable material.

[0225] The chip 2 has no back copper layer, and the heat-conducting copper block 8c as the heat-conducting part and the third opening 312 on the back of the core board 1b are formed by exposure and development processes, which have better processing properties. In a specific implementation, the other layers of the front build-up layer T and the back build-up layer B (the front second build-up layer 4 and the back second build-up layer 9) can be made of ABF material as a dielectric layer.

[0226] The other structures and connections of the embedded substrate 100e can be Fig.12 The embedded substrate is the same as that shown in FIG.

[0227] Combine the following Fig.15 Brief Description Fig.14 The process flow of the buried substrate 100e is described in FIG.

[0228] Step S1501, preparing a core board.

[0229] Step S1502: Preparation for embedding and mounting.

[0230] For the above steps S1501 to S1502, please refer to Fig. 9 Schematic diagram of the process of step S901 to step S902.

[0231] Step S1503, mounting chips and electronic components, and pressing and filling.

[0232] The chip 2 and the electronic component 5 are built into the embedding groove 1-1 of the core board 1b, and mounted on the adhesive film 1-2 on the front side. The exposed and developable material is used as the embedding filling material 1-3, and the dielectric layer 71 of the first build-up layer 7 on the back side is formed while filling the gaps between the devices and between the devices and the embedding grooves.

[0233] Step S1504 , laminating the dielectric layer 31 of the front first build-up layer 3 .

[0234] The adhesive film 1 - 2 is removed, and the exposable and developable material is pressed onto the core board 1 b to form a dielectric layer 31 , which is then bonded to the front surface of the chip 2 and the electronic component 5 .

[0235] Step S1505, forming holes by using exposure and development processes.

[0236] Based on the exposure and development process, a first opening 311 is formed on the dielectric layer 31 of the first build-up layer 3 on the front side, corresponding to the pad 22 of the chip 2, and a second opening 312 is formed corresponding to the pin of the electronic component 5; a third opening 313 is formed corresponding to the interface pad 111 of the multi-layer circuit layer 11b; and a fourth opening 314b is formed on the embedded filling material 1-3 layers on the back side of the chip 2, corresponding to the thermal conductive copper block, and the back side of the chip 2 is exposed in the fourth opening 314b.

[0237] Step S1506, forming each conductive structure, and the surface copper of the first front build-up layer and the first back build-up layer.

[0238] First, a seed layer is formed, and then the walls of the first opening 311, the second opening 312, and the third opening 313 are electroplated to form conductive blind holes, respectively forming the first conductive structure 33, the second conductive structure 34, and the third conductive structure 35, and the fourth opening 314 is electroplated to form a thermal conductive copper block 8c. At the same time, surface copper is electroplated on the front and back sides, and the surface copper layer on the front side is used to form the circuit layer 32 of the first build-up layer on the front side, and the surface copper layer on the back side is used to form the circuit layer 72 of the first build-up layer on the back side.

[0239] Step S1507, patterning the front copper layer and the back copper layer.

[0240] After the surface treatment, lamination, exposure, development, etching and stripping processes may be used to form corresponding circuit layers, thereby completing the front first build-up layer 3 and the back first build-up layer 7 .

[0241] Step S1508, forming the outer layer of the front build-up layer and the back build-up layer, forming the outer solder resist layer, and processing the surface of the outer metal layer.

[0242] The foregoing Fig.14 In the buried substrate architecture described, except for the front first build-up layer 3 and the back first build-up layer 7, the other build-up layers of the front build-up layer T and the back build-up layer B are made of ABF material. In other possible implementations, the dielectric layers of the other build-up layers of the front build-up layer T and the back build-up layer B can also be made of an exposable and developable material. Fig.16 , which is a cross-sectional view of another embedded substrate structure provided in an embodiment of the present application. Fig.14 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0243] like Fig.16 As shown, the core board 1b of the embedded substrate 100f is embedded with a chip 2 and an electronic component 5. Both sides of the core board 1b include three layers of build-up layers, wherein the dielectric layers of each build-up layer of the front build-up layer T and the back build-up layer B are made of an exposable and developable material. In this way, each outer layer of blind holes and blind grooves are formed by exposure and development processes, which is more efficient.

[0244] The other structures and connections of the embedded substrate 100f can be Fig.14 The embedded substrate is the same as that shown in FIG.

[0245] Combine the following Fig.17 Brief Description Fig.16 The process flow of the buried substrate 100f is described in FIG.

[0246] Step S1701, preparing a core board.

[0247] Step S1702: preparation for embedding and mounting.

[0248] Step S1703, mounting chips and electronic components, and pressing and filling.

[0249] Step S1704: Laminating the dielectric layer of the first front build-up layer.

[0250] Step S1705, forming holes by exposure and development process.

[0251] Step S1706, forming each conductive structure, and the surface copper of the first front build-up layer and the first back build-up layer.

[0252] Step S1707, patterning the front copper layer and the back copper layer.

[0253] For the above steps S1701 to S1707, please refer to Fig. 9 Schematic diagram of the process steps S1501 to S1507.

[0254] Step S1708, laminating to form the dielectric layer of the front second build-up layer and the back second build-up layer, and forming holes by exposure and development process.

[0255] Based on the exposure and development process, corresponding openings are formed on the dielectric layer 41 of the second build-up layer on the front side and the dielectric layer 91 of the second build-up layer on the back side, respectively, to construct the circuit layer and the thermal conductive copper block 8c structure of the corresponding build-up layer.

[0256] Step S1709, forming circuit layers of the front second build-up layer and the back second build-up layer.

[0257] In a specific implementation, an electroplating process can be used to form a copper layer on the front and back sides respectively. After surface treatment, lamination, exposure, development, etching and stripping processes can be used to form corresponding circuit layers to complete the front second build-up layer 4 and the back second build-up layer 9.

[0258] Step S1710, forming other outer layers of the front build-up layer and the back build-up layer, forming an outer solder resist layer, and processing the surface of the outer metal layer.

[0259] The molding of the front build-up layer and the other outer build-up layers of the back build-up layer can be seen in the process diagrams of step S1708 to step S1709, which will not be described in detail here.

[0260] The foregoing Figure 4 In the embedded substrate architecture described, except for the first front build-up layer 3, the other build-up layers of the front build-up layer T and the back build-up layers B are all made of ABF material. In other possible implementations, the dielectric layers of the other build-up layers of the front build-up layer T and the back build-up layers B can also be made of PP material. Fig.18, which is a cross-sectional view of another embedded substrate structure provided in an embodiment of the present application. Figure 4 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0261] like Fig.18 As shown, the core board 1b of the embedded substrate 100g is embedded with a chip 2 and an electronic component 5, and the embedding material between the devices and the embedding grooves of the devices and the core board can be ABF. Both sides of the core board 1b include three layers of build-up layers, among which the outer layer of the front build-up layer T (the second front build-up layer 4) and the dielectric layer of each layer of the back build-up layer B (the first back build-up layer 7 and the second back build-up layer 9) are made of PP material. With this arrangement, compared with ABF material, PP material has good strength and high temperature resistance, and the overall strength of the substrate is enhanced.

[0262] In this embodiment, the back of the chip 2a is in contact with the heat-conducting structure 8 arranged in the array. The heat-conducting part formed by the heat-conducting structure 8 in the array can effectively reduce the Z-direction thermal resistance of the back of the chip 2a, and quickly conduct the heat generated by the chip, which has good high thermal conductivity. At the same time, the inner end side of each heat-conducting structure 8 is in contact with the back copper layer 23 of the chip 2a, and the outer end side of each heat-conducting structure 8 extends to the surface layer of the back build-up layer B; the heat-conducting structure 8 arranged in the array passes through the ABF embedded material and the PP build-up material in turn, and produces a pinning effect at the joint interface between the two, reducing the risk of delamination between the ABF embedded material and the PP build-up material, and the PP cost is lower.

[0263] The other structures and connections of the embedded substrate 100g can be Fig.14 The embedded substrate is the same as that shown in FIG.

[0264] Combine the following Fig.19 Brief Description Fig.18 The process flow of the buried substrate 100g is described in FIG.

[0265] Step S1901, preparing a core board.

[0266] Step S1902, preparation for embedding and mounting.

[0267] Step S1903, mounting chips and electronic components, and pressing and filling.

[0268] ABF is used as the embedding filling material 1-3 to fill the gaps between the devices and between the embedding grooves of the devices and the core board.

[0269] For the above steps S1901 to S1903, please refer to Figure 3 Schematic diagram of the process of steps S301 to S303.

[0270] Step S1904, laminating the dielectric layer of the first build-up layer on the front side, and laminating the first build-up layer on the back side.

[0271] Remove the adhesive film 1-2, press the exposable and developable material onto the core board 1 to form the dielectric layer 31 of the first front build-up layer, and bond it to the front of the chip 2 and the electronic component 5. At the same time, press the PP material and copper foil onto the core board 1 to form the first back build-up layer 7.

[0272] Step S1905, forming holes on the front side by using exposure and development processes; and forming holes on the back side.

[0273] Based on the exposure and development process, on the dielectric layer 31 of the first front build-up layer 3, a first opening 311 is formed corresponding to the pad 22 of the chip 2a, a second opening 312 is formed corresponding to the pin of the electronic component 5, and a third opening 313 is formed corresponding to the interface pad 111 of the PTH through hole 11. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings to construct the corresponding conductive structure.

[0274] Based on the laser hole forming process, a third opening 313 is formed on the first build-up layer 7 on the back side, corresponding to the interface pad 111 of the PTH through hole 11, and a fourth opening 314 is formed corresponding to the array thermal conductive structure through the embedded filling material 1-3 layers on the back side of the chip 2a, so as to construct the corresponding thermal conductive structure 8.

[0275] Step S1906, forming each conductive structure and the heat conductive structure arranged in the array, as well as the surface copper of the front first build-up layer and the back first build-up layer, and patterning them.

[0276] First, the glue removal process is performed, and then the seed layer can be formed first; then, the walls of the first opening 311, the second opening 312 and the third opening 313 are electroplated to form conductive blind holes, forming the first conductive structure 33, the second conductive structure 34 and the third conductive structure 35 respectively; and the fourth opening 314 is electroplated to form an array-arranged thermal conductive structure 8.

[0277] At the same time, copper is electroplated on the front and back sides and patterned. The front copper layer is used to form the circuit layer 32 of the front first build-up layer, and the back copper layer is used to form the circuit layer 72 of the back first build-up layer, thereby completing the front first build-up layer 3 and the back first build-up layer 7.

[0278] Step S1907, forming a second front build-up layer and a second back build-up layer.

[0279] In a specific implementation, PP material and copper foil are laminated on the first build-up layer on the front side and the first build-up layer on the back side, respectively. Then, holes are opened by laser, and corresponding copper layers are formed on the front side and the back side respectively by electroplating process. The surface is patterned to form corresponding circuit layers, and the second build-up layer 4 on the front side and the second build-up layer 9 on the back side are completed.

[0280] Step S1908, forming other outer layers of the front build-up layer and the back build-up layer, forming an outer solder resist layer, and processing the surface of the outer metal layer.

[0281] In the above embodiments, the substrate of the core board is made of organic materials. In other specific implementations, the substrate of the core board can also be made of glass materials. Fig. 20 , which is a cross-sectional view of another embedded substrate structure provided in an embodiment of the present application. Figure 8 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0282] like Fig. 20 As shown, the core board 1c of the embedded substrate 100i is embedded with a chip 2a and an electronic component 5, and the front of the chip 2a and the electronic component 5 are aligned with the first surface 1A of the core board 1c. Both sides of the core board 1c include three layers, namely, a front layer T and a back layer B.

[0283] Compared to Figure 8 The difference of the embedded substrate described in this embodiment is that the core board 1c is a glass core board, and the base of the core board 1c is provided with TGV through holes 11c formed by the TGV process, so as to realize the conduction between the first surface 1A and the second surface 1B of the core board 1c, and have the functions of power supply, signal transmission and heat conduction. In this way, the modulus of the glass substrate frame is relatively high, and the overall strength of the substrate is improved. At the same time, based on the CTE adjustability of the glass material, in the specific implementation, glass with a CTE close to that of the chip substrate can be selected, which can effectively reduce the structural stress. In addition, based on the good TGV hole density and hole filling ability, the Z-direction heat transfer conduction and flow capacity can also be improved.

[0284] The chip 2a has a back copper layer 23, and the Z-direction thermal resistance of the back of the chip 2a is effectively reduced by the thermal conductive copper block 8c abutting against it. Similarly, the thermal conductive copper block 8c passes through the ABF embedding material and the PP build-up material in sequence, generating a pinning effect at the bonding interface between the two, thereby reducing the risk of delamination between the ABF embedding material and the PP build-up material.

[0285] In this embodiment, ABF is used as the embedding material to fill the gaps between the devices and between the devices and the embedding grooves of the core board. The dielectric layer 31 of the front first build-up layer 3 is formed by exposure and development process, and the dielectric layers of the front second build-up layer 4 and the back build-up layer B are made of PP.

[0286] The other structures and connections of the embedded substrate 100i can be Figure 8 The embedded substrate is the same as that shown in FIG.

[0287] Combine the following Fig.21 Brief Description Fig. 20 The process flow of the buried substrate 100i is described in FIG.

[0288] Step S2101, preparing a core board 1c.

[0289] First, after the glass core board is received, a laser processing process is used to open a hole at the location of the TGV through hole 11c and a groove is opened at the location of the embedded device. Then, the hole is filled by electroplating based on the TGV process to form the interface pad 111.

[0290] Step S2102: Preparation for embedding and mounting: Paste the adhesive film 1-2 on the first surface 1A of the core board 1c.

[0291] Step S2103, mounting chips and electronic components, and pressing and filling.

[0292] Specifically, the chip 2a and the electronic component 5 are built into the embedding groove 1-1 and mounted on the adhesive film 1-2 from the front side. Next, a filling and pressing operation is performed, and the embedding filling material 1-3 can be ABF, or can be selected according to actual process conditions.

[0293] Here, while the gaps between the devices and between the devices and the embedded grooves are filled by pressing, the embedded filling material 1-3 also forms a dielectric layer 71 of the back first build-up layer 7 bonded to the second surface 1B side of the core board 1c.

[0294] Step S2104 , laminating the dielectric layer 31 of the front first build-up layer 3 .

[0295] The adhesive film 1 - 2 is removed, and the exposable and developable material is pressed onto the core board 1 c to form a dielectric layer 31 , which is then bonded to the front side of the chip 2 a and the electronic component 5 .

[0296] Step S2105, forming holes on the front side and forming holes on the back side by using exposure and development processes.

[0297] Specifically, on the dielectric layer 31 of the first front build-up layer 3, a first opening 311 is formed corresponding to the pad 22 of the chip 2a, a second opening 312 is formed corresponding to the pin of the electronic component 5, and a third opening 313 is formed corresponding to the interface pad 111 of the TGV through hole 11c. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings to construct a conductive structure.

[0298] Based on the laser hole forming process, a third opening 313 is formed on the embedded filling material 1-3 layers on the back side of the chip 2a, corresponding to the interface pad 111 of the TGV through hole 11c, and a fourth opening 314b is formed corresponding to the thermal conductive copper block 8c, so as to construct the corresponding thermal conductive copper block 8c.

[0299] Step S2106, forming the surface copper of each conductive structure, the front first build-up layer and the back first build-up layer, and performing surface patterning.

[0300] First, the adhesive removal process is performed, and then the seed layer can be formed first; then, the walls of the first opening 311, the second opening 312 and the third opening 313 are electroplated to form conductive blind holes, respectively forming the first conductive structure 33, the second conductive structure 34 and the third conductive structure 35. The fourth opening 314b is electroplated to form a thermal conductive copper block 8c.

[0301] At the same time, copper is formed by electroplating on the front and back surfaces. The copper layer on the front surface is patterned to form the circuit layer 32 of the first build-up layer on the front surface, and the copper layer on the back surface is patterned to form the circuit layer 72 of the first build-up layer on the back surface.

[0302] Step S2106, forming the outer layers of the front build-up layer T and the back build-up layer B, forming the outer solder resist layer 6, and processing the surface of the outer metal layer.

[0303] In the above embodiments, both sides of the core board are provided with build-up layers: front build-up layer T and back build-up layer B. In a specific implementation, only the front build-up layer T may be provided. Fig. 22 , which is a cross-sectional view of another embedded substrate structure provided in an embodiment of the present application. Fig. 20 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0304] like Fig. 22 As shown, the core board 1c of the embedded substrate 100j is embedded with a chip 2 and an electronic component 5. Fig. 20The difference of the embedded substrate described in this embodiment is that the back of the chip 2 and the electronic component 5 is aligned with the second surface 1B of the glass core board 1c, and the first surface A of the core board 1c is provided with a front build-up layer T, and there is no back build-up layer B. In other words, the build-up layer of the embedded substrate is arranged in an asymmetric manner. In this way, the heat conduction path on the back of the chip is shorter, which can maximize the heat conduction capacity and meet the product evolution trend of ultra-thin embedded architecture.

[0305] The core board 1c is a glass core board, and a TGV through hole 11c is provided on the base of the core board 1c to realize the conduction between the first surface 1A and the second surface 1B of the core board 1c. In this way, the modulus of the glass substrate frame is relatively high, and the overall strength of the substrate is improved; in the specific implementation, glass with a CTE close to that of the chip substrate can be selected to effectively reduce the structural stress. In addition, based on the good TGV hole density and hole filling ability, the Z-direction heat transfer conduction and flow capacity can be improved.

[0306] In this embodiment, the dielectric layer 31 of the first front build-up layer 3 and the embedding material filling the gaps between the devices and between the devices and the embedding grooves of the core board are all materials that can be exposed and developed.

[0307] The other structures and connections of the embedded substrate 100j can be Fig. 20 The embedded substrate is the same as that shown in FIG.

[0308] Combine the following Fig.23 Brief Description Fig. 22 The process flow of the buried substrate 100j is described in FIG.

[0309] Step S2301, preparing a core board 1c.

[0310] Step S2302: Preparation for embedding and mounting: Paste the adhesive film 1-2 on the second surface 1B of the core board 1c.

[0311] For the above steps S2301 to S2302, please refer to Fig.21 Process diagram of steps S2101 to S2102.

[0312] Step S2303, mounting chips and electronic components, and pressing and filling.

[0313] Specifically, the chip 2a and the electronic component 5 are built into the embedding groove 1-1, and the back side is mounted on the adhesive film 1-2. Next, a filling and pressing operation is performed. The embedding filling material 1-3 can be an exposed and developable material. While the gaps between the components and between the components and the embedding grooves are filled by pressing, a dielectric layer 31 of the front first build-up layer 3 is formed which is bonded to the first surface 1A side of the core board 1c.

[0314] Step S2304, forming holes on the front side by using exposure and development processes.

[0315] The adhesive film 1-2 is removed, and on the dielectric layer 31 of the first front build-up layer 3, a first opening 311 is formed corresponding to the pad 22 of the chip 2a, a second opening 312 is formed corresponding to the pin of the electronic component 5, and a third opening 313 is formed corresponding to the interface pad 111 of the TGV through hole 11c. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings to construct a conductive structure.

[0316] Step S2305, forming each conductive structure and the copper of the first build-up layer on the front side, and performing surface patterning.

[0317] First, the debonding process is performed, and then a seed layer can be formed first; then, the walls of the first opening 311, the second opening 312 and the third opening 313 are electroplated to form conductive blind holes, forming the first conductive structure 33, the second conductive structure 34 and the third conductive structure 35 respectively.

[0318] At the same time, copper is formed by electroplating on the front and back surfaces. The copper layer on the front surface is patterned to form the circuit layer 32 of the first build-up layer on the front surface, and the copper layer on the back surface is used to form the back interface of the substrate.

[0319] Step S2306, forming the outer layer of the front build-up layer T.

[0320] Step S2307, patterning the back copper layer.

[0321] In a specific implementation, the thickness of the back copper layer can be increased so as to form a back interface of the substrate through patterning.

[0322] Step S2308, forming an outer solder resist layer 6, and processing the surface of the outer metal.

[0323] In the above-mentioned embodiment in which the build-up layers are arranged asymmetrically, the base core board is a glass core board. In a specific implementation, for the embedded substrate in which the build-up layers are arranged asymmetrically, a core board made of organic materials can also be used. Fig.24 , which is a cross-sectional view of another embedded substrate structure provided in an embodiment of the present application. Fig. 22 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0324] like Fig.24 As shown, the core board 1b of the embedded substrate 100k is embedded with a chip 2 and an electronic component 5. Fig. 22The difference between the embedded substrate described in this embodiment is that the core board 1b is a core board made of organic materials. For example, but not limited to, the base of the core board 1b includes a multi-layer circuit layer 11b, which has large flow capacity and high thermal conductivity. At the same time, the dielectric layer of the outer layer of the front build-up layer T is made of PP material. Based on the combined structure of the organic core board and PP, the possibility of unidirectional bending and warping of the build-up board can be avoided, which can effectively improve the stability and reliability of the use state.

[0325] The back of the chip 2 and the electronic component 5 are aligned with the second surface 1B of the core board 1b, and the first surface A of the core board 1c is provided with a front build-up layer T, but no back build-up layer B. In this way, the heat conduction path on the back of the chip is shorter, which can maximize the heat conduction capacity.

[0326] In this embodiment, the material of the dielectric layer 31 of the first front build-up layer 3 and the embedding material filling the gaps between the devices and between the devices and the embedding grooves of the core board are all materials that can be exposed and developed.

[0327] The other structures and connections of the embedded substrate 100k can be Fig. 22 The embedded substrate is the same as that shown in FIG.

[0328] Combine the following Fig.25 Brief Description Fig.24 The process flow of the buried substrate 100k is described in FIG.

[0329] Step S2501, preparing a core board 1b.

[0330] Step S2502, preparing for embedded mounting, the adhesive film is attached to the second side of the core board.

[0331] Step S2503, mounting chips and electronic components.

[0332] Step S2504, pressing and filling.

[0333] An exposed and developable material is used as the embedded filling material 1-3 to form the dielectric layer 31 of the front first build-up layer 3 while filling the gaps between the devices and between the devices and the embedded grooves.

[0334] For the above steps S2501 to S2502, please refer to Fig. 9 The process diagram of step S901 to step S902 in FIG. 25 can refer to the process diagram of step S901 to step S902 in FIG. 25. Fig.13 Schematic diagram of the process of steps S1303 to S1304.

[0335] Step S2505, bonding and gluing the carrier board.

[0336] After removing the adhesive film 1-2, the back side is bonded to a carrier 1-4. In a specific implementation, thermal adhesive or photo-adhesive can be used to bond the carrier, for example but not limited to, the carrier can be FR4, BT core, metal plate or glass plate.

[0337] Step S2506, forming holes on the front side by using exposure and development processes to shape each conductive structure and form a first build-up layer on the front side.

[0338] Based on the exposure and development process, corresponding openings are formed on the dielectric layer 31 of the first front build-up layer 3 to construct the corresponding conductive structure. After the seed layer is formed, the walls of each opening are electroplated to form conductive blind holes to construct the corresponding conductive structure. At the same time, copper is electroplated on the front side, and the copper layer on the front side is patterned to form the circuit layer 32 of the first front build-up layer 3.

[0339] Step S2507, forming the outer layer of the front build-up layer T.

[0340] Step S2508, forming an outer solder resist layer 6, and processing the surface of the outer metal.

[0341] In the above embodiments, the core plate is used as the core retainer. In other specific implementations, the core retainer can also be formed by filling materials. Fig.26 , which is a cross-sectional view of another embedded substrate provided in the embodiment of the present application. Fig. 22 and Fig.24 The differences and connections between the described embodiments, and the components or structures with the same functions are indicated in the figures with the same symbols.

[0342] like Fig.26 As shown, the core retainer 1d of the embedded substrate 100m is a filling dielectric layer formed by a filling dielectric material, in which a chip 2 and an electronic component 5 are embedded. That is, a coreless board frame structure, a simple process, and reasonable control of manufacturing costs. Among them, the first surface 1A and the second surface 1B of the core retainer 1d are connected by a copper column 11d, and the copper column 11d has good heat conduction and flow capacity.

[0343] and Fig. 22 and Fig. 22 The same as the embedded substrate described above is that this embodiment also adopts a single-sided build-up layer structure, the back of the chip 2 and the electronic component 5 is aligned with the second surface 1B of the core retainer 1d, and the first surface A side of the core retainer 1d is provided with a front build-up layer T, and there is no back build-up layer B. In this way, the back copper layer or substrate of the chip 2 is directly exposed at the bottom, and the heat conduction path on the back of the chip is short, which can maximize the thermal conductivity.

[0344] In this embodiment, the material of the dielectric layer 31 of the first build-up layer 3 on the front side, as well as the embedded material filling the gaps between the devices and between the embedded grooves of the devices and the core board, are all materials that can be exposed and developed. In this way, on the one hand, the window size on the chip side can be used to the maximum extent to construct a first conductive structure, and the first conductive structure can have a larger flow cross-section, which can effectively improve the flow capacity and have good thermal conductivity. On the other hand, on the basis of meeting the requirements of large flow and high thermal conductivity on the front side of the chip, the dielectric layer of the first build-up layer on the front side and the outer protective layer on the chip side have a material thermal expansion coefficient that tends to be close, and both have organic materials, which can reduce the bonding stress between the circuit layer and the front side of the chip and reduce the risk of delamination.

[0345] The other structures and connections of the embedded substrate 100m can be Fig. 22 The embedded substrate is the same as that shown in FIG.

[0346] Combine the following Fig. 27 Brief Description Fig.26 The process flow of the buried substrate 100m is described in FIG.

[0347] Step S2701: A separable copper foil 1-6 is coated on a first carrier board 1-5. For example but not limited to, the first carrier board 1-5 may be an organic core board.

[0348] Step S2702, processing copper pillars 11d on the copper foil 1-6, for example but not limited to, using lamination, exposure, development, electroplating and stripping processes; attaching temporary bonding glue 1-7 on the copper foil 1-6, and mounting the chip 2 and the electronic component 5.

[0349] Step S2703, the filling dielectric material is pressed, for example but not limited to pressing with an exposable and developable material, to form a filling material layer of the core retaining body 1d and a dielectric layer 31 of the front first build-up layer 3, respectively, and forming holes by exposure and development process.

[0350] Specifically, a first opening 311 is formed corresponding to the pad of the chip 2, a second opening 312 is formed corresponding to the pin of the electronic component 5, and a third opening 313 is formed corresponding to the copper pillar 11d. In a specific implementation, after the holes are formed, the electrical connection interfaces or pins of each device are exposed in the corresponding openings to construct a conductive structure.

[0351] Step S2704, forming each conductive structure and the copper of the first front build-up layer, and performing surface patterning.

[0352] First, a seed layer is formed, and then, the walls of the first opening 311 , the second opening 312 and the third opening 313 are electroplated to form conductive blind holes, thereby forming the first conductive structure 33 , the second conductive structure 34 and the third conductive structure 35 , respectively.

[0353] At the same time, copper is electroplated on the front surface and patterned to form the circuit layer 32 of the first build-up layer on the front surface.

[0354] Step S2705, forming the outer layer of the front build-up layer T.

[0355] Step S2706, front-side bonding of the second carrier 1-8, for example but not limited to, the material of the second carrier 1-8 can be FR4, BT, stainless steel or glass, the second carrier 1-8 and the core retaining body 1d are bonded by a temporary bonding material, the temporary bonding material includes but is not limited to pyrolytic glue, photolytic glue or photocuring glue, etc.; remove the first carrier, the removal method includes but is not limited to pyrolysis, photolysis or mechanical stripping; finally, remove the copper foil 1-6 by etching, and remove the temporary bonding glue 1-7.

[0356] Step S2707, patterning the back side interface to form a back side solder resist layer 6.

[0357] Step S2708, removing the second carrier 1-8, the removal method includes but is not limited to thermal decomposition, photolysis or mechanical stripping; then, forming a front solder resist layer 6, such as but not limited to liquid solder resist, dry film solder resist, PID or PI.

[0358] Finally, the surface is metal treated, including but not limited to ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold), ENIG (Electroless Nickel / Immersion Gold), OSP (Organic solderability preservative) or SOP process.

[0359] The embedded substrate architecture solutions described in the above embodiments can be widely used in packaging structures of different functional modules. In practical applications, the above technical advantages are particularly significant in the power module architecture scenario. Fig.28 , which is a schematic diagram of an application scenario of a power supply device provided in an embodiment of the present application.

[0360] like Fig.28 As shown, the power supply device 1000 includes a chip 2, an inductor 10 and a plurality of electronic components. The chip 2 and some of the electronic components are Fig.12The embedded substrate 100d structure described above forms a first package; the inductor 10 and another part of the electronic components form a second package 200, and the second package 200 is overlapped with the first package (embedded substrate 100d). The back of the power supply device 1000 is assembled on one side of the system board 2000, the XPU 3000 is assembled on the other side of the system board 2000, and the heat dissipation component 4000 is attached to the XPU 3000.

[0361] When in use, large flow and high thermal conductivity can be achieved. The flow path is shown by thin arrows in the figure, and the heat dissipation path is shown by thick arrows in the figure.

[0362] In other implementations, the first package body may also be formed using the aforementioned other embedded substrate architectures. Fig.29 , which is a schematic diagram of an application scenario of a power supply device provided in an embodiment of the present application.

[0363] Fig.19 The power supply device 1000a shown in the figure has a chip 2 and some electronic components, which adopt Fig.26 The embedded substrate 100m structure described forms a first package; the inductor 10 and another part of the electronic components form a second package 200, and the second package 200 is overlapped with the first package (embedded substrate 100m). The front of the power supply device 1000a is assembled on one side of the system board 2000, and the XPU 3000 is assembled on the other side of the system board 2000. The first heat dissipation component 4000a is attached to the XPU 3000, and the second heat dissipation component 4000b is attached to the back of the power supply device 1000a.

[0364] Likewise, the flow path is shown in the figure by thin arrows, and the heat dissipation path is shown in the figure by thick arrows.

[0365] It should be understood that other functional components of the power supply device are not the core invention of the present application, and those skilled in the art can implement them according to the prior art, so they will not be described in detail herein.

[0366] In addition to the aforementioned embedded substrate, this embodiment also provides an electronic device, see Fig.30 , which is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0367] like Fig.30 As shown, the electronic device 10000 includes a housing 301 and a mainboard 302 disposed in the housing 301. The mainboard 302 is provided with an embedded substrate 100 as described in the above embodiment. Based on the good large through-flow and high thermal conductivity of the embedded substrate, it can be widely used in different high-density application scenarios.

[0368] In a specific implementation, the electronic device can be a server, a computer or a high-performance computing cluster, for a high-power, highly integrated, ultra-large-scale data center server; in addition, the electronic device can also be a switch, a router or an edge device, etc., which is not limited in the embodiments of the present application.

[0369] It should be understood that other functions of the electronic device are not the core invention of the present application, and those skilled in the art can implement them according to the prior art, so they will not be described in detail herein.

[0370] The above are only preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An embedded substrate, characterized in that: The embedded substrate comprises a core retainer, a build-up layer and a chip embedded in the core retainer; the core retainer comprises a first surface and a second surface, and the front surface of the chip is arranged toward the first surface of the core retainer; An outer protective layer is arranged outside the pads of the chip, and the outer protective layer has windows arranged corresponding to the pads on the chip; The build-up layer comprises a front build-up layer covering the first surface of the core retainer, the front build-up layer comprises a front first build-up layer, and the front first build-up layer is respectively bonded to the first surface of the core retainer and the front surface of the chip; The first front build-up layer comprises a dielectric layer and a circuit layer which are stacked together, a conductive structure electrically connected to the circuit layer is provided in the dielectric layer of the first front build-up layer, and the conductive structure comprises a first conductive structure electrically connected to a pad on the chip; Among them, the dielectric layer of the first front build-up layer is made of an exposeable and developable material, and an opening for constructing the conductive structure is formed by exposure and development, and the opening for constructing the first conductive structure is a first opening; the window opening of the outer protective layer has a first projection on the first surface, and the first opening corresponding to the window opening has a second projection on the first surface, and the second projection covers the first projection.

2. The embedded substrate according to claim 1, characterized in that: The embedded substrate further includes an electronic component embedded in the core retaining body, the conductive structure further includes a second conductive structure electrically connected to the pins of the electronic component, and the opening for constructing the second conductive structure is a second opening.

3. The embedded substrate according to claim 2, characterized in that: The electronic component is provided in plurality, and at least one of the plurality of electronic components is a capacitor or a resistor.

4. The embedded substrate according to any one of claims 1 to 3, characterized in that: The embedded substrate further includes a flow-through structure built into the core retaining body, the conductive structure further includes a third conductive structure electrically connected to the flow-through structure, and the opening for constructing the third conductive structure is a third opening.

5. The embedded substrate according to any one of claims 1 to 4, characterized in that: The core retainer is a core plate made of organic material.

6. The embedded substrate according to claim 5, characterized in that: The flow-through structure in the core plate is a PTH or a copper column that passes through the core plate substrate, or the flow-through structure in the core plate is a multi-layer hole structure in the core plate substrate.

7. The embedded substrate according to any one of claims 1 to 4, characterized in that: The core retaining body is a core plate made of glass material.

8. The embedded substrate according to claim 7, characterized in that: The flow-through structure in the core plate is a TGV.

9. The embedded substrate according to any one of claims 5 to 8, characterized in that: The chip and the electronic components embedded in the core board are arranged in alignment with the first surface of the core board, or are arranged in alignment with the second surface of the core board.

10. The embedded substrate according to any one of claims 5 to 9, characterized in that: The embedding material around the chip and the electronic components embedded in the core board is ABF, or the embedding material around the chip and the electronic components embedded in the core board is an exposable and developable material.

11. The embedded substrate according to any one of claims 1 to 10, characterized in that: The build-up layer further includes a back surface build-up layer covering the second surface of the core retainer.

12. The embedded substrate according to claim 11, characterized in that: A heat conducting portion is provided in the back surface build-up layer, an inner end side of the heat conducting portion is in contact with the back surface of the chip, and an outer end side of the heat conducting portion extends to the surface layer of the back surface build-up layer.

13. The embedded substrate according to claim 12, characterized in that: The heat conducting part is a copper block, or a blind hole or a copper bar arranged in an array.

14. The embedded substrate according to claim 13, characterized in that: The back surface of the chip has a back copper layer, and the inner end side of the heat conducting portion abuts against the back copper layer.

15. The embedded substrate according to any one of claims 11 to 14, characterized in that: The back side build-up layer includes a first back side build-up layer, which is bonded to the second side of the core retaining body; the first back side build-up layer includes a dielectric layer and a circuit layer which are stacked together, and a conductive structure electrically connected to the circuit layer is provided in the dielectric layer of the first back side build-up layer.

16. The embedded substrate according to claim 15, characterized in that: The dielectric layer of the first back build-up layer is made of an exposable and developable material, and openings for constructing a conductive structure are formed by exposure and development.

17. The embedded substrate according to claim 15, characterized in that: The dielectric layer of the first back build-up layer is made of PP material.

18. The embedded substrate according to any one of claims 15 to 17, characterized in that: The back side build-up layer includes at least one back side second build-up layer, the back side second build-up layer is stacked on the back side first build-up layer, the back side second build-up layer includes a stacked dielectric layer and a circuit layer, and the dielectric layer of the back side second build-up layer is made of ABF, PP or an exposable and developable material.

19. The embedded substrate according to any one of claims 1 to 18, characterized in that: The front build-up layer includes at least one front second build-up layer, which is sequentially stacked on the front first build-up layer. The front second build-up layer includes a stacked dielectric layer and a circuit layer, and the dielectric layer of the front second build-up layer is made of ABF, PP or an exposable and developable material.

20. The embedded substrate according to any one of claims 1 to 4, characterized in that: The core retaining body is a filling medium layer made of a filling medium material.

21. The embedded substrate according to claim 20, characterized in that: The filling medium material is an exposed and developable material.

22. The embedded substrate according to claim 20 or 21, characterized in that: The flow-through structure in the filling medium layer is a copper column.

23. The embedded substrate according to any one of claims 20 to 22, characterized in that: The chip and the electronic components embedded in the core board are arranged in alignment with the second surface of the filling medium layer.

24. A power supply device, characterized in that: The invention comprises a chip, an inductor element and a plurality of electronic components, wherein the chip and some of the plurality of electronic components form a first package body by using the embedded substrate described in any one of claims 1 to 23, and the inductor element and another part of the plurality of electronic components form a second package body, and the second package body is overlapped with the first package body.

25. An electronic device, characterized in that: It comprises a system board and a power supply device, wherein the power supply device is arranged on the system board, and the power supply device is the power supply device according to claim 24.

26. An electronic device, characterized in that: It comprises a main board and an embedded component, wherein the embedded component is arranged on the main board, and the embedded component is made of the embedded substrate according to any one of claims 1 to 23.

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