Manufacturing method of memory device
In the DRAM manufacturing process, the width and height of the hard mask layer are reduced by using multiple cleaning processes to form grooves with suitable depth and aspect ratios, which solves the problem of material filling difficulties and improves the efficiency and density of the memory structure.
Patent Information
- Application Number
- CN202510136521.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-10-08
- Filing Date
- 2025-02-07
- Publication Date
- 2025-05-06
AI Technical Summary
In the existing dynamic random access memory (DRAM) manufacturing processes, narrower trenches make it difficult to fill materials, resulting in a decrease in memory cell performance.
By forming a hard mask layer on the substrate and passing through the trench thereon, and performing multiple cleaning processes to reduce the width and height of the mask layer, the depth-width ratio of the trench is appropriate, thereby forming a character line layer with fewer pores in the trench.
The density and efficiency of the character line layer in the memory structure are improved, the stress of the hard mask layer and the dielectric layer is reduced, the pore problem is reduced, and the overall performance of the memory is improved.
Smart Images
Figure CN119947092A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a method for manufacturing a memory device. Background Art
[0002] A typical dynamic random access memory (DRAM) memory cell has a capacitor and a transistor, where the capacitor temporarily stores data based on the charged state of the capacitor. The bit line is electrically connected to the source / drain region of the transistor, and the word line is electrically connected to the drain region of the transistor. As technology scales, the manufacturing process for forming memory cells faces more challenges. For example, as the trench becomes narrower, it is more difficult to fill the material into the trench. Summary of the invention
[0003] Some embodiments of the present invention provide a method for manufacturing a memory device, comprising: forming a hard mask layer above a substrate, wherein the hard mask layer is made of an oxide-based material and has a first width; forming a groove in the substrate through the hard mask layer; performing a first cleaning process on the substrate, wherein the first width of the hard mask layer is reduced to a second width after the first cleaning process is completed; forming a first dielectric layer to line the groove; forming a first word line layer in the groove; forming a second word line layer in the groove and above the first word line layer; forming a cap layer in the groove and above the second word line layer; removing the hard mask layer; and forming a drain contact layer above the cap layer.
[0004] In some embodiments, the manufacturing method further includes forming a second dielectric layer over the substrate before forming the hard mask layer, wherein the second dielectric layer has a third width before the first cleaning process, and the third width of the second dielectric layer decreases to a fourth width after the first cleaning process is completed.
[0005] In some embodiments, both the hard mask layer and the second dielectric layer are made of oxide-based materials.
[0006] In some embodiments, the hard mask layer and the second dielectric layer are made of the same material.
[0007] In some embodiments, the corners of the hard mask layer become more rounded after the first cleaning process is completed.
[0008] In some embodiments, the manufacturing method further includes performing a second cleaning process after forming the first word line layer, so that the second width of the hard mask layer is reduced to a third width after the second cleaning process is completed.
[0009] In some embodiments, the manufacturing method further includes, after performing the second cleaning process, forming a third dielectric layer to line the trench and cover the first word line layer, wherein the third dielectric layer contacts the sidewall and bottom surface of the second word line layer.
[0010] In some embodiments, a portion of the first dielectric layer is exposed by the first word line layer, and a second cleaning process is performed such that the portion of the first dielectric layer is removed.
[0011] In some embodiments, the manufacturing method further includes performing a thermal process on the substrate after performing the first cleaning process to form a thermal oxide layer to line the trench, wherein a portion of the oxide layer is exposed after the second cleaning process is completed.
[0012] In some embodiments, the manufacturing method further includes performing a third cleaning process after forming the second word line layer, so that the third width of the hard mask layer is reduced to a fourth width after the third cleaning process is completed.
[0013] Some embodiments of the present invention provide a method for manufacturing a memory device, comprising: forming a hard mask layer above a substrate, wherein the hard mask layer is made of an oxide-type material and has a first height; forming a groove in the substrate through the hard mask layer; performing a first cleaning process on the substrate, wherein the first height of the hard mask layer is reduced to a second height after the first cleaning process is completed; forming a first dielectric layer to line the groove; forming a first word line layer in the groove; forming a second word line layer in the groove and above the first word line layer; forming a cap layer in the groove and above the second word line layer; and forming a drain contact layer above the cap layer.
[0014] In some embodiments, the manufacturing method further includes performing a second cleaning process after forming the first word line layer, so that the second height of the hard mask layer decreases to a third height after the second cleaning process is completed.
[0015] In some embodiments, forming the first word line layer includes forming a conductive layer to overfill the trench, and etching back the conductive layer until a top surface of the conductive layer is lower than the top surface of the substrate, wherein a portion of the first dielectric layer is exposed after etching back the conductive layer.
[0016] In some embodiments, the portion of the first dielectric layer is removed after the second cleaning process is completed.
[0017] In some embodiments, the corners of the hard mask layer become more rounded after the second cleaning process is completed.
[0018] In some embodiments, the manufacturing method further includes, after performing the second cleaning process, forming a second dielectric layer to line the trench and cover a top surface of the first word line layer.
[0019] In some embodiments, forming the second word line layer includes forming a conductive layer to overfill the trench, and etching back the conductive layer until a top surface of the conductive layer is lower than a top surface of the substrate, wherein a portion of the second dielectric layer is exposed after etching back the conductive layer.
[0020] In some embodiments, the manufacturing method further includes performing a third cleaning process after forming the second word line layer, so that the third height of the hard mask layer is reduced to a fourth height after the third cleaning process is completed.
[0021] In some embodiments, the portion of the second dielectric layer is removed after the third cleaning process is completed.
[0022] In some embodiments, the corners of the hard mask layer become more rounded after the third cleaning process is completed.
[0023] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The present invention will be more fully understood by reading the following detailed description of the embodiments with reference to the following accompanying drawings:
[0025] Figures 1 to 12 Illustrated is a cross-sectional view of a memory structure formed in some embodiments of the present invention.
[0026] Fig.13 FIG. 2 is a circuit diagram of a memory device in some embodiments of the present invention. DETAILED DESCRIPTION
[0027] Some embodiments of the present invention are directed to methods of forming memory structures. Specifically, word line layers in the memory layers of the present invention are formed with fewer voids to achieve better performance of the memory structure.
[0028] Figures 1 to 12 A cross-sectional view of a memory structure formed in some embodiments of the present invention is shown. Figure 1 , a substrate 100 is provided, and an isolation structure 105 is formed in the substrate 100 to define an active area AA in the substrate 100. The active area AA is a protruding portion of the substrate 100. The active area AA and the substrate 100 not including the active area AA may have different conductivity types. In some embodiments, if the active area AA is an n-type region, the substrate 100 not including the active area AA is a p-type region. In some embodiments, the substrate 100 is made of a semiconductor such as silicon. In some embodiments, the isolation structure 105 is made of silicon oxide, silicon nitride, or the like.
[0029] Subsequently, a dielectric layer 112 and a hard mask layer 114 are formed over the substrate 100 and the isolation structure 105. The dielectric layer 112 and the hard mask layer 114 expose a portion of the substrate 100 and the isolation structure 105. The dielectric layer 112 and the hard mask layer 114 may be made of an oxide-based material. The dielectric layer 112 and the hard mask layer 114 may be made of the same material, such as silicon oxide. The hard mask layer 114 has a height H1, and the hard mask layer 114 has a width W1. The dielectric layer 112 has a width W2. In some embodiments, the composition of the dielectric layer 112 and the hard mask layer 114 may be different. For example, the oxygen content of the dielectric layer 112 and the hard mask layer 114 may be different.
[0030] See also Figure 2 , a trench T is formed in the substrate 100 and the isolation structure 105 through the dielectric layer 112 and the hard mask layer 114. The trench T may be formed by performing an etching process to etch the substrate 100 and the isolation structure 105 through the dielectric layer 112 and the hard mask layer 114. In some embodiments, the trench T may be formed by performing a dry etching process.
[0031] See also Figure 3 , a first cleaning process is performed on the substrate 100 to remove byproducts formed in the previous stage. For example, the byproduct may be native oxide formed on the surface of the substrate 100 at the exposed surface of the substrate 100. Since the dielectric layer 112 and the hard mask layer 114 are also made of oxide, the first cleaning process also partially etches the dielectric layer 112 and the hard mask layer 114. For example, the width W1 of the hard mask layer 114 is reduced to a width W3 after the first cleaning process is completed. The height H1 of the hard mask layer 114 is reduced to a height H2 after the first cleaning process is completed. The corners of the hard mask layer 114 become more rounded after the first cleaning process is completed. The width W2 of the dielectric layer 112 is reduced to a width W4 after the first cleaning process is completed. In some embodiments, the first cleaning process is performed by using an ammonia and hydrogen peroxide mixture (APM), a sulfuric acid and hydrogen peroxide mixture (SPM), or other suitable solutions as an etchant.
[0032] See also Figure 4 , a thermal process is performed on the substrate 100 to conformally form a thermal oxide layer 120 on the exposed surface of the substrate 100. Subsequently, a dielectric layer 122 is formed in the trench T and over the hard mask layer 114. Figure 3The first cleaning process is performed in the embodiment of the present invention, so that the thermal oxide layer 120 formed conformally on the substrate 100 is smooth and has fewer defects. After forming the thermal oxide layer 120 and the dielectric layer 122, the conductive layer 132 is formed to overfill the trench T. In some embodiments, the thermal oxide layer 120 may be a silicon oxide layer. The dielectric layer 122 may be made of silicon oxide, silicon nitride, or the like. The conductive layer 132 is made of titanium nitride. Since the height of the hard mask layer 114 and the width of the hard mask layer 114 are reduced after the first cleaning process, the aspect ratio of the trench T may also be reduced after the first cleaning process. Therefore, it is easier to form the conductive layer 132 with fewer pores in the trench T.
[0033] See also Figure 5 , the conductive layer 132 is etched back until the top surface of the conductive layer 132 is lower than the top surface of the substrate 100, so that the word line layer 130 is formed in the trench T. A portion of the dielectric layer 122 is exposed after the conductive layer 132 is etched back. Since the conductive layer 132 with fewer pores has been formed in the previous stage, the resulting word line layer 130 also has fewer pores when the hard mask layer 114 is made of silicon oxide.
[0034] See also Figure 6 , a second cleaning process is performed to remove byproducts formed in a previous stage (such as a process of forming the word line layer 130). The byproducts may be post-etching residues or native oxides on the word line layer 130. The second cleaning process also partially etches the dielectric layer 112 and the hard mask layer 114. For example, the width W3 of the hard mask layer 114 is reduced to a width W5 after the second cleaning process is completed. The height H2 of the hard mask layer 114 is reduced to a height H3 after the second cleaning process is completed. The corners of the hard mask layer 114 become more rounded after the second cleaning process is completed. The width W4 of the dielectric layer 112 is reduced to a width W6 after the second cleaning process is completed. The portion of the dielectric layer 122 exposed by the word line layer 130 is also partially removed after the second cleaning process is completed. In some embodiments, a portion of the dielectric layer 122 is removed so that the thermal oxide layer 120 is exposed after the second cleaning process is completed. In some embodiments, the second cleaning process is performed by using dilute hydrofluoric acid (DHF) or other suitable solutions as an etchant.
[0035] See also Figure 7, a dielectric layer 124 is formed to line the trench T and cover the top surface of the word line layer 130. The dielectric layer 124 may be made of silicon oxide, silicon nitride, or the like. Subsequently, a conductive layer 142 overfills the trench T and is formed above the word line layer 130. In some embodiments, the conductive layer 142 is made of polysilicon. Since the height of the hard mask layer 114 and the width of the top surface of the hard mask layer 114 are reduced after the second cleaning process, the aspect ratio of the trench T may also be reduced after the second cleaning process. Therefore, it is easier to form a conductive layer 142 with fewer pores in the trench T.
[0036] See also Figure 8 , the conductive layer 142 is etched back until the top surface of the conductive layer 142 is lower than the top surface of the substrate 100, so that the word line layer 140 is formed in the trench T and above the respective word line layer 130. A portion of the dielectric layer 124 is exposed after the conductive layer 142 is etched back. The word line layer 130 and the word line layer 140 are separated by the dielectric layer 124, and the dielectric layer 124 is in contact with the sidewall and bottom surface of the word line layer 140. Since the conductive layer 142 with fewer pores has been formed in the previous stage, the resulting word line layer 140 also has fewer pores when the hard mask layer 114 is made of silicon oxide. Each word line layer 130 and its overlying word line layer 140 may be collectively referred to as a word line structure WL.
[0037] See also Fig. 9 , a third cleaning process is performed to remove byproducts formed in a previous stage (such as a process of forming the word line layer 140). The byproducts may be post-etching residues or native oxides on the word line layer 140. The third cleaning process also partially etches the dielectric layer 112 and the hard mask layer 114. For example, the width W5 of the hard mask layer 114 is reduced to a width W7 after the third cleaning process is completed. The height H3 of the hard mask layer 114 is reduced to a height H4 after the third cleaning process is completed. The corners of the hard mask layer 114 become more rounded after the third cleaning process is completed. The width W6 of the dielectric layer 112 is reduced to a width W8 after the third cleaning process is completed. A portion of the dielectric layer 124 exposed by the word line layer 140 is also partially removed after the third cleaning process is completed. In some embodiments, a portion of the dielectric layer 124 is removed so that the thermal oxide layer 120 is exposed after the second cleaning process. In some embodiments, the third cleaning process is performed by using DHF as an etchant.
[0038] See also Fig.10 A dielectric layer 126 is formed to line the trench T and cover the top surfaces of the word line layer 140 and the hard mask layer 114. The dielectric layer 126 may be made of silicon oxide, silicon nitride or the like.
[0039] Subsequently, a dielectric layer 152 overfills the trench T and is formed over the dielectric layer 152. Since the height of the hard mask layer 114 and the width of the top surface of the hard mask layer 114 are reduced after the third cleaning process, the aspect ratio of the trench T may also be reduced after the third cleaning process. Therefore, it is easier to form a dielectric layer 152 with fewer pores in the trench T. In some embodiments, the dielectric layer 152 may be a silicon nitride layer.
[0040] See also Fig.11 , planarization is performed to remove excess material of the dielectric layer 152. In some embodiments, planarization is performed until the dielectric layer 112 is exposed. The remaining portion of the dielectric layer 152 in the trench T is referred to as a cap layer 150. Since the dielectric layer 152 with fewer pores has been formed in the previous stage, the resulting cap layer 150 also has fewer pores when the hard mask layer 114 is made of silicon oxide.
[0041] Discuss in more detail, implementation Figure 2 The first cleaning process in Figure 6 The second cleaning process in Figure 8 The third cleaning process in the cleaning process is performed to remove byproducts (e.g., native oxide) obtained by their respective processes, and such cleaning process can also shrink the hard mask layer 114 and the dielectric layer 112. The width of the top surface of the hard mask layer 114, the height of the hard mask layer 114, and the width of the top surface of the dielectric layer 112 are gradually reduced after the cleaning process. Therefore, the aspect ratio of the trench T is continuously reduced after the cleaning process is performed, and the gap filling capability of the trench will be improved. Materials such as the word line layer 130, the word line layer 140, and the cap layer 150 formed in the trench T therefore have fewer pores. In addition, the stress of the hard mask layer 114 and the dielectric layer 112 made of silicon oxide is smaller, so the hard mask layer 114 and the dielectric layer 112 apply less stress to the underlying material, such as the substrate 100. The wiggling problem of the resulting profiles of the word line layer 130 , the word line layer 140 , and the cap layer 150 formed in the trench T is thus reduced.
[0042] See also Fig.12 , a dielectric layer 160 is formed on the cap layer 150 and the dielectric layer 112. Subsequently, a drain contact layer 170 is formed on the cap layer 150 and the dielectric layer 160. In some embodiments, the dielectric layer 152 may be a silicon nitride layer. The drain contact layer 170 may be made of a conductive material such as polysilicon.
[0043] After forming the drain contact layer 170 , subsequent processes may be performed to form other components, such as bit lines and capacitors to form a memory device. Fig.13 FIG. 1 is a circuit diagram of a memory device in some embodiments of the present invention. Fig.13, a memory device (e.g., a dynamic random access memory, DRAM) may include a plurality of memory cells MC. A typical DRAM memory cell includes a capacitor CA and a transistor TR, wherein the capacitor CA temporarily stores data based on the charged state of the capacitor CA. The bit line BL is electrically connected to the source / drain region of the transistor TR, and the word line WL is electrically connected to the drain region of the transistor TR. The capacitor CA is electrically connected to another source / drain region of the respective transistor TR. In some embodiments, Figure 8 The word line structure WL in can serve as the drain electrode of the transistor TR, the dielectric layers 122, 124 and 126 can serve as the drain dielectric layer of the transistor TR, the substrate 100 can serve as the channel region of the transistor TR, and the active area AA can serve as the source / drain region of the transistor TR.
[0044] Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0045] It is obvious to those skilled in the art that various modifications and variations may be made to the structure of the present invention without departing from the scope and spirit of the present invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of the present invention, with the limitation that the modifications and variations are within the scope of the following claims.
[0046]
Explanation of symbols
[0047] 100:Substrate
[0048] 105: Isolation Structure
[0049] 112: Dielectric layer
[0050] 114: Hard mask layer
[0051] 120: Thermal oxide layer
[0052] 122: Dielectric layer
[0053] 124: Dielectric layer
[0054] 126: Dielectric layer
[0055] 130: Character line layer
[0056] 132: Conductive layer
[0057] 140: Character line layer
[0058] 142: Conductive layer
[0059] 150: Top cover
[0060] 152: Dielectric layer
[0061] 160: Dielectric layer
[0062] 170: drain contact layer
[0063] AA: Active Area
[0064] BL: Bit Line
[0065] CA:Capacitor
[0066] H1: First Height
[0067] H2: Height
[0068] H3: Height
[0069] H4: Height
[0070] MC:Memory Cell
[0071] TR: Transistor
[0072] T: Groove
[0073] W1: Width
[0074] W2: Width
[0075] W3: Width
[0076] W4: Width
[0077] W5: Width
[0078] W6: Width
[0079] W7: Width
[0080] W8: Width
[0081] WL: word line structure / word line.
Claims
1. A method for manufacturing a memory device, characterized in that: The following steps are involved: Forming a hard mask layer above the substrate, wherein the hard mask layer is made of an oxide material and has a first width; forming a trench in the substrate through the hard mask layer; performing a first cleaning process on the substrate, wherein the first width of the hard mask layer is reduced to a second width after the first cleaning process is completed; forming a first dielectric layer to line the trench; forming a first word line layer in the trench; forming a second word line layer in the trench and above the first word line layer; forming a cap layer in the trench and above the second word line layer; removing the hard mask layer; and A drain contact layer is formed over the cap layer.
2. The manufacturing method according to claim 1, characterized in that: Further comprising the following steps: A second dielectric layer is formed over the substrate before forming the hard mask layer, wherein the second dielectric layer has a third width before the first cleaning process, and the third width of the second dielectric layer decreases to a fourth width after the first cleaning process is completed.
3. The manufacturing method according to claim 2, characterized in that: The hard mask layer and the second dielectric layer are both made of oxide materials.
4. The manufacturing method according to claim 2, characterized in that: The hard mask layer and the second dielectric layer are made of the same material.
5. The manufacturing method according to claim 1, characterized in that: The corners of the hard mask layer become more rounded after the first cleaning process is completed.
6. The manufacturing method according to claim 1, characterized in that: Further including: After forming the first word line layer, a second cleaning process is performed, so that the second width of the hard mask layer is reduced to a third width after the second cleaning process is completed.
7. The manufacturing method according to claim 6, characterized in that: Further including: After performing the second cleaning process, a third dielectric layer is formed to line the trench and cover the first word line layer, wherein the third dielectric layer contacts the sidewall and bottom surface of the second word line layer.
8. The manufacturing method according to claim 6, characterized in that: A portion of the first dielectric layer is exposed by the first word line layer, and the second cleaning process is performed so that the portion of the first dielectric layer is removed.
9. The manufacturing method according to claim 8, characterized in that: Further including: A thermal process is performed on the substrate after the first cleaning process is completed to form a thermal oxide layer to line the trench, wherein a portion of the thermal oxide layer is exposed after the second cleaning process is completed.
10. The manufacturing method according to claim 6, characterized in that: Further including: After forming the second word line layer, a third cleaning process is performed, so that the third width of the hard mask layer is reduced to a fourth width after the third cleaning process is completed.
11. A method for manufacturing a memory device, characterized in that: The following steps are involved: Forming a hard mask layer above the substrate, wherein the hard mask layer is made of an oxide material and has a first height; forming a trench in the substrate through the hard mask layer; performing a first cleaning process on the substrate, wherein the first height of the hard mask layer decreases to a second height after the first cleaning process is completed; forming a first dielectric layer to line the trench; forming a first word line layer in the trench; forming a second word line layer in the trench and above the first word line layer; forming a cap layer in the trench and above the second word line layer; and A drain contact layer is formed over the cap layer.
12. The manufacturing method according to claim 11, characterized in that: Further including: After forming the first word line layer, a second cleaning process is performed, so that the second height of the hard mask layer is reduced to a third height after the second cleaning process is completed.
13. The manufacturing method according to claim 12, characterized in that: The step of forming the first word line layer includes: forming a conductive layer so as to overfill the trench; and The conductive layer is etched back until a top surface of the conductive layer is lower than the top surface of the substrate, wherein a portion of the first dielectric layer is exposed after etching back the conductive layer.
14. The manufacturing method according to claim 13, characterized in that: The portion of the first dielectric layer is removed after the second cleaning process is completed.
15. The manufacturing method according to claim 12, characterized in that: The corners of the hard mask layer become more rounded after the second cleaning process is completed.
16. The manufacturing method according to claim 12, characterized in that: Further including: After performing the second cleaning process, a second dielectric layer is formed to line the trench and cover a top surface of the first word line layer.
17. The manufacturing method according to claim 16, characterized in that: The step of forming the second word line layer includes the following steps: forming a conductive layer so as to overfill the trench; and The conductive layer is etched back until the top surface of the conductive layer is lower than the top surface of the substrate, wherein a portion of the second dielectric layer is exposed after the conductive layer is etched back.
18. The manufacturing method according to claim 17, characterized in that: Further comprising the following steps: After forming the second word line layer, a third cleaning process is performed, so that the third height of the hard mask layer is reduced to a fourth height after the third cleaning process is completed.
19. The manufacturing method according to claim 18, characterized in that: The portion of the second dielectric layer is removed after the third cleaning process is completed.
20. The manufacturing method according to claim 18, characterized in that: The corners of the hard mask layer become more rounded after the third cleaning process is completed.