A trench super junction field effect transistor and a method for manufacturing the same

Abstract

This invention provides a trench-type superjunction field-effect transistor and its fabrication method. Conductive pillars are formed in a first trench using an epitaxial filling method, reducing the aspect ratio of the formed conductive pillars and resulting in a smaller pitch size. Then, a third epitaxial layer with multiple sub-epitaxy layers is formed on a second epitaxial layer using a multilayer epitaxial process, with simultaneous epitaxy and etching to form well regions within the multiple sub-epitaxy layers. This significantly reduces the thermal budget and photolithography costs during the superjunction field-effect transistor fabrication process, and also results in a smaller pitch size for the well regions formed in the sub-epitaxy layers of the third epitaxial layer. The combination of these processes results in narrower P-type conductive pillars and a wider N-type epitaxial layer containing the P-type conductive pillars. This slows down the switching speed of the body diode region formed by the P-type well region, P-type conductive pillars, and N-type epitaxial layer during device depletion and expansion, thereby reducing transient capacitance and improving the device's EMI performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication technology, and in particular to a trench-type superjunction field-effect transistor and its fabrication method. Background Technology

[0002] Super Junction Trench MOSFETs, as an advanced power MOS device technology, combine the advantages of trench structure and super junction technology. The trench structure allows for higher current density and lower resistance, while the super junction technology enables the device to maintain a high breakdown voltage while reducing on-resistance. As a result, they are widely used in modern electronic fields with medium and high voltage requirements.

[0003] In existing technologies, the cell region of SJ-MOSFET devices obtained using the trench filling method is formed by etching an N-type epitaxial layer through deep trenches and then filling it with a P-type epitaxial layer. The superjunction switching process involves charging and discharging the parasitic capacitance of the MOSFET device, causing the channel of the MOSFET device to turn on and off. The P-type well region, P-type conductive pillars, and N-type epitaxial layer of the superjunction form a body diode, which acts as a freewheeling diode during the superjunction switching process. However, because the charging and discharging process of the parasitic capacitance of the MOSFET device resonates with the inductors and capacitors in the application topology, the gate voltage of the MOSFET device becomes uncontrolled, leading to MOSFET device failure. Therefore, it is known that the EMI performance of the superjunction MOSFET can be improved by improving the parasitic capacitance of the MOSFET device. However, when reducing the pitch size to improve the parasitic capacitance of the MOSFET device, it is difficult to achieve the reduction of the pitch size using traditional deep trench filling technology, while multilayer epitaxial technology is also limited by thermal budget and photolithography costs, making it difficult to improve the parasitic capacitance of the MOSFET device.

[0004] Therefore, how to provide a trench-type superjunction field-effect transistor that can both reduce pitch size and improve the EMI performance of superjunction MOS has become an urgent problem to be solved. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a trench superjunction field-effect transistor and its fabrication method, so as to solve the problem that it is difficult to reduce the pitch size of trench superjunction field-effect transistors in the prior art, and thus the EMI performance cannot be improved.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a trench superjunction field-effect transistor, the method comprising: providing a semiconductor substrate having a first conductivity type, and sequentially forming a first epitaxial layer of the first conductivity type, a second epitaxial layer of the first conductivity type, and a first hard mask layer on the surface of the semiconductor substrate from bottom to top;

[0007] The first hard mask layer is patterned, and the first epitaxial layer and the second epitaxial layer are etched to form a plurality of first trenches in the first epitaxial layer and the second epitaxial layer;

[0008] Fill the first trench with conductive pillars of a second conductivity type, and remove the first hard mask layer;

[0009] A third epitaxial layer of the first conductivity type is formed on the second epitaxial layer, and ion implantation of a predetermined depth is performed on the surface of the third epitaxial layer to form a well region of the second conductivity type.

[0010] A second conductivity type body region is formed on the third epitaxial layer, and a second hard mask layer is formed on the body region;

[0011] The second hard mask layer is patterned, the body region and the third epitaxial layer are etched, a plurality of second trenches are formed in the body region and the third epitaxial layer, and the second hard mask layer is removed;

[0012] A first interlayer dielectric layer is formed on the inner wall of the second trench, and a first polysilicon layer filling the second trench is formed on the first interlayer dielectric layer, wherein the first polysilicon layer, the first interlayer dielectric layer and the body region have flush surfaces;

[0013] A source region having a first conductivity type and a second interlayer dielectric layer are formed on the body region, and a first electrode contact hole is formed that penetrates the second interlayer dielectric layer and exposes the body region on its bottom surface, and a second electrode contact hole is formed that exposes the first polysilicon.

[0014] A front metal layer is formed by filling the first electrode contact hole and the second electrode contact hole with metal.

[0015] Optionally, the doping concentration of the conductive pillar is 0.6E15 NA / cm. 3 ~1.5E15 NA / cm 3 The width of the conductive post is 2 to 5 μm, and the depth of the conductive post in the first trench is 15 to 25 μm.

[0016] Optionally, the third epitaxial layer includes a plurality of sub-epitaxial layers formed sequentially, the number of sub-epitaxial layers being 3 to 6, the well regions formed in each sub-epitaxial layer having the same width, and the width of the well region being greater than 20% to 80% of the width of the conductive pillar.

[0017] Optionally, the method for forming the conductive pillar includes: depositing the conductive pillar in the first trench by introducing an epitaxial gas, a doping gas, and an etching gas based on a CVD process, and performing a chemical mechanical polishing process on the conductive pillar so that the conductive pillar, the second epitaxial layer, and the first trench have flush surfaces.

[0018] Optionally, the first interlayer dielectric layer includes one or a combination of silicon oxide, silicon nitride, and silicon phosphate glass; the second interlayer dielectric layer includes one or a combination of silicon oxide, silicon nitride, and silicon phosphate glass.

[0019] Optionally, after forming the front metal layer, the method further includes the following steps: forming a photoresist layer on the upper surface of the front metal layer and patterning the photoresist layer; etching the front metal layer based on the patterned photoresist layer to form a plurality of first isolation trenches, the first isolation trenches separating the source region from the front metal layer on the first polysilicon to form the source electrode on the source region, forming the gate electrode on the first polysilicon, and removing the remaining photoresist layer.

[0020] Optionally, after forming the source electrode, the process further includes the following steps: forming a passivation layer on the upper surface of the front metal layer, and performing photolithography etching on the passivation layer to form multiple pad windows to expose the source electrode and the gate electrode; performing back-side thinning on the substrate layer to form a drain electrode; and performing a back-side gold process on the lower surface of the drain electrode to form a back-side metal layer.

[0021] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0022] The present invention also provides a trench-type superjunction field-effect transistor, the trench-type superjunction field-effect transistor comprising:

[0023] A semiconductor substrate of a first conductivity type, and a first epitaxial layer, a second epitaxial layer of the first conductivity type, and a first hard mask layer located on the surface of the semiconductor substrate;

[0024] The first trench is located in the first epitaxial layer and the second epitaxial layer;

[0025] A conductive post of a second conductivity type is located in and completely fills the first trench, and the conductive post, the second epitaxial layer and the first trench have flush surfaces;

[0026] A third epitaxial layer of the first conductivity type is located on the second epitaxial layer;

[0027] A well region of the second conductivity type is located in the third epitaxial layer and connected to the conductive pillar;

[0028] The second conductivity type of the body region is located on the third epitaxial layer;

[0029] The second trench is located in the third epitaxial layer and the body region;

[0030] The first interlayer dielectric layer is located on the inner wall of the second trench;

[0031] A first polysilicon layer is located on the first interlayer dielectric layer and fills the second trench;

[0032] The source region is located on the body region and has a surface flush with the first interlayer dielectric layer and the first polysilicon.

[0033] A second interlayer dielectric layer is located on the source region and has a first electrode contact hole that exposes the source region and a second electrode contact hole that exposes the first polysilicon.

[0034] A front metal layer, the front metal layer filling the first electrode contact hole and the second electrode contact hole and having a first isolation trench in the front metal layer, the first isolation trench isolating the source region from the front metal layer on the first polysilicon, such that the front metal layer on the source region forms the source and the front metal layer on the first polysilicon forms the gate.

[0035] The drain is located on the back side of the semiconductor substrate, and a back metal layer is disposed on the lower surface of the drain.

[0036] Optionally, the third epitaxial layer includes multiple sub-epitaxy layers, and the number of sub-epitaxy layers is 3 to 6.

[0037] Optionally, the width of the conductive post is 2 to 5 μm, and the width of the well region is greater than 20% to 80% of the width of the conductive post.

[0038] Optionally, the trench-type superjunction field-effect transistor further includes a passivation layer located on the front metal layer, and the passivation layer has a plurality of pad windows that expose the source and the gate.

[0039] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0040] As described above, the present invention provides a trench-type superjunction field-effect transistor and its fabrication method, which has the following beneficial effects: by using an epitaxial deep trench filling method, the aspect ratio of the first trench formed by etching and epitaxial layer filling is reduced, so that the conductive pillars formed in the first and second epitaxial layers have a smaller pitch size. Subsequently, by controlling the number of sub-epitaxy layers in the third epitaxial layer through multilayer epitaxial processes, the thermal budget and photolithography cost in the superjunction field-effect transistor formation process are significantly reduced, so that the well region formed in the sub-epitaxy layers in the third epitaxial layer also has a smaller pitch size. The combination of the above processes results in narrower conductive pillars and a wider well region, thereby slowing down the switching speed of the body diode region formed by the P-type well region, P-type conductive pillars and N-type epitaxial layer when the device is depleted and unfolded, thereby reducing the transient capacitance and improving the EMI performance of the device. Attached Figure Description

[0041] Figure 1 The diagram shows a flow chart of the fabrication method of the trench superjunction field-effect transistor of the present invention.

[0042] Figure 2 The diagram shows a cross-sectional structure of the present invention after forming a first epitaxial layer, a second epitaxial layer and a first hard mask layer on a semiconductor substrate.

[0043] Figure 3 The diagram shows a cross-sectional structure after the first groove is formed according to the present invention.

[0044] Figure 4 The diagram shows a cross-sectional structure of the conductive pillar formed according to the present invention.

[0045] Figure 5 The diagram shows a cross-sectional structure of the third epitaxial layer and the well region after the present invention is formed.

[0046] Figure 6 The diagram shows a cross-sectional structure of the formed body region and the second hard mask layer of the present invention.

[0047] Figure 7 The diagram shows a cross-sectional structure after the second trench is formed according to the present invention.

[0048] Figure 8 The diagram shows a cross-sectional structure of the first interlayer dielectric layer and the first polysilicon layer after the present invention has been formed.

[0049] Figure 9 The diagram shows a cross-sectional structure of the source region and the second interlayer dielectric layer after the present invention is formed.

[0050] Figure 10 The diagram shows a cross-sectional structure after the formation of the first electrode contact hole and the second electrode contact hole according to the present invention.

[0051] Figure 11 The diagram shows a cross-sectional structure of the present invention after the formation of the front metal layer, the first isolation trench, the gate, and the source.

[0052] Figure 12 The diagram shows a cross-sectional structure after the passivation layer and pad window are formed according to the present invention.

[0053] Figure 13 The diagram shows a cross-sectional structure of the drain electrode and the back metal layer formed in this invention.

[0054] Component designation explanation

[0055] 111. Semiconductor substrate; 112. First epitaxial layer; 113. Second epitaxial layer; 12. First trench; 13. First hard mask layer; 131. First silicon dioxide layer; 132. First silicon nitride layer; 133. Second silicon dioxide layer; 14. Conductive pillar; 15. Third epitaxial layer; 151. First sub-epitaxy layer; 152. Second sub-epitaxy layer; 153. Third sub-epitaxy layer; 16. Well region; 17. Body region; 18. Second hard mask layer; 181. Third silicon dioxide layer; 182. Second silicon nitride layer; 183. First... 19. Second trench; 201. First interlayer dielectric layer; 202. First polysilicon; 21. Source region; 22. Second interlayer dielectric layer; 221. Fifth silicon oxide layer; 222. Silicon phosphate glass layer; 231. First electrode contact hole; 232. Second electrode contact hole; 24. Front metal layer; 241. Gate; 242. Source; 25. First isolation trench; 26. Passivation layer; 261. Silicon nitride layer; 262. Polyimide layer; 27. Drain; 28. Back metal layer; S1-S9, Steps. Detailed Implementation

[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0058] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0059] Please see Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0060] Example 1

[0061] This embodiment provides a method for fabricating a trench-type superjunction field-effect transistor. Please refer to [link to relevant documentation]. Figure 1 The diagram shows the process flow of this preparation method, which includes the following steps:

[0062] S1: Provide a semiconductor substrate 111 having a first conductivity type, and form a first epitaxial layer 112 of the first conductivity type, a second epitaxial layer 113 of the first conductivity type and a first hard mask layer 13 sequentially from bottom to top on the surface of the semiconductor substrate 111;

[0063] S2: Pattern the first hard mask layer 13 and etch the first epitaxial layer 112 and the second epitaxial layer 113 to form a plurality of first trenches 12 in the first epitaxial layer 112 and the second epitaxial layer 113;

[0064] S3: Fill the first trench 12 with conductive pillars 14 having a second conductivity type, and remove the first hard mask layer 13;

[0065] S4: A third epitaxial layer 15 of a first conductivity type is formed on the second epitaxial layer 113, and ion implantation of a predetermined depth is performed on the surface of the third epitaxial layer 15 to form a well region 16 of a second conductivity type.

[0066] S5: A second conductivity type body region 17 is formed on the third epitaxial layer 15, and a second hard mask layer 18 is formed on the body region 17;

[0067] S6: Pattern the second hard mask layer 18, etch the body region 17 and the third epitaxial layer 15, form a plurality of second trenches 19 in the body region 17 and the third epitaxial layer 15, and remove the second hard mask layer 18.

[0068] S7: A first interlayer dielectric layer 201 is formed on the inner wall of the second trench 19, and a first polysilicon 202 filling the second trench 19 is formed on the first interlayer dielectric layer 201, wherein the first polysilicon 202, the first interlayer dielectric layer 201 and the body region 17 have flush surfaces.

[0069] S8: A source region 21 having a first conductivity type and a second interlayer dielectric layer 22 are formed on the body region 17, and a first electrode contact hole 231 is formed that penetrates the second interlayer dielectric layer 22 and exposes the bottom surface of the body region 17, and a second electrode contact hole 232 that exposes the first polysilicon 202 is formed.

[0070] S9: Fill the first electrode contact hole 231 and the second electrode contact hole 232 with metal to form a front metal layer 24.

[0071] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type. Furthermore, the conductivity types of the first and second conductivity types are opposite; for example, the first conductivity type is N-type and the second conductivity type is P-type, or vice versa. This embodiment uses an example where the first conductivity type is N-type and the second conductivity type is P-type. Additionally, the N-type dopant ion can be a pentavalent ion such as nitrogen, phosphorus, arsenic, or antimony, and the P-type dopant ion can be a trivalent ion such as boron, aluminum, gallium, or indium. The specific choice depends on actual needs and is not overly restrictive here.

[0072] The fabrication method of the trench-type superjunction field-effect transistor of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0073] like Figure 2 As shown, in step S1, a semiconductor substrate 111 with a first conductivity type is provided, and a first epitaxial layer 112 of the first conductivity type, a second epitaxial layer 113 of the first conductivity type and a first hard mask layer 13 are sequentially formed from bottom to top on the surface of the semiconductor substrate 111.

[0074] Specifically, such as Figure 2The diagram shows a cross-sectional view of the semiconductor substrate 111. The semiconductor substrate 111 is of a first conductivity type, and a first epitaxial layer 112 and a second epitaxial layer 113 of the first conductivity type are sequentially formed on the front side of the semiconductor substrate 111.

[0075] Optionally, the doping concentrations of the semiconductor substrate 111, the first epitaxial layer 112, and the second epitaxial layer 113 can decrease sequentially. The semiconductor substrate 111 can be an N+-doped silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, etc., and the first epitaxial layer 112 and the second epitaxial layer 113 are lightly doped single-crystal silicon epitaxial layers. In this embodiment, the semiconductor substrate 111 is selected as an N+-doped silicon substrate, and the first epitaxial layer 112 and the second epitaxial layer 113 are selected as N-type single-crystal silicon epitaxial layers. Before performing subsequent processes, the semiconductor substrate 111 can be cleaned, for example, by sequentially cleaning with an organic solvent such as acetone and deionized water to remove contaminants from the surface of the semiconductor substrate 111, followed by drying; or by first removing the natural oxide layer on the surface of the semiconductor substrate 111 with a diluted acid solution, then cleaning with deionized water, and finally drying; or by performing multiple cleanings using the aforementioned methods.

[0076] Furthermore, a first hard mask layer 13 is formed on the surface of the second epitaxial layer 113, thereby helping to improve etching accuracy. The first hard mask layer 13 can be a single silicon oxide layer of a certain thickness, or it can include a combination of silicon oxide-silicon nitride-silicon oxide layers stacked from bottom to top. Preferably, in this embodiment, the first hard mask layer includes a first silicon dioxide layer 131, a first silicon nitride layer 132, and a second silicon dioxide layer 133 from bottom to top, and the thickness of the second silicon dioxide layer 133 is typically greater than the thickness of the first silicon dioxide layer 131. The structural layers of the first hard mask layer can be formed sequentially using chemical vapor deposition (CVD) or by thermal oxidation to form the first silicon dioxide layer 131 and the first silicon nitride layer 132 and the second silicon dioxide layer 133 using CVD. The first silicon dioxide layer 131 serves as a buffer layer to buffer the stress between the first silicon nitride layer 132 and the second epitaxial layer 113. The first silicon nitride layer 132 serves as an etching stop layer for the second silicon dioxide layer 133. After the first trench 12 is defined in the first hard mask layer 13, the second silicon dioxide layer 133 will be consumed as a hard mask when etching the first trench 12 in the second epitaxial layer 113. Therefore, the first hard mask layer with a silicon dioxide-silicon nitride-silicon dioxide structure helps to improve etching accuracy and protect the semiconductor substrate 111.

[0077] like Figure 3As shown, step S2 is performed to pattern the first hard mask layer 13 and etch the first epitaxial layer 112 and the second epitaxial layer 113 to form a plurality of first trenches 12 in the first epitaxial layer 112 and the second epitaxial layer 113.

[0078] Specifically, using the first hard mask layer 13, the region of the first trench 12 to be fabricated is defined by a patterned photolithography process, thereby etching the required first trench 12. The depth of the first trench 12 within the first epitaxial layer 112 and the second epitaxial layer 113 is 15–25 μm. The specific implementation of the patterned photolithography and etching process can be achieved using conventional methods known to those skilled in the art, and no specific limitations are made here.

[0079] like Figure 4 As shown, step S3 is performed, in which conductive pillars 14 having a second conductivity type are filled into the first trench 12, and the hard mask layer is removed.

[0080] As a preferred example, the process for fabricating the conductive pillar 14 is as follows: Based on chemical vapor deposition (CVD), during epitaxial growth, in order to fill the entire deep trench with the epitaxial layer and avoid premature sealing, an etching gas is introduced simultaneously with the epitaxial gas and dopant gas. By adjusting the flow rate of the etching gas, for example, increasing it to approximately 1800 sccm, a method of simultaneous deposition and etching is adopted, which reduces the overall epitaxial growth rate to a low level. The sidewalls of the deep trench are almost short, and the epitaxial growth only proceeds from the bottom upwards. The epitaxial gas can be selected as needed. For example, for silicon epitaxy, the epitaxial gas can be silane; for germanium epitaxy, the epitaxial gas can be germanane. The dopant gas can be, for example, an N-containing gas or a B-containing gas when depositing an N-type epitaxial layer. The etching gas is, for example, hydrogen chloride gas.

[0081] The specific method is as follows: First, using the above-mentioned process, epitaxial gas, doping gas and etching gas are introduced to form a conductive pillar 14 with a second conductivity type that extends from bottom to top and is flush with the top of the second epitaxial layer inside the first trench 12. The airflow of the doping gas is adjusted so that the doping concentration of the portion of the conductive pillar 14 that is flush with the top of the second epitaxial layer is the same as the doping concentration of the second epitaxial layer.

[0082] As an example, the top of the formed conductive pillar 14 is generally higher than the top of the second epitaxial layer. Therefore, after the conductive pillar 14 is formed, the surface of the conductive pillar 14 can be planarized using methods including but not limited to chemical mechanical polishing (CMP) to remove the epitaxial material of the conductive pillar 14 on the surface of the second epitaxial layer 113 surrounding the first trench 12, thereby exposing the second epitaxial layer 113 and making the surface of the conductive pillar 14 flush with the surface of the second epitaxial layer 113. The CMP process combines the effects of mechanical grinding and chemical etching to form a smooth and flat surface on the second epitaxial layer 113, providing a good surface foundation for subsequent processes. After the surface of the conductive pillar 14 is planarized, residual first hard mask layers are also removed using processes including but not limited to etching.

[0083] As an example, the doping concentration of the conductive pillar 14 is 0.6E15 NA / cm3 to 1.5E15 NA / cm3, the width of the conductive pillar 14 is 2 to 5 μm, and the depth of the conductive pillar 14 in the first trench 12 is 15 to 25 μm. Preferably, in this embodiment, the doping concentration of the conductive pillar 14 is 1.00E15 NA / cm3, the width of the conductive pillar 14 is 3 μm, and the depth of the conductive pillar 14 in the first trench 12 is 20 μm. By reasonably setting the thickness of the first epitaxial layer 112 and the second epitaxial layer 113, the impact on the Rsp performance of the device is reduced or even avoided, thereby reducing or even avoiding the resulting impact on the device's conductivity, power loss, switching speed, and withstand voltage.

[0084] like Figure 5 As shown, step S4 is performed to form a third epitaxial layer 15 of the first conductivity type on the second epitaxial layer 113, and to perform ion implantation to a predetermined depth on the surface of the third epitaxial layer 15 to form a well region 16 of the second conductivity type.

[0085] As an example, the third epitaxial layer 15 includes a plurality of sub-epiaxial layers formed sequentially, the number of sub-epiaxial layers being 3 to 6, and the well region 16 formed in each sub-epiaxial layer having the same width, and the width of the well region 16 being greater than 20% to 80% of the width of the conductive post 14.

[0086] Specifically, a first sub-epilithographic layer 151 of a third epitaxial layer 15 of a first conductivity type is formed on the second epitaxial layer 113 using chemical vapor deposition. The implantation region for P-type ions is defined by photolithography. Then, an ion implantation process and high-temperature push-in are used to form a well region 16 of a second conductivity type at a predetermined depth in the first sub-epilithographic layer 151. An electrical connection is formed between the well region 16 and the conductive pillars 14 in the first trench 12. Then, a second sub-epilithographic layer 152 of the third epitaxial layer 15 of the first conductivity type is formed on the surface of the first sub-epilithographic layer 151 using chemical vapor deposition, while simultaneously performing ion implantation. The well region 16 of the second conductivity type is formed in the second sub-epitaxial layer 152. Multiple sub-epitaxial layers can be formed by continuing to use the same process steps described above. The number of sub-epitaxial layers is 3 to 6, for example, 3, 4, 5 or 6 layers. The well region 16 formed in each sub-epitaxial layer by the above process has the same width. The width of the well region 16 is 20% to 80% greater than the width of the conductive pillar 14. For example, when the width of the conductive pillar 14 is 3 μm, the width of the well region 16 can be 3.6 μm, 4.5 μm or 5.4 μm. The specific selection is made according to actual needs and is not excessively limited here.

[0087] like Figure 6 As shown, step S5 is performed to form a body region 17 of a second conductivity type on the third epitaxial layer 15 and a second hard mask layer 18 on the body region 17.

[0088] As an example, the body region 17 includes a P-type body region 17, and the method for forming the body region 17 includes ion implantation. For example, ion implantation can be used to implant P-type impurities into the top sub-epilithial layer in the third epitaxial layer 15. In other examples, photolithography is used to define the implantation region as needed. After forming the body region 17, a second hard mask layer 18 is formed on the surface of the body region 17. The structure of the second hard mask layer 18 can be a single silicon oxide layer of a certain thickness, or it can include a combination of silicon oxide-silicon nitride-silicon oxide layers stacked from bottom to top. Preferably, in this embodiment, the second hard mask layer 18 includes a third silicon dioxide layer 181, a second silicon nitride layer 182, and a fourth silicon dioxide layer 183 from bottom to top. Each structural layer of the second hard mask layer 18 can be formed sequentially by chemical vapor deposition, or the third silicon dioxide layer 181 can be formed by thermal oxidation, and the second silicon nitride layer 182 and the fourth silicon dioxide layer 183 can be formed by chemical vapor deposition. The second hard mask layer 18 with a silicon dioxide-silicon nitride-silicon dioxide structure helps to improve etching accuracy and also helps to protect the semiconductor substrate 111.

[0089] like Figure 7As shown, step S6 is performed to graphically represent the second hard mask layer 18, etch the body region 17 and the third epitaxial layer 15, form a plurality of second trenches 19 in the body region 17 and the third epitaxial layer 15, and remove the second hard mask layer 18.

[0090] Specifically, using the second hard mask layer 18, the region where the second trench 19 needs to be fabricated is defined by a patterned photolithography process, thereby etching the required second trench 19 into the body region 17 and the third epitaxial layer 15. The specific implementation of the patterned photolithography and etching processes can be achieved using conventional methods known to those skilled in the art, and are not specifically limited here. Furthermore, after forming the second trench 19, residual portions of the second hard mask layer 18 are removed using processes including, but not limited to, etching.

[0091] like Figure 8 As shown, in step S7, a first interlayer dielectric layer 201 is formed on the inner wall of the second trench 19, and a first polysilicon 202 filling the second trench 19 is formed on the first interlayer dielectric layer 201, wherein the first polysilicon 202, the first interlayer dielectric layer 201 and the body region 17 have flush surfaces.

[0092] Specifically, the first interlayer dielectric layer 201 is typically formed using a furnace tube and a CVD process to grow a first interlayer dielectric layer 201 of a certain thickness on the surface of the body region 17 and the sidewalls of the second trench 19. Optionally, the first interlayer dielectric layer 201 includes one or a combination of silicon oxide layer, silicon nitride layer 261, and silicon phosphate glass layer 222. Preferably, in this embodiment, the first interlayer dielectric layer 201 includes a silicon oxide layer.

[0093] Furthermore, a first polysilicon 202 filling the second trench 19 is formed on the first interlayer dielectric layer 201 on the sidewall of the second trench 19. The first polysilicon 202 is first planarized to expose the surface of the first interlayer dielectric layer 201. Then, a surface planarization process is performed on the first polysilicon 202 and the first interlayer dielectric layer 201 until the first polysilicon 202, the first interlayer dielectric layer 201, and the body region 17 have flush surfaces. The surface planarization process may include mechanical polishing or CMP, and is not excessively limited here.

[0094] like Figure 9As shown, in step S8, a source region 21 having a first conductivity type and a second interlayer dielectric layer 22 are formed on the body region 17, and a first electrode contact hole 231 is formed that penetrates the second interlayer dielectric layer 22 and exposes the bottom surface of the body region 17, and a second electrode contact hole 232 that exposes the first polysilicon 202 is formed.

[0095] Specifically, an N-type impurity is implanted into the body region 17 using an ion implantation process to form a source region 21 with a first conductivity type, such that the source region 21 has a flush surface with the first interlayer dielectric layer 201 and the first polysilicon 202. A second interlayer dielectric layer 22 is formed on the source region 21 using a PECVD process. Optionally, the second interlayer dielectric layer 22 includes one or a combination of silicon oxide layer, silicon nitride layer 261, and silicon phosphate glass layer 222. Preferably, in this embodiment, the second interlayer dielectric layer 22 includes a fifth silicon oxide layer 221 located on the source region 21 and a silicon phosphate glass layer 222 located on the fifth silicon oxide layer 221.

[0096] Furthermore, electrode contact holes are etched in the second interlayer dielectric layer 22 to form a first electrode contact hole 231 that penetrates the second interlayer dielectric layer 22 and the source region 21 and exposes the body region 17 on the bottom surface, and a second electrode contact hole 232 that penetrates the second interlayer dielectric layer 22 and the source region 21 and exposes the first polysilicon 202 on the bottom surface.

[0097] Specifically, a photoresist mask layer is formed on the second interlayer dielectric layer 22. The photoresist mask layer is exposed using masks with different critical dimensions. The regions of the first electrode contact hole 231 and the second electrode contact hole 232 are defined in the developed photoresist mask layer. The first electrode contact hole 231 and the second electrode contact hole 232 with different critical dimensions are formed by a dry etching process through the second interlayer dielectric layer 22 and the source region 21. The bottom of the first electrode contact hole 231 exposes the body region 17, and the bottom of the second electrode contact hole 232 exposes the first polysilicon 202. The depth of the first electrode contact hole 231 in the body region 17 is equal to the depth of the second electrode contact hole 232 in the first polysilicon 202.

[0098] like Figure 10 As shown, step S9 is performed, where metal is filled into the first electrode contact hole 231 and the second electrode contact hole 232 to form a front metal layer 24.

[0099] Specifically, to ensure a good metal connection between the first electrode contact hole 231 and the second electrode contact hole 232, this embodiment uses metal to fill the first electrode contact hole 231 and the second electrode contact hole 232, and thins them to form metal connection pillars. To prevent the metallization of the first polysilicon 202, a barrier layer can be formed by chemical vapor deposition to cover the inner walls of the first electrode contact hole 231 and the second electrode contact hole 232. Preferably, the material of the barrier layer includes Ti / TiN, and the material of the metal includes tungsten.

[0100] Furthermore, such as Figure 11 As shown, the front metal layer 24 is formed on the surface of the second interlayer dielectric layer 22 and is connected to the metal connecting post in the first electrode contact hole 231 and the second electrode contact hole 232.

[0101] Furthermore, such as Figure 11 As shown, after forming the front metal layer 24, a photoresist layer is formed on the upper surface of the front metal layer 24, and the photoresist layer is patterned; based on the patterned photoresist layer, the front metal layer 24 is etched to form a plurality of first isolation trenches 25. The first isolation trenches 25 isolate the source region 21 from the front metal layer 24 on the first polysilicon 202, thereby forming a gate 241 on the first polysilicon 202 and forming the source electrode 242 on the source region 21, and then removing the residual photoresist layer.

[0102] Furthermore, such as Figure 12 As shown, a passivation layer 26 is formed on the upper surface of the front metal layer 24, and the passivation layer 26 is photolithographically etched to form multiple pad windows to expose the source 242 and the gate 241; as shown Figure 13 As shown, the substrate layer is thinned on the back side to form a drain 27; a back gold process is performed on the lower surface of the drain 27 to form a back metal layer 28.

[0103] As an example, the passivation layer 26 can be a single-layer or multi-layer stacked structure. For example, the passivation layer 26 can include only a silicon nitride layer 261, or it can include a silicon nitride layer 261 and a polymer layer located on the silicon nitride layer 261. Preferably, in this embodiment, the passivation layer 26 is selected to include a silicon nitride layer 261 and a polyimide layer 262. The silicon nitride layer 261 can be formed by chemical vapor deposition, and the polyimide layer 262 can be formed by spin coating, so that the passivation layer 26 can better protect the underlying structure. After that, etching is performed to form the pad windows that expose the source 242 and the gate 241.

[0104] As an example, the back metal layer 28 can be at least one of the following material layers: copper layer, gold layer, nickel layer, etc., and there can also be an adhesion layer between the back metal layer 28 and the drain electrode 27, such as a titanium layer and / or a titanium nitride layer, to enhance the adhesion between the back metal layer 28 and the drain electrode 27.

[0105] The trench-type superjunction field-effect transistor fabrication method proposed in this embodiment reduces the aspect ratio of the first trench 12 formed by etching and epitaxial layer filling through epitaxial deep trench filling, resulting in smaller pitch dimensions for the conductive pillars 14 formed in the first epitaxial layer 112 and the second epitaxial layer 113. Subsequently, the number of sub-epitaxy layers in the third epitaxial layer 15 is controlled through multilayer epitaxial processes to significantly reduce the thermal budget and photolithography costs in the superjunction field-effect transistor formation process, resulting in smaller pitch dimensions for the well region 16 formed in the sub-epitaxy layers of the third epitaxial layer 15. The combination of the above processes results in narrower conductive pillars 14 and a wider region where the conductive pillars 14 are located, thereby slowing down the switching speed of the body diode region formed by the P-type well region 16, the P-type conductive pillars 14, and the N-type epitaxial layer when the device is depleted and expanded, thereby reducing the transient capacitance and improving the EMI performance of the device.

[0106] Example 2

[0107] This embodiment provides a trench-type superjunction field-effect transistor, the trench-type superjunction field-effect transistor comprising:

[0108] A semiconductor substrate 111 of a first conductivity type, and a first epitaxial layer 112, a second epitaxial layer 113 of a first conductivity type and a first hard mask layer 13 located on the surface of the semiconductor substrate 111.

[0109] The first trench 12 is located in the first epitaxial layer 112 and the second epitaxial layer 113;

[0110] The conductive post 14 of the second conductivity type is located in the first trench 12 and completely fills the first trench 12, and the conductive post 14, the second epitaxial layer 113 and the first trench 12 have flush surfaces.

[0111] The third epitaxial layer 15 of the first conductivity type is located on the second epitaxial layer 113;

[0112] The second conductivity type of well region 16 is located in the third epitaxial layer 15 and is connected to the conductive pillar 14;

[0113] The second conductivity type of body region 17 is located on the third epitaxial layer 15;

[0114] The second trench 19 is located in the third epitaxial layer 15 and the body region 17;

[0115] The first interlayer dielectric layer 201 is located on the inner wall of the second trench 19;

[0116] The first polysilicon 202 is located on the first interlayer dielectric layer 201 and fills the second trench 19;

[0117] Source region 21 is located on the body region 17 and has a surface flush with the first interlayer dielectric layer 201 and the first polysilicon 202.

[0118] The second interlayer dielectric layer 22 is located on the source region 21 and has a first electrode contact hole 231 that exposes the source region 21 and a second electrode contact hole 232 that exposes the first polysilicon 202.

[0119] A front metal layer 24 is provided, which fills the first electrode contact hole 231 and the second electrode contact hole 232 and has a first isolation trench 25. The first isolation trench 25 isolates the source region 21 from the front metal layer 24 on the first polysilicon 202, so that the front metal layer 24 on the source region 21 forms a source 242 and the front metal layer 24 on the first polysilicon 202 forms a gate 241.

[0120] The drain 27 is located on the back side of the semiconductor substrate 111, and a back metal layer 28 is disposed on the lower surface of the drain 27.

[0121] In this embodiment, the first conductivity type includes N-type and P-type, and the second conductivity type includes P-type and N-type. The first conductivity type and the second conductivity type are different; for example, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type. This embodiment uses the example of the first conductivity type being N-type and the second conductivity type being P-type. Furthermore, the N-type doped ions can be pentavalent ions such as nitrogen, phosphorus, arsenic, and antimony, and the P-type doped ions can be trivalent ions such as boron, aluminum, gallium, and indium. The specific selection depends on actual needs and is not overly restricted here.

[0122] As an example, the third epitaxial layer 15 includes multiple sub-epitaxy layers, and the number of sub-epitaxy layers is 3 to 6. Specifically, the number of sub-epitaxy layers is 3 to 6, for example, it can be 3, 4, 5 or 6 layers.

[0123] As an example, the width of the conductive post 14 is 2–5 μm, and the width of the well region 16 is greater than 20%–80% of the width of the conductive post 14. Specifically, the width of the conductive post 14 can be 2 μm, 3 μm, 4 μm, or 5 μm, and the width of the well region 16 located in the third epitaxial layer 15 should be greater than 20%–80% of the width of the conductive post 14. For example, when the width of the conductive post 14 is 3 μm, the width of the well region 16 can be 3.6 μm, 4.5 μm, or 5.4 μm, depending on actual needs, and no excessive restrictions are imposed here.

[0124] As an example, the trench superjunction field-effect transistor further includes a passivation layer 26 located on the front metal layer 24, and the passivation layer 26 has a plurality of pad windows that expose the source 242 and the gate 241.

[0125] Specifically, the passivation layer 26 can be a single layer or a multi-layer stacked structure. For example, the passivation layer 26 can include only a silicon nitride layer 261, or it can include a silicon nitride layer 261 and a polymer layer located on the silicon nitride layer 261. Preferably, in this embodiment, the passivation layer 26 is selected to include a silicon nitride layer 261 and a polyimide layer 262, so that the passivation layer 26 can better protect the underlying structure. The passivation layer 26 has multiple pad windows, which expose the source 242 and the gate 241.

[0126] In summary, this invention provides a trench-type superjunction field-effect transistor and its fabrication method. Conductive pillars are formed in the first trench using a deep trench filling method, reducing the aspect ratio of the conductive pillars formed by etching and epitaxial layer filling. This results in smaller pitch dimensions for the conductive pillars formed in the first and second epitaxial layers. Subsequently, a third epitaxial layer with multiple sub-epitaxy layers is formed on the second epitaxial layer using a multilayer epitaxial process. Well regions are formed in the multiple sub-epitaxy layers through simultaneous epitaxy and etching, significantly reducing the thermal budget and photolithography costs during superjunction field-effect transistor fabrication. The well regions formed in the sub-epitaxy layers of the third epitaxial layer also have smaller pitch dimensions. The combination of these processes results in narrower P-type conductive pillars and a wider N-type epitaxial layer containing the P-type conductive pillars. This slows down the switching speed of the body diode region formed by the P-type well region, P-type conductive pillars, and N-type epitaxial layer during device depletion and expansion, thereby reducing transient capacitance and improving the device's EMI performance. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0127] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a trench-type superjunction field-effect transistor, characterized in that, The preparation method includes: A semiconductor substrate having a first conductivity type is provided, and a first epitaxial layer of the first conductivity type, a second epitaxial layer of the first conductivity type, and a first hard mask layer are sequentially formed from bottom to top on the surface of the semiconductor substrate; The first hard mask layer is patterned, and the first epitaxial layer and the second epitaxial layer are etched to form a plurality of first trenches in the first epitaxial layer and the second epitaxial layer; The first trench is filled with conductive pillars of a second conductivity type, and the first hard mask layer is removed. The width of the conductive pillars is 2~5μm. A third epitaxial layer of a first conductivity type is formed on the second epitaxial layer. The third epitaxial layer includes a plurality of sub-epitaxy layers formed sequentially, the number of sub-epitaxy layers being 3 to 6. Ion implantation is performed on the surface of the third epitaxial layer to form a well region of a second conductivity type. The well regions formed in each of the sub-epitaxy layers have the same width, and the width of the well region is greater than 20% to 80% of the width of the conductive pillar. A second conductivity type body region is formed on the third epitaxial layer, and a second hard mask layer is formed on the body region; The second hard mask layer is patterned, the body region and the third epitaxial layer are etched, a plurality of second trenches are formed in the body region and the third epitaxial layer, and the second hard mask layer is removed; A first interlayer dielectric layer is formed on the inner wall of the second trench, and a first polysilicon layer filling the second trench is formed on the first interlayer dielectric layer, wherein the first polysilicon layer, the first interlayer dielectric layer and the body region have flush surfaces; A source region having a first conductivity type and a second interlayer dielectric layer are formed on the body region, and a first electrode contact hole is formed that penetrates the second interlayer dielectric layer and exposes the body region on its bottom surface, and a second electrode contact hole is formed that exposes the first polysilicon. A front metal layer is formed by filling the first electrode contact hole and the second electrode contact hole with metal.

2. The method for fabricating a trench-type superjunction field-effect transistor according to claim 1, characterized in that: The doping concentration of the conductive pillar is 0.6E15 NA / cm. 3 ~1.5E15 NA / cm 3 The depth of the conductive post in the first trench is 15~25μm.

3. The method for fabricating a trench-type superjunction field-effect transistor according to claim 1, characterized in that: The method for forming the conductive pillar includes: depositing the conductive pillar in the first trench by introducing an epitaxial gas, a doping gas, and an etching gas based on a CVD process, and performing a chemical mechanical polishing process on the conductive pillar so that the conductive pillar, the second epitaxial layer, and the first trench have flush surfaces.

4. The method for fabricating a trench-type superjunction field-effect transistor according to claim 1, characterized in that: The first interlayer dielectric layer includes one or a combination of silicon oxide, silicon nitride, and silicon phosphate glass layers; the second interlayer dielectric layer includes one or a combination of silicon oxide, silicon nitride, and silicon phosphate glass layers.

5. The method for fabricating a trench-type superjunction field-effect transistor according to claim 1, characterized in that, After forming the front metal layer, the process further includes the following steps: forming a photoresist layer on the upper surface of the front metal layer and patterning the photoresist layer; etching the front metal layer based on the patterned photoresist layer to form a plurality of first isolation trenches, the first isolation trenches separating the source region from the front metal layer on the first polysilicon to form a source electrode on the source region, a gate electrode on the first polysilicon, and removing the remaining photoresist layer.

6. The method for fabricating a trench-type superjunction field-effect transistor according to claim 5, characterized in that, After forming the source electrode, the process further includes the following steps: forming a passivation layer on the upper surface of the front metal layer, and performing photolithography etching on the passivation layer to form multiple pad windows to expose the source electrode and the gate electrode; and performing back-side thinning on the substrate layer to form the drain electrode. A back-gold process is performed on the lower surface of the drain electrode to form a back metal layer.

7. A trench-type superjunction field-effect transistor, characterized in that, The trench-type superjunction field-effect transistor includes: A semiconductor substrate of a first conductivity type, and a first epitaxial layer, a second epitaxial layer of the first conductivity type, and a first hard mask layer located on the surface of the semiconductor substrate; The first trench is located in the first epitaxial layer and the second epitaxial layer; A conductive post of a second conductivity type is located in and completely fills the first trench. The width of the conductive post is 2~5μm, and the conductive post, the second epitaxial layer and the first trench have flush surfaces. A third epitaxial layer of a first conductivity type is located on the second epitaxial layer, the third epitaxial layer comprising a plurality of sub-epitaxy layers and the number of sub-epitaxy layers being 3 to 6; A well region of the second conductivity type is located in the third epitaxial layer and connected to the conductive pillar, wherein the width of the well region is greater than 20% to 80% of the width of the conductive pillar; The second conductivity type of the body region is located on the third epitaxial layer; The second trench is located in the third epitaxial layer and the body region; The first interlayer dielectric layer is located on the inner wall of the second trench; A first polysilicon layer is located on the first interlayer dielectric layer and fills the second trench; The source region is located on the body region and has a surface flush with the first interlayer dielectric layer and the first polysilicon. A second interlayer dielectric layer is located on the source region and has a first electrode contact hole that exposes the source region and a second electrode contact hole that exposes the first polysilicon. A front metal layer, the front metal layer filling the first electrode contact hole and the second electrode contact hole and having a first isolation trench in the front metal layer, the first isolation trench isolating the source region from the front metal layer on the first polysilicon, such that the front metal layer on the source region forms the source and the front metal layer on the first polysilicon forms the gate. The drain is located on the back side of the semiconductor substrate, and a back metal layer is disposed on the lower surface of the drain.

8. The trench-type superjunction field-effect transistor according to claim 7, characterized in that, The trench-type superjunction field-effect transistor further includes a passivation layer located on the front metal layer, and the passivation layer has a plurality of pad windows, the pad windows exposing the source and the gate.

9. The trench-type superjunction field-effect transistor according to any one of claims 7 to 8, characterized in that: The first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

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