Vertical power semiconductor device including sensor electrode

Abstract

A vertical power semiconductor device including a sensor electrode includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite the first surface. The SiC semiconductor body includes: a transistor cell region including a gate structure; a gate pad region; and an interconnection region electrically coupling the gate electrode of the gate structure and the gate pad of the gate pad region via a gate interconnect. The vertical power semiconductor device also includes a sensor electrode. The vertical power semiconductor device further includes a first interlayer dielectric including a first interface for the sensor electrode and a second interface for at least one of the gate electrode or the gate interconnect. The conduction band offset at the first interface is in a range from 1 eV to 2.5 eV. The vertical power semiconductor device also includes a second interface for at least one of the gate electrode or the gate interconnect. The second interlayer dielectric laterally adjoins the first interlayer dielectric.

Description

Technical Field

[0001] The present disclosure relates to a vertical power semiconductor device, and in particular to a vertical power semiconductor device including a sensor electrode. Background Art

[0002] Technology development of new generation SiC power semiconductor devices (e.g., insulated gate field effect transistors (IGFETs), such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs)) aims to improve electrical device characteristics, such as short circuit withstand time. When improving the short circuit withstand time of SiC power semiconductor devices, various tradeoffs and challenges must be met.

[0003] There is a need to improve the short circuit current capability of SiC power semiconductor devices. Summary of the invention

[0004] An example of the present disclosure relates to a vertical power semiconductor device. The vertical power semiconductor device includes: a silicon carbide SiC semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes: a transistor cell region including a gate structure; a gate pad region; and an interconnect region, a gate electrode of the gate structure and a gate pad of the gate pad region being electrically coupled via the gate interconnect. The vertical power semiconductor device also includes a sensor electrode. The vertical power semiconductor device also includes: a first interlayer dielectric including a first interface for the sensor electrode and a second interface for at least one of the gate electrode or the gate interconnect. The value of the conduction band offset at the first interface of the first interlayer dielectric is in the range from 1eV to 2.5eV. The vertical power semiconductor device also includes: a second interlayer dielectric including a second interface for at least one of the gate electrode or the gate interconnect. The second interlayer dielectric is adjacent to the first interlayer dielectric in the lateral direction.

[0005] Another example of the present disclosure relates to a vertical power semiconductor device. The vertical power semiconductor device includes: a silicon carbide SiC semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes: a transistor cell region including a gate structure; a gate pad region; and an interconnect region, a gate electrode of the gate structure and a gate pad of the gate pad region being electrically coupled via the gate interconnect. The power semiconductor device also includes a sensor electrode. The power semiconductor device also includes: a first interlayer dielectric including a first interface for the sensor electrode and a second interface for at least one of the gate electrode or the gate interconnect. The value of the valence band offset at the second interface of the first interlayer dielectric is in the range from 1.0 eV to 2.5 eV. The vertical power semiconductor device also includes: a second interlayer dielectric including a second interface for at least one of the gate electrode or the gate interconnect. The second interlayer dielectric is adjacent to the first interlayer dielectric in the lateral direction.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of SiC power semiconductor devices and power systems and together with the description serve to explain the principles of the embodiments. Additional embodiments are described in the following detailed description and claims.

[0008] Figure 1A A view schematically and exemplarily showing a configuration example of a SiC power semiconductor device including a first interlayer dielectric including a first interface for a sensor electrode and a second interface for a gate electrode or a gate interconnect.

[0009] Figure 1B A partial cross-sectional view schematically and exemplarily showing a configuration example of a SiC power MOSFET including a trench gate structure.

[0010] Figure 1C A top view of a configuration example of a SiC power MOSFET is schematically and exemplarily shown.

[0011] Figures 2A to 5B A top view and a partial cross-sectional view schematically and exemplarily show a configuration example of a SiC power MOSFET including a sensor electrode.

[0012] Figure 6 An energy band diagram including the valence band energy Ev of a second interface between a first interlayer dielectric and one of the gate electrode or gate interconnect is schematically and exemplarily shown.

[0013] Fig. 7A and 7B A configuration example of a power system including a vertical power semiconductor device and a gate driver circuit is illustrated. DETAILED DESCRIPTION

[0014] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and in which specific examples of processable semiconductor substrates are illustrated as diagrams. It should be understood that other examples may be used and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example can be used on other examples or used in conjunction with other examples to produce another example. It is intended that the present disclosure includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The accompanying drawings are not drawn to scale and are for illustration purposes only. If not otherwise indicated, corresponding elements are designated by the same reference numerals in different drawings.

[0015] The terms "having", "containing", "including", "comprising" and the like are open ended and indicate the presence of stated structures, elements or features but do not exclude the presence of additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0016] The term "electrically connected" may describe a permanent low resistance connection between electrically connected elements, such as direct contact between the elements involved or a low resistance connection via metal and / or heavily doped semiconductor materials. The term "electrically coupled" may include that one or more intervening elements suitable for signal and / or power transfer may be connected between the electrically coupled elements, such as elements that may be controlled to temporarily provide a low resistance connection in a first state and a high resistance electrical decoupling in a second state.

[0017] If two elements A and B are combined using "or", if not explicitly or implicitly defined otherwise, this should be understood to disclose all possible combinations, i.e. only A, only B and A and B. Alternative wordings for the same combination are "at least one of A and B" or "A and / or B". The same applies to combinations of more than two elements, if appropriately modified.

[0018] Ranges given for physical dimensions include the boundary values. For example, the range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value (e.g., "at most" and "at least").

[0019] The main constituents of a layer or structure of a chemical compound or alloy are such elements whose atoms form said chemical compound or alloy.For example, silicon (Si) and carbon (C) are the main constituents of a silicon carbide (SiC) layer.

[0020] The term “on” should not be interpreted as meaning only “directly on.” On the contrary, if an element is disposed “on another element” (for example, a layer is “on another layer” or “on a substrate”), another component (for example, another layer) may be disposed between the two elements (for example, if a layer is “on a substrate,” another layer may be disposed between the layer and the substrate).

[0021] An example configuration of a vertical power semiconductor device includes: a silicon carbide SiC semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes: a transistor cell region including a gate structure; a gate pad region; and an interconnect region, a gate electrode of the gate structure and a gate pad of the gate pad region being electrically coupled via the gate interconnect. The vertical power semiconductor device also includes a sensor electrode. The power semiconductor device also includes: a first interlayer dielectric including a first interface for the sensor electrode and a second interface for at least one of the gate electrode or the gate interconnect. The value of the conduction band offset at the first interface of the sensor electrode may be in the range of from 1 eV to 2.5 eV or from 1.5 eV to 2.1 eV.

[0022] For example, the vertical power semiconductor device may be part of an integrated circuit, or may be a discrete semiconductor device or a semiconductor module. For example, the power semiconductor device may be or may include an insulated gate field effect transistor (IGFET), such as a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The vertical power semiconductor device has a load current flowing between a first surface and a second surface opposite to the first surface. The vertical power semiconductor device may be configured to conduct a current exceeding 1A or exceeding 10A or exceeding 30A or exceeding 50A or exceeding 75A or even exceeding 100A, and may also be configured to block a voltage between load electrodes (e.g., between the collector and emitter on an IGBT, or between the drain and source of a MOSFET) in a range of hundreds or up to several thousand volts, such as 400V, 650V, 1.2kV, 1.7kV, 3.3kV, 4.5kV, 5.5kV, 6kV, 6.5kV, 10kV. For example, the blocking voltage may correspond to a voltage level specified in a data sheet of the power semiconductor device.

[0023] The vertical power semiconductor device may be based on a semiconductor body from a crystalline SiC semiconductor material having a band gap larger than that of silicon (i.e., larger than 1.12 eV). For example, the semiconductor material may be 2H-SiC (SiC in 2H polymorph), 6H-SiC, or 15R-SiC. According to an example, the semiconductor material is silicon carbide in 4H polymorph (4H-SiC). The semiconductor body may include or consist of a semiconductor substrate having no semiconductor layer (e.g., a layer grown epitaxially), one or more than one semiconductor layer thereon.

[0024] For example, the first surface may be a front surface or top surface of the semiconductor body, and the second surface may be a back surface or rear surface of the semiconductor body. For example, the semiconductor body may be attached to a lead frame via the second surface. On the first surface of the semiconductor body, for example, bonding pads may be arranged, and bonding wires may be bonded on the bonding pads.

[0025] In order to achieve the desired current carrying capacity, a vertical SiC power semiconductor device can be designed by a plurality of transistor primitives connected in parallel. The transistor primitives connected in parallel may be, for example, transistor primitives formed in the shape of a strip or a strip segment. Of course, the transistor primitives can also have any other shape, such as a circle, an ellipse, a polygon (such as a hexagon or an octahedron). The transistor primitives are arranged in a transistor primitive region of a SiC semiconductor body. The transistor primitive region may be an active region, in which the emitter region of an IGBT (or the source region of a MOSFET) and the collector region of an IGBT (or the drain region of a MOSFET) are arranged to be opposite to each other along a vertical direction. In the active region, for example, through a contact plug on the first surface of the SiC semiconductor body, a load current may enter or leave the semiconductor body of the power semiconductor device. The vertical power semiconductor device may also include an edge termination region, which may include a termination structure. In a blocking mode of the vertical power semiconductor device or in a reverse bias mode of the vertical power semiconductor device, a blocking voltage between the transistor primitive region and the field-free region decreases laterally across the termination structure. The termination structure may have a higher or slightly lower voltage blocking capability than the transistor cell region. For example, the termination structure may include a junction termination extension (JTE) with or without lateral doping variation (VLD), one or more laterally separated guard rings, or any combination thereof.

[0026] For example, the gate structure may be a planar gate structure, or may be a trench gate structure. The gate structure may be stripe-shaped. The gate structure may also have another layout or geometric shape in a plan view, such as a hexagon, a square, a circle, an ellipse. For example, via a gate interconnect, the gate electrode of the gate structure may be electrically connected to a gate pad in a gate pad region. The gate interconnect or a portion thereof may be arranged outside the transistor primitive region, for example, in an interconnect region, the interconnect region being arranged laterally between the transistor primitive region and the edge termination region. The gate interconnect may include one or more conductive materials, for example: a metal, a metal alloy, such as Cu, Au, AlCu, Ag or an alloy thereof; a metal compound, such as TiN; a highly doped semiconductor material, such as highly doped polysilicon. For example, the one or more conductive materials may form a layer stack. At least a portion of the gate interconnect may be a so-called gate runner, which merges with the gate pad. The gate pad and, for example, a sensor electrode and / or a first load electrode pad (for example, a source pad of a MOSFET or an emitter pad of an IGBT) may be part of a wiring region on a SiC semiconductor body. The wiring area may include one or more than one (e.g., two, three, four or even more) wiring levels. Each wiring level may be formed by a single conductive layer or a stack of conductive layers (e.g., (one or more) metal layers). For example, the wiring levels may be patterned photolithographically. Between the stacked wiring levels, an interlayer dielectric structure may be arranged. (One or more) contact plugs and / or (one or more) contact lines may be formed in the openings of the interlayer dielectric structure to electrically connect the portions of the different wiring levels (e.g., metal lines or contact areas) to each other. For example, the sensor electrodes may be formed by one or more metals or metal alloys of the wiring area.

[0027] The first interlayer dielectric may be arranged in at least one of the following: arranged in the transistor primitive region, for example, arranged directly above the gate electrode and arranged directly below the sensor electrode; arranged in the gate interconnect region, for example, arranged directly above the conductive material in the trench having the potential of the gate electrode and arranged directly below the sensor electrode. Therefore, in at least one of the transistor primitive region or the interconnect region, the first interface and the second interface of the first dielectric layer may face each other. For example, the second interlayer dielectric may be or include an oxide of silicon. For example, the oxide of silicon may include deposited SiO2 and / or thermal SiO2. In addition, or as an alternative, for example, the second interlayer dielectric may be or include a silicate glass, such as tetraethyl silicate (TEOS).

[0028] For example, the materials of the sensor electrode at the first interface, the gate electrode and / or gate interconnect at the second interface, the first interlayer dielectric between the first interface and the second interface, and the gate dielectric between the gate electrode and the SiC semiconductor body can be selected so that at normal operating temperature (e.g., less than 250° C.) and at a nominal positive gate voltage (e.g., 18 V), the first interlayer dielectric electrically isolates the gate electrode from the sensor electrode, and the gate dielectric electrically isolates the gate electrode from the SiC semiconductor body. For this case, the overall gate-to-sensor electrode leakage may be small, e.g., in the μA range or below. However, at higher temperatures, e.g., in the event of a short circuit, the conduction band offset of the first interface in the configuration examples described herein allows a much higher thermal leakage current to flow between i) the gate electrode (and / or gate interconnect) and the sensor electrode, compared to the thermal leakage current flowing between ii) the gate electrode and the SiC semiconductor body. The leakage current through the first interlayer dielectric at high temperatures can typically be the sum of the electron current from the sensor electrode into the gate electrode (and / or gate interconnect) and the hole current from the gate electrode (and / or gate interconnect) into the sensor electrode. Typically, either electron or hole current dominates, depending on the corresponding band offset.

[0029] Once a certain critical temperature is exceeded, the increased leakage current between the gate electrode (and / or gate interconnect) and the sensor electrode can allow a fast feedback loop to be triggered, which can be used to disconnect or shut down the vertical power device via a reduction or disconnection of the gate-to-source voltage VGS. The configuration example described herein for reducing channel overdrive operates similarly to a thermally sensitive resistor (thermistor) with a negative temperature coefficient (NTC). It can be directly incorporated in the transistor primitive region, where the sensor electrode is placed directly on top of the first interlayer dielectric that electrically isolates the gate electrode; and / or it can be incorporated in a different passive device region (e.g., a gate interconnect region, such as a gate track region). In the configuration example described herein including a first interlayer dielectric having a low conduction band offset (for the sensor electrode) compared to the conduction band offset of the gate dielectric (for the SiC semiconductor body), the original transistor primitive area design (e.g., MOS system) governing the channel properties does not need to be modified to achieve the desired functionality, because the material of the gate electrode is less relevant for achieving the technical effect of reducing channel overdrive, considering the leakage current flowing from the sensor electrode through the first interlayer dielectric toward the gate electrode. Therefore, the configuration example described herein can allow for increased short-circuit ruggedness without affecting the area-specific on-state resistance RonxA of the vertical power semiconductor device.

[0030] For example, a portion of the sensor electrode at the first interface may be made of aluminum, copper, titanium, nickel, molybdenum, tungsten, or alloys thereof.

[0031] For example, a portion of the first interlayer dielectric at the first interface may be made of a high-k material.

[0032] For example, the high-k material may be aluminum oxide, zirconium oxide, aluminum nitride, hafnium oxide, yttrium oxide, silicon nitride oxide, silicon nitride or aluminum nitride.For example, the first interlayer dielectric may also include a layer stack of the above high-k materials.

[0033] For example, the gate structure may include a gate dielectric disposed between the gate electrode and the SiC semiconductor body. A portion of the gate dielectric at the channel interface for the SiC semiconductor body may be a high-k dielectric. In some other examples, a portion of the gate dielectric at the channel interface for the SiC semiconductor body may be an oxide, such as a thermal oxide (such as thermal SiO2) or a deposited and annealed oxide. The portion of the gate dielectric may also include a layer stack of dielectric materials, such as a combination of oxides and high-k materials.

[0034] For example, the conduction band offset at the first interface of the first interlayer dielectric may be smaller than the conduction band offset at the channel interface. Thus, at a positive gate voltage (on-state), the onset of thermionic electron tunneling current between the sensor electrode and the gate electrode occurs at a (much) lower threshold temperature than the onset of thermionic tunneling current between the gate electrode and the SiC semiconductor body. Thus, the MOS interface and the gate oxide are not altered or degraded by large leakage currents flowing from the gate electrode through the gate oxide into the semiconductor body.

[0035] For example, the gate structure may be a planar or trench gate structure. At least a portion of the second interface may be arranged in the transistor cell region. The portion of the second interface may be directly opposite to the first interface, ie, facing the first interface.

[0036] For example, at least a portion of the second interface may be arranged in the interconnect region. The portion of the second interface may be directly opposite the first interface. For example, the gate interconnect may include a gate resistor having a gate resistance in the range from 5Ω to 20Ω.

[0037] For example, the vertical power semiconductor device may further include a source electrode or an emitter electrode. The second interlayer dielectric may include a first interface for the source electrode or the emitter electrode. The conduction band offset at the first interface of the second interlayer dielectric may be greater than the conduction band offset at the first interface of the first interlayer dielectric. Thus, heat-assisted electron tunneling between the sensor electrode and the gate electrode and / or the gate interconnect is triggered at a lower temperature than between the source electrode or the emitter electrode and the gate electrode and / or the gate interconnect.

[0038] For example, the sensor electrode and the source electrode or the emitter electrode may be separated from each other laterally. For example, the sensor electrode and the source electrode or the emitter electrode may be electrically isolated. For example, the sensor electrode may be electrically connected to a sensor pad area, and the sensor pad area may be electrically connected to an external circuit (e.g., a gate driver circuit). For example, the sensor electrode and the source electrode or the emitter electrode may be separate parts of one or more wiring layers in a wiring area. For example, the sensor electrode and the source electrode or the emitter electrode may be formed of the same (one or more) conductive materials. In some configuration examples, the (one or more) conductive materials of the sensor electrode and the source electrode or the emitter electrode may be at least partially different from each other.

[0039] For example, the sensor electrode may become a source electrode or an emitter electrode in the lateral direction. Thermally assisted electron tunneling between the sensor electrode and the gate electrode and / or the gate interconnect may be sensed via the gate pad by a sensing unit integrated in the gate driver circuit. For example, the gate driver circuit may be integrated in a chip or die different from the chip or die of the SiC semiconductor body of the vertical power semiconductor device.

[0040] For example, the conduction band offset at the first interface of the second interlayer dielectric may be 0.5 eV to 1.5 eV greater than the conduction band offset at the first interface of the first interlayer dielectric. Thus, when a certain critical temperature is exceeded, the increased electron leakage current flows mainly through the first interlayer dielectric.

[0041] Another configuration example of a vertical power semiconductor device includes: a silicon carbide SiC semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes: a transistor cell region including a gate structure; a gate pad region; and an interconnect region, a gate electrode of the gate structure and a gate pad of the gate pad region being electrically coupled via the gate interconnect. The vertical power semiconductor device also includes a sensor electrode. The vertical power semiconductor device also includes: a first interlayer dielectric including a first interface for the sensor electrode and a second interface for at least one of the gate electrode or the gate interconnect. The value of the valence band offset at the second interface of the first interlayer dielectric may be in the range of from 1.0 eV to 2.5 eV or from 1.5 eV to 2.1 eV. The vertical power semiconductor device may also include: a second interlayer dielectric including a second interface for at least one of the gate electrode or the gate interconnect. The second interlayer dielectric may be adjacent to the first interlayer dielectric in the lateral direction. Once a certain critical temperature is exceeded, the increased hole leakage current between the gate electrode (and / or gate interconnect) and the sensor electrode may allow triggering of a fast feedback loop that can be used to disconnect or shut down the vertical power device via a reduction or disconnection of the gate-to-source voltage VGS.

[0042] The band offset (e.g., conduction band offset) at the first interface may correspond to the band offset (e.g., conduction band offset) between the material of the first interlayer dielectric and the material of the sensor electrode. Similarly, the band offset (e.g., valence band offset) at the second interface may correspond to the band offset (e.g., valence band offset) between the material of the first interlayer dielectric and the material of the gate dielectric. For example, the materials of the first interlayer dielectric and the sensor electrode may be selected so that a desired band offset (e.g., conduction band offset) is achieved. Separately or in combination, the materials of the first interlayer dielectric and the gate dielectric may be selected so that a desired band offset (e.g., valence band offset) is achieved. It may further be desirable to select the materials of the first interlayer dielectric and the gate dielectric so that a desired band offset (e.g., conduction band offset or valence band offset) is achieved.

[0043] For example, the vertical semiconductor device may further include a source electrode or an emitter electrode. The second interlayer dielectric may include a second interface for at least one of the gate electrode or the gate interconnect. The valence band offset at the second interface of the second interlayer dielectric may be greater than the valence band offset at the second interface of the first interlayer dielectric. Thus, thermally assisted hole tunneling between the sensor electrode and the gate electrode and / or the gate interconnect is triggered at a lower temperature than between the source electrode or the emitter electrode and the gate electrode and / or the gate interconnect.

[0044] For example, the value of the valence band offset at the second interface of the second interlayer dielectric can be 0.5 eV to 3.0 eV greater than the value of the valence band offset at the second interface of the first interlayer dielectric. Thus, when a certain critical temperature is exceeded, the increased hole leakage current flow is restricted through the first interlayer dielectric.

[0045] Another example of the present disclosure relates to a power system. The power system may include a vertical power semiconductor device of any configuration example described in the configuration examples described herein. The power system may also include: a gate driver circuit electrically coupled to a sensor electrode. The gate driver circuit may include a sensor unit. The sensor unit may be configured to generate a sensing signal value, wherein generating the sensing signal value may include sensing a current from the sensor electrode and generating a comparison result by comparing the sensing signal value with a threshold. The sensor unit may also be configured to, based on the comparison result, cause the gate driver circuit to disconnect the vertical power semiconductor device by applying a gate disconnect signal (e.g., VGS=0V) to the gate electrode.

[0046] Sensing current from a sensor electrode may be performed via a separate sensor pad of a vertical power semiconductor device, or via leakage current from a gate pad in the case where the sensor electrode is electrically connected to a source electrode and an emitter electrode. Generating a sense signal value may be performed by sensing a voltage drop of the leakage current from the sensor electrode across a resistor (e.g., a sense resistor or a gate resistor). For example, sensing current from a sensor electrode connected to a source electrode or an emitter electrode may be performed during a steady state of the gate voltage. For example, sensing current from a sensor electrode separated from a source electrode or an emitter electrode may also be performed permanently.

[0047] For example, a power system may include: a first chip including a vertical power semiconductor device; and a second chip including a gate driver circuit.

[0048] The examples and features described above and below may be combined.

[0049] Some of the above and following examples are described in conjunction with a silicon carbide semiconductor body or substrate. Alternatively, a wide bandgap semiconductor substrate (e.g., a wide bandgap wafer) may be processed, for example, including a wide bandgap semiconductor material other than silicon carbide. The wide bandgap semiconductor wafer may have a bandgap larger than the bandgap of silicon (1.12 eV). For example, the wide bandgap semiconductor wafer may be a silicon carbide (SiC) wafer or a gallium arsenide (GaAs) wafer or a gallium nitride (GaN) wafer.

[0050] More details and aspects are mentioned in conjunction with the examples described above or below. The description and drawings illustrate the principles of the present disclosure only. In addition, all examples described herein are primarily intended to be used explicitly only for illustration purposes to help readers understand the principles and concepts of the present disclosure contributed by (one or more) inventors to promote the art. All statements describing the principles, aspects and examples of the present disclosure and specific examples of the present disclosure herein are intended to cover their equivalents.

[0051] In the following, another example of a field effect transistor FET is explained in conjunction with the accompanying drawings. The functional and structural details described for the above examples will be equally applicable to the exemplary embodiments illustrated in the accompanying drawings and further described below. In the illustrated examples, an n-channel FET is illustrated. However, the examples described herein may also be applied to p-channel devices, such as p-channel MOSFETs or p-channel IGBTs.

[0052] Details of the structure or functions or technical benefits of the features described above are equally applicable to the following examples, and vice versa.

[0053] Figure 1A A portion of a power semiconductor device 100 configured as a planar or trench gate SiC power MOSFET is schematically and exemplarily illustrated.

[0054] The power semiconductor device 100 includes a first interlayer dielectric 120 including a first interface 1221 for the sensor electrode 116 and a second interface 1222 for the gate electrode 1061 or the gate interconnect 114 (such as a gate track or gate interconnect line). The schematic energy band diagram illustrates the conduction band energy Ec versus the direction x / y. B,0 Exists at the first interface 1221. For example, the conduction band offset Φ B,0 It can be in the range from 1 eV to 2.5 eV.

[0055] Figure 1B A partial cross-sectional view schematically and exemplarily shows a configuration example of a power semiconductor device 100 configured as a trench gate SiC power MOSFET. The SiC power MOSFET is a vertical power semiconductor device that also includes an edge termination region (not shown in FIG. 2 ) at least partially surrounding a transistor cell region 104.

[0056] The gate structure 106 includes a gate electrode 1061, which is electrically isolated from the SiC semiconductor body 102 by a gate dielectric 1062 of the gate structure 106. The gate dielectric 1062 is adjacent to a channel region 113. The channel region 113 is defined by a portion of the p-doped body region 134, which is adjacent to the gate dielectric 1062 at a channel interface 121 with the gate structure 106. The gate structure 106 is configured as a trench gate structure 107. For example, the conductivity of the channel region 113 can be controlled by a potential applied to the gate electrode 1061, for example, by a field effect. For example, a positive voltage applied to the gate electrode 1061 can induce an n-type inversion channel, for example, in the channel region 113 adjacent to the gate dielectric 1062. The p-doped body region 134 may be electrically connected to the source electrode or emitter electrode 142 via the first surface 1031, for example, by a contact plug and / or a recessed contact of the source electrode or emitter electrode 142 on the top surface of the body region 134, the recessed contact may extend into the SiC semiconductor body 102 and / or may be electrically connected to the body region 134 via the sidewall of the recessed contact (not shown in FIG. 2 ). For example, the channel region 113 as part of the body region 134 may include partial compensation by n-type dopants for adjusting the threshold voltage VTH. For example, partial compensation may be achieved by tilted ion implantation through the sidewalls of the trench. The gate dielectric 1062 of the gate structure 106 is also connected to the n-type dopant. + The doped source region 136 is adjacent to n + The doped source region 136 is arranged between the p-doped body region 134 and the first surface 1031 .

[0057] At the bottom side of the gate structure 106, the gate dielectric 1062 may adjoin the p-doped diode region 124. The p-doped diode region 124 may include one or more sub-regions overlapping each other along the vertical direction y. Along the sidewalls of the trench gate structure 107 opposite to the sidewalls where the channel interface 121 is located, the p-doped diode region 124 may extend upward to the first surface 1031 (not shown in FIG. 2 ). The gate dielectric 1062 of the gate structure 106 also adjoins the n-doped current extension region 138, which is arranged between the p-doped main region 134 and the n-doped drift region 140. The n-doped drift region 140 has a smaller doping concentration than the current extension region 138. At the second surface 1032 of the SiC semiconductor body 102, the drift region 140 is electrically connected to the drain electrode or collector electrode 126. Between the drift zone 140 and the second surface 1032 further doped semiconductor regions may be arranged, for example a highly n-doped drift contact region or an n-doped field stop region.

[0058] The second interlayer dielectric 144 is arranged on top of the gate electrode 1061 with an intermediate second interface 1232. The source electrode or emitter electrode 142 is arranged on top of the second interlayer dielectric 144 with an intermediate first interface 1231. The conduction band offset at the first interface 1231 of the second interlayer dielectric 144 is greater than that at the Figure 1A The conduction band of the first interface 1221 of the first interlayer dielectric 120 shown in FIG. 1 is offset.

[0059] Figure 1C The schematic top view of FIG. 1 is a schematic and exemplary top view for illustrating a configuration example of a vertical power semiconductor device 100. The vertical power semiconductor device includes a gate pad 112 in the gate pad region 108. A gate interconnect 114 in the interconnect region 110 electrically connects a gate electrode (not shown in FIG. 1 ) to a gate electrode 112. Figure 1C The gate interconnection includes a gate track 1141 and a gate finger 1142. The transistor cell (not shown in FIG. 1 ) of the vertical power semiconductor device 100 Figure 1C ) is arranged below the source electrode or emitter electrode 142 in the transistor cell region 104. Figure 1A The sensor electrodes 116 may be integrated in the interconnect region 110 and / or the transistor cell region 104 .

[0060] Figures 2A to 5B The schematic top view and cross-sectional view of FIG. 1 relate to a configuration example for illustrating the arrangement of sensor electrodes of the vertical power semiconductor device 100 .

[0061] Reference Figure 2A Schematic top view of Figure 2B , the sensor electrode 116 is arranged in the transistor cell region 104 and is laterally separated from the source electrode or emitter electrode 142. The first interlayer dielectric 120 has a first interface 1221 for the sensor electrode 116 and a second interface 1222 for the gate electrode 1061. The second interlayer dielectric 144 has a first interface 1231 for the source electrode or emitter electrode 142 and a second interface 1232 for the gate electrode 1061. The second interlayer dielectric 144 is laterally adjacent to the first interlayer dielectric 120. The sensor electrode 116 is electrically isolated from the deep p-doped well 146 by the first interlayer dielectric 120. Once a certain critical temperature is exceeded, the electron leakage current between the gate electrode 1061 and the sensor electrode 116 can be sensed via the sensing pin and the sensor pad, for example, by an external sensor unit. This may allow for triggering a fast feedback loop that can be used to disconnect or shut down the vertical power device 100 via a reduction or disconnection of the gate-to-source voltage VGS.

[0062] Reference Figure 3A Schematic top view of Figure 3B In the configuration example illustrated in the corresponding cross-sectional view of FIG, the sensor electrode 116 is laterally adjacent to the source electrode or emitter electrode 142. Once a certain critical temperature is exceeded, the electron leakage current between the gate electrode 1061 and the sensor electrode 116 can be sensed as a gate-to-source leakage current via the gate pin and the gate pad 112, for example, by an external sensor unit. This can allow triggering a fast feedback loop that can be used to disconnect or shut down the vertical power device 100 via a reduction or disconnection of the gate-to-source voltage VGS.

[0063] Reference Figure 4A Schematic top view of Figure 4B In the configuration example illustrated in the corresponding cross-sectional view of , the sensor electrode 116 is laterally adjacent to the source electrode or emitter electrode 142 . Figure 3B The deep p-doped well 146 is Figure 4A and 4B 1 is omitted in the configuration example, and the sensor electrode 116 is electrically connected to the transistor cell in the SiC semiconductor body 102 via a contact plug, for example.

[0064] Reference Figure 5A Schematic top view of Figure 5B , the sensor electrode 116 is arranged in the interconnection region 110 including the gate interconnection 114. The sensor 116 is laterally and electrically connected to the gate interconnection 114 (e.g., Figure 1C The gate tracks 1141 or gate fingers 1142 shown in the figure are separated.

[0065] In the above examples, the increased leakage current between the gate electrode 1061 (and / or the gate interconnect 114) and the sensor electrode 116 has been illustrated as a conduction band offset φ at the first interface 1221 of the first interlayer dielectric 120. B,0 The electron current on the gate-to-source voltage VGS can trigger a fast feedback loop that can be used to disconnect or shut down the vertical power device 100 via a reduction or disconnection of the gate-to-source voltage VGS.

[0066] Reference Figure 6 ( Figure 6 Schematic energy band diagram showing valence band energy Ev versus direction x / y), hole leakage current from the second interface 1222 of the gate electrode 1061 or the gate interconnect 114 can also trigger a fast feedback loop, which can be used to disconnect or shut down the vertical power device 100 by reducing or disconnecting the gate-to-source voltage VGS. B,1 The value of may be in the range from 1.0 eV to 2.5 eV.

[0067] Fig. 7A and 7B The schematic diagram of FIG. 1 illustrates a configuration example of a power system 1001 .

[0068] Reference Fig. 7A , the power system 1001 includes a vertical power semiconductor device 100 that can be configured according to any of the configuration examples described in this document. The vertical power semiconductor device 100 includes: a drain electrode D, which is electrically connected to the drain pin Pin2; a source electrode S, which is electrically connected to the source pin Pin3; and a gate electrode G, which is electrically connected to the gate pin PIN1. The vertical power semiconductor device 100 also includes: a sensor pin Pin4, which is electrically connected to the sensing electrode 116 of the vertical power semiconductor device 100. The sensor pin Pin4 is separated from the source pin Pin3 (see, for example Figure 2A , 2B , 5A, 5B configuration examples).

[0069] The power system 1001 further includes a gate driver circuit 200, the gate driver circuit 200 includes a sensor unit 201, and the sensor unit 201 is Fig. 7A Schematically illustrated by a feedback loop in FIG. 1 , the sensor unit 201 is used to generate a sense signal value by sensing the current I_sensor from the sensor pin Pin4 of the vertical power semiconductor device 100, and to generate a comparison result by comparing the sense signal value (e.g., the temperature T obtained from the sensed current I_sensor) with a threshold value (e.g., a critical temperature Tcrit). According to the comparison result, when the sensed temperature exceeds the critical temperature Tcrit, the gate driver circuit 200 can disconnect the vertical power semiconductor device 100 by applying a gate disconnection signal VGS=0V to the gate electrode via the gate pin Pin1.

[0070] exist Figure 7B In the configuration example of the power system 1001 shown in FIG. Fig. 7A The sensor pin Pin4 is omitted because the sensor electrode 116 is electrically connected to the source electrode S (see, for example, Figure 3A , 3B , 4A, 4B). For this configuration example, the gate current I_G including the leakage current from the sensor electrode through the first interlayer dielectric is used in a feedback loop to generate a sense signal value.

[0071] In the power system 1001 , for example, the vertical power semiconductor device 100 and the gate driver circuit 200 may be integrated in separate dies or chips.

[0072] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A vertical power semiconductor device (100), comprising: A silicon carbide (SiC) semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite to the first surface (1031), the SiC semiconductor body (102) comprising: a transistor cell region (104) comprising a gate structure (106); a gate pad region (108); and an interconnect region (110) electrically coupling a gate electrode (1061) of the gate structure (106) and a gate pad (112) of the gate pad region (108) via a gate interconnect (114); sensor electrode (116); A first interlayer dielectric (120) comprising a first interface (1221) for the sensor electrode (116) and a second interface (1222) for at least one of the gate electrode (1061) or the gate interconnect (114), wherein a conduction band offset (Φ) at the first interface (1221) of the first interlayer dielectric (120) is B,0 ) has a value in the range from 1 eV to 2.5 eV; and A second interlayer dielectric (144) includes a second interface (1232) for at least one of the gate electrode (1061) or the gate interconnect (114), wherein the second interlayer dielectric (144) is laterally adjacent to the first interlayer dielectric (120).

2. The vertical power semiconductor device (100) according to the preceding claim, wherein a portion of the sensor electrode (116) at the first interface (1121) is made of aluminum, copper, titanium, nickel, molybdenum, tungsten or alloys thereof.

3. The vertical power semiconductor device (100) according to any one of the preceding claims, wherein a portion of the first interlayer dielectric (120) at the first interface (1121) is made of a high-k material.

4. The vertical power semiconductor device (100) of the preceding claim, wherein the high-k material is aluminum oxide, zirconium oxide, aluminum nitride, hafnium oxide, yttrium oxide, silicon nitride oxide, silicon nitride or aluminum nitride.

5. A vertical power semiconductor device (100) as claimed in any one of the preceding claims, wherein the gate structure (106) comprises a gate dielectric (1062) arranged between the gate electrode (1061) and the SiC semiconductor body (102), and a portion of the gate dielectric (1062) at a channel interface (121) with the SiC semiconductor body (102) is a high-k dielectric.

6. The vertical power semiconductor device (100) according to any one of the preceding claims, wherein the conduction band offset (Φ B,0 ) is smaller than the conduction band offset at the channel interface (121).

7. A vertical power semiconductor device (100) as claimed in any of the preceding claims, wherein the gate structure (106) is a planar or trench gate structure (107), and at least a portion of the second interface (1222) is arranged in the transistor cell region (104), the portion of the second interface being directly opposite to the first interface (1221).

8. The vertical power semiconductor device (100) as claimed in any one of the preceding claims, wherein at least a portion of the second interface (1222) is arranged in the interconnection region (110), the portion of the second interface directly opposing the first interface (1221).

9. The vertical power semiconductor device of any preceding claim, further comprising: A source electrode or an emitter electrode (142), wherein the second interlayer dielectric (144) comprises a first interface (1231) for the source electrode or the emitter electrode (142), and wherein the conduction band offset (Φ) at the first interface (1231) of the second interlayer dielectric (144) is B,0 ) is greater than the conduction band offset (Φ) at the first interface (1221) of the first interlayer dielectric (120) B,0 ).

10. A vertical power semiconductor device as claimed in the preceding claim, wherein the sensor electrode (116) and the source or emitter electrode (142) are laterally spaced apart from one another.

11. The vertical power semiconductor device of claim 9, wherein the sensor electrode (116) laterally becomes the source electrode or emitter electrode (142).

12. A vertical power semiconductor device (100) as claimed in any one of the three preceding claims, wherein the conduction band offset (φ) at the first interface (1231) of the second interlayer dielectric (144) is B,0 ) is greater than the conduction band offset (Φ) at the first interface (1221) of the first interlayer dielectric (120) B,0 ) is 0.5eV to 1.5eV.

13. A vertical power semiconductor device (100), comprising: A silicon carbide (SiC) semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite to the first surface (1031), the SiC semiconductor body (102) comprising: a transistor cell region (104) comprising a gate structure (106); a gate pad region (108); and an interconnect region (110) electrically coupling a gate electrode (1061) of the gate structure (106) and a gate pad (112) of the gate pad region (108) via a gate interconnect (114); sensor electrodes (116); and A first interlayer dielectric (120) comprising a first interface (1221) for the sensor (116) and a second interface (1222) for at least one of the gate electrode (1061) or the gate interconnect (114), wherein a valence band offset (Φ) of the second interface (1222) of the first interlayer dielectric (120) is B,1 ) has a value in the range from 1 eV to 2.5 eV; and A second interlayer dielectric (144) includes a second interface (1232) for at least one of the gate electrode (1061) or the gate interconnect (114), wherein the second interlayer dielectric (144) is laterally adjacent to the first interlayer dielectric (120).

14. The vertical power semiconductor device (100) according to the preceding claim, further comprising: A source electrode or an emitter electrode (142), wherein the second interlayer dielectric (144) includes a second interface (1232) for at least one of the gate electrode (1061) or the gate interconnect (114), and wherein a valence band offset (φ) at the second interface (1232) of the second interlayer dielectric (144) is B,1 ) is greater than the valence band offset (Φ) at the second interface (1222) of the first interlayer dielectric (120) B,1 ).

15. The vertical power semiconductor device (100) of the preceding claim, wherein the valence band offset (Φ B,1 ) is greater than the valence band offset (Φ) at the second interface (1222) of the first interlayer dielectric (120). B,1 ) value is 0.5eV to 3.0eV.

16. A power system (1001), comprising: A vertical power semiconductor device (100) as claimed in any one of the preceding claims; A gate driver circuit (200) is electrically coupled to the sensor electrode (116), the gate driver circuit (200) comprising a sensor unit (201), wherein the sensor unit is configured to: generating a sensing signal value (T), wherein generating the sensing signal value (T) comprises sensing a current (I_sensor, I_G) from the sensor electrode (116) and generating a comparison result by comparing the sensing signal value (T) with a threshold value (Tcrit); and Based on the comparison result, the gate driver circuit (200) turns off the vertical power semiconductor device (100) by applying a gate turn-off signal to the gate electrode (1061).

17. The power system (1001) according to the preceding claim, further comprising: A first chip comprising the vertical power semiconductor device (100); and a second chip comprising the gate driver circuit (200).

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