Image sensor

Abstract

An image sensor includes: a substrate; a first pixel disposed in the substrate, the first pixel including a first photoelectric conversion region; a second pixel disposed adjacent to the first pixel in the substrate, the second pixel including a second photoelectric conversion region; a first floating diffusion region in the first pixel; a second floating diffusion region in the second pixel; an insulating layer on the substrate; and a first buried connector passing through the insulating layer and connected to the first floating diffusion region and the second floating diffusion region, where the first buried connector includes an upper surface at a vertical level higher than the upper surface of the insulating layer and a lower surface at a vertical level lower than the upper surface of the insulating layer. And the lower surface of the first embedded connector is at a vertical level higher than or equal to the lower surface of the insulating layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0150278 filed on November 2, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to an image sensor, and more particularly, to an image sensor including a photodiode. Background Art

[0004] An image sensor is a device that converts an optical image signal into an electrical signal. The image sensor includes a plurality of pixels that receive light to convert the received light into an electrical signal, and each pixel includes a photodiode region. Because the size of each pixel decreases as the integration of the image sensor increases, the electrically connected components of the pixel circuit for driving each pixel decrease, and noise occurs as the integration increases, or the photoelectric conversion efficiency such as conversion gain decreases as the integration increases. Summary of the invention

[0005] The inventive concept provides an image sensor having improved performance and reliability.

[0006] An image sensor according to an embodiment includes: a substrate including a front surface and a back surface opposite to the front surface; a first pixel disposed in the substrate, the first pixel including a first photoelectric conversion region; a second pixel disposed in the substrate adjacent to the first pixel in a first horizontal direction, wherein the first horizontal direction is a direction parallel to the front surface of the substrate, the second pixel including a second photoelectric conversion region; a pixel isolation structure disposed between the first pixel and the second pixel, the pixel isolation structure extending in a vertical direction in the substrate and surrounding each of the first pixel and the second pixel, wherein the vertical direction is perpendicular to the front surface of the substrate surface direction; a first floating diffusion region, which is set in the first pixel to be adjacent to the front surface of the substrate; a second floating diffusion region, which is set in the second pixel to be adjacent to the front surface of the substrate; an insulating layer, which is set on the front surface of the substrate; and a first buried connector, which passes through the insulating layer and is connected to the first floating diffusion region and the second floating diffusion region, wherein the first buried connector includes a lower surface and an upper surface set in the substrate, the upper surface of the first buried connector is set at a vertical level higher than the upper surface of the insulating layer, and the lower surface of the first buried connector is set at a vertical level higher than or equal to the lower surface of the insulating layer.

[0007] An image sensor according to an embodiment includes: a substrate including a front surface and a back surface opposite to the front surface; a first pixel arranged in the substrate, the first pixel including a first photoelectric conversion region; a second pixel arranged to be adjacent to the first pixel in a first horizontal direction in the substrate, the second pixel including a second photoelectric conversion region, wherein the first horizontal direction is a direction parallel to the front surface of the substrate; a pixel isolation structure arranged between the first pixel and the second pixel, the pixel isolation structure extending in a vertical direction in the substrate and surrounding each of the first pixel and the second pixel, wherein the vertical direction is a direction perpendicular to the front surface of the substrate; a first floating diffusion region arranged in the first pixel to be adjacent to the front surface of the substrate; a second floating diffusion region arranged in the second pixel to be adjacent to the front surface of the substrate; an insulating layer arranged on the front surface of the substrate; and a buried connector passing through the insulating layer and connected to the first floating diffusion region and the second floating diffusion region, wherein the uppermost portion of the lower surface of the buried connector is arranged at a vertical level higher than or equal to the lower surface of the insulating layer, and the upper surface of the buried connector is arranged at a vertical level higher than the front surface of the substrate.

[0008] An image sensor according to an embodiment includes: a substrate including a front surface and a back surface opposite to the front surface; a first pixel arranged in the substrate, the first pixel including a plurality of first photoelectric conversion regions; a second pixel arranged to be adjacent to the first pixel in a first horizontal direction in the substrate, the second pixel including a plurality of second photoelectric conversion regions, wherein the first horizontal direction is a direction parallel to the front surface of the substrate; a third pixel arranged to be adjacent to the first pixel in the substrate in a second horizontal direction intersecting the first horizontal direction, the third pixel including a plurality of third photoelectric conversion regions; a fourth pixel arranged to be adjacent to the second pixel in the substrate in a second horizontal direction, the fourth pixel including a plurality of fourth photoelectric conversion regions; a pixel isolation structure extending in a vertical direction in the substrate, surrounding each of the first pixel, the second pixel, the third pixel and the fourth pixel, and extending in the first horizontal direction and the second horizontal direction, wherein the vertical direction is a direction perpendicular to the front surface of the substrate; a first floating diffusion region arranged in the first a second floating diffusion region, which is arranged in a pixel to be adjacent to the front surface of the substrate and shared by a plurality of first photoelectric conversion regions; a second floating diffusion region, which is arranged in a second pixel to be adjacent to the front surface of the substrate and shared by a plurality of second photoelectric conversion regions; a third floating diffusion region, which is arranged in a third pixel to be adjacent to the front surface of the substrate and shared by a plurality of third photoelectric conversion regions; a fourth floating diffusion region, which is arranged in a fourth pixel to be adjacent to the front surface of the substrate and shared by a plurality of fourth photoelectric conversion regions; an insulating layer, which is arranged on the front surface of the substrate; an embedded connector, which contacts the first floating diffusion region to the fourth floating diffusion region and includes a portion passing through the insulating layer and embedded in the substrate; and a color filter and a lens, each of which is arranged on the back surface of the substrate, wherein the embedded connector includes a material having an etching selectivity relative to the insulating layer, the uppermost portion of the lower surface of the embedded connector is arranged at a vertical level higher than or equal to the lower surface of the insulating layer, and the upper surface of the embedded connector is arranged at a vertical level higher than the front surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a perspective view schematically showing an image sensor according to an embodiment;

[0011] Figure 2 is shown corresponding to Figure 1 A layout diagram of an image sensor with one pixel;

[0012] Figure 3 It is along Figure 2 A cross-sectional view taken along line AA;

[0013] Figure 4 It is along Figure 2A cross-sectional view taken along line BB;

[0014] Figure 5 yes Figure 4 An enlarged cross-sectional view of area EX1;

[0015] Figure 6 is an equivalent circuit diagram of an image sensor according to an embodiment;

[0016] Figure 7 is a layout diagram showing an image sensor according to an embodiment;

[0017] Figure 8 is a layout diagram showing an image sensor according to an embodiment;

[0018] Fig. 9 is a layout diagram showing an image sensor according to an embodiment;

[0019] Fig.10 is a perspective view schematically showing an image sensor according to an embodiment;

[0020] Fig.11 It is along Fig.10 A cross-sectional view taken along line CC;

[0021] Fig.12 is a cross-sectional view illustrating a method of manufacturing an image sensor according to an embodiment;

[0022] Fig.13 is a cross-sectional view illustrating a method of manufacturing an image sensor according to an embodiment;

[0023] Fig.14 is a cross-sectional view illustrating a method of manufacturing an image sensor according to an embodiment;

[0024] Fig.15 is a cross-sectional view illustrating a method of manufacturing an image sensor according to an embodiment;

[0025] Fig.16 is a cross-sectional view illustrating a method of manufacturing an image sensor according to an embodiment; and

[0026] Fig.17 is a block diagram showing a configuration of an image sensor according to an embodiment. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. However, the inventive concept can be implemented in many different forms and should not be construed as being limited to the example embodiments set forth herein. It should also be emphasized that the present disclosure provides details of alternative examples, but does not list all of the alternative examples. In addition, any consistency of details between the examples should not be construed as meaning that these details are necessary. When determining the requirements of the present invention, reference should be made to the language of the claims.

[0028] Although language such as "an embodiment," "one embodiment," or "a particular embodiment" may be used to refer to the drawings described herein, these drawings and their corresponding descriptions are not intended to contradict other drawings or descriptions unless the context so dictates. Thus, particular aspects of a particular drawing may be identical to particular features in other drawings, and / or a particular drawing may be a different expression or different portion of a particular exemplary embodiment.

[0029] Items described herein in the singular may be provided in the plural, for example, as seen in the accompanying drawings. Therefore, unless the context indicates otherwise, it should be understood that a description of a single item provided in the plural may apply to the remaining plural items.

[0030] Figure 1 is a perspective view schematically showing an image sensor 100 according to an embodiment.

[0031] Figure 2 is shown corresponding to Figure 1 FIG. 1 is a layout diagram of an image sensor 100 having one pixel PX. Figure 3 It is along Figure 2 A cross-sectional view taken along line AA. Figure 4 It is along Figure 2 A cross-sectional view taken along line BB. Figure 5 yes Figure 4 An enlarged cross-sectional view of area EX1.

[0032] Reference Figures 1 to 5 , the image sensor 100 may be a stacked image sensor in which a first stack ST1 , a second stack ST2 , and a third stack ST3 are stacked in a vertical direction.

[0033] Ordinal numbers such as "first", "second", "third", etc. may be simply used as labels for specific elements, steps, etc. to distinguish these elements, steps, etc. from each other. Terms that are not described with "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, a term referred to with a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0034] The active pixel region APR may be disposed at a central portion of the image sensor 100, and a plurality of pixels PX may be disposed in the active pixel region APR. Each of the plurality of pixels PX may be a region that receives light from the outside of the image sensor 100 and converts the received light into an electrical signal. The plurality of pixels PX may be disposed in the first stack ST1 and the second stack ST2. For example, a photoelectric conversion region PD for receiving external light may be disposed in the first stack ST1, and a transistor configured to convert a pixel circuit for converting photocharges accumulated in the photoelectric conversion region PD into an electrical signal may be disposed in the second stack ST2.

[0035] The pad region PDR may be disposed on at least one side (e.g., a lateral side) of the active pixel region APR, and for example, in a plan view, the pad region PDR may be disposed on four side surfaces of the active pixel region APR. A plurality of pads PAD may be disposed in the pad region PDR and may be configured to transmit and receive electrical signals to and from an external device.

[0036] The peripheral circuit region PCR may include a logic circuit block and / or a memory device. For example, the logic circuit block may include a plurality of logic transistors LCT, and may provide a specific signal to each pixel PX of the active pixel region APR, or may control an output signal of each pixel PX. For example, the logic transistor LCT may include at least one of a row decoder, a row driver, a column decoder, a timing generator, a correlated double sampler (CDS), an analog-to-digital converter (ADC), and an input / output (I / O) buffer.

[0037] The active pixel region APR may include a plurality of pixels PX, and a plurality of photoelectric conversion regions PD may be respectively disposed in the plurality of pixels PX. In the active pixel region APR, the plurality of pixels PX may be arranged in a matrix form including a plurality of rows and a plurality of columns in a first direction X and a second direction Y, the first direction X being parallel to the upper surface of the first semiconductor substrate 110 (e.g., the back surface of the semiconductor substrate), and the second direction Y being perpendicular to the first direction X and parallel to the upper surface of the first semiconductor substrate 110. Some of the plurality of pixels PX may be optical black pixels (not shown). The optical black pixels may be used as reference pixels for the active pixel region APR, and may perform a function of automatically correcting dark signals.

[0038] As used herein, terms such as "same," "equivalent," "planar," "coplanar," "parallel," and "perpendicular" include consistency or near consistency including variations that may result, for example, from manufacturing processes. The term "substantially" may be used herein to emphasize this meaning unless the context or other description indicates otherwise.

[0039] In some embodiments, Figure 2As shown, the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 may be arranged in a matrix form. Each of the first pixel PX1 to the fourth pixel PX4 of the first stack ST1 may include a photoelectric conversion region PD and a floating diffusion region FD.

[0040] For example, the first pixel PX1 may include a first photoelectric conversion region PD1 and a first floating diffusion region FD1. The second pixel PX2 may include a second photoelectric conversion region PD2 and a second floating diffusion region FD2. The third pixel PX3 may include a third photoelectric conversion region PD3 and a third floating diffusion region FD3. The fourth pixel PX4 may include a fourth photoelectric conversion region PD4 and a fourth floating diffusion region FD4.

[0041] In some embodiments, two photoelectric conversion regions PD may be provided in one pixel PX. For example, the first pixel PX1 may include two first photoelectric conversion regions PD1. For example, the second pixel PX2 may include two second photoelectric conversion regions PD2. For example, the third pixel PX3 may include two third photoelectric conversion regions PD3. For example, the fourth pixel PX4 may include two fourth photoelectric conversion regions PD4.

[0042] The first stack ST1 may include a first semiconductor substrate 110 having a front surface 110F and a back surface 110B, a photoelectric conversion region PD and a floating diffusion region FD each formed in the first semiconductor substrate 110, a double transfer gate 150 and a first front structure FS1 each disposed on the front surface 110F of the first semiconductor substrate 110, and a color filter CF and a microlens ML each disposed on the back surface 110B of the first semiconductor substrate 110.

[0043] The second stack ST2 may include a second semiconductor substrate 120 having a front surface 120F and a back surface 120B, pixel transistors PXT and second front structures FS2 each disposed on the front surface 120F of the second semiconductor substrate 120 , and a back structure BS2 disposed on the back surface 120B of the second semiconductor substrate 120 .

[0044] The third stack ST3 may include a third semiconductor substrate 130 having a front surface 130F, and a logic transistor LCT and a third front structure FS3 each disposed on the front surface 130F of the third semiconductor substrate 130 .

[0045] The second stack member ST2 may be disposed between the first stack member ST1 and the third stack member ST3, and, for example, the second front side structure FS2 of the second stack member ST2 may be configured to face the first front side structure FS1 of the first stack member ST1, and the back side structure BS2 of the second stack member ST2 may be configured to face the third front side structure FS3 of the third stack member ST3.

[0046] In some embodiments, each of the first to third semiconductor substrates 110 to 130 may include a P-type semiconductor substrate. For example, at least one of the first to third semiconductor substrates 110 to 130 may be formed of a P-type silicon substrate and / or may include a P-type silicon substrate. In some embodiments, at least one of the first to third semiconductor substrates 110 to 130 may be formed of a P-type bulk substrate and a P-type or N-type epitaxial layer grown thereon and / or may include a P-type bulk substrate and a P-type or N-type epitaxial layer grown thereon, and in other embodiments, at least one of the first to third semiconductor substrates 110 to 130 may be formed of an N-type bulk substrate and a P-type or N-type epitaxial layer grown thereon and / or may include an N-type bulk substrate and a P-type or N-type epitaxial layer grown thereon.

[0047] The pixel isolation structure 140 may be disposed in the first semiconductor substrate 110 of the first stack ST1. A plurality of pixels PX may be defined by the pixel isolation structure 140. The pixel isolation structure 140 may include a conductive layer 142, an insulating liner 144, and an upper insulating layer 146. The conductive layer 142 may be disposed in a pixel trench 140T passing through the first semiconductor substrate 110. The insulating liner 144 may be disposed on the inner sidewall of the pixel trench 140T passing through the first semiconductor substrate 110, and may be disposed between the conductive layer 142 and the first semiconductor substrate 110 to extend upward from the front surface 110F of the first semiconductor substrate 110 to the back surface 110B of the first semiconductor substrate 110. The upper insulating layer 146 may be disposed in a portion of the pixel trench 140T adjacent to the front surface 110F of the first semiconductor substrate 110.

[0048] In some embodiments, the pixel isolation structure 140 may pass through the first semiconductor substrate 110. For example, the pixel isolation structure 140 may be a front side deep trench isolation (FDTI). Different from the illustration, the pixel isolation structure 140 may not pass through the first semiconductor substrate 110. For example, the pixel isolation structure 140 may be a back side deep trench isolation (BDTI).

[0049] In some embodiments, the conductive layer 142 may be formed of and / or may include at least one of doped polysilicon, metal, metal silicide, metal nitride, and a metal-containing layer. The insulating liner 144 may be formed of and / or may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The upper insulating layer 146 may be formed of and / or may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0050] A plurality of photoelectric conversion regions PD may be provided in the first semiconductor substrate 110 of the first stack ST1 in the plurality of pixels PX. The photoelectric conversion region PD may be a region doped with n-type impurities. For example, the photoelectric conversion region PD may have an impurity concentration difference between its upper and lower portions, and thus may have a potential gradient. Alternatively, the photoelectric conversion region PD may be formed in the form of a plurality of impurity regions stacked in a vertical direction.

[0051] like Figure 2 and Figure 4 As shown, the floating diffusion region FD may be disposed in an inner region of the first semiconductor substrate 110 adjacent to the front surface 110F of the first stack ST1. The floating diffusion region FD may be a region storing charges transferred from an adjacent photoelectric conversion region PD. In some embodiments, two photoelectric conversion regions PD are disposed in one pixel PX, and the floating diffusion region FD may be shared by the two photoelectric conversion regions PD. For example, in some embodiments, one pixel PX includes two photoelectric conversion regions PD, and the floating diffusion region FD may be a region storing charges transferred from the two photoelectric conversion regions PD of the corresponding pixel PX.

[0052] The first floating diffusion region FD1 of the first pixel PX1 may be shared by the two first photoelectric conversion regions PD1. The second floating diffusion region FD2 of the second pixel PX2 may be shared by the two second photoelectric conversion regions PD2. The third floating diffusion region FD3 of the third pixel PX3 may be shared by the two third photoelectric conversion regions PD3. The fourth floating diffusion region FD4 of the fourth pixel PX4 may be shared by the two fourth photoelectric conversion regions PD4.

[0053] The first floating diffusion region FD1 of the first pixel PX1 , the second floating diffusion region FD2 of the second pixel PX2 , the third floating diffusion region FD3 of the third pixel PX3 , and the fourth floating diffusion region FD4 of the fourth pixel PX4 may be isolated from each other by the pixel isolation structure 140 .

[0054] A ground region (not shown) may be disposed in an inner region of the first semiconductor substrate 110 adjacent to the front surface 110F of the first stack ST1 .

[0055] like Figure 2 and Figure 3As shown, the double transfer gate 150 may be disposed on the front surface 110F of the first semiconductor substrate 110 of the first stack ST1. The double transfer gate 150 may include a first portion 150_1, a second portion 150_2, and a third portion 150_3, the first portion 150_1 and the second portion 150_2 may be disposed in a transfer gate trench 150T extending from the front surface 110F of the first semiconductor substrate 110 to the inside of the first semiconductor substrate 110, and the third portion 150_3 may be disposed on the front surface 110F of the first semiconductor substrate 110. The third portion 150_3 may be surrounded by the first insulating layer 111 and the second insulating layer 112 on the front surface 110F of the first semiconductor substrate 110. The third portion 150_3 may be connected to the first portion 150_1 and the second portion 150_2, and may be provided as one body, and the third portion 150_3 may overlap at least a portion of each of the first portion 150_1 and the second portion 150_2 in the vertical direction Z.

[0056] It should be understood that when an element is referred to as being "connected" or "coupled" to another element or "located on" another element, it can be directly connected or coupled to another element or directly located on another element, or there can be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or is referred to as "contacting" or "in contact with" another element (or any form of the word "contacting"), there are no intervening elements at the point of contact.

[0057] exist Figure 3 , it is shown that the front surface 110F of the first semiconductor substrate 110 is disposed downward toward the second stack ST2, and the back surface 110B of the first semiconductor substrate 110 is disposed upward, and therefore, the third portion 150_3 may be disposed at a vertical level lower than the front surface 110F of the first semiconductor substrate 110. For example, the distance between the third portion 150_2 and the second stack ST2 in the vertical direction Z may be set to be smaller than the distance between the front surface 110F of the first semiconductor substrate 110 and the second stack ST2 in the vertical direction Z.

[0058] In detail, two double transfer gates 150 respectively corresponding to the two first photoelectric conversion regions PD1 of the first pixel PX1 may be provided. The double transfer gates 150 may be adjacent to the front surface 110F of the first semiconductor substrate 110. The two double transfer gates 150 respectively corresponding to the two first photoelectric conversion regions PD1 of the first pixel PX1 may be shared by the first floating diffusion region FD1 of the first pixel PX1.

[0059] In some embodiments, the transfer gate insulating layer 154 may be disposed on an inner wall of the transfer gate trench 150T. The transfer gate insulating layer 154 may be disposed between the double transfer gate electrode 152 and the first semiconductor substrate 110 to have a relatively uniform thickness.

[0060] In some embodiments, the spacer 156 may be disposed on a sidewall of the transfer gate electrode 152 of the third portion 150_3 of the double transfer gate 150 , and may be disposed on the front surface 110F of the first semiconductor substrate 110 .

[0061] like Figure 3 and Figure 4 As shown, the first front structure FS1 may be disposed on the front surface 110F of the first semiconductor substrate 110 of the first stack ST1. The first front structure FS1 may include a first insulating layer 111 and a second insulating layer 112 disposed on the front surface 110F of the first semiconductor substrate 110. For example, the first insulating layer 111 and the second insulating layer 112 may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride and / or may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. For example, the first insulating layer 111 may be formed of silicon oxide and / or may include silicon oxide, and the second insulating layer 112 may be formed of silicon nitride and / or may include silicon nitride. In addition, each of the first insulating layer 111 and the second insulating layer 112 may be formed in a stacked structure having a plurality of insulating layers (not shown), and an additional insulating liner (not shown) may also be disposed between two adjacent insulating layers of the plurality of insulating layers.

[0062] like Figure 4 As shown, an embedded connector 160 (e.g., an embedded conductive element) passing through the first insulating layer 111 and the second insulating layer 112 of the first front structure FS1 of the first stack ST1 and connected to the first floating diffusion region FD1 of the first pixel PX1 and the third floating diffusion region FD3 of the third pixel PX3 may be disposed in the first stack ST1.

[0063] The term "buried" may refer to a structure, pattern, and / or layer that is at least partially formed below the top surface of another structure, pattern, and / or layer. In some embodiments, when a first structure, pattern, and / or layer is "buried" in a second structure, pattern, and / or layer, the second structure, pattern, and / or layer may surround at least a portion of the first structure, pattern, and / or layer. For example, when a first structure, pattern, and / or layer is at least partially inserted into a second structure, pattern, and / or layer, the first structure, pattern, and / or layer may be considered to be buried.

[0064] For details, refer to Figure 5The buried connector 160 may pass through the first insulating layer 111 and the second insulating layer 112, and may be buried in the first semiconductor substrate 110 from the front surface 110F of the first semiconductor substrate 110. For example, the buried connector 160 may include a portion surrounded by the first insulating layer 111 and the second insulating layer 112 and a portion buried in the first semiconductor substrate 110.

[0065] In some embodiments, the first floating diffusion region FD1 of the first pixel PX1 and the third floating diffusion region FD3 of the third pixel PX3 adjacent to each other in the second horizontal direction (Y direction) may be spaced apart from each other in the second horizontal direction (Y direction) with the pixel isolation structure 140 interposed therebetween.

[0066] In some embodiments, the first floating diffusion area FD1 of the first pixel PX1 and the third floating diffusion area FD3 of the third pixel PX3 may be electrically connected to each other through the buried connection 160. In detail, each of the first floating diffusion area FD1 of the first pixel PX1 and the third floating diffusion area FD3 of the third pixel PX3 may contact and be electrically connected to the buried connection 160.

[0067] As used herein, items described as being "electrically connected" are configured so that electrical signals can be passed from one item to another. Thus, a passive conductive component (e.g., wiring, pads, internal wires, etc.) that is physically connected to a passive electrically insulating component (e.g., a prepreg material layer of a printed circuit board, an electrically insulating adhesive connecting two devices, an electrically insulating bottom fill or molded layer, etc.) is not electrically connected to the component. In addition, items that are "directly electrically connected" to each other are electrically connected through one or more passive components such as, for example, wires, pads, internal wires, feedthroughs, etc. Thus, components that are directly electrically connected do not include components that are electrically connected through active components such as transistors or diodes. Directly electrically connected elements can be directly physically connected and directly electrically connected.

[0068] In some embodiments, the buried connector 160 may overlap the pixel isolation structure 140 in the vertical direction (Z direction). For example, the buried connector 160 may include a portion buried toward a portion of the pixel isolation structure 140 adjacent to the front surface 110F of the first semiconductor substrate 110.

[0069] In some embodiments, the buried connection member 160 may include a portion overlapping the first floating diffusion area FD1 of the first pixel PX1 and the third floating diffusion area FD3 of the third pixel PX3 in the vertical direction (Z direction). The buried connection member 160 may include a portion disposed between the first floating diffusion area FD1 of the first pixel PX1 and the third floating diffusion area FD3 of the third pixel PX3. The buried connection member 160 may include a portion overlapping the first floating diffusion area FD1 of the first pixel PX1 and the third floating diffusion area FD3 of the third pixel PX3 in the second horizontal direction (Y direction).

[0070] In some embodiments, the buried connector 160 may include an upper surface 160_1 disposed in the first semiconductor substrate 110 and a lower surface 160_2 opposite to the upper surface 160_1. The first insulating layer 111 may include an upper surface 111_1 facing the front surface 110F of the first semiconductor substrate 110. The second insulating layer 112 may include a lower surface 112_1 opposite to the upper surface 111_1 of the first insulating layer 111. The upper surface 111_1 of the first insulating layer 111 may be a surface contacting the front surface 110F of the first semiconductor substrate 110. The lower surface 112_1 of the second insulating layer 112 may be a surface contacting the third insulating layer 113.

[0071] The upper surface 160_1 of the buried connector 160 may be disposed at a vertical level higher than the upper surface 111_1 of the first insulating layer 111. The upper surface 160_1 of the buried connector 160 may be disposed at a vertical level higher than the front surface 110F of the first semiconductor substrate 110. Here, disposed at a high or low vertical level may refer to disposed at a higher or lower vertical level in the +Z direction.

[0072] The lower surface 160_2 of the buried connector 160 may be disposed at a vertical level higher than or equal to the lower surface 112_1 of the second insulating layer 112. In detail, the lower surface 160_2 of the buried connector 160 may include a portion disposed at a vertical level equal to the lower surface 112_1 of the second insulating layer 112. In detail, the lower surface 160_2 of the buried connector 160 may include a portion disposed at a vertical level higher than the lower surface 112_1 of the second insulating layer 112.

[0073] In some embodiments, the lower surface 160_2 of the buried connector 160 may include a recessed portion 160_2R. In detail, the lower surface 160_2 of the buried connector 160 may be recessed toward the inside of the buried connector 160. For example, the recessed portion 160_2R of the lower surface 160_2 of the buried connector 160 may be recessed toward the upper surface 160_1 of the buried connector 160.

[0074] In some embodiments, the recessed portion 160_2R of the buried connector 160 may overlap the pixel isolation structure 140 in the vertical direction (Z direction).

[0075] Unlike the illustration, the buried connector 160 may not include the recessed portion 160_2R, and the lower surface 160_2 of the buried connector 160 may be disposed at a vertical level equal to the lower surface 112_1 of the second insulating layer 112 .

[0076] The lower surface 160_2 of the buried connector 160 may be disposed at a vertical level lower than the upper surface 111_1 of the first insulating layer 111. The lower surface 160_2 of the buried connector 160 may be disposed at a vertical level lower than the front surface 110F of the first semiconductor substrate 110. The lower surface 160_2 of the buried connector 160 may be disposed at a vertical level lower than the upper surface of the second insulating layer 112.

[0077] In some embodiments, the buried connector 160 may have an etching selectivity corresponding to each of the first insulating layer 111 and the second insulating layer 112. For example, the buried connector 160 may include a material having an etching selectivity corresponding to silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. For example, the buried connector 160 may include polysilicon and / or doped polysilicon. For example, the buried connector 160 may include a metal such as tungsten (W) and / or copper (Cu).

[0078] like Figure 2 As shown, the buried connection 160 may overlap the first floating diffusion region FD1 of the first pixel PX1, the second floating diffusion region FD2 of the second pixel PX2, the third floating diffusion region FD3 of the third pixel PX3, and the fourth floating diffusion region FD4 of the fourth pixel PX4 in the vertical direction (Z direction).

[0079] As described above, the buried connection member 160 may be connected to each of the first floating diffusion area FD1 of the first pixel PX1, the second floating diffusion area FD2 of the second pixel PX2, the third floating diffusion area FD3 of the third pixel PX3, and the fourth floating diffusion area FD4 of the fourth pixel PX4. The buried connection member 160 may contact and be electrically connected to each of the first floating diffusion area FD1 of the first pixel PX1, the second floating diffusion area FD2 of the second pixel PX2, the third floating diffusion area FD3 of the third pixel PX3, and the fourth floating diffusion area FD4 of the fourth pixel PX4.

[0080] Refer to Figure 3 and Figure 4The first front structure FS1 may include a third insulating layer 113 and a fourth insulating layer 114 disposed on the first insulating layer 111 and the second insulating layer 112. The first front structure FS1 may also include a conductive via 116 passing through the third insulating layer 113 and a wiring layer 117 and a via 119 each disposed in the fourth insulating layer 114.

[0081] In some embodiments, the contact 170 (see FIG. Figure 2 ) may be disposed on the buried connector 160 passing through the first insulating layer 111 and the second insulating layer 112. The buried connector 160 may be connected to the wiring layer 117 and the through-hole 119, each disposed in the fourth insulating layer 114, by using the contact 170. As described above, since the buried connector 160 contacts the first to fourth floating diffusion regions FD1 to FD4, the contact 170 may be connected to the first to fourth floating diffusion regions FD1 to FD4.

[0082] The second front structure FS2 may be disposed on the front surface 120F of the second semiconductor substrate 120 of the second stack ST2. The second front structure FS2 may include a first insulating layer 121 and a second insulating layer 122 disposed on the front surface 120F of the second semiconductor substrate 120. The first insulating layer 121 may cover the pixel transistor PXT disposed on the front surface 120F of the second semiconductor substrate 120. The second front structure FS2 may also include a conductive through-piece 126 passing through the first insulating layer 121 and a wiring layer 127 and a through-piece 129 each disposed in the second insulating layer 122. The conductive through-piece 126, the wiring layer 127, and the through-piece 129 may be configured to be electrically connected to the pixel transistor PXT. In some embodiments, the pixel transistor PXT may include a reset transistor RX, a select transistor SX, and a source follower transistor SFX (see Figure 6 ).

[0083] The back side structure BS2 may be disposed on the back side surface 120B of the second semiconductor substrate 120 of the second stack ST2 . The back side structure BS2 may include a third insulating layer 123 disposed on the back side surface 120B of the second semiconductor substrate 120 .

[0084] The third front structure FS3 may be disposed on the front surface 130F of the third semiconductor substrate 130 of the third stack ST3. The third front structure FS3 may include a first insulating layer 131 and a second insulating layer 132 disposed on the front surface 130F of the third semiconductor substrate 130. The first insulating layer 131 may cover the logic transistor LCT disposed on the front surface 130F of the third semiconductor substrate 130. The third front structure FS3 may also include a conductive through-piece 136 passing through the first insulating layer 131 and a wiring layer 137 and a through-piece 139 each disposed in the second insulating layer 132. The conductive through-piece 136, the wiring layer 137, and the through-piece 139 may be provided to be electrically connected to the logic transistor LCT.

[0085] In some embodiments, the conductive vias 116, 126 and 136, the wiring layers 117, 127 and 137, and the vias 119, 129 and 139 may be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), and tungsten nitride (WN) and / or may include at least one of copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), and tungsten nitride (WN).

[0086] like Figure 3 and Figure 4 As shown, the second front structure FS2 of the second stack ST2 may be set to face the first front structure FS1 of the first stack ST1. The first bonding layer BI1 may be arranged between the first front structure FS1 and the second front structure FS2. The back structure BS2 of the second stack ST2 may be set to face the third front structure FS3 of the third stack ST3. The second bonding layer BI2 may be arranged between the back structure BS1 and the third front structure FS3. Each of the first bonding layer BI1 and the second bonding layer BI2 may be formed according to a stacking structure of multiple insulating layers, for example, may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon carbonitride and / or may include at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon carbonitride.

[0087] In some embodiments, the first bonding pad BP1 may be disposed at a boundary between the first stack ST1 and the second stack ST2. The first bonding pad BP1 may be surrounded by the first bonding layer BI1. The first bonding pad BP1 may include an upper pad portion of the first stack ST1 and a lower pad portion of the second stack ST2, and the upper pad portion and the lower pad portion may be arranged to overlap each other and may be attached to each other. For example, an interface (e.g., a bonding interface) between the upper pad portion and the lower pad portion may be disposed between the first front structure FS1 and the second front structure FS2. The first bonding pad BP1 may be formed of copper and / or may include copper. For example, the first stack ST1 and the second stack ST2 may be stacked by a metal-oxide hybrid bonding process.

[0088] In some embodiments, the second bonding pad BP2 may be disposed at a boundary between the second stack ST2 and the third stack ST3. The second bonding pad BP2 may be surrounded by the second bonding layer BI2. The second stack ST2 and the third stack ST3 may be stacked by a metal-oxide hybrid bonding process. The second bonding pad BP2 may be formed of copper and / or may include copper.

[0089] According to an embodiment, an image sensor 100 including a buried connection member 160 may be provided. The buried connection member 160 may connect the floating diffusion regions FD of the pixels PX that are adjacent to each other and spaced apart from each other by the pixel isolation structure 140 therebetween. Therefore, it is not necessary to form a contact that is separately connected to each of the floating diffusion regions FD of the pixels PX that are adjacent to each other, or the number of required contacts may be reduced, and thus, the capacitance caused by the contact may be reduced. Therefore, photoelectric conversion efficiency such as conversion gain and noise may be improved. That is, according to an embodiment, an image sensor 100 with enhanced performance and reliability may be provided.

[0090] Figure 6 is an equivalent circuit diagram of the image sensor 100 according to the embodiment.

[0091] Reference Figure 6 , the plurality of pixels PX may be arranged in a matrix form. Each of the plurality of pixels PX may include a transfer transistor TX and a pixel transistor (not shown). Here, the pixel transistor may include a reset transistor RX, a select transistor SX, and a source follower transistor SFX. The reset transistor RX may include a reset gate RG, the select transistor SX may include a select gate SG, the source follower transistor SFX may include a source follower gate (not shown), and the transfer transistor TX may include a transfer gate TG. The transfer gate TG may correspond to the above reference Figures 1 to 5 A dual transfer gate 150 is depicted.

[0092] Each of the plurality of pixels PX may further include a photoelectric conversion region PD and a floating diffusion region FD. The photoelectric conversion region PD may correspond to the above reference Figures 1 to 5 The photoelectric conversion region PD described. The photoelectric conversion region PD may generate and accumulate photocharges in proportion to the amount of light incident from the outside, and may use a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), and a combination thereof.

[0093] In some embodiments, each of the plurality of pixels PX may include two photoelectric conversion regions PD, two transfer transistors TX, and one floating diffusion region FD.

[0094] The transfer gate TG may transfer the charges generated in the photoelectric conversion region PD to the floating diffusion region FD. For example, each of the two transfer gates TG of one pixel PX may transfer the charges generated in each of the two photoelectric conversion regions PD to the floating diffusion region FD. The floating diffusion region FD may accumulate and store the charges generated and transferred by the photoelectric conversion region PD. The source follower transistor SFX may be controlled based on the amount of photocharge accumulated in the floating diffusion region FD.

[0095] The reset transistor RX may periodically reset the charge accumulated in the floating diffusion area FD. The drain electrode of the reset transistor RX may be connected to the floating diffusion area FD, and the source electrode may be connected to a source voltage V DD When the reset transistor RX is turned on, the source voltage V connected to the source electrode of the reset transistor RX DD The electric charge accumulated in the floating diffusion area FD may be discharged when the reset transistor RX is turned on, and thus, the floating diffusion area FD may be reset.

[0096] The source follower transistor SFX may be connected to a current source (not shown) provided outside the plurality of pixels PX to function as a source follower buffer amplifier, and may use a potential change in the floating diffusion region FD to output an amplified voltage to an output line V OUT .

[0097] The selection transistor SX can select a plurality of pixels PX in a row unit, and when the selection transistor SX is turned on, the source voltage V DD It can be transferred to the source electrode of the source follower transistor SFX.

[0098] Figures 7 to 9 1 is a layout diagram showing image sensors 101, 102 and 103 according to an embodiment. Figures 1 to 5 The differences in image sensor 100 are described.

[0099] Reference Figure 7, the image sensor 101 may include a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4. Figures 1 to 5 Similar to the described image sensor 100 , each of the first pixel PX1 , the second pixel PX2 , the third pixel PX3 , and the fourth pixel PX4 of the image sensor 101 may include two photoelectric conversion regions PD, and the two photoelectric conversion regions PD may share one floating diffusion region FD.

[0100] In some embodiments, the first buried connection 161_1 may be disposed to overlap the first floating diffusion region FD1 of the first pixel PX1 and the third floating diffusion region FD3 of the third pixel PX3, which are adjacent to each other in the second horizontal direction (Y direction), in the vertical direction (Z direction). Similarly, the second buried connection 161_2 may be disposed to overlap the second floating diffusion region FD2 of the second pixel PX2 and the fourth floating diffusion region FD4 of the fourth pixel PX4, which are adjacent to each other in the second horizontal direction (Y direction), in the vertical direction (Z direction).

[0101] The first buried connection 161_1 may be connected to the first and third floating diffusion areas FD1 and FD3. The first buried connection 161_1 may contact the first and third floating diffusion areas FD1 and FD3.

[0102] The second buried connection 161_2 may be connected to the second floating diffusion area FD2 and the fourth floating diffusion area FD4. The second buried connection 161_2 may contact the second floating diffusion area FD2 and the fourth floating diffusion area FD4.

[0103] and Figure 1 Unlike the image sensor 100 including all of the buried connectors 160 connected to the first to fourth floating diffusion areas FD1 to FD4, the image sensor 101 may include two buried connectors (ie, a first buried connector 161_1 and a second buried connector 161_2) respectively connected to two floating diffusion areas FD.

[0104] The first contact 171_1 may be disposed on the first buried connection 161_1. The first contact 171_1 may be connected to the first floating diffusion area FD1 and the third floating diffusion area FD3 through the first buried connection 161_1. The second contact 171_2 may be disposed on the second buried connection 161_2. The second contact 171_2 may be connected to the second floating diffusion area FD2 and the fourth floating diffusion area FD4 through the second buried connection 161_2.

[0105] Reference Figure 8 , the image sensor 102 may include a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4. Figures 1 to 6 Unlike the described image sensor 100 , each of the first pixel PX1 , the second pixel PX2 , the third pixel PX3 , and the fourth pixel PX4 of the image sensor 102 may include one photoelectric conversion region PD and one floating diffusion region FD.

[0106] In some embodiments, the buried connection member 162 can be configured to overlap with the first floating diffusion area FD1 of the first pixel PX1, the second floating diffusion area FD2 of the second pixel PX2, the third floating diffusion area FD3 of the third pixel PX3 and the fourth floating diffusion area FD4 of the fourth pixel PX4 in the vertical direction (Z direction).

[0107] The buried connector 162 may be connected to the first to fourth floating diffusion areas FD1 to FD4. The buried connector 162 may contact the first to fourth floating diffusion areas FD1 to FD4.

[0108] The contact 172 may be disposed on the buried connection 162. The contact 172 may be connected to the first to fourth floating diffusion areas FD1 to FD4 through the buried connection 162.

[0109] Reference Fig. 9 The image sensor 103 may include a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4. Each of the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 of the image sensor 103 may include a photoelectric conversion region PD and a floating diffusion region FD.

[0110] In some embodiments, the first buried connection 163_1 may be disposed to overlap the first floating diffusion region FD1 of the first pixel PX1 and the third floating diffusion region FD3 of the third pixel PX3, which are adjacent to each other in the second horizontal direction (Y direction), in the vertical direction (Z direction). Similarly, the second buried connection 163_2 may be disposed to overlap the second floating diffusion region FD2 of the second pixel PX2 and the fourth floating diffusion region FD4 of the fourth pixel PX4, which are adjacent to each other in the second horizontal direction (Y direction), in the vertical direction (Z direction).

[0111] The first buried connection 163_1 may be connected to the first and third floating diffusion areas FD1 and FD3. The first buried connection 163_1 may contact the first and third floating diffusion areas FD1 and FD3.

[0112] The second buried connection 163_2 may be connected to the second floating diffusion area FD2 and the fourth floating diffusion area FD4. The second buried connection 163_2 may contact the second floating diffusion area FD2 and the fourth floating diffusion area FD4.

[0113] The first contact 173_1 may be disposed on the first buried connection 163_1. The first contact 173_1 may be connected to the first floating diffusion area FD1 and the third floating diffusion area FD3 through the first buried connection 163_1. The second contact 173_2 may be disposed on the second buried connection 163_2. The second contact 173_2 may be connected to the second floating diffusion area FD2 and the fourth floating diffusion area FD4 through the second buried connection 163_2.

[0114] Fig.10 is a perspective view schematically showing an image sensor 200 according to an embodiment. Fig.11 It is along Fig.10 The following is a cross-sectional view taken along the line CC of FIG. Figures 1 to 5 The differences in image sensor 100 are described.

[0115] Reference Fig.10 and Fig.11 , the image sensor 200 may be a stacked image sensor in which the first stack ST21 and the second stack ST22 are stacked in a vertical direction.

[0116] In some embodiments, a plurality of pixels PX, a photoelectric conversion region PD, and a plurality of pixel transistors may be disposed in the first stack ST21. The peripheral circuit region PCR may be disposed in the second stack ST22 and may include a logic circuit block and / or a memory device. For example, the logic circuit block may include a plurality of logic transistors LCT.

[0117] The first stack ST21 may include a first semiconductor substrate 210, a first front side structure FS21 disposed on a first surface 210F of the first semiconductor substrate 210, and a color filter CF and a microlens ML each disposed on a second surface 210B of the first semiconductor substrate 210. The second stack ST22 may include a second semiconductor substrate 220 and a second front side structure FS22 disposed on a first surface 220F of the second semiconductor substrate 220.

[0118] For example, the second front-side structure FS22 of the second stack ST22 may be disposed to face and contact the first front-side structure FS21 of the first stack ST21 .

[0119] In some embodiments, the first front side structure FS21 may include a first insulating layer 211 and a second insulating layer 212 disposed on the first surface 210F of the first semiconductor substrate 210 .

[0120] The first front-side structure FS21 may include a third insulating layer 213 and a fourth insulating layer 214 disposed on the first insulating layer 211 and the second insulating layer 212. The first front-side structure FS21 may further include a wiring layer 217 disposed in the fourth insulating layer 214.

[0121] The second front side structure FS22 may include a first insulating layer 221 and a second insulating layer 222 disposed on the first surface 220F of the second semiconductor substrate 220. The first insulating layer 221 may cover the logic transistor LCT disposed on the first surface 220F of the second semiconductor substrate 220. The second front side structure FS22 may also include a conductive via 226 passing through the first insulating layer 221 and a wiring layer 227 disposed in the second insulating layer 222. The conductive via 226 and the wiring layer 227 may be provided to be electrically connected to the logic transistor LCT.

[0122] In the first and second stacks ST21 and ST22 , the first and second front structures FS21 and FS22 may be disposed to face each other, for example, the fourth insulating layer 214 of the first front structure FS21 may be disposed to contact the second insulating layer 222 of the second front structure FS22 .

[0123] The pixel isolation structure 240 may be disposed in the first semiconductor substrate 210 of the first stack ST21. A plurality of pixels PX may be defined by the pixel isolation structure 240. The pixel isolation structure 240 may include a conductive layer 242, an insulating liner 244, and an upper insulating layer 246.

[0124] A plurality of photoelectric conversion regions (not shown) may be respectively disposed in the first stack ST21 of the plurality of pixels PX. For example, one or more photoelectric conversion regions may be disposed in each pixel PX.

[0125] The floating diffusion region FD may be disposed in an inner region of the first semiconductor substrate 110 adjacent to the first surface 210F of the first stack ST21. The floating diffusion regions FD disposed in a plurality of adjacent pixels PX may be separated from each other by a pixel isolation structure 240 therebetween.

[0126] In some embodiments, the buried connector 260 may pass through the first insulating layer 211 and the second insulating layer 212, and may be connected to the floating diffusion region FD disposed in a plurality of adjacent pixels PX. For example, the buried connector 260 may be connected to the floating diffusion region FD of each of the plurality of pixels PX adjacent to each other in the first horizontal direction (X direction) and / or the second horizontal direction (Y direction). The buried connector 260 may overlap the pixel isolation structure 240 in the vertical direction (Z direction). The description of the buried connector 260 may refer to the above reference. Figures 1 to 5 The embedded connector 160 is described.

[0127] Figures 12 to 16 is a cross-sectional view showing a method of manufacturing the image sensor 100 according to an embodiment. In detail, Figures 12 to 16 corresponds to along Figure 2 A cross-sectional view of a section taken along line BB.

[0128] Reference Fig.12 , a pixel isolation structure 140 and floating diffusion regions FD1 and FD3 may be formed in the first semiconductor substrate 110. Next, a first insulating layer 111 and a second insulating layer 112 may be formed on the front surface 110F of the first semiconductor substrate 110. When the front surface 110F of the first semiconductor substrate 110 is set upward, the first insulating layer 111 and the second insulating layer 112 may be formed on the front surface 110F of the first semiconductor substrate 110.

[0129] Next, a hard mask layer HM may be formed on the first insulating layer 111 and the second insulating layer 112. In some embodiments, the hard mask layer HM may be a layer used in a previous process. For example, the hard mask layer HM may be reused without being newly formed after performing the previous process.

[0130] Reference Fig.13 , a photomask layer (not shown) may be formed on the hard mask layer HM, and a buried connector trench 160T may be formed by patterning the hard mask layer HM, the first insulating layer 111, and the second insulating layer 112. The buried connector trench 160T may be formed by etching a portion of each of the floating diffusion regions FD1 and FD3 of the hard mask layer HM, the first insulating layer 111, the second insulating layer 112, and the first semiconductor substrate 110. A portion of each of the floating diffusion regions FD1 and FD3 may be exposed through the buried connector trench 160T.

[0131] In some embodiments, a portion of the pixel isolation structure 140 may be etched together. Next, the hard mask layer HM may be removed.

[0132] Reference Fig.14 , a buried connector layer 160L may be formed in the buried connector trench 160T and on the first insulating layer 111 and the second insulating layer 112. In some embodiments, a portion of the buried connector layer 160L overlapping the buried connector trench 160T in the vertical direction (Z direction) may have a shape that is recessed toward the front surface 110F of the first semiconductor substrate 110.

[0133] Reference Fig.15, the buried connector 160 may be formed by removing a portion of the buried connector layer 160L formed on the first insulating layer 111 and the second insulating layer 112. In detail, the process of removing a portion of the buried connector layer 160L may be performed by using a chemical mechanical polishing (CMP) process. The process of performing the CMP process may include a process of stopping the CMP process when the first insulating layer 111 and the second insulating layer 112 are exposed during the removal of the buried connector layer 160L. Therefore, the lower surface 160_2 (see Figure 5 ) may be disposed at a level higher than or equal to the lower surface 112_1 of the second insulating layer 112 (see Figure 5 ) at a vertical level (i.e., a higher vertical level in the +Z direction).

[0134] In some other embodiments, the process of removing a portion of the buried connector layer 160L may be performed by utilizing an etch-back process.

[0135] Reference Fig.16 A third insulating layer 113 may be formed on the buried connector 160 and the second insulating layer 112, and a wiring layer 117, a via 119, and a fourth insulating layer 114 surrounding the wiring layer 117 and the via 119 may be formed on the third insulating layer 113. Next, a first bonding layer BI1 and a first bonding pad BP1 may be formed.

[0136] Then, the above reference can be formed by performing the post-process Figures 1 to 6 An image sensor 100 is described.

[0137] Based on the above reference Figures 12 to 16 The method of manufacturing the image sensor 100 described above can manufacture the buried connector 160 according to the embodiment by using the hard mask layer HM used in the previous process. Therefore, the image sensor 100 having a simplified manufacturing process can be provided.

[0138] Fig.17 is a block diagram showing a configuration of an image sensor 1100 according to an embodiment.

[0139] Reference Fig.17 , the image sensor 1100 may include a pixel array 1110, a controller 1130, a row driver 1120, and a pixel signal processor 1140. The image sensor 1100 may include the above reference Figures 1 to 11 At least one of the image sensors 100, 101, 102, 103, and 200 described.

[0140] The pixel array 1110 may include a plurality of unit pixels arranged in two dimensions, and each unit pixel may include a photoelectric conversion element. The photoelectric conversion element may absorb light to generate charges, and an electrical signal (output voltage) based on the generated charges may be provided to the pixel signal processor 1140 through a vertical signal line. The unit pixels included in the pixel array 1110 may provide an output voltage in a row unit at a time, so a row of unit pixels of the pixel array 1110 may be simultaneously activated by a selection signal output from the row driver 1120. The unit pixels of the selected row may output an output voltage based on the absorbed light to an output line of the corresponding column.

[0141] The controller 1130 may allow the pixel array 1110 to absorb light and accumulate charges, or may control the row driver 1120 to temporarily store the accumulated charges and output an electrical signal based on the stored charges to the outside of the pixel array 1110. In addition, the controller 1130 may control the pixel signal processor 1140 to measure an output voltage provided by the pixel array 1110.

[0142] The pixel signal processor 1140 may include a CDS 1142, an ADC 1144, and a buffer 1146. The CDS 1142 may sample and hold an output voltage provided by the pixel array 1110. The CDS 1142 may double sample a specific noise level and a level based on the generated output voltage to output a level corresponding to the difference therebetween. In addition, the CDS 1142 may receive a ramp signal generated by a ramp signal generator 1148, and may compare the ramp signals to output a comparison result.

[0143] The ADC 1144 may convert an analog signal corresponding to a level received from the CDS 1142 into a digital signal. The buffer 1146 may latch the digital signal, and the latched digital signal may be sequentially output to the outside of the image sensor 1100 and may be transferred to an image processor (not shown).

[0144] In the above, specific embodiments have been described in the drawings and the specification. The embodiments described herein are only used to describe the inventive concept, and the description of any specific embodiment should not be used to limit the meaning or limit the scope of the inventive concept defined in the appended claims. Therefore, it will be appreciated by those of ordinary skill in the art that various modifications and other equivalent embodiments can be implemented from the inventive concept. Therefore, the spirit and scope of the inventive concept can be defined based on the spirit and scope of the appended claims.

[0145] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: a substrate comprising a front surface and a back surface opposite to the front surface; A first pixel is disposed in the substrate, wherein the first pixel includes a first photoelectric conversion region; a second pixel disposed adjacent to the first pixel in a first horizontal direction in the substrate, the second pixel comprising a second photoelectric conversion region, wherein the first horizontal direction is a direction parallel to a front surface of the substrate; a pixel isolation structure disposed between the first pixel and the second pixel, the pixel isolation structure extending in a vertical direction in the substrate and surrounding each of the first pixel and the second pixel, wherein the vertical direction is a direction perpendicular to a front surface of the substrate; a first floating diffusion region disposed adjacent to a front surface of the substrate in the first pixel; a second floating diffusion region disposed adjacent to a front surface of the substrate in the second pixel; an insulating layer disposed on the front surface of the substrate; and a first buried connection member passing through the insulating layer and connected to the first floating diffusion region and the second floating diffusion region, wherein the first buried connector comprises a lower surface and an upper surface disposed in the substrate, The upper surface of the first buried connector is disposed at a higher vertical level than the upper surface of the insulating layer, and The lower surface of the first buried connector is disposed at a vertical level higher than or equal to a lower surface of the insulating layer.

2. The image sensor according to claim 1, wherein: The first floating diffusion region and the second floating diffusion region are spaced apart from each other in the first horizontal direction, and the pixel isolation structure is interposed between the first floating diffusion region and the second floating diffusion region.

3. The image sensor according to claim 2, wherein: The first buried connection contacts the first floating diffusion region and the second floating diffusion region, and The first floating diffusion region and the second floating diffusion region are electrically connected to each other through the first buried connection.

4. The image sensor according to claim 1, wherein: A lower surface of the first buried connector is disposed at a lower vertical level than an upper surface of the insulating layer.

5. The image sensor according to claim 1, wherein: The first buried connector includes a material having an etching selectivity with respect to the insulating layer.

6. The image sensor according to claim 5, wherein: The first buried connector includes polysilicon.

7. The image sensor according to claim 1, wherein: The lower surface of the first buried connector includes a portion recessed toward the inside of the first buried connector.

8. The image sensor according to claim 1, wherein: The first buried connection includes a portion overlapping the pixel isolation structure between the first pixel and the second pixel in the vertical direction.

9. The image sensor according to claim 1, further comprising: a third pixel disposed adjacent to the first pixel in the substrate in a second horizontal direction intersecting the first horizontal direction, the third pixel including a third photoelectric conversion region; a fourth pixel disposed adjacent to the second pixel in the substrate in the second horizontal direction, the fourth pixel including a fourth photoelectric conversion region; a third floating diffusion region disposed adjacent to the front surface of the substrate in the third pixel; as well as a fourth floating diffusion region disposed adjacent to the front surface of the substrate in the fourth pixel, Wherein, the first buried connection is also connected to the third floating diffusion area and the fourth floating diffusion area.

10. The image sensor according to claim 1, further comprising: a third pixel disposed adjacent to the first pixel in the substrate in a second horizontal direction intersecting the first horizontal direction, the third pixel including a third photoelectric conversion region; a fourth pixel disposed adjacent to the second pixel in the substrate in the second horizontal direction, the fourth pixel including a fourth photoelectric conversion region; a third floating diffusion region disposed adjacent to the front surface of the substrate in the third pixel; a fourth floating diffusion region disposed adjacent to the front surface of the substrate in the fourth pixel; as well as A second buried connector passes through the insulating layer and contacts the third floating diffusion region and the fourth floating diffusion region.

11. An image sensor, comprising: a substrate comprising a front surface and a back surface opposite to the front surface; A first pixel is disposed in the substrate, wherein the first pixel includes a first photoelectric conversion region; a second pixel disposed adjacent to the first pixel in a first horizontal direction in the substrate, the second pixel comprising a second photoelectric conversion region, wherein the first horizontal direction is a direction parallel to a front surface of the substrate; a pixel isolation structure disposed between the first pixel and the second pixel, the pixel isolation structure extending in a vertical direction in the substrate and surrounding each of the first pixel and the second pixel, wherein the vertical direction is a direction perpendicular to a front surface of the substrate; a first floating diffusion region disposed adjacent to a front surface of the substrate in the first pixel; a second floating diffusion region disposed adjacent to a front surface of the substrate in the second pixel; an insulating layer disposed on the front surface of the substrate; and a buried connection member that passes through the insulating layer and is connected to the first floating diffusion region and the second floating diffusion region, wherein the uppermost portion of the lower surface of the embedded connector is disposed at a vertical level higher than or equal to the lower surface of the insulating layer, and An upper surface of the buried connector is disposed at a higher vertical level than a front surface of the substrate.

12. The image sensor according to claim 11, wherein: The buried connector contacts each of the first floating diffusion area and the second floating diffusion area between the first floating diffusion area and the second floating diffusion area.

13. The image sensor according to claim 11, wherein: The buried connection includes portions respectively overlapping the first floating diffusion region and the second floating diffusion region in the vertical direction.

14. The image sensor according to claim 11, wherein: The lower surface of the buried connector is disposed at a lower vertical level than the upper surface of the insulating layer.

15. The image sensor according to claim 11, wherein: The buried connector includes a material having an etching selectivity with respect to the insulating layer.

16. The image sensor according to claim 15, wherein: The buried connector includes polysilicon.

17. The image sensor according to claim 15, wherein: The insulating layer includes silicon nitride.

18. The image sensor according to claim 11, wherein: The buried connector includes a portion buried in the substrate.

19. An image sensor, comprising: a substrate comprising a front surface and a back surface opposite to the front surface; A first pixel is disposed in the substrate, wherein the first pixel includes a plurality of first photoelectric conversion regions; a second pixel disposed adjacent to the first pixel in a first horizontal direction in the substrate, the second pixel comprising a plurality of second photoelectric conversion regions, wherein the first horizontal direction is a direction parallel to a front surface of the substrate; a third pixel disposed adjacent to the first pixel in the substrate in a second horizontal direction intersecting the first horizontal direction, the third pixel including a plurality of third photoelectric conversion regions; a fourth pixel disposed adjacent to the second pixel in the substrate in the second horizontal direction, the fourth pixel including a plurality of fourth photoelectric conversion regions; a pixel isolation structure extending in a vertical direction in the substrate, surrounding each of the first pixel, the second pixel, the third pixel, and the fourth pixel, and extending in the first horizontal direction and the second horizontal direction, wherein the vertical direction is a direction perpendicular to a front surface of the substrate; a first floating diffusion region disposed adjacent to the front surface of the substrate in the first pixel and shared by the plurality of first photoelectric conversion regions; a second floating diffusion region disposed adjacent to the front surface of the substrate in the second pixel and shared by the plurality of second photoelectric conversion regions; a third floating diffusion region disposed adjacent to the front surface of the substrate in the third pixel and shared by the plurality of third photoelectric conversion regions; a fourth floating diffusion region disposed adjacent to the front surface of the substrate in the fourth pixel and shared by the plurality of fourth photoelectric conversion regions; an insulating layer disposed on the front surface of the substrate; a buried connector that contacts the first floating diffusion region to the fourth floating diffusion region and includes a portion that passes through the insulating layer and is buried in the substrate; and a color filter and a lens, each of which is disposed on a back surface of the substrate, wherein the buried connector comprises a material having an etching selectivity relative to the insulating layer, The uppermost portion of the lower surface of the buried connector is disposed at a vertical level higher than or equal to the lower surface of the insulating layer, and An upper surface of the buried connector is disposed at a higher vertical level than a front surface of the substrate.

20. The image sensor according to claim 19, wherein: The insulating layer includes silicon nitride, and The buried connector includes polysilicon.

Images