Semiconductor epitaxial layer, micro light-emitting diode chip and manufacturing method of micro light-emitting diode chip

Abstract

The invention discloses a semiconductor epitaxial layer, which comprises a plurality of layers of Gax I < n > 1-x P and a GaP layer, the GaP layer is positioned and contacted with the surface of the plurality of layers of Gax I < n > 1-x P, the value of x in at least some layers of Gax I < n > 1-x P is gradually increased from bottom to top, and x is a positive number. The GaXI n1-XP component gradient growth is introduced to replace the original Al Ga I nP growth, so that the mismatch caused by lattice constants among materials is relieved, the GaP current expansion layer with better quality can be obtained, the uniform expansion of P-surface current is facilitated, and the excellent photoelectric property is obtained.

Description

Technical Field

[0001] The present invention relates to the field of LED technology, and in particular to a semiconductor epitaxial layer, a micro light emitting diode chip and a manufacturing method thereof. Background Art

[0002] Infrared light-emitting diodes are usually made of PN junctions made of materials with high infrared radiation efficiency (GaAs). They are an important light-emitting device and are widely used in various photoelectric switches, remote control transmission circuits, vehicle sensors and other fields. Infrared light-emitting diode epitaxial wafers are the basic structure for preparing infrared light-emitting diodes. Figure 1 As shown, from bottom to top, it includes: substrate 001, first semiconductor layer 002, light emitting layer 003, second semiconductor layer 004, and current spreading layer 005. The substrate 001 may be made of GaAs material, for example, and the N-type and second semiconductor layers are usually made of AlGaInP material. GaP material has high electrical conductivity and high light transmittance, which is conducive to ohmic contact and light extraction, so the current spreading layer is mostly made of GaP material.

[0003] However, the lattice constant of GaP is Its AlGaInP The lattice mismatch is about 3.6%. This lattice size mismatched growth greatly increases the misfit dislocations in the current spreading layer, such as Figure 1 As shown, the lines in the current spreading layer 005 represent the mismatch dislocation conditions. It can be seen that some mismatch dislocations may even run through the entire current spreading layer, affecting the quality of the current spreading layer, and further affecting the overall ESD resistance of the infrared light-emitting diode. In order to improve the quality of GaP junctions, some existing products, for example, use a composition gradient method. Specifically, a multi-layer P-type AlGaInP transition layer is formed, in which the Al component in each layer of AlGaInP gradually increases, while the Ga component gradually decreases, thereby reducing the lattice constant difference between the materials. However, Al x Ga 1-x InP belongs to the III-III'-III"-V type quaternary solid solution, which contains Al. Therefore, the growth of AlGaInP needs to overcome the contamination of O and C caused by Al. At the same time, Al x Ga 1-x The oxygen content of InP increases with the increase of x, and the oxygen concentration rises sharply when x>0.4. For AlGaInP materials, although increasing the growth temperature is beneficial to suppress the incorporation of oxygen impurities, the temperature increase will cause the re-evaporation of In and is not conducive to the incorporation of p-type impurities, making the growth window of AlGaInP materials narrower, which is not conducive to mass production control. Summary of the invention

[0004] In view of some or all of the problems in the prior art, the present invention provides a semiconductor epitaxial layer in a first aspect, comprising:

[0005] Multilayer Ga x In 1-x P, where at least some layers of Ga x In 1-x The value of x in P increases gradually from bottom to top, and x is a positive number; and

[0006] A GaP layer located on and contacting the multilayer Ga x In 1-x The surface of P.

[0007] Furthermore, the Ga x In 1-x The value of x in P ranges from 50% to 90%.

[0008] Furthermore, at least some Ga x In 1-x The value of x in the P layer increases linearly or arithmetically from bottom to top.

[0009] Furthermore, the multilayer Ga x In 1-x The x value of the top layer in the P layer is 90%.

[0010] Furthermore, each layer of Ga x In 1-x P also includes impurity elements.

[0011] Furthermore, the impurity elements include one or more of the following elements: Be, Mg, Zn, Cd, and C.

[0012] Furthermore, the doping concentration of the impurity element is 0.5e18 to 5e18.

[0013] Furthermore, at least some Ga x In 1-x The thickness of the P layer is the same.

[0014] Furthermore, at least some Ga x In 1-x The thickness of P is 5 nm to 400 nm.

[0015] Furthermore, the multilayer Ga x In 1-x The number of layers of P is 3 or more.

[0016] Based on the semiconductor epitaxial layer as described above, the second aspect of the present invention provides a micro light emitting diode chip, which includes a plurality of micro light emitting mesas, wherein the plurality of micro light emitting mesas form an array, and each micro light emitting mesas includes:

[0017] substrate;

[0018] A first semiconductor layer, which is disposed on the substrate;

[0019] a light-emitting layer, disposed on the first semiconductor layer;

[0020] A second semiconductor layer, which is disposed on the light-emitting layer and includes the semiconductor epitaxial layer as described above, and the first semiconductor layer and the second semiconductor layer have different conductivity types; and

[0021] A top conductive layer is disposed on the second semiconductor layer.

[0022] Furthermore, the material of the substrate includes GaAs.

[0023] Furthermore, the material of the first semiconductor layer includes AlGaInP.

[0024] Furthermore, the material of the top conductive layer includes a transparent conductive material.

[0025] Furthermore, the light-emitting layer is a quantum well structure (QW, QuantumWell).

[0026] Furthermore, the light-emitting layer is a multiple quantum well structure (MQW, Multiple Quantum Well), including a plurality of quantum well layers (Well) and a plurality of quantum barrier layers (Barrier) alternately arranged in a repeated manner.

[0027] Furthermore, the first semiconductor layer is of P type, and the second semiconductor layer is of N type.

[0028] Furthermore, the first semiconductor layer is of N type, and the second semiconductor layer is of P type.

[0029] Furthermore, the micro light emitting diode chip further includes a passivation layer, and the passivation layer at least covers the side wall of the micro light emitting mesa.

[0030] Furthermore, the substrate includes a pixel driving circuit.

[0031] Furthermore, the top conductive layer continuously covers the top of the array formed by the micro-luminescent mesas.

[0032] Furthermore, the bottom of the micro-luminescent mesa is electrically connected to the substrate via a metal structure.

[0033] Furthermore, the metal structure is a metal layer or a first metal hole; an array of second metal holes is arranged on the surface of the substrate, and each of the second metal holes is electrically connected to each of the metal layers or each of the first metal holes.

[0034] Furthermore, the material of the metal structure is an alloy of one or more of the following metals: Ni, Al, Ti, Ni, Pt, Au.

[0035] Furthermore, the material of the metal hole is an alloy of one or more of the following metals: Ni, Al, Ti, Ni, Pt, Au.

[0036] Furthermore, the micro-LED chip also includes a micro-lens structure, which is arranged on the micro-light-emitting mesa, wherein the micro-lens structure includes a lens array composed of a plurality of micro-lenses, and the lens array is arranged above the array area formed by the light-emitting mesa.

[0037] The third aspect of the present invention provides a method for manufacturing the micro-LED chip as described above, wherein the formation of the micro-light-emitting mesa comprises:

[0038] providing a substrate;

[0039] growing a first semiconductor layer on the substrate;

[0040] growing a light emitting layer on the first semiconductor layer;

[0041] A second semiconductor layer is grown on the light emitting layer, wherein the second semiconductor layer comprises a multilayer Ga x In 1-x P, and each layer of Ga x In 1-x The Ga and In compositions in P are different; and

[0042] A top conductive layer is grown on the second semiconductor layer.

[0043] Furthermore, the second semiconductor layer is formed at a temperature of 630 degrees Celsius to 680 degrees Celsius.

[0044] Furthermore, the second semiconductor layer is generated at a pressure of 30 mbar to 200 mbar.

[0045] The semiconductor epitaxial layer provided by the present invention is characterized by introducing Ga X In 1-X The P component grows in a gradual manner, replacing the original AlGaInP growth, which alleviates the mismatch caused by the lattice constant between materials, and is conducive to obtaining a better quality GaP current expansion layer, which is conducive to the uniform expansion of the P-side current, thereby obtaining excellent optoelectronic performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0047] Figure 1 A schematic diagram showing the structure of a semiconductor epitaxial layer in the prior art is shown;

[0048] Figure 2 A schematic diagram showing the structure of a semiconductor epitaxial layer according to an embodiment of the present invention;

[0049] Figures 3A to 3C The multilayer Ga of the semiconductor epitaxial layer of different embodiments of the present invention are shown respectively. x In 1-x Schematic diagram of the structure of P;

[0050] Figure 4 A schematic structural diagram of a micro light emitting diode chip according to an embodiment of the present invention is shown;

[0051] Figure 5 A schematic diagram showing a process of manufacturing a micro-luminescent mesa according to an embodiment of the present invention; and

[0052] Figures 6A to 6E A schematic diagram showing a process of manufacturing a micro-luminescent mesa according to an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments can be implemented without one or more specific details or with other replacement and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the inventive point of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn in correct proportions.

[0054] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0055] It should be noted that the embodiments of the present invention describe the process steps in a specific order, but this is only for the purpose of illustrating the specific embodiment, rather than limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0056] In the present invention, the term "from bottom to top" refers to from the first epitaxially grown layer to the last epitaxially grown layer in the order of epitaxial growth, or from the substrate to the top epitaxial layer.

[0057] In the AlGaInP series red LED, the final growth ends with GaP growth, but the lattice mismatch between GaP and AlGaInP is about 3.6%, which greatly increases the mismatch dislocations in the GaP epitaxial layer. To solve this problem, the present invention starts from the perspective of slowly reducing the lattice size, and before growing GaP, GaP is grown. X In 1-X The Ga component of P grows in a gradual manner and transitions to growing GaP, which effectively buffers the material mismatch growth caused by the difference in lattice size and is beneficial to reducing misfit dislocations within GaP.

[0058] The technical solution of the present invention is further described below in conjunction with the accompanying drawings of the embodiments.

[0059] Figure 2 FIG. 1 is a schematic diagram showing the structure of a semiconductor epitaxial layer according to an embodiment of the present invention. Figure 2 As shown, a semiconductor epitaxial layer includes multiple layers of Ga X In 1-X P201 and GaP layer 202, wherein the GaP layer is arranged on a multi-layer Ga x In 1-x P surface, and the multilayer Ga x In 1-x As mentioned above, each layer of Ga x In 1-x The Ga and In components in P are different. Specifically, each layer of Ga x In 1-x The value of x in P increases gradually from bottom to top, where x is a positive number, and each layer of Ga x In 1-x The Ga component in P gradually increases, while the In component gradually decreases.

[0060] In one embodiment of the present invention, the value range of x is 50% to 90%. In one embodiment of the present invention, from bottom to top, the Ga component in each layer of material increases layer by layer, while the In component decreases layer by layer, that is, the multilayer Ga x In 1-xThe value of x in P increases layer by layer. In one embodiment of the present invention, each layer of Ga x In 1-x The element composition of the P material remains unchanged. In other embodiments of the present invention, at least one layer of Ga x In 1-x P, the composition of the elements in the material has a gradual change. Specifically, in one embodiment of the present invention, from bottom to top, the multilayer Ga x In 1-x The values ​​of x in material P increase in arithmetic progression. Figure 3A and 3B As shown, the multilayer Ga x In 1-x For example, P may include 5 layers, and from bottom to top, the values ​​of x in each layer are 50%, 60%, 70%, 80% and 90% respectively ( Figure 3A ). The multilayer Ga x In 1-x For example, P may include three layers, and from bottom to top, the values ​​of x in each layer are 50%, 70%, and 90% respectively ( Figure 3B ). It should be understood that in some other embodiments of the present invention, the multilayer Ga x In 1-x The number of layers of P is not limited to 3 or 5, but other values ​​may be used. Similarly, the value of x in each layer of material may be increased arithmetic or asymptotically, which will not be described in detail here. Figure 3C As shown, in one embodiment of the present invention, the multilayer Ga x In 1-x In P, the value of x of at least one layer of material increases from bottom to top, for example, linearly. Specifically, Figure 3C As shown, in the second layer Ga x In 1-x In P, the value of x gradually changes from 50% to 70%, and in the fourth layer Ga x In 1-x In P, the value of x changes gradually from 70% to 90%. It should be understood that in some other embodiments of the present invention, the composition gradient layers are not limited to 2 layers, and may be more or less, and the composition gradient may be, for example, in a linear gradient manner or other manners.

[0061] In one embodiment of the present invention, each layer of Ga x In 1-x The thickness of P can be the same or different, but the thickness of each layer should be in the range of 5 nm to 400 nm.

[0062] In one embodiment of the present invention, the multilayer Ga x In 1-xP includes impurity elements, wherein the impurity elements include one or more of the following elements: Be, Mg, Zn, Cd, and C. In one embodiment of the present invention, the doping concentration of the impurity elements is 0.5e18 to 5e18.

[0063] In one embodiment of the present invention, the thickness of the GaP layer 202 is between 0.02 and 0.1 um, and the GaP layer is a highly doped layer with a doping concentration greater than 1e19.

[0064] Based on the semiconductor epitaxial layer as described above, the present invention further provides a light-emitting element, such as an infrared light-emitting diode, a micro infrared light-emitting diode, etc., wherein the light-emitting element comprises the semiconductor epitaxial layer as described above. The light-emitting element can further form a light-emitting diode chip or a micro light-emitting diode chip.

[0065] Based on the semiconductor epitaxial layer as described above, Figure 4 A schematic diagram showing the structure of a micro light emitting diode chip according to an embodiment of the present invention is shown in FIG. Figure 4 As shown, a micro-LED chip includes a substrate 401 and an array of a plurality of micro-light-emitting mesas, wherein the array is bonded to the substrate 401, wherein each micro-light-emitting mesas includes the semiconductor epitaxial layer as described above. In one embodiment of the present invention, the size of the micro-LED chip does not exceed 1 cm, preferably does not exceed 20 μm.

[0066] In one embodiment of the present invention, each micro-light-emitting mesa includes, from bottom to top, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer. In one embodiment of the present invention, the first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer. In some embodiments, the first semiconductor layer is a P-type semiconductor layer, and the second semiconductor layer is an N-type semiconductor layer.

[0067] In one embodiment of the present invention, the material of the first semiconductor layer is AlGaInP of the first type, and the thickness of the first semiconductor layer is 3 to 3.5 microns. In some other embodiments of the present invention, the first semiconductor layer may also include structures such as an ohmic contact layer. The ohmic contact layer is located between the substrate and the first semiconductor layer, and the material is GaAs, and the GaAs has a higher N-type doping concentration, for example, higher than 1e18, preferably higher than 2e18. The thickness of the ohmic contact layer is not higher than 200nm, preferably 50 to 100nm.

[0068] In one embodiment of the present invention, the light-emitting layer is a quantum well structure (QW, Quantum Well). In one embodiment of the present invention, the light-emitting layer is a multiple quantum well structure (MQW, Multiple Quantum Well), which includes multiple quantum well layers (Well) and multiple quantum barrier layers (Barrier) alternately arranged in a repeated manner. In one embodiment of the present invention, the material of the quantum well layer is InGaAs, and the material of the quantum barrier layer is AlGaAs. By adjusting the element content in the quantum well layer, the radiation band of the light-emitting layer can be adjusted. In one embodiment of the present invention, the light-emitting layer provides radiation above 680nm, thereby forming an infrared light-emitting diode epitaxial wafer. In one embodiment of the present invention, the thickness of the quantum well layer is 3 to 15nm, the thickness of the quantum barrier layer is 5 to 50nm, and the number of quantum well layers in the light-emitting layer is not more than 25, preferably 3 to 12.

[0069] In one embodiment of the present invention, the second semiconductor layer comprises the semiconductor epitaxial layer as described above, and the first semiconductor layer and the second semiconductor layer have different conductivity types.

[0070] like Figure 4 As shown, the array is bonded to the surface of the substrate 401 through the bottom stack 412, and the bottom stack includes a bonding layer, a barrier layer, a reflective layer and an adhesion layer from bottom to top. The bonding layer is made of AuSn alloy, the barrier layer is made of metals such as Ti and Pt to prevent the alloy from diffusing when it is melted during the bonding process, and the adhesion layer is made of metals with good adhesion such as Cr to increase the adhesion between the epitaxial layer and the IC metal layer. In one embodiment of the present invention, the reflective layer is made of a metal with a high reflectivity, such as Au, Sn, etc., to improve the reflectivity of the light emitted from the bottom of the multi-quantum well MQW.

[0071] The substrate may be, for example, a gallium arsenide GaAs substrate. In one embodiment of the present invention, the GaAs substrate is a single crystal GaAs substrate doped with Si. In one embodiment of the present invention, the substrate includes a pixel driving circuit. In some embodiments of the present invention, the substrate 401 may be electrically connected to each micro-light-emitting mesa through a separate metal interconnection. In some further embodiments of the present invention, each micro-light-emitting mesa may be electrically controlled individually by the substrate. In some embodiments of the present invention, the substrate may be electrically connected to the electrode of the micro-light-emitting mesa through a metal interconnection, wherein the metal interconnection may be, for example, a metal layer or a first metal hole, and an array of second metal holes is provided on the surface of the substrate, and each of the second metal holes is electrically connected to each of the metal layers or each of the first metal holes. The material of the metal structure is an alloy of one or more of the following metals: Ni, Al, Ti, Ni, Pt, Au; the material of the metal hole is an alloy of one or more of the following metals: Ni, Al, Ti, Ni, Pt, Au. In some embodiments of the present invention, a dielectric layer may be formed in the gap between the micro-light-emitting mesas. In some embodiments of the present invention, a dielectric layer may also be formed in the gap between the interconnections.

[0072] In one embodiment of the present invention, the microarray includes a plurality of micro-luminescent mesas, each of which may form at least a portion of a pixel element on a micro-light-emitting diode chip. The micro-luminescent mesas are formed in an array in the micro-light-emitting diode chip, with a resolution of, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K or 4K. The diameter of the micro-luminescent mesas is in the nanometer range, for example, 20nm to 100nm. In one embodiment of the present invention, the spacing of the array, i.e., the minimum center-to-center distance between the micro-luminescent mesas, may be between about 2 microns and about 50 microns. In one embodiment of the present invention, the number of pixels on a micro-light-emitting diode chip may be between thousands and millions.

[0073] like Figure 4 As shown, the surface of the plurality of micro-light-emitting mesas 402 also includes a continuous top conductive layer 403, which is arranged above the array and contacts and covers the top of each micro-light-emitting mesas 402, and is in electrical contact with the top surface of the micro-light-emitting mesas, so as to connect the top surfaces of the micro-light-emitting mesas 402, i.e., the second semiconductor layer, in series, which is a transparent conductive layer. In one embodiment of the present invention, the micro-light-emitting mesas 402 can be arranged on the driving panel 401 in a regular or irregular manner as pixels of a micro-light-emitting diode chip. In one embodiment of the present invention, the material of the top conductive layer 403 is GaP. In one embodiment of the present invention, the thickness of the top conductive layer 403 is 4 to 5 um.

[0074] like Figure 4 As shown, there are partitions between the pixels formed by each micro-luminescent mesa 402, and a second electrode 404 is arranged at the partition, and the second electrode 404 is arranged on the surface of the top conductive layer 403. In one embodiment of the present invention, the second electrode 404 is a ring-shaped reflective electrode, which is arranged around the micro-luminescent mesa 402, and is formed by magnetron sputtering or evaporation. For example, the material can use Al or Al alloy metal as the side wall reflective mirror, and the electrode stack metal can be Ni, Al, Ti, Ni, Pt, Au and other metal materials. In one embodiment of the present invention, each second electrode is connected to each other.

[0075] In some embodiments of the present invention, a deep groove is provided at the partition between two adjacent micro light-emitting mesas 402, and the deep groove runs through the array, specifically, runs through the bottom stack at the partition, and the second electrode 404 is provided at the deep groove. In one embodiment of the present invention, the second electrode between adjacent micro light-emitting mesas has at least two peaks. In some embodiments of the present invention, a deep groove is not provided at the partition between two adjacent micro light-emitting mesas 402, but a passivation layer and a top conductive layer are directly formed, so that the surface of the top conductive layer between two adjacent micro light-emitting mesas 402 is a horizontal or substantially horizontal plane, the second electrode is formed there, and its morphological interface is a trapezoid or approximately a trapezoid, and the surface of the second electrode is not higher than the highest point of the continuous top conductive layer.

[0076] As shown in the figure, in one embodiment of the present invention, the micro-LED chip further includes a passivation layer 405. The passivation layer 405 is coated on the surface and side of the micro-light-emitting mesa 402, but exposes at least a portion of the top surface of the micro-light-emitting mesa, and the top conductive layer 403 is disposed on the surface of the passivation layer 405. In one embodiment of the present invention, the passivation layer 405 can be formed by CVD deposition of SiO2 or ALD deposition of Al2O3 film to effectively reduce the chip leakage rate. In some embodiments of the present invention, the passivation layer only covers the side of the micro-light-emitting mesa, but not the top surface of the micro-light-emitting mesa, and the highest point of the passivation layer is flush with the top surface of the micro-light-emitting mesa. In these embodiments, the top conductive layer covering the top of the micro-light-emitting mesa is in a horizontal or substantially horizontal plane. In some embodiments of the present invention, the passivation layer not only covers the side surfaces of the micro-luminescent mesa, but also covers the edge portion of the top surface of the micro-luminescent mesa, so that there is a bulge at the top edge of the micro-luminescent mesa, so that the top conductive layer 603 covering it also forms a bulge at the top edge of the micro-luminescent mesa.

[0077] In one embodiment of the present invention, the driving backplane 401 includes a substrate, a driving circuit, and an IC copper pillar 411 connected to the driving circuit, and the array is electrically connected to the IC copper pillar 411. The substrate can be a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO and sapphire substrates. In some embodiments, the substrate is about 700 microns thick. The driving circuit, for example, includes a complementary metal oxide semiconductor (CMOS) device or a TFT device. As shown in the figure, the IC copper pillar 411 includes a first IC copper pillar and a second IC copper pillar, wherein the first IC copper pillar is electrically connected to the first semiconductor layer of the semiconductor light-emitting module in a one-to-one correspondence, and the second IC copper pillar is electrically connected to the first electrode 406. In one embodiment of the present invention, the polarity of the first electrode is opposite to that of the second electrode. In one embodiment of the present invention, each semiconductor light-emitting module has a common first electrode. The first electrode can be, for example, a P electrode or an anode electrode, and the second electrode is an electrode with a polarity opposite to that of the first electrode, such as an N electrode or a cathode electrode. In one embodiment of the present invention, the first and second electrodes and their connecting parts can be made of materials such as graphene, ITO, aluminum-doped zinc oxide (AZO) or fluorine-doped tin oxide (FTO) or any combination of the above materials. In another embodiment of the present invention, the first and second electrodes and their connecting parts can be made of non-transparent or transparent conductive materials, such as indium tin oxide (ITO).

[0078] As shown in the figure, in one embodiment of the present invention, the micro-LED chip further includes a micro-lens array. The micro-lens array is arranged above the array formed by the micro-light-emitting mesas, wherein at least one micro-lens 407 is arranged on the surface of the top conductive layer of the micro-light-emitting mesas, and the horizontal profile of the micro-lens is greater than the maximum horizontal profile of the micro-light-emitting mesas. The micro-lens is mainly used to converge and / or collimate the optical fiber, for example, by adjusting the thickness, curvature and other parameters of the micro-lens so that the focus of the micro-lens is located in the micro-light-emitting mesas.

[0079] As shown in the figure, in one embodiment of the present invention, the microlenses of the microlens array correspond to the micro-light-emitting mesas one by one. At the same time, in some embodiments of the present invention, there is a gap between adjacent microlenses and their bottoms are connected to each other. The bottom of the gap may be lower than the top of the micro-light-emitting mesas, or lower than the bottom of the light-emitting layer of the micro-light-emitting mesas, or located above the second electrode, or located between the two peaks of the second electrode. In some other embodiments of the present invention, adjacent microlenses are completely connected, but there is a gap in the connecting portion. And the bottom of the connecting portion may be lower than the top of the micro-light-emitting mesas, or lower than the bottom of the light-emitting layer of the micro-light-emitting mesas, or located above the second electrode, or located between the two peaks of the second electrode. In addition, in one embodiment of the present invention, there is an air gap inside the microlens.

[0080] In an embodiment of the present invention, the microlens can be formed by multiple depositions. In the process of forming the microlens, a SiO2 film layer needs to be deposited first, and then ion etching is performed. The microlens is formed on the surface of the passivation isolation layer at the position corresponding to each light-emitting table.

[0081] Preferably, the first semiconductor layer 202 is an N-type semiconductor layer, and the second semiconductor layer 204 is a P-type semiconductor layer. In some embodiments, the first semiconductor layer 202 is a P-type semiconductor layer, and the second semiconductor layer 204 is an N-type semiconductor layer.

[0082] The present invention further provides a schematic flow chart of a method for manufacturing a micro-LED chip as described above. A method for manufacturing a micro-LED chip comprises:

[0083] First, a micro-luminescent table top is provided. Figure 5 A schematic diagram showing a process of manufacturing a micro-luminescent table according to an embodiment of the present invention is shown as follows: Figure 5 As shown, a method for manufacturing a micro-luminescent table comprises:

[0084] First, in step 501, Fig. 6A As shown, a substrate is provided. A growth substrate 601 is provided, preferably GaAs, on which each layer structure of the epitaxial wafer is epitaxially grown by a deposition process such as metal-organic chemical vapor deposition (MOCVD) method;

[0085] Next, in step 502, if Figure 6BAs shown, a first semiconductor layer is formed. A first semiconductor layer 602 is grown on the substrate. In one embodiment of the present invention, the first semiconductor layer mainly comprises N-type AlGaInP. The growth conditions of the N-type AlGaInP include: a growth temperature of 670 to 680 degrees Celsius, a thickness of 3 to 3.5 um, a V / III ratio of 40 to 50, a growth rate of 1.2 to 1.7 nm / s, and a carrier concentration of 1 to 2e18 cm -3 In some embodiments of the present invention, before growing the N-type AlGaInP, an N-type GaAs ohmic contact layer may be grown first. The growth conditions of the N-type GaAs ohmic contact layer include: growth temperature of 650 to 670 degrees Celsius, thickness of 60 to 90 nm, V / III of 20 to 30, growth rate of 0.4 to 0.6 nm / s, carrier concentration of 4 to 6e18 cm -3 ;

[0086] Next, in step 503, if Figure 6C As shown, a light emitting layer is formed. A light emitting layer 603 is grown on the first semiconductor layer. In one embodiment of the present invention, the growth conditions of the light emitting layer include: a growth temperature of 660 to 670 degrees Celsius, a thickness of 150 to 200 nm, a V / III ratio of 20 to 30, and a growth rate of 0.4 to 0.6 nm / s;

[0087] Next, in step 504, if Fig.6D As shown, a second semiconductor layer is formed. A second semiconductor layer 604 is grown on the light emitting layer, wherein the second semiconductor layer mainly comprises a P-type transition layer, and the P-type transition layer comprises multiple layers of Ga x In 1-x P, and each layer of Ga x In 1-x The Ga and In components in P are different. In one embodiment of the present invention, the second semiconductor layer is formed at a temperature of 630 to 680 degrees Celsius, the thickness of each layer is 5 to 400 nm, the growth pressure is 30 to 200 mbar, and includes one or more impurities of Be, Mg, Zn, Cd, and C, and the doping concentration is 0.5e18 to 5e+18. In one embodiment of the present invention, after the P-type transition layer is grown, a P-type GaP ohmic contact layer can be further formed on its surface; and

[0088] Finally, in step 505, if Fig. 6EAs shown, a current spreading layer is formed. A current spreading layer 605 is grown on the second semiconductor layer. In one embodiment of the present invention, the material of the current spreading layer is P-type GaP, and the growth conditions of the P-type GaP current spreading layer include: growth temperature 700 to 710 degrees Celsius, thickness 4 to 5um, V / III 20 to 30, growth rate 2.5 to 3nm / s, magnesium carrier concentration 1 to 3e18cm -3 ;

[0089] Next, a metal layer is formed on the substrate, and the micro-luminescent table obtained in the above steps is bonded to the metal layer so that it is electrically connected to the metal layer to form a light-emitting area of ​​the micro-display chip. For example, an adhesion layer, a reflective layer, a barrier layer and a bonding metal can be deposited in sequence on the surface of the first semiconductor layer. Then, the micro-luminescent table is bonded to the substrate through the bonding metal so that the IC copper column on the substrate is electrically interconnected with the micro-luminescent table. In one embodiment of the present invention, after the chip is bonded, the substrate can also be ground and thinned to be removed, or the substrate can be removed by laser stripping to further thin the buffer layer structure to facilitate the subsequent PN step structure. In an embodiment of the present invention, the bonding process can, for example, adopt hot pressing bonding, eutectic bonding process, etc. Then, step etching is performed, and the micro-luminescent table is ion-etched to form a regular trapezoidal structure pixel point by adjusting the photolithographic morphology. In one embodiment of the present invention, the horizontal angle of the regular trapezoidal structure pixel point can be, for example, 65° to 85°;

[0090] Next, a passivation layer is formed on the side wall and surface of each pixel. In one embodiment of the present invention, the passivation isolation layer is formed by CVD deposition of SiO2 film layer and / or ALD deposition of Al2O3 film layer to reduce the chip leakage rate. After the deposition is completed, a photolithography opening is performed above the corresponding pixel to expose at least a portion of the surface of the second semiconductor layer. A top conductive layer is further formed on the surface of the passivation layer to realize the shared series connection of the second semiconductor layer of each pixel. An annular reflective electrode is formed at the partition of each pixel. In one embodiment of the present invention, the annular reflective electrode is realized by magnetron sputtering or evaporation process. In one embodiment of the present invention, the second electrode uses Al or Al alloy metal as the side wall reflective mirror, and the electrode stack metal uses Ni, Al, Ti, Pt, Au and other metal materials. In one embodiment of the present invention, before forming the passivation layer, deep groove etching can also be performed at the partition of each pixel, for example, by photolithography and IBE inert gas physical etching process, and the subsequent second electrode is formed at the deep groove. Subsequently, a first electrode is formed on the substrate, wherein the first electrode is connected to the IC copper column, plays a role of protecting the pad and facilitating subsequent wiring; and

[0091] Finally, SiO2 is deposited, and the photolithography morphology is adjusted to form a microlens. In one embodiment of the present invention, a SiO2 film layer, i.e., the first transmission layer, is deposited by PECVD, and the thickness of the film layer is about 2.5 to 3.5 um. Subsequently, the photolithography morphology of the microlens is adjusted, such as the thickness of the glue, the exposure energy, and the hardening temperature, etc., to complete the photolithography array morphology corresponding to the pixel point position, and the SiO2 material of the microlens passivation protection layer is ion-etched to form a hemispherical SiO2 microlens with a lens-like morphology, which can improve the light extraction efficiency to a certain extent. At this point, the initial structure of the micro-LED chip is formed. Since the step coverage of PECVD deposited SiO2 is not good, micro cracks are easily formed at the deep grooves of the pixel points, causing the quantum well light source to form diffuse reflection here, reducing the light output efficiency of the microlens. In addition, due to the microlens photolithography size and ion etching, the overall microlens curvature radius, the lower spacer height, the ball height, and the lens ball width are all relatively small, and the optimal conditions of the lens are not achieved. Therefore, in some embodiments of the present invention, secondary deposition can be performed to increase the microlens curvature radius, the lower spacer height, the ball height, and the lens ball width. In one embodiment of the present invention, the film thickness of the secondary SiO2 deposition needs to be determined based on the film thickness of the previous microlens deposition SiO2 and the microlens etching morphology. In one embodiment of the present invention, the film thickness of the secondary deposition is preferably 0.2 to 1um, and a single or multiple deposition operation can be performed. In one embodiment of the present invention, the secondary deposition of SiO2 uses a mixed gas of SiH4 and N2O, and the ratio of SiH4 to N2O is 1:5. At the same time, the gas flow rate is controlled at a relatively low level so that the deposition rate is much lower than that of the previous microlens deposition. The secondary deposition uses a high vacuum environment process condition and a large flow of inert gas N2 to further improve the step coverage effect of the secondary deposition SiO2, making it less likely to produce defects, and even repairing the micro defects of the previous microlens deposition, thereby obtaining a better brightness enhancement effect.

[0092] The semiconductor epitaxial layer provided by the present invention is characterized by introducing Ga X In 1-X The P component grows in a gradual manner, replacing the original AlGaInP growth, which alleviates the mismatch caused by the lattice constant between materials, and is conducive to obtaining a better quality GaP current expansion layer, which is conducive to the uniform expansion of the P-side current, thereby obtaining excellent optoelectronic performance.

[0093] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A semiconductor epitaxial layer, characterized in that: include: Multilayer Ga x In 1-x P, where at least some layers of Ga x In 1-x The value of x in P increases gradually from bottom to top, and x is a positive number; as well as A GaP layer is located in and contacts the multilayer Ga x In 1-x The surface of P.

2. The semiconductor epitaxial layer according to claim 1, characterized in that The Ga x In 1-x The value of x in P ranges from 50% to 90%.

3. The semiconductor epitaxial layer according to claim 1, characterized in that At least some Ga x In 1-x The value of x in the P layer increases linearly or arithmetically from bottom to top.

4. The semiconductor epitaxial layer according to claim 1, characterized in that The multilayer Ga x In 1-x The x value of the top layer in the P layer is 90%.

5. The semiconductor epitaxial layer according to claim 1, characterized in that Each layer of Ga x In 1-x P also includes impurity elements.

6. The semiconductor epitaxial layer according to claim 5, characterized in that The impurity elements include one or more of the following elements: Be, Mg, Zn, Cd, and C.

7. The semiconductor epitaxial layer according to claim 6, characterized in that The doping concentration of the impurity element is 0.5e18 to 5e18.

8. The semiconductor epitaxial layer according to claim 1, characterized in that At least some Ga x In 1-x The thickness of the P layer is the same.

9. The semiconductor epitaxial layer according to claim 8, characterized in that: At least some Ga x In 1-x The thickness of P is 5 nm to 400 nm.

10. The semiconductor epitaxial layer according to claim 1, characterized in that The multilayer Ga x In 1-x The number of layers of P is 3 or more.

11. A micro light emitting diode chip, characterized in that: An array comprising a plurality of micro-light-emitting mesas, wherein each micro-light-emitting mesas comprises: substrate; A first semiconductor layer, disposed on the substrate; a light-emitting layer, disposed on the first semiconductor layer; A second semiconductor layer, which is disposed on the light emitting layer and comprises the semiconductor epitaxial layer according to any one of claims 1 to 10, and the first semiconductor layer and the second semiconductor layer have different conductivity types; and A top conductive layer is disposed on the second semiconductor layer.

12. The micro light emitting diode chip according to claim 11, characterized in that: The material of the substrate includes GaAs.

13. The micro light emitting diode chip according to claim 11, characterized in that: The material of the first semiconductor layer includes AlGaInP.

14. The micro light emitting diode chip according to claim 11, characterized in that: The top conductive layer is made of transparent conductive material.

15. The micro light emitting diode chip according to claim 11, characterized in that: The light-emitting layer is a multiple quantum well structure, which includes a plurality of quantum well layers and a plurality of quantum barrier layers which are alternately arranged in a repeated manner.

16. The micro light emitting diode chip according to claim 11, characterized in that: The first semiconductor layer is of P type, and the second semiconductor layer is of N type; or The first semiconductor layer is of N type, and the second semiconductor layer is of P type.

17. The micro light emitting diode chip according to claim 11, characterized in that: The invention also includes a passivation layer, wherein the passivation layer at least covers the side wall of the micro-light-emitting mesa.

18. The micro light emitting diode chip according to claim 11, characterized in that: The substrate includes a pixel driving circuit.

19. The micro light emitting diode chip according to claim 11, characterized in that: The top conductive layer continuously covers the top of the array formed by the micro-light-emitting mesas.

20. The micro light emitting diode chip according to claim 11, characterized in that: The bottom of the micro-luminescent mesa is electrically connected to the substrate via a metal structure.

21. The micro light emitting diode chip according to claim 20, characterized in that: The metal structure is a metal layer or a first metal hole; an array of second metal holes is arranged on the surface of the substrate, and each of the second metal holes is electrically connected to each of the metal layers or each of the first metal holes.

22. The micro light emitting diode chip according to claim 21, characterized in that: The material of the metal structure is an alloy of one or more of the following metals: Ni, Al, Ti, Ni, Pt, Au; the material of the metal hole is an alloy of one or more of the following metals: Ni, Al, Ti, Ni, Pt, Au.

23. The micro light emitting diode chip according to claim 11, characterized in that: It also includes a microlens structure, which is arranged on the micro-light-emitting mesa, wherein the microlens structure includes a lens array composed of a plurality of microlenses, and the lens array is arranged above the array area formed by the light-emitting mesa.

24. A method for manufacturing a micro light emitting diode chip, characterized in that: Includes steps: providing a substrate; growing a first semiconductor layer on the substrate; growing a light emitting layer on the first semiconductor layer; A second semiconductor layer is grown on the light emitting layer, wherein the second semiconductor layer comprises a multilayer Ga x In 1-x P, and each layer of Ga x In 1-x The Ga and In compositions in P are different; and A top conductive layer is grown on the second semiconductor layer.

25. The manufacturing method according to claim 24, characterized in that: The second semiconductor layer is formed at a temperature of 630 degrees Celsius to 680 degrees Celsius.

26. The manufacturing method according to claim 24, characterized in that: The second semiconductor layer is generated at a pressure of 30 mbar to 200 mbar.

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