Method of manufacturing display device

Abstract

A method of manufacturing a display device includes aligning a light emitting element in an alignment region between electrodes spaced apart from each other. The alignment light emitting element includes applying a first alignment voltage between the electrodes, applying a second alignment voltage to the first signal line overlapping the alignment region, and applying a third alignment voltage to the second signal line overlapping the alignment region. The first signal line is formed by a first conductive layer, and the second signal line is formed by the first conductive layer and a second conductive layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0139279 filed in the Korean Intellectual Property Office on October 18, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a method of manufacturing a display device. Background Art

[0004] Recently, as interest in information display increases, research and development of display devices have been continuously conducted. Summary of the invention

[0005] Embodiments provide a method of manufacturing a display device capable of improving the degree of alignment of a light emitting element.

[0006] However, the embodiments are not limited to those described herein. The above and other embodiments will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to aspects of the present disclosure, a method for manufacturing a display device may include aligning a light-emitting element in an alignment region between electrodes spaced apart from each other, wherein the aligning the light-emitting element may include: applying a first alignment voltage between the electrodes; applying a second alignment voltage to a first signal line overlapping the alignment region; and applying a third alignment voltage to a second signal line overlapping the alignment region, and the first signal line may be formed by a first conductive layer, and the second signal line may be formed by the first conductive layer and the second conductive layer.

[0008] The first alignment voltage, the second alignment voltage, and the third alignment voltage may be applied simultaneously.

[0009] The first alignment voltage may be higher than the second alignment voltage.

[0010] The second alignment voltage may be higher than the third alignment voltage.

[0011] The electrode may be electrically separated from the first signal line and the second signal line.

[0012] Aligning the light emitting element may further include applying a fourth alignment voltage to a third signal line overlapping the alignment region.

[0013] The third signal line may be formed of the first conductive layer, the second conductive layer, and the third conductive layer.

[0014] The first alignment voltage, the second alignment voltage, the third alignment voltage, and the fourth alignment voltage may be applied simultaneously.

[0015] The third alignment voltage may be higher than the fourth alignment voltage.

[0016] The electrode may be electrically separated from the third signal line.

[0017] Aligning the light emitting element may further include applying a fifth alignment voltage to the electrode layer overlapping the alignment region.

[0018] The electrode layer may be formed of the fourth conductive layer.

[0019] The electrode layer may overlap with the first signal line or the second signal line.

[0020] The first alignment voltage, the second alignment voltage, the third alignment voltage, and the fifth alignment voltage may be applied simultaneously.

[0021] The first alignment voltage may be higher than the fifth alignment voltage.

[0022] The electrode may be electrically separated from the electrode layer.

[0023] The electrode layer may be electrically separated from the first signal line and the second signal line.

[0024] The electrode layer may overlap the electrode.

[0025] The method may further include forming a connection electrode on the light emitting element.

[0026] The connection electrode may be electrically connected to the first signal line or the second signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0028] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that where an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals always represent the same elements.

[0029] Figure 1 is a schematic perspective view showing a light emitting element according to an embodiment.

[0030] Figure 2 is a schematic cross-sectional view showing a light emitting element according to an embodiment.

[0031] Figure 3is a schematic plan view showing a display device according to an embodiment.

[0032] Figure 4 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0033] Figure 5 is a schematic plan view showing a pixel circuit region of a pixel according to an embodiment.

[0034] Figure 6 is a schematic plan view showing first to third pixels according to an embodiment.

[0035] Figure 7 and Figure 8 is a schematic plan view showing a pixel according to an embodiment.

[0036] Fig. 9 and Fig.10 It is along Figure 7 A schematic cross-sectional view taken along line AA′ shown in FIG.

[0037] Fig.11 and Fig.12 It is along Figure 7 A schematic cross-sectional view taken along line BB′ shown in FIG.

[0038] Fig.13 It is along Figure 8 A schematic cross-sectional view taken along line CC' shown in FIG.

[0039] Fig.14 It is along Figure 8 A schematic cross-sectional view taken along line DD′ shown in FIG.

[0040] Fig.15 is a schematic cross-sectional view showing first to third pixels according to an embodiment.

[0041] Fig.16 is a schematic cross-sectional view showing a pixel according to an embodiment.

[0042] Figures 17 to 25 are schematic plan views and cross-sectional views illustrating process steps of a method of manufacturing a display device according to an embodiment.

[0043] Figure 26 to Figure 34 are schematic plan views and cross-sectional views illustrating process steps of a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0044] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive and do not limit the present disclosure. For example, the specific shape, configuration and characteristics of an embodiment can be used or implemented in another embodiment.

[0045] Unless otherwise specified, the embodiments shown should be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments, etc. (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the present invention.

[0046] The use of cross hatching and / or shading is generally provided in the drawings to clarify the boundaries between adjacent elements. Therefore, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements, unless otherwise stated. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments may be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0047] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to or directly coupled to another element or layer, or there can be an intervening element or layer. However, when an element or layer is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this reason, the term "connection" can refer to a physical connection, electrical connection and / or fluid connection with or without an intervening element. In addition, the axis of the first direction, the axis of the second direction and the axis of the third direction are not limited to three axes such as the X-axis, the Y-axis and the Z-axis of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the axis of the first direction, the axis of the second direction and the axis of the third direction can be perpendicular to each other, or different directions that are not perpendicular to each other can be represented. For the purpose of this disclosure, "at least one of A and B" can be understood to mean only A, only B or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0049] For descriptive purposes, spatially relative terms such as "below," "below," "under," "down," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein to describe the relationship of one element to another element(s) as shown in the drawings. In addition to the orientation depicted in the drawings, spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, elements described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the term "below" may encompass both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0050] The term used herein is used to describe the purpose of a particular embodiment, and is not intended to be limiting. As used herein, the singular "one", "a kind of" and "described" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the term "comprising", "comprising", "including" and / or "including" specifies the existence of stated features, integral bodies, steps, operations, elements, components and / or its groups, but does not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or its groups. It should also be noted that, as used herein, the term "substantially", "about" and similar terms are used as approximate terms and not as degree terms, and therefore, are used to explain the inherent deviation in the value measured, calculated and / or provided that will be recognized by a person of ordinary skill in the art.

[0051] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of embodiments and / or intermediate structures. Therefore, changes in the shapes in the figures caused by, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments disclosed herein need not be interpreted as being limited to the illustrated shapes of specific regions, but should include deviations in shapes caused by, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore, are not necessarily intended to be limiting.

[0052] As is customary in the art, for functional blocks, units and / or modules, some embodiments are described and shown in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electrical circuits (or optical circuits) such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connectors, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform various functions discussed herein, and they can be selectively driven by firmware and / or software. It can also be envisioned that each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and related circuits) for performing other functions. In addition, without departing from the scope of the present invention, each block, unit and / or module of some embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the invention.

[0053] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings.

[0054] Figure 1 is a schematic perspective view showing a light emitting element LD according to an embodiment. Figure 2 is a schematic cross-sectional view showing a light emitting element LD according to an embodiment. Figure 1 and Figure 2 Columnar light emitting elements LD are shown in FIG. 1 , but the type and / or shape of the light emitting elements LD are not limited thereto.

[0055] refer to Figure 1 and Figure 2 The light emitting element LD may include a first semiconductor layer 11 , an active layer 12 , a second semiconductor layer 13 and / or a contact electrode 14 .

[0056] The light emitting element LD may be arranged (or formed) in a column shape extending in one direction. The light emitting element LD may have a first end portion EP1 and a second end portion EP2. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be arranged at the first end portion EP1 of the light emitting element LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 may be arranged at the second end portion EP2 of the light emitting element LD. For example, the first semiconductor layer 11 may be arranged at the first end portion EP1 of the light emitting element LD, and the second semiconductor layer 13 may be arranged at the second end portion EP2 of the light emitting element LD.

[0057] In some embodiments, the light emitting element LD may be a light emitting element manufactured into a columnar shape by an etching process, etc. In this specification, the term "column shape" may include a rod-like shape or a bar-like shape having an aspect ratio greater than 1, such as a cylinder or a polygonal column, and the shape of its cross section is not limited thereto.

[0058] The light emitting element LD may have a size ranging from nanometer to micrometer. In an example, the light emitting element LD may have a diameter D (or width) ranging from nanometer to micrometer and / or a length L ranging from nanometer to micrometer. However, the size of the light emitting element LD is not limited thereto, and the size of the light emitting element LD may be variously changed according to the design conditions of various types of devices (e.g., display devices, etc.) using the light emitting device using the light emitting element LD as a light source.

[0059] The first semiconductor layer 11 may be a first conductive type semiconductor layer. For example, the first semiconductor layer 11 may include a p-type semiconductor layer. In an example, the first semiconductor layer 11 may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and include a p-type semiconductor layer doped with a first conductive type dopant such as Mg. However, the material of the first semiconductor layer 11 is not limited thereto. For example, the first semiconductor layer 11 may be formed of various materials.

[0060] The active layer 12 may be disposed between the first semiconductor layer 11 and the second semiconductor layer 13. The active layer 12 may include any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but the embodiment is not limited thereto. The active layer 12 may include GaN, InGaN, InAlGaN, AlGaN, AlN, etc. For example, the active layer 12 may be formed of various materials.

[0061] When a voltage that is a threshold voltage or higher is applied to ends (e.g., opposite ends) of the light emitting element LD, the light emitting element LD can emit light as electron-hole pairs are recombined in the active layer 12. Light emission of the light emitting element LD can be controlled by utilizing such a principle, so that the light emitting element LD can be used as a light source for various light emitting devices (including pixels of a display device).

[0062] The second semiconductor layer 13 may be formed on the active layer 12, and may include a semiconductor layer having a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include an n-type semiconductor layer. In an example, the second semiconductor layer 13 may include any semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and include an n-type semiconductor layer doped with a second conductive type dopant such as Si, Ge, or Sn. However, the material of the second semiconductor layer 13 is not limited thereto. For example, the second semiconductor layer 13 may be formed of various materials.

[0063] The contact electrode 14 may be provided on the first end portion EP1 and / or the second end portion EP2 of the light emitting element LD. Figure 2 For example, a separate contact electrode may be provided on the second semiconductor layer 13.

[0064] The contact electrode 14 may include a transparent metal or a transparent metal oxide. In an example, the contact electrode 14 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and zinc tin oxide (ZTO), but the embodiment is not limited thereto. In the case where the contact electrode 14 may be made of a transparent metal or a transparent metal oxide, light generated in the active layer 12 of the light emitting element LD may pass through the contact electrode 14 and be emitted to the outside of the light emitting element LD.

[0065] The insulating film INF may be disposed on the surface of the light emitting element LD. The insulating film INF may be disposed (e.g., directly disposed) on the surface of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the contact electrode 14. The insulating film INF may expose the first end portion EP1 and the second end portion EP2 of the light emitting element LD having different polarities. In some embodiments, the insulating film INF may expose the side portion of the contact electrode 14 and / or the second semiconductor layer 13 of the light emitting element LD adjacent to the first end portion EP1 and / or the second end portion EP2.

[0066] The insulating film INF can prevent electrical short circuits that occur when the active layer 12 contacts conductive materials other than the first and second semiconductor layers 11 and 13. The insulating film INF can minimize surface defects of the light emitting element LD, thereby improving the life span and light emission efficiency of the light emitting element LD.

[0067] The insulating film INF may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ). For example, the insulating film INF may be formed as a double layer, and the layers included in the double layer may include different materials. In an example, the insulating film INF may be formed to include aluminum oxide (AlO x ) and silicon oxide (SiO x ), but the embodiment is not limited thereto. In some embodiments, the insulating film INF may be omitted.

[0068] The light emitting device including the above-mentioned light emitting element LD can be used in various types of devices (including display devices) that require a light source. For example, the light emitting element LD can be arranged in each pixel of the display panel and used as the light source of each pixel. However, the application field of the light emitting element LD is not limited to the above examples. For example, the light emitting element LD can be used in other types of devices (such as, lighting devices) that require a light source.

[0069] Figure 3 is a schematic plan view showing a display device according to an embodiment.

[0070] exist Figure 3 In the embodiment, the display device (for example, the display panel PNL provided (or arranged) in the display device) will be used as Figure 1 and Figure 2 The light emitting element LD described in the embodiment shown in FIG. 1 is shown as an example of an electronic device in which the light emitting element LD is used as a light source.

[0071] For ease of description, Figure 3 , the structure of the display panel PNL will be shown based on the display area DA. However, in some embodiments, at least one driving circuit (eg, at least one of a scan driver and a data driver) and lines not shown in the drawings may be further provided in the display panel PNL.

[0072] refer to Figure 3 , the display panel PNL and the base layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA other than the display area DA. The display area DA may form a screen in which an image is displayed, and the non-display area NDA may be other areas other than the display area DA.

[0073] The pixel unit PXU may be disposed in the display area DA. The pixel unit PXU may include a first pixel PXL1, a second pixel PXL2, and / or a third pixel PXL3. Hereinafter, in the case where at least one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be arbitrarily designated, or in the case where two or more kinds of pixels of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be inclusively designated, the corresponding pixel will be referred to as a "pixel PXL".

[0074] The pixel PXL can be based on the stripe structure, However, the arrangement structure of the pixels PXL is not limited thereto, and the pixels PXL may be arranged in the display area DA by using various structures and / or methods.

[0075] In some embodiments, two or more kinds of pixels PXL may emit light of different colors. In an example, a first pixel PXL1 emitting light of a first color, a second pixel PXL2 emitting light of a second color, and a third pixel PXL3 emitting light of a third color may be arranged in a display area DA. At least one first pixel PXL1, at least one second pixel PXL2, and at least one third pixel PXL3 disposed adjacent to each other may form a pixel unit PXU capable of emitting light of various colors. For example, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be a pixel emitting light of a selected color. In some embodiments, the first pixel PXL1 may be a red pixel emitting red light, the second pixel PXL2 may be a green pixel emitting green light, and the third pixel PXL3 may be a blue pixel emitting blue light. However, embodiments are not limited thereto.

[0076] In an embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 have light-emitting elements that emit light of the same color, and may include color conversion layers and / or color filters of different colors disposed on the corresponding light-emitting elements to emit light of the first color, the second color, and the third color, respectively. In another embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may have a light-emitting element of the first color, a light-emitting element of the second color, and a light-emitting element of the third color as light sources, respectively, so that the light-emitting elements may emit light of the first color, light of the second color, and light of the third color, respectively. However, the color, type, and / or number of the pixels PXL of each pixel unit PXU are not limited thereto. In the example, the color of the light emitted by each pixel PXL may be variously changed.

[0077] The pixel PXL may include at least one light source driven by a selected control signal (eg, a scan signal and a data signal) and / or a selected power source (eg, a first driving power source and a second driving power source). Figure 1 and Figure 2 At least one light emitting element LD of the embodiment shown in , for example, an ultra-small columnar light emitting element LD having a size of nanometer to micrometer level. However, the embodiment is not limited thereto. For example, various types of light emitting elements LD may be used as the light source of the pixel PXL.

[0078] In an embodiment, each pixel PXL may be formed as an active pixel. However, the type, structure and / or driving method of the pixel PXL applied to the display device are not limited thereto. For example, each pixel PXL may be formed as a pixel of a passive or active light-emitting display device using various structures and / or driving methods.

[0079] The non-display area NDA may be disposed at the periphery of the display area DA. The display pad DP and the alignment pad AP may be disposed in the non-display area NDA. The display pad DP may be electrically connected to at least one driving circuit. The pixel PXL may be electrically connected to the display pad DP through a fan-out line to receive a driving signal from the driving circuit. The electrode ( Figure 6 The ALE shown in FIG. 1 can be electrically connected to the alignment pad AP to receive an alignment signal. Figure 3 , it is shown that the display pad DP and the alignment pad AP are disposed at only the lower side of the display panel PNL. However, the embodiment is not limited thereto. For example, the display pad DP and the alignment pad AP may be disposed at the upper side and the lower side of the display panel PNL, respectively.

[0080] Figure 4 is a schematic diagram of an equivalent circuit of a pixel PXL according to an embodiment.

[0081] Figure 4 Shown included in Figure 3 The electrical connection relationship of the components in each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 shown in FIG. 1 is shown in FIG. 1 , and the components included in each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 are not limited thereto. Figure 4 In the embodiment, the pixel PXL may include not only the components included in each of the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 , but also a region in which the components are disposed.

[0082] refer to Figure 4 Each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include a light emitting unit EMU (or a light emitting portion) generating light having brightness corresponding to the data signal. The pixel PXL may further include a pixel circuit PXC for driving the light emitting unit EMU.

[0083] For example, the light emitting unit EMU may include a first connection electrode ELT1 connected to a first driving power source VDD through a pixel circuit PXC and a first power line PL1, a fifth connection electrode ELT5 connected to a second driving power source VSS through a second power line PL2, and a light emitting element LD connected between the first connection electrode ELT1 and the fifth connection electrode ELT5. The first driving power source VDD and the second driving power source VSS may have different potentials (or voltages) so that the light emitting element LD may emit light. In an example, the first driving power source VDD may be set as a high potential power source, and the second driving power source VSS may be set as a low potential power source.

[0084] In an embodiment, the light emitting unit EMU may include at least one series connection stage. Each series connection stage may include a pair of electrodes (e.g., two electrodes) and at least one light emitting element LD connected in a forward bias direction between the pair of electrodes. The number of series connection stages of the light emitting unit EMU and the number of light emitting elements LD of each series connection stage are not limited thereto. In an example, the number of light emitting elements LD of each series connection stage may be equal to or different from each other, and the number of light emitting elements LD is not limited thereto.

[0085] For example, the light emitting unit EMU may include a first series stage including at least one first light emitting element LD1, a second series stage including at least one second light emitting element LD2, a third series stage including at least one third light emitting element LD3, and a fourth series stage including at least one fourth light emitting element LD4.

[0086] The first series stage may include a first connection electrode ELT1, a second connection electrode ELT2, and at least one first light emitting element LD1 connected between the first connection electrode ELT1 and the second connection electrode ELT2. Each first light emitting element LD1 may be connected between the first connection electrode ELT1 and the second connection electrode ELT2 in a forward bias direction. For example, a first end EP1 of the first light emitting element LD1 may be connected to the first connection electrode ELT1, and a second end EP2 of the first light emitting element LD1 may be connected to the second connection electrode ELT2.

[0087] The second series stage may include a second connection electrode ELT2 and a third connection electrode ELT3 and at least one second light emitting element LD2 connected between the second connection electrode ELT2 and the third connection electrode ELT3. Each second light emitting element LD2 may be connected between the second connection electrode ELT2 and the third connection electrode ELT3 in a forward bias direction. For example, a first end EP1 of the second light emitting element LD2 may be connected to the second connection electrode ELT2, and a second end EP2 of the second light emitting element LD2 may be connected to the third connection electrode ELT3.

[0088] The third series stage may include a third connection electrode ELT3 and a fourth connection electrode ELT4 and at least one third light emitting element LD3 connected between the third connection electrode ELT3 and the fourth connection electrode ELT4. Each third light emitting element LD3 may be connected in a forward bias direction between the third connection electrode ELT3 and the fourth connection electrode ELT4. For example, a first end EP1 of the third light emitting element LD3 may be connected to the third connection electrode ELT3, and a second end EP2 of the third light emitting element LD3 may be connected to the fourth connection electrode ELT4.

[0089] The fourth series stage may include a fourth connection electrode ELT4 and a fifth connection electrode ELT5 and at least one fourth light emitting element LD4 connected between the fourth connection electrode ELT4 and the fifth connection electrode ELT5. Each fourth light emitting element LD4 may be connected in a forward bias direction between the fourth connection electrode ELT4 and the fifth connection electrode ELT5. For example, a first end EP1 of the fourth light emitting element LD4 may be connected to the fourth connection electrode ELT4, and a second end EP2 of the fourth light emitting element LD4 may be connected to the fifth connection electrode ELT5.

[0090] The first electrode of the light emitting unit EMU (eg, the first connection electrode ELT1) may be an anode electrode of the light emitting unit EMU. The last electrode of the light emitting unit EMU (eg, the fifth connection electrode ELT5) may be a cathode electrode of the light emitting unit EMU.

[0091] In the case where the light-emitting elements LD are connected in a series / parallel structure, the power efficiency can be improved compared to the case where the number of light-emitting elements LD equal to the number of the above-mentioned light-emitting elements LD is only connected in parallel. In the pixel PXL in which the light-emitting elements LD are connected in a series / parallel structure, even if a short circuit defect or the like occurs in some series stages, the brightness can be expressed (or conveyed) by the light-emitting elements LD of other series stages. Therefore, the probability of dark spot defects occurring in the pixel PXL can be reduced. However, the embodiment is not limited thereto, and the light-emitting unit EMU can be formed by connecting the light-emitting elements LD only in series or by connecting the light-emitting elements LD only in parallel.

[0092] Each of the light emitting elements LD may include a first end EP1 (e.g., a p-type end) connected to a first driving power source VDD via at least one electrode (e.g., a first connection electrode ELT1), a pixel circuit PXC, and / or a first power line PL1, and a second end EP2 (e.g., an n-type end) connected to a second driving power source VSS via at least another electrode (e.g., a fifth connection electrode ELT5) and a second power line PL2. For example, the light emitting element LD may be connected in a forward bias direction between the first driving power source VDD and the second driving power source VSS. The light emitting element LD connected in a forward bias direction may form an effective light source of the light emitting unit EMU.

[0093] In the case where a driving current is provided by the corresponding pixel circuit PXC, the light emitting element LD can emit light with a brightness corresponding to the driving current. For example, during each frame period, the pixel circuit PXC can provide the light emitting unit EMU with a driving current corresponding to the grayscale value to be expressed (or communicated) in the corresponding frame. Therefore, in the case where the light emitting element LD emits light with a brightness corresponding to the driving current, the light emitting unit EMU can express (or communicate) the brightness corresponding to the driving current.

[0094] The light emitting element LD of the light emitting unit EMU may emit light having a brightness corresponding to the driving current provided by the corresponding pixel circuit PXC. For example, the pixel circuit PXC may provide a driving current corresponding to the grayscale value of the corresponding frame data to the light emitting unit EMU during each frame period. The driving current provided to the light emitting unit EMU may be shunted to flow through each of the light emitting elements LD. Therefore, in the case where each light emitting element LD emits light having a brightness corresponding to the current flowing therethrough, the light emitting unit EMU may emit light with a brightness corresponding to the driving current.

[0095] The pixel circuit PXC may be connected to a scan line (e.g., an i-th scan line Si) and a data line (e.g., a j-th data line Dj) of a corresponding pixel PXL. In an example, the pixel PXL may be disposed on an i-th row and a j-th column of a display area DA, and the pixel circuit PXC of the pixel PXL may be connected to an i-th scan line Si and a j-th data line Dj of the display area DA. The pixel circuit PXC may be connected to an i-th control line CLi and a j-th sensing line SENj of the display area DA.

[0096] The pixel circuit PXC may include first, second and third transistors T1, T2 and T3 and a storage capacitor Cst.

[0097] The first transistor T1 may be a driving transistor for controlling a driving current applied to the light emitting unit EMU, and may be connected between the first driving power source VDD and the light emitting unit EMU. For example, the first terminal of the first transistor T1 may be connected (or coupled) to the first driving power source VDD via the first power line PL1, the second terminal of the first transistor T1 may be connected to the second node N2, and the gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control the amount of driving current applied to the light emitting unit EMU from the first driving power source VDD via the second node N2. In an embodiment, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode. However, the embodiment is not limited thereto. In some embodiments, the first terminal may be a source electrode, and the second terminal may be a drain electrode.

[0098] The second transistor T2 may be a switching transistor for selecting the pixel PXL in response to the scan signal and activating the pixel PXL, and may be connected between the j-th data line Dj and the first node N1. The first terminal of the second transistor T2 may be connected to the j-th data line Dj, the second terminal of the second transistor T2 may be connected to the first node N1, and the gate electrode of the second transistor T2 may be connected to the i-th scan line Si. The first terminal and the second terminal of the second transistor T2 may be different terminals. For example, in the case where the first terminal is a drain electrode, the second terminal may be a source electrode.

[0099] In the case where a scan signal having a gate-on voltage (e.g., a high level voltage) is supplied from the i-th scan line Si, the second transistor T2 may be turned on to electrically connect the j-th data line Dj and the first node N1 to each other. The first node N1 may be a point at which the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are connected to each other, and the second transistor T2 may transmit the data voltage to the gate electrode of the first transistor T1.

[0100] The third transistor T3 can connect the first transistor T1 to the j-th sensing line SENj to obtain (or acquire) a sensing signal through the j-th sensing line SENj, and use the sensing signal to detect the characteristics of each pixel PXL (including the threshold voltage of the first transistor T1, etc.). Information about the characteristics of each pixel PXL can be used to convert image data, so that the characteristic deviation between the pixels PXL can be compensated. The second terminal of the third transistor T3 can be connected to the second terminal of the first transistor T1, the first terminal of the third transistor T3 can be connected to the j-th sensing line SENj, and the gate electrode of the third transistor T3 can be connected to the i-th control line CLi.

[0101] The first terminal of the third transistor T3 may be connected to an initialization power source. The third transistor T3 may be an initialization transistor capable of initializing the second node N2, and may transmit a voltage of the initialization power source to the second node N2 when a sensing control signal is provided to the i-th control line CLi. Therefore, the second storage electrode (or upper electrode) of the storage capacitor Cst connected to the second node N2 may be initialized.

[0102] A first storage electrode of the storage capacitor Cst may be connected to the first node N1, and a second storage electrode of the storage capacitor Cst may be connected to the second node N2. The storage capacitor Cst may be charged with a data voltage corresponding to a data signal supplied to the first node N1 during one frame period. Therefore, the storage capacitor Cst may store a voltage corresponding to a difference between a voltage of the gate electrode of the first transistor T1 and a voltage of the second node N2.

[0103] Although already Figure 4, an embodiment in which the first transistor T1, the second transistor T2, and the third transistor T3 are all implemented with n-type transistors is shown, but the embodiment is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be changed to a p-type transistor. Figure 4 2 shows an embodiment in which the light emitting unit EMU is connected between the pixel circuit PXC and the second driving power source VSS, but the light emitting unit EMU may be connected between the first driving power source VDD and the pixel circuit PXC.

[0104] The structure of the pixel circuit PXC can be modified and implemented in various ways. In an example, the pixel circuit PXC may further include at least one transistor element (such as a transistor element for initializing the first node N1 and / or a transistor element for controlling the emission time of the light emitting element LD) or other circuit elements (such as a boost capacitor for increasing the voltage of the first node N1).

[0105] Figure 5 is a schematic plan view showing a pixel circuit area PXCA of a pixel PXL according to an embodiment. Figure 6 2 is a schematic plan view showing first to third pixels PXL1 to PXL3 according to an embodiment. Figure 6 In the figure, some components of the pixel PXL will be omitted for ease of description. Figure 7 and Figure 8 is a schematic plan view showing a pixel PXL according to an embodiment. In the example, Figure 7 and Figure 8 Any one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 is shown, and the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may have substantially the same or similar structures as each other. Figures 6 to 8 , each pixel PXL includes Figure 4 0 shows an embodiment of a light emitting element LD arranged in four series stages. However, in some embodiments, the number of series stages per pixel PXL may be variously changed.

[0106] Fig. 9 and Fig.10 It is along Figure 7 A schematic cross-sectional view taken along line AA′ shown in FIG. Fig.11 and Fig.12 It is along Figure 7 A schematic cross-sectional view taken along line BB′ shown in FIG. Fig.13 It is along Figure 8 A schematic cross-sectional view taken along line CC' shown in FIG. Fig.14 It is along Figure 8A schematic cross-sectional view taken along line DD′ shown in FIG.

[0107] refer to Figure 5 , the pixel circuit PXC may include a first pixel circuit PXC1 of a first pixel PXL1, a second pixel circuit PXC2 of a second pixel PXL2, and a third pixel circuit PXC3 of a third pixel PXL3. The first pixel circuit PXC1 may be provided (or arranged) in a first pixel circuit region PXCA1, the second pixel circuit PXC2 may be provided (or arranged) in a second pixel circuit region PXCA2, and the third pixel circuit PXC3 may be provided (or arranged) in a third pixel circuit region PXCA3.

[0108] The pixel PXL may include an insulating layer and a conductive layer. The insulating layer may include, for example, a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, a protective layer PSV and / or a through-hole layer VIA arranged in sequence. The conductive layer may be arranged and / or formed between the above-mentioned insulating layers. The conductive layer may include a first conductive layer arranged on the base layer BSL, a second conductive layer arranged on the gate insulating layer GI, a third conductive layer arranged on the interlayer insulating layer ILD and / or a fourth conductive layer arranged on the protective layer PSV. However, the insulating layer and the conductive layer are not limited to the above-mentioned embodiments. In some embodiments, in addition to the insulating layer and the conductive layer, another insulating layer and another conductive layer may also be included.

[0109] The conductive layer may include a signal line for driving the light emitting unit EMU. The signal line may include a first scan line S1, a second scan line S2, data lines D1, D2 and D3, a power line PL and / or an initialization power line IPL. In an embodiment, in order to improve the alignment of the light emitting element LD, in the step of aligning the light emitting element LD, the signal line may be connected to the electrode ( Figure 6 The ALE shown in Figure 1 provides an alignment voltage. This will be referred to later. Figures 17 to 34 Detailed description.

[0110] The scan signal and the control signal may be selectively applied to the first scan line S1. The first scan line S1 may extend along a first direction (e.g., an X-axis direction). The first scan line S1 may be formed by a third conductive layer formed on the interlayer insulating layer ILD. The third conductive layer may be formed as a single layer or multiple layers made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and any oxide or alloy thereof.

[0111] The first scan line S1 may be disposed on the connection line CNL to be connected to the connection line CNL through a contact hole. In an example, the first scan line S1 may be electrically connected to the connection line CNL through a contact hole passing through the interlayer insulating layer ILD.

[0112] The connection line CNL may be formed of a second conductive layer disposed and / or formed on the gate insulating layer GI. The second conductive layer and the third conductive layer may include the same material. The second conductive layer may include at least one material selected from materials such as the material of the third conductive layer.

[0113] In an embodiment, the connection line CNL may be integral with the second gate electrode GE2 of the second transistor T2 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. In an example, a portion of the connection line CNL may be the second gate electrode GE2 of the second transistor T2 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. Therefore, the connection line CNL may be connected to the second gate electrode GE2 of the second transistor T2 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3.

[0114] The connection line CNL may be integral with the third gate electrode GE3 of the third transistor T3 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. In an example, another portion of the connection line CNL may be the third gate electrode GE3 of the third transistor T3 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3. Therefore, the connection line CNL may be connected to the third gate electrode GE3 of the third transistor T3 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3.

[0115] As described above, since the connection line CNL is connected to the first scan line S1 through the contact hole, the first scan line S1 can be electrically connected to some components (e.g., the second transistor T2 and the third transistor T3) of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 through the connection line CNL. The first scan line S1 can provide a scan signal to the second transistor T2 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 during the driving period of the light emitting element LD, and provide a control signal to the third transistor T3 of each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 during the sensing period.

[0116] The connection line CNL may be a common component commonly provided for the first pixel circuit PXC1 , the second pixel circuit PXC2 , and the third pixel circuit PXC3 . In an example, the first pixel circuit PXC1 , the second pixel circuit PXC2 , and the third pixel circuit PXC3 may share a single connection line CNL.

[0117] The data lines D1, D2, and D3 may be spaced apart from each other along a first direction (e.g., an X-axis direction), and include a first data line D1, a second data line D2, and a third data line D3 extending in a second direction (e.g., a Y-axis direction) intersecting the first direction (e.g., the X-axis direction). A data signal may be applied to each of the first data line D1, the second data line D2, and the third data line D3. Each of the first data line D1, the second data line D2, and the third data line D3 may be a reference signal. Figure 4 Described is the j-th data line Dj.

[0118] The first data line D1 may be electrically connected to the second transistor T2 of the first pixel circuit PXC1, the second data line D2 may be electrically connected to the second transistor T2 of the second pixel circuit PXC2, and the third data line D3 may be electrically connected to the second transistor T2 of the third pixel circuit PXC3. The first data line D1, the second data line D2, and the third data line D3 may be formed by a first conductive layer disposed on the base layer BSL. The first conductive layer and the third conductive layer may include the same material. The first conductive layer may include at least one material selected from materials such as the material of the third conductive layer.

[0119] The power line PL may include a first power line PL1 and a second power line PL2. The first driving power source ( Figure 4 A voltage of VDD (shown in ) may be applied to the first power line PL1. The first power line PL1 may extend along the second direction (e.g., the Y-axis direction). In an embodiment, the first power line PL1 may include a first layer FL and a second layer SL. The first layer FL may be formed by a first conductive layer disposed and / or formed on the base layer BSL. The second layer SL may be formed by a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. The first layer FL and the first data line D1, the second data line D2, and the third data line D3 may be provided / disposed in the same layer (e.g., the first conductive layer) (or formed as the same layer (e.g., the first conductive layer)). The second layer SL and the first scan line S1 may be provided or disposed in the same layer (e.g., the third conductive layer) (or formed as the same layer (e.g., the third conductive layer)). The second layer SL may be electrically connected to the first layer FL through at least one contact hole. In an example, the second layer SL may be electrically connected to the first layer FL through at least one contact hole sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD.

[0120] The second driving power supply ( Figure 4 A voltage of VSS (shown in FIG. 1 ) may be applied to the second power line PL2. The second power line PL2 may include a vertical power line PL2_1 and a horizontal power line PL2_2.

[0121] The vertical power line PL2_1 may extend in a second direction (e.g., a Y-axis direction). The vertical power line PL2_1 may be implemented as a single-layer structure including a first layer FL. The first layer FL may be formed by a first conductive layer disposed and / or formed on a base layer BSL. The first layer FL of the first power line PL1 and the first data line D1, the second data line D2, and the third data line D3 may be provided / disposed in the same layer (e.g., a first conductive layer) (or formed as the same layer (e.g., a first conductive layer)). The first layer FL may be spaced apart from the first data line D1, the second data line D2, the third data line D3, and the first power line PL1 in a plan view.

[0122] The vertical power line PL2_1 and the horizontal power line PL2_2 may be electrically connected to each other through a contact hole. In an example, the horizontal power line PL2_2 may be electrically connected to the vertical power line PL2_1 through a contact hole that sequentially passes through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. The second power line PL2 including the vertical power line PL2_1 and the horizontal power line PL2_2 may have a mesh structure.

[0123] The second scan line S2 may extend in a second direction (e.g., a Y-axis direction) intersecting a first direction (e.g., an X-axis direction) as an extending direction of the first scan line S1. The second scan line S2 may at least partially overlap the first scan line S1 and intersect the first scan line S1. The second scan line S2 may provide a scan signal during a driving period of the light emitting element LD, and may provide a control signal during a sensing period.

[0124] In an embodiment, the second scan line S2 may include a (2-1)th scan line S2_1 and a (2-2)th scan line S2_2. Each of the (2-1)th scan line S2_1 and the (2-2)th scan line S2_2 may be disposed adjacent to the power line PL and spaced apart from the power line PL. In an example, the (2-1)th scan line S2_1 may be disposed adjacent to the first power line PL1 extending in the second direction (e.g., the Y-axis direction) and spaced apart from the first power line PL1. The (2-2)th scan line S2_2 may be disposed adjacent to the vertical power line PL2_1 extending in the second direction (e.g., the Y-axis direction) and spaced apart from the vertical power line PL2_1.

[0125] In an embodiment, each of the (2-1)th scan line S2_1 and the (2-2)th scan line S2_2 may be implemented as a three-layer structure including a first conductive line CL1, a second conductive line CL2, and a third conductive line CL3. The first conductive line CL1 may be formed of a first conductive layer disposed and / or formed on the base layer BSL, the second conductive line CL2 may be formed of a second conductive layer disposed and / or formed on the gate insulating layer GI, and the third conductive line CL3 may be formed of a third conductive layer disposed and / or formed on the interlayer insulating layer ILD.

[0126] The first conductive line CL1, the first data line D1, the second data line D2, and the third data line D3, the first layer FL of the first power line PL1, and the vertical power line PL2_1 of the second power line PL2 may be provided / set in the same layer (e.g., the first conductive layer) (or formed as the same layer (e.g., the first conductive layer)). The second conductive line CL2 and the connection line CNL may be provided / set in the same layer (e.g., the second conductive layer) (or formed as the same layer (e.g., the second conductive layer)). The third conductive line CL3 and the first scan line S1 and the second layer SL of the first power line PL1 may be provided / set in the same layer (e.g., the third conductive layer) (or formed as the same layer (e.g., the third conductive layer)). The third conductive line CL3 may be connected to each of the first conductive line CL1 and the second conductive line CL2 through a contact hole. In an example, the third conductive line CL3 may be electrically connected to the first conductive line CL1 through a contact hole sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. The third conductive line CL3 may be electrically connected to the second conductive line CL2 through a contact hole passing through the interlayer insulating layer ILD. Therefore, the first conductive line CL1 and the second conductive line CL2 may be connected to each other through the third conductive line CL3 .

[0127] In an embodiment, the third conductive line CL3 may be disposed and / or formed on the second conductive line CL2, and the interlayer insulating layer ILD is interposed between the second conductive line CL2 and the third conductive line CL3. The second conductive line CL2 may be disposed and / or formed on the first conductive line CL1, and the gate insulating layer GI and the buffer layer BFL are interposed between the first conductive line CL1 and the second conductive line CL2. The first conductive line CL1, the second conductive line CL2, and the third conductive line CL3 may overlap each other in a plan view and a cross-section.

[0128] In the embodiment, it has been described that the (2-1)th scan line S2_1 and the (2-2)th scan line S2_2 are implemented as a three-layer structure including a first conductive line CL1, a second conductive line CL2, and a third conductive line CL3. However, the embodiment is not limited thereto. In some embodiments, the (2-1)th scan line S2_1 and the (2-2)th scan line S2_2 may be implemented as a single-layer structure, a double-layer structure, or a multi-layer structure including three or more layers.

[0129] The initialization power line IPL may extend in the second direction (eg, the Y-axis direction) and be disposed between the first power line PL1 and the first data line D1. The initialization power line IPL may be a reference line. Figure 4 The j-th sensing line SENj described. The voltage of the initialization power supply may be applied to the initialization power line IPL. In an embodiment, the initialization power line IPL may be formed by a first conductive layer disposed and / or formed on the base layer BSL. The initialization power line IPL, the first data line D1, the second data line D2, and the third data line D3, the first layer FL of the first power line PL1, the vertical power line PL2_1 of the second power line PL2, and the first conductive line CL1 of the second scan line S2 may be provided / disposed in the same layer (e.g., the first conductive layer) (or formed as the same layer (e.g., the first conductive layer)).

[0130] The initialization power line IPL may be electrically connected to the third transistor T3 of the first pixel circuit PXC1 through the second conductive pattern CP2 and electrically connected to the third transistor T3 of each of the second and third pixel circuits PXC2 and PXC3 through the fifth conductive pattern CP5.

[0131] The second conductive pattern CP2 may be formed of a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. The second conductive pattern CP2 and the first scan line S1 may be provided / disposed in (or formed as) the same layer (eg, third conductive layer).

[0132] One end of the second conductive pattern CP2 may be connected to the initialization power line IPL through a contact hole. In an example, one end of the second conductive pattern CP2 may be electrically connected to the initialization power line IPL through a contact hole sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD.

[0133] The other end of the second conductive pattern CP2 may be connected to the third transistor T3 of the first pixel circuit PXC1 through a contact hole. In an example, the other end of the second conductive pattern CP2 may be electrically connected to the third drain region DE3 of the third transistor T3 of the first pixel circuit PXC1 through a contact hole sequentially passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0134] The fifth conductive pattern CP5 may be formed by a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. The fifth conductive pattern CP5 and the second conductive pattern CP2 may be provided / disposed in the same layer (eg, the third conductive layer) (or formed as the same layer (eg, the third conductive layer)).

[0135] One end of the fifth conductive pattern CP5 may be connected to the initialization power line IPL through a contact hole. In an example, one end of the fifth conductive pattern CP5 may be electrically connected to the initialization power line IPL through a contact hole sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD.

[0136] The other end of the fifth conductive pattern CP5 may be connected to the third transistor T3 of each of the second pixel circuit PXC2 and the third pixel circuit PXC3 through a contact hole. In an example, the other end of the fifth conductive pattern CP5 may be electrically connected to the third drain region DE3 of the third transistor T3 of each of the second pixel circuit PXC2 and the third pixel circuit PXC3 through a contact hole sequentially passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0137] The first power line PL1, the second power line PL2, the initialization power line IPL, the connection line CNL, the first scan line S1 and the second scan line S2 described above may be common components commonly provided (or set) in the first pixel circuit PXC1, the second pixel circuit PXC2 and the third pixel circuit PXC3.

[0138] Each of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. In an example, the first pixel circuit PXC1 may include a first transistor T1, a second transistor T2, and a third transistor T3, and a first storage capacitor Cst1. The second pixel circuit PXC2 may include a first transistor T1, a second transistor T2, and a third transistor T3, and a second storage capacitor Cst2. The third pixel circuit PXC3 may include a first transistor T1, a second transistor T2, and a third transistor T3, and a third storage capacitor Cst3.

[0139] The first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may have structures that are substantially similar or identical to each other. Hereinafter, the first pixel circuit PXC1 among the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 will be mainly described, and the second pixel circuit PXC2 and the third pixel circuit PXC3 will be briefly described.

[0140] The first pixel circuit PXC1 may include a first transistor T1 , a second transistor T2 , a third transistor T3 , and a first storage capacitor Cst1 .

[0141] The first transistor T1 may include a first gate electrode GE1 , a first active pattern ACT1 , a first source region SE1 , and a first drain region DE1 .

[0142] The first gate electrode GE1 may be connected to the second source region SE2 of the second transistor T2 through the first conductive pattern CP1. The first gate electrode GE1 may be formed of a second conductive layer disposed and / or formed on the gate insulating layer GI. The first gate electrode GE1 and the connection line CNL may be provided / disposed in the same layer (e.g., the second conductive layer) (or formed as the same layer (e.g., the second conductive layer)).

[0143] The first conductive pattern CP1 may be formed by the third conductive layer. One end of the first conductive pattern CP1 may be connected to the first gate electrode GE1 through a contact hole. In an example, one end of the first conductive pattern CP1 may be electrically connected to the first gate electrode GE1 through a contact hole passing through the interlayer insulating layer ILD. The other end of the first conductive pattern CP1 may be connected to the second source region SE2 through a contact hole. In an example, the other end of the first conductive pattern CP1 may be electrically connected to the second source region SE2 through a contact hole passing through the gate insulating layer GI and the interlayer insulating layer ILD in sequence.

[0144] Each of the first active pattern ACT1, the first source region SE1, and the first drain region DE1 may be a semiconductor pattern made of polysilicon, amorphous silicon, an oxide semiconductor, etc. Each of the first active pattern ACT1, the first source region SE1, and the first drain region DE1 may be formed of a semiconductor layer that is not doped with impurities or doped with impurities. In an example, each of the first source region SE1 and the first drain region DE1 may be formed of a semiconductor layer that is not doped with impurities, and the first active pattern ACT1 may be formed of a semiconductor layer that is not doped with impurities. In an example, n-type impurities may be used as impurities.

[0145] The first active pattern ACT1 , the first source region SE1 , and the first drain region DE1 may be disposed and / or formed on the buffer layer BFL.

[0146] The first active pattern ACT1 may be a region overlapping the first gate electrode GE1 and may be a channel region of the first transistor T1. In the case where the first active pattern ACT1 is formed to be long, the channel region of the first transistor T1 may be formed to be long. The driving range of the voltage applied to the first transistor T1 may be widened. Therefore, the gray level of the light (or light) emitted from the light emitting element LD may be finely controlled.

[0147] The first source region SE1 may be connected to (or in contact with) one end of the first active pattern ACT1 . The first source region SE1 may be electrically connected to the first lower conductive layer BML1 through a contact hole passing through the buffer layer BFL.

[0148] The first lower conductive layer BML1 may be formed of a first conductive layer disposed and / or formed on the base layer BSL. The first lower conductive layer BML1, the first data line D1, the second data line D2, and the third data line D3, the first power line PL1, the vertical power line PL2_1, the first conductive line CL1 of the second scan line S2, and the initialization power line IPL may be provided / disposed in the same layer (e.g., the first conductive layer) (or formed as the same layer (e.g., the first conductive layer)). The first lower conductive layer BML1 may be electrically connected to the first source region SE1 through a contact hole. In the case where the first lower conductive layer BML1 is connected to the first transistor T1, the swing width margin of the second driving power supply VSS may be further ensured. The driving range of the voltage supplied to the first gate electrode GE1 of the first transistor T1 may be widened.

[0149] The first drain region DE1 may be connected to (or in contact with) the other end of the first active pattern ACT1. The first drain region DE1 may be connected to the first power line PL1 through a contact hole. In an example, the first drain region DE1 may be electrically connected to the first layer FL of the first power line PL1 through a contact hole passing through the buffer layer BFL.

[0150] The second transistor T2 may include a second gate electrode GE2 , a second active pattern ACT2 , a second source region SE2 , and a second drain region DE2 .

[0151] The second gate electrode GE2 may be integral with the connection line CNL. The second gate electrode GE2 may be a region of the connection line CNL. As described above, since the connection line CNL is connected to the first scan line S1 through the contact hole, a signal (eg, a scan signal) applied to the first scan line S1 may be ultimately provided to the second gate electrode GE2.

[0152] Each of the second active pattern ACT2, the second source region SE2, and the second drain region DE2 may be a semiconductor pattern made of polysilicon, amorphous silicon, an oxide semiconductor, etc. Each of the second active pattern ACT2, the second source region SE2, and the second drain region DE2 may be formed of a semiconductor layer that is not doped with impurities or doped with impurities. In an example, each of the second source region SE2 and the second drain region DE2 may be formed of a semiconductor layer doped with impurities, and the second active pattern ACT2 may be formed of a semiconductor layer that is not doped with impurities. In an example, n-type impurities may be used as impurities.

[0153] The second active pattern ACT2 , the second source region SE2 , and the second drain region DE2 may be disposed and / or formed on the buffer layer BFL.

[0154] The second active pattern ACT2 may be a region overlapping the second gate electrode GE2 and may be a channel region of the second transistor T2 .

[0155] The second source region SE2 may be connected to (or in contact with) one end portion of the second active pattern ACT2 . The second source region SE2 may be connected to the first gate electrode GE1 through the first conductive pattern CP1 .

[0156] The second drain region DE2 may be connected to (or in contact with) the other end of the second active pattern ACT2. The second drain region DE2 may be connected to the first data line D1 through the third conductive pattern CP3.

[0157] The third conductive pattern CP3 may be formed by a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. One end of the third conductive pattern CP3 may be electrically connected to the first data line D1 through a contact hole that sequentially passes through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. The other end of the third conductive pattern CP3 may be connected to the second drain region DE2 through a contact hole that sequentially passes through the gate insulating layer GI and the interlayer insulating layer ILD. The second drain region DE2 and the first data line D1 may be electrically connected to each other through the third conductive pattern CP3.

[0158] The third transistor T3 may include a third gate electrode GE3 , a third active pattern ACT3 , a third source region SE3 , and a third drain region DE3 .

[0159] The third gate electrode GE3 may be integrated with the connection line CNL. The third gate electrode GE3 may be another region of the connection line CNL. As described above, since the connection line CNL is connected to the first scan line S1 through the contact hole, a signal (eg, a control signal) applied to the first scan line S1 may be ultimately provided to the third gate electrode GE3.

[0160] Each of the third active pattern ACT3, the third source region SE3, and the third drain region DE3 may be a semiconductor pattern made of polysilicon, amorphous silicon, an oxide semiconductor, etc. Each of the third active pattern ACT3, the third source region SE3, and the third drain region DE3 may be formed of a semiconductor layer that is not doped with impurities or doped with impurities. In an example, each of the third source region SE3 and the third drain region DE3 may be formed of a semiconductor layer that is not doped with impurities, and the third active pattern ACT3 may be formed of a semiconductor layer that is not doped with impurities. In an example, n-type impurities may be used as impurities.

[0161] The third active pattern ACT3 , the third source region SE3 , and the third drain region DE3 may be disposed and / or formed on the buffer layer BFL.

[0162] The third active pattern ACT3 may be a region overlapped with the third gate electrode GE3 and may be a channel region of the third transistor T3 .

[0163] The third source region SE3 may be connected to (or in contact with) one end portion of the third active pattern ACT3. The third source region SE3 may be electrically connected to the first lower conductive layer BML1 through a contact hole passing through the buffer layer BFL.

[0164] The third drain region DE3 may be connected to (or in contact with) the other end of the third active pattern ACT3. The third drain region DE3 may be electrically connected to the initialization power line IPL through the second conductive pattern CP2.

[0165] The first storage capacitor Cst1 may include a first lower electrode LE1 and a first upper electrode UE1. The first storage capacitor Cst1 may be a reference Figure 4 The storage capacitor Cst is described.

[0166] The first lower electrode LE1 may be integral with the first gate electrode GE1. In an example, the first lower electrode LE1 may be a region of the first gate electrode GE1.

[0167] The first upper electrode UE1 may be disposed on the first lower electrode LE1 and overlap the first lower electrode LE1 in a plan view and have a size (or area) larger than that of the first lower electrode LE1. However, the embodiment is not limited thereto. The first upper electrode UE1 may overlap each of the first source region SE1 and the third source region SE3 in a plan view. The first upper electrode UE1 may be formed by a third conductive layer disposed and / or formed on the interlayer insulating layer ILD.

[0168] The first upper electrode UE1 may be electrically connected to the first lower conductive layer BML1 through a contact hole sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. As described above, since the first source region SE1 and the third source region SE3 are electrically connected to the first lower conductive layer BML1, the first upper electrode UE1 may be electrically connected to the first source region SE1 and the third source region SE3 through the first lower conductive layer BML1.

[0169] The second pixel circuit PXC2 may include a first transistor T1, a second transistor T2, a third transistor T3, and a second storage capacitor Cst2.

[0170] The first transistor T1 may include a first gate electrode GE1 , a first active pattern ACT1 , a first source region SE1 , and a first drain region DE1 .

[0171] The first gate electrode GE1 may be connected to the second source region SE2 of the second transistor T2 .

[0172] The first active pattern ACT1 may be a channel region of the first transistor T1 .

[0173] The first source region SE1 may be connected to the first active pattern ACT1. The first source region SE1 may be electrically connected to the second lower conductive layer BML2 through a contact hole passing through the buffer layer BFL.

[0174] The second lower conductive layer BML2 may be a component corresponding to the first lower conductive layer BML1. The second lower conductive layer BML2 may be formed of a first conductive layer disposed and / or formed on the base layer BSL. The second lower conductive layer BML2 may be electrically connected to the first source region SE1 through a contact hole. The second lower conductive layer BML2 may be electrically connected to the third source region SE3 of the third transistor T3 through a contact hole passing through the buffer layer BFL. The second lower conductive layer BML2 may be electrically connected to the second upper electrode UE2 of the second storage capacitor Cst2 through a contact hole passing through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD in sequence.

[0175] The first drain region DE1 may be connected to the first active pattern ACT1. The first drain region DE1 may be electrically connected to the first layer FL of the first power line PL1 through a contact hole passing through the buffer layer BFL.

[0176] The second transistor T2 may include a second gate electrode GE2 , a second active pattern ACT2 , a second source region SE2 , and a second drain region DE2 .

[0177] The second gate electrode GE2 may be integrated with the connection line CNL and connected to the first scan line S1 .

[0178] The second active pattern ACT2 may be a channel region of the second transistor T2 .

[0179] The second source region SE2 may be connected to the second active pattern ACT2. The second source region SE2 may be connected to the first gate electrode GE1 through the seventh conductive pattern CP7.

[0180] The seventh conductive pattern CP7 may be formed by a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. One end of the seventh conductive pattern CP7 may be electrically connected to the second source region SE2 through a contact hole sequentially passing through the gate insulating layer GI and the interlayer insulating layer ILD. The other end of the seventh conductive pattern CP7 may be connected to the first gate electrode GE1 through a contact hole passing through the interlayer insulating layer ILD.

[0181] The second drain region DE2 may be connected to the second active pattern ACT2. The second drain region DE2 may be connected to the second data line D2 through the eighth conductive pattern CP8.

[0182] The eighth conductive pattern CP8 may be formed by a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. One end of the eighth conductive pattern CP8 may be electrically connected to the second data line D2 through a contact hole sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. The other end of the eighth conductive pattern CP8 may be electrically connected to the second drain region DE2 through a contact hole sequentially passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0183] The third transistor T3 may include a third gate electrode GE3 , a third active pattern ACT3 , a third source region SE3 , and a third drain region DE3 .

[0184] The third gate electrode GE3 may be integrated with the connection line CNL and connected to the first scan line S1 .

[0185] The third active pattern ACT3 may be a channel region of the third transistor T3 .

[0186] The third source region SE3 may be connected to the third active pattern ACT3 The third source region SE3 may be electrically connected to the second lower conductive layer BML2.

[0187] The third drain region DE3 may be connected to the third active pattern ACT3. The third drain region DE3 may be connected to the initialization power line IPL through the fifth conductive pattern CP5.

[0188] The second storage capacitor Cst2 may have a structure that is the same as or substantially similar to that of the first storage capacitor Cst1 of the first pixel circuit PXC1 described above. In an example, the second storage capacitor Cst2 may include a second lower electrode LE2 and a second upper electrode UE2.

[0189] The second lower electrode LE2 may be a second conductive layer and may be integrated with a corresponding transistor (eg, the first gate electrode GE1 of the first transistor T1). The second upper electrode UE2 may be a third conductive layer and may overlap with the second lower electrode LE2. The second upper electrode UE2 may be electrically connected to the second lower conductive layer BML2 through a contact hole.

[0190] As described above, the second upper electrode UE2 may be electrically connected to each of the first and third source regions SE1 and SE3 through the second lower conductive layer BML2 .

[0191] The third pixel circuit PXC3 may include first, second, and third transistors T1, T2, and T3, and a third storage capacitor Cst3.

[0192] The first transistor T1 may include a first gate electrode GE1 , a first active pattern ACT1 , a first source region SE1 , and a first drain region DE1 .

[0193] The first gate electrode GE1 may be connected to the second source region SE2 of the second transistor T2 .

[0194] The first active pattern ACT1 may be a channel region of the first transistor T1 .

[0195] The first source region SE1 may be connected to the first active pattern ACT1. The first source region SE1 may be electrically connected to the third lower conductive layer BML3 through a contact hole passing through the buffer layer BFL.

[0196] The third lower conductive layer BML3 may be a component corresponding to each of the first lower conductive layer BML1 and the second lower conductive layer BML2. The third lower conductive layer BML3 may be formed of the first conductive layer. The third lower conductive layer BML3 may be electrically connected to the first source region SE1 through a contact hole. The third lower conductive layer BML3 may be electrically connected to the third source region SE3 of the third transistor T3 through a contact hole passing through the buffer layer BFL. For example, the third lower conductive layer BML3 may be electrically connected to the third upper electrode UE3 of the third storage capacitor Cst3 through a contact hole passing through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD in sequence.

[0197] The first drain region DE1 may be connected to the first active pattern ACT1. The first drain region DE1 may be electrically connected to the first layer FL of the first power line PL1 through a contact hole passing through the buffer layer BFL.

[0198] The second transistor T2 may include a second gate electrode GE2 , a second active pattern ACT2 , a second source region SE2 , and a second drain region DE2 .

[0199] The second gate electrode GE2 may be integrated with the connection line CNL to be connected to the first scan line S1 .

[0200] The second active pattern ACT2 may be a channel region of the second transistor T2 .

[0201] The second source region SE2 may be connected to the second active pattern ACT2. The second source region SE2 may be connected to the first gate electrode GE1 through the fourth conductive pattern CP4.

[0202] The fourth conductive pattern CP4 may be formed by a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. One end of the fourth conductive pattern CP4 may be electrically connected to the second source region SE2 through a contact hole that sequentially passes through the gate insulating layer GI and the interlayer insulating layer ILD. The other end of the fourth conductive pattern CP4 may be connected to the first gate electrode GE1 through a contact hole that passes through the interlayer insulating layer ILD. Therefore, the first gate electrode GE1 and the second source region SE2 may be connected to each other through the fourth conductive pattern CP4.

[0203] The second drain region DE2 may be connected to the second active pattern ACT2. The second drain region DE2 may be connected to the third data line D3 through the sixth conductive pattern CP6.

[0204] The sixth conductive pattern CP6 may be formed by a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. One end of the sixth conductive pattern CP6 may be electrically connected to the third data line D3 through a contact hole that sequentially passes through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. The other end of the sixth conductive pattern CP6 may be electrically connected to the second drain region DE2 through a contact hole that sequentially passes through the gate insulating layer GI and the interlayer insulating layer ILD. Therefore, the second drain region DE2 and the third data line D3 may be connected to each other through the sixth conductive pattern CP6.

[0205] The third transistor T3 may include a third gate electrode GE3 , a third active pattern ACT3 , a third source region SE3 , and a third drain region DE3 .

[0206] The third gate electrode GE3 may be integrated with the connection line CNL and connected to the first scan line S1 .

[0207] The third active pattern ACT3 may be a channel region of the third transistor T3 .

[0208] The third source region SE3 may be connected to the third active pattern ACT3. The third source region SE3 may be electrically connected to the third lower conductive layer BML3 through a contact hole.

[0209] The third drain region DE3 may be connected to the third active pattern ACT3. The third drain region DE3 may be connected to the initialization power line IPL through the fifth conductive pattern CP5. In an embodiment, the third drain region DE3 of the third transistor T3 and the second drain region DE2 of the second transistor T2 may share the fifth conductive pattern CP5.

[0210] The third storage capacitor Cst3 may have a structure that is the same as or substantially similar to that of each of the first storage capacitor Cst1 and the second storage capacitor Cst2. In an example, the third storage capacitor Cst3 may include a third lower electrode LE3 and a third upper electrode UE3.

[0211] The third lower electrode LE3 may be a second conductive layer and may be integrated with a corresponding transistor (eg, the first gate electrode GE1 of the first transistor T1). The third upper electrode UE3 may be a third conductive layer and may overlap with the third lower electrode LE3. The third upper electrode UE3 may be electrically connected to the third lower conductive layer BML3 through a contact hole.

[0212] As described above, the third upper electrode UE3 may be electrically connected to each of the first source region SE1 and the third source region SE3 through the third lower conductive layer BML3 .

[0213] refer to Figures 6 to 8, each pixel PXL may include an emission area EA and a non-emission area NEA. The emission area EA may be a region including a light emitting element LD to emit light. The non-emission area NEA may surround the emission area EA. The non-emission area NEA may be a region in which a bank BNK surrounding the emission area EA is provided. The bank BNK may be provided (or provided) in the non-emission area NEA to at least partially surround the emission area EA.

[0214] The bank BNK may include an opening overlapping the emission area EA. The opening of the bank BNK may provide a space in which the light emitting element LD is provided (or disposed) in a process of providing the light emitting element LD to each pixel PXL. For example, a designed type and / or designed amount of light emitting element ink may be provided to the space separated by the opening of the bank BNK.

[0215] The bank BNK may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the embodiment is not limited thereto, and the bank BNK may include various kinds of inorganic insulating materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0216] In some embodiments, the bank BNK may include at least one light blocking material and / or at least one reflective material. Thus, light leakage between adjacent pixels PXL may be prevented. For example, the bank BNK may include at least one black pigment.

[0217] Each pixel PXL may include a definition wall (or partition wall) WL, an electrode ALE, a light emitting element LD, and / or a connection electrode ELT.

[0218] The defining walls WL may overlap the emission area EA and be spaced apart from each other. The defining walls WL may be at least partially disposed in the non-emission area NEA. The defining walls WL may extend along the second direction (e.g., the Y-axis direction) and be spaced apart from each other along the first direction (e.g., the X-axis direction).

[0219] Each of the defining walls WL may partially overlap with at least one electrode ALE in at least the emission area EA. For example, the defining wall WL may be disposed on the bottom surface of the electrode ALE. Since the defining wall WL is disposed on the bottom surface of the region of each of the electrodes ALE, the region of each of the electrodes ALE may protrude in the upper direction (i.e., the third direction (e.g., the Z-axis direction)) in the region where the defining wall WL is formed. In the case where the defining wall WL and / or the electrode ALE include a reflective material, a reflective wall structure may be formed at the periphery of the light emitting element LD. Therefore, the light emitted from the light emitting element LD may be emitted in the upper direction of the pixel PXL (e.g., the front direction of the display panel PNL including the viewing angle range), and thus the light emitting efficiency of the display panel PNL may be improved.

[0220] The electrodes ALE may be provided (or disposed) in at least the emission area EA. The electrodes ALE may extend along the second direction (eg, the Y-axis direction) and be spaced apart from each other along the first direction (eg, the X-axis direction).

[0221] Each of the first electrode ALE1, the second electrode ALE2, and the third electrode ALE3 may extend along the second direction (eg, the Y-axis direction), and the first electrode ALE1, the second electrode ALE2, and the third electrode ALE3 may be spaced apart from each other along the first direction (eg, the X-axis direction) to be sequentially arranged.

[0222] In the process of aligning the light emitting element LD, a pair of electrodes ALE adjacent to each other may receive different alignment voltages. For example, when the first electrode ALE1, the second electrode ALE2, and the third electrode ALE3 are sequentially arranged along a first direction (e.g., an X-axis direction), the first electrode ALE1 and the second electrode ALE2 may receive different alignment voltages, and the second electrode ALE2 and the third electrode ALE3 may receive different alignment voltages.

[0223] Each of the light emitting elements LD may be aligned between the pair of electrodes ALE in the emission area EA. Each of the light emitting elements LD may be electrically connected between the pair of connection electrodes ELT.

[0224] The first light emitting element LD1 may be aligned between the first electrode ALE1 and the second electrode ALE2. The first light emitting element LD1 may be electrically connected between the first connection electrode ELT1 and the second connection electrode ELT2. In an example, the first light emitting element LD1 may be aligned in a first region (e.g., an upper region) of the first electrode ALE1 and the second electrode ALE2. The first end EP1 of the first light emitting element LD1 may be electrically connected to the first connection electrode ELT1, and the second end EP2 of the first light emitting element LD1 may be electrically connected to the second connection electrode ELT2.

[0225] The second light emitting element LD2 may be aligned between the first electrode ALE1 and the second electrode ALE2. The second light emitting element LD2 may be electrically connected between the second connection electrode ELT2 and the third connection electrode ELT3. In an example, the second light emitting element LD2 may be aligned in a second region (e.g., a lower end region) of the first electrode ALE1 and the second electrode ALE2. The first end EP1 of the second light emitting element LD2 may be electrically connected to the second connection electrode ELT2, and the second end EP2 of the second light emitting element LD2 may be electrically connected to the third connection electrode ELT3.

[0226] The third light emitting element LD3 may be aligned between the second electrode ALE2 and the third electrode ALE3. The third light emitting element LD3 may be electrically connected between the third connection electrode ELT3 and the fourth connection electrode ELT4. In an example, the third light emitting element LD3 may be aligned in a second region (e.g., a lower end region) of the second electrode ALE2 and the third electrode ALE3. The first end EP1 of the third light emitting element LD3 may be electrically connected to the third connection electrode ELT3, and the second end EP2 of the third light emitting element LD3 may be electrically connected to the fourth connection electrode ELT4.

[0227] The fourth light emitting element LD4 may be aligned between the second electrode ALE2 and the third electrode ALE3. The fourth light emitting element LD4 may be electrically connected between the fourth connection electrode ELT4 and the fifth connection electrode ELT5. In an example, the fourth light emitting element LD4 may be aligned in a first region (e.g., an upper region) of the second electrode ALE2 and the third electrode ALE3. The first end EP1 of the fourth light emitting element LD4 may be electrically connected to the fourth connection electrode ELT4, and the second end EP2 of the fourth light emitting element LD4 may be electrically connected to the fifth connection electrode ELT5.

[0228] In the example, the first light emitting element LD1 may be disposed in the upper left region of the emission area EA, and the second light emitting element LD2 may be disposed in the lower left region of the emission area EA. The third light emitting element LD3 may be disposed in the lower right region of the emission area EA, and the fourth light emitting element LD4 may be disposed in the upper right region of the emission area EA. However, the arrangement and / or connection structure of the light emitting elements LD may be variously changed according to the structure of the light emitting unit EMU and / or the number of series stages.

[0229] Each of the connection electrodes ELT may be provided (or arranged) in at least the emission area EA and overlap with at least one electrode ALE and / or at least one light emitting element LD. For example, each of the connection electrodes ELT may be formed on the electrode ALE and / or the light emitting element LD to overlap with the electrode ALE and / or the light emitting element LD. Therefore, each of the connection electrodes ELT may be electrically connected to the light emitting element LD.

[0230] The first connection electrode ELT1 may be disposed on a first region (eg, an upper end region) of the first electrode ALE1 and the first end portion EP1 of the first light emitting element LD1 to be electrically connected to the first end portion EP1 of the first light emitting element LD1.

[0231] The second connection electrode ELT2 may be disposed on a first region (e.g., an upper region) of the second electrode ALE2 and a second end portion EP2 of the first light emitting element LD1 to be electrically connected to the second end portion EP2 of the first light emitting element LD1. In addition, the second connection electrode ELT2 may be disposed on a second region (e.g., a lower region) of the first electrode ALE1 and a first end portion EP1 of the second light emitting element LD2 to be electrically connected to the first end portion EP1 of the second light emitting element LD2. For example, the second connection electrode ELT2 may electrically connect the second end portion EP2 of the first light emitting element LD1 and the first end portion EP1 of the second light emitting element LD2 to each other in the emission area EA. For example, the second connection electrode ELT2 may have a curved shape. For example, the second connection electrode ELT2 may have a structure that is bent or curved at a boundary between a region in which at least one first light emitting element LD1 is disposed and a region in which at least one second light emitting element LD2 is disposed.

[0232] The third connection electrode ELT3 may be disposed on the second region (e.g., the lower end region) of the second electrode ALE2 and the second end EP2 of the second light emitting element LD2 to be electrically connected to the second end EP2 of the second light emitting element LD2. In addition, the third connection electrode ELT3 may be disposed on the second region (e.g., the lower end region) of the third electrode ALE3 and the first end EP1 of the third light emitting element LD3 to be electrically connected to the first end EP1 of the third light emitting element LD3. For example, the third connection electrode ELT3 may electrically connect the second end EP2 of the second light emitting element LD2 and the first end EP1 of the third light emitting element LD3 to each other in the emission area EA. For example, the third connection electrode ELT3 may have a curved shape. For example, the third connection electrode ELT3 may have a structure that is bent or curved at a boundary between a region in which at least one second light emitting element LD2 is arranged and a region in which at least one third light emitting element LD3 is arranged.

[0233] The fourth connection electrode ELT4 may be disposed on the second region (e.g., the lower end region) of the second electrode ALE2 and the second end EP2 of the third light emitting element LD3 to be electrically connected to the second end EP2 of the third light emitting element LD3. In addition, the fourth connection electrode ELT4 may be disposed on the first region (e.g., the upper end region) of the third electrode ALE3 and the first end EP1 of the fourth light emitting element LD4 to be electrically connected to the first end EP1 of the fourth light emitting element LD4. For example, the fourth connection electrode ELT4 may electrically connect the second end EP2 of the third light emitting element LD3 and the first end EP1 of the fourth light emitting element LD4 to each other in the emission area EA. For example, the fourth connection electrode ELT4 may have a curved shape. For example, the fourth connection electrode ELT4 may have a structure that is bent or curved at a boundary between a region in which at least one third light emitting element LD3 is disposed and a region in which at least one fourth light emitting element LD4 is disposed.

[0234] The fifth connection electrode ELT5 may be disposed on the first region (eg, upper end region) of the second electrode ALE2 and the second end portion EP2 of the fourth light emitting element LD4 to be electrically connected to the second end portion EP2 of the fourth light emitting element LD4.

[0235] The first connection electrode ELT1, the third connection electrode ELT3 and / or the fifth connection electrode ELT5 may be formed of the same conductive layer. The second connection electrode ELT2 and the fourth connection electrode ELT4 may be formed of the same conductive layer. Figure 7 For example, the first connection electrode ELT1, the third connection electrode ELT3 and / or the fifth connection electrode ELT5 may be formed of a fifth conductive layer, and the second connection electrode ELT2 and the fourth connection electrode ELT4 may be formed of a sixth conductive layer different from the fifth conductive layer. In another example, Figure 8 As shown in FIG. 1 , the first connection electrode ELT1 , the second connection electrode ELT2 , the third connection electrode ELT3 , the fourth connection electrode ELT4 , and the fifth connection electrode ELT5 may be formed of the same conductive layer.

[0236] In the above manner, the light emitting elements LD aligned between the electrodes ALE can be connected in a designed form by using the connecting electrode ELT. For example, the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3 and the fourth light emitting element LD4 can be connected in series in sequence by using the connecting electrode ELT.

[0237] In the following, reference will be made to Figures 9 to 14 The cross-sectional structure of the pixel PXL is described in detail. Fig. 9 , Fig.10 and Fig.13, a pixel circuit is shown ( Figure 4 The first transistor T1 of the first to third transistors T1 to T3 will be described representatively, and the second transistor T2 and the third transistor T3 will be described briefly. The structure of the first transistor T1 for each layer and / or the position of the first transistor T1 for each layer are not limited to Fig. 9 , Fig.10 and Fig.13 The embodiments shown in FIG. 1 and various changes may be made in some embodiments.

[0238] Each pixel PXL according to an embodiment may include a circuit element including a first transistor T1 disposed on the base layer BSL and various lines connected to the first transistor T1. The electrode ALE forming the light emitting unit EMU, the light emitting element LD and / or the connection electrode ELT may be disposed above the circuit element.

[0239] The base layer BSL can be used to form a base member, and can be a rigid or flexible substrate or film. In an example, the base layer BSL can be a rigid substrate made of glass or tempered glass, a flexible substrate (or film) made of a plastic or metal material, or at least one insulating layer. The material and / or properties of the base layer BSL are not limited thereto. In an embodiment, the base layer BSL may be substantially transparent. The term "substantially transparent" may mean transmitting light with a certain transmittance or greater. In another embodiment, the base layer BSL may be translucent or opaque. In addition, in some embodiments, the base layer BSL may include a reflective material.

[0240] The first lower conductive layer BML1 and the vertical power line PL2_1 of the second power line PL2 may be disposed on the base layer BSL. The first lower conductive layer BML1 and the vertical power line PL2_1 may be disposed in the same layer (or formed as the same layer). For example, the first lower conductive layer BML1 and the vertical power line PL2_1 may be formed simultaneously by the same process, but the embodiment is not limited thereto.

[0241] Each of the first lower conductive layer BML1 and the vertical power line PL2_1 can be formed as a single layer or a multilayer made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and any oxide or alloy thereof.

[0242] The buffer layer BFL may be disposed on the first lower conductive layer BML1 and the vertical power line PL2_1. The buffer layer BFL may prevent impurities from diffusing into each circuit element. The buffer layer BFL may be formed as a single layer, but may also be formed as a multilayer including at least two layers. In the case where the buffer layer BFL is provided as a multilayer, the layers may be formed of the same material or of different materials.

[0243] The first active pattern ACT1 may be disposed on the buffer layer BFL. The first active pattern ACT1 may be made of polysilicon, amorphous silicon, an oxide semiconductor, or the like.

[0244] The gate insulating layer GI may be disposed on the buffer layer BFL and the first active pattern ACT1. In an example, the gate insulating layer GI may be disposed between the first active pattern ACT1 of the first transistor T1 and the first gate electrode GE1. The gate insulating layer GI may be formed as a single layer or multiple layers and include various kinds of inorganic insulating materials, including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0245] The first gate electrode GE1 of the first transistor T1 may be disposed on the gate insulating layer GI. The first gate electrode GE1 may be disposed on the gate insulating layer GI to overlap the first active pattern ACT1 in a third direction (eg, Z-axis direction).

[0246] The first gate electrode GE1 may be formed as a single layer or multiple layers made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and any oxide or alloy thereof. For example, the first gate electrode GE1 may be formed as a multilayer in which titanium (Ti), copper (Cu), and / or indium tin oxide (ITO) are sequentially stacked or repeatedly stacked.

[0247] An interlayer insulating layer ILD may be disposed on the first gate electrode GE1. In an example, the interlayer insulating layer ILD may be disposed between the first gate electrode GE1 and the first and second transistor electrodes TE1 and TE2.

[0248] The interlayer insulating layer ILD may be formed as a single layer or multiple layers and include various kinds of inorganic insulating materials, including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0249] The first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 and the horizontal power line PL2_2 of the second power line PL2 may be disposed on the interlayer insulating layer ILD. The first transistor electrode TE1 and the second transistor electrode TE2 and the horizontal power line PL2_2 may be disposed in the same layer (or formed as the same layer). For example, the first transistor electrode TE1 and the second transistor electrode TE2 and the horizontal power line PL2_2 may be formed simultaneously by the same process, but the embodiment is not limited thereto.

[0250] The first transistor electrode TE1 and the second transistor electrode TE2 may overlap with the first active layer ACT1' in a third direction (e.g., the Z-axis direction), wherein the first active layer ACT1' may include a first source region, a first drain region, and a first channel region. The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to the first active layer ACT1'. For example, the first transistor electrode TE1 may be electrically connected to a region (e.g., the first source region) of the first active layer ACT1' through a contact hole passing through the interlayer insulating layer ILD. The first transistor electrode TE1 may be electrically connected to the first lower conductive layer BML1 through a contact hole passing through the interlayer insulating layer ILD and the buffer layer BFL. The second transistor electrode TE2 may be electrically connected to other regions (e.g., the first drain region) of the first active layer ACT1' through a contact hole passing through the interlayer insulating layer ILD.

[0251] The horizontal power line PL2_2 may overlap the vertical power line PL2_1 in a third direction (eg, Z-axis direction). The horizontal power line PL2_2 may be electrically connected to the vertical power line PL2_1. For example, the horizontal power line PL2_2 may be electrically connected to the vertical power line PL2_1 through a contact hole passing through the interlayer insulating layer ILD and the buffer layer BFL.

[0252] The first transistor electrode TE1 and the second transistor electrode TE2 and the horizontal power line PL2_2 can be formed as a single layer or a multilayer made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn) and any oxide or alloy thereof.

[0253] The protective layer PSV may be disposed on the first and second transistor electrodes TE1 and TE2 and the horizontal power line PL2_2. The protective layer PSV may be formed as a single layer or multiple layers and include various kinds of inorganic insulating materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0254] The via layer VIA may be disposed on the protective layer PSV. The via layer VIA may be made of an organic material to flatten the step difference at the lower portion. For example, the via layer VIA may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the embodiment is not limited thereto, and the via layer VIA may include various kinds of inorganic insulating materials, including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0255] The defining wall WL may be disposed on the via layer VIA. The defining wall WL may play a role in forming a step difference so that the light emitting element LD may be easily aligned in the emission area EA.

[0256] In some embodiments, the defining wall WL may have various shapes. In an embodiment, the defining wall WL may have a shape protruding in a third direction (e.g., Z-axis direction) on the base layer BSL. The defining wall WL may be formed to have an inclined surface inclined at a certain angle relative to the base layer BSL. However, the embodiment is not limited thereto, and the defining wall WL may have a side wall having a curved shape, a stepped shape, etc. In an example, the defining wall WL may have a cross-section having a semicircular shape, a semi-elliptical shape, etc.

[0257] The defining wall WL may include at least one organic material and / or at least one inorganic material. In an example, the defining wall WL may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the embodiment is not limited thereto, and the defining wall WL may include various kinds of inorganic insulating materials, including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0258] The electrode ALE may be disposed on the through-hole layer VIA and the defining wall WL. The electrode ALE may at least partially cover the side surface and / or the top surface of the defining wall WL. The electrode ALE disposed on the top surface of the defining wall WL may have a shape corresponding to the defining wall WL. In an example, the electrode ALE disposed on the defining wall WL may include an inclined surface or a curved surface having a shape corresponding to the shape of the defining wall WL. The defining wall WL and the electrode ALE may function as a reflective member and reflect the light emitted from the light emitting element LD and guide the reflected light in the front direction of the pixel PXL (i.e., the third direction (e.g., the Z-axis direction)). Therefore, the luminous efficiency of the display panel PNL can be improved.

[0259] The electrodes ALE may be spaced apart from each other. The electrodes ALE may be disposed in the same layer (or formed as the same layer). For example, the electrodes ALE may be simultaneously formed by the same process, but the embodiment is not limited thereto.

[0260] In the step of aligning the light emitting element LD, the electrode ALE can be aligned with the above-mentioned alignment pad ( Figure 3The AP shown in FIG. 1 receives an alignment voltage. Therefore, an electric field may be formed between the electrodes ALE so that the light emitting element LD provided (or arranged) in each pixel PXL may be aligned with a bias between the electrodes ALE. In an embodiment, in order to improve the alignment of the light emitting element LD, reference is made to FIG. Figure 5 The signal line described together with the electrode ALE can receive an alignment voltage. This will be referred to later Figures 17 to 34 Detailed description.

[0261] The electrode ALE may include at least one conductive material. In an example, the electrode ALE may include at least one conductive material of: at least one metal of various metal materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc.) or any alloy thereof; at least one conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO)) and a conductive polymer (such as PEDOT), but the embodiment is not limited thereto.

[0262] In an embodiment, if Fig.10 and Fig.12 As shown in , an electrode layer MTL may also be provided below the electrode ALE. The electrode layer MTL may overlap with an alignment region in which the light emitting element LD is aligned. The electrode layer MTL may at least partially overlap with the electrode ALE. The electrode layer MTL may be electrically separated from the electrode ALE. In an embodiment, in order to improve the alignment of the light emitting element LD, the electrode layer MTL together with the electrode ALE may receive an alignment voltage in the step of aligning the light emitting element LD. This will refer to Figures 29 to 34 Detailed description.

[0263] The electrode layer MTL may be formed of a fourth conductive layer disposed on the protective layer PSV. The fourth conductive layer and the third conductive layer may include the same material. The fourth conductive layer may include at least one material selected from materials such as the material of the third conductive layer. A second interlayer insulating layer ILD2 may also be disposed between the electrode layer MTL and the electrode ALE. The second interlayer insulating layer ILD2 may be formed as a single layer or multiple layers and include various kinds of inorganic insulating materials, including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0264] The first insulating layer INS1 may be disposed on the electrode ALE. The first insulating layer INS1 may be formed as a single layer or multiple layers and include various kinds of inorganic insulating materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0265] The bank BNK may be disposed on the first insulating layer INS1. The opening of the bank BNK may provide a space in which the light emitting element LD is provided (or disposed) in the step of providing the light emitting element LD to each of the pixels PXL. For example, a designed kind and / or a designed amount of light emitting element ink may be provided to the space separated by the opening of the bank BNK.

[0266] The bank BNK may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the embodiment is not limited thereto, and the bank BNK may include various kinds of inorganic insulating materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0267] The light emitting element LD may be disposed between the electrodes ALE. The light emitting element LD may be provided (or disposed) in the opening of the bank BNK to be disposed between the defining walls WL.

[0268] The light emitting element LD may be prepared in a form in which the light emitting element LD is dispersed in a light emitting element ink to be provided to each of the pixels PXL by an inkjet printing process or the like. In an example, the light emitting element LD may be dispersed in a volatile solvent to be provided to each pixel PXL. Subsequently, when an alignment voltage is provided through the electrode ALE and an electric field is formed between the electrodes ALE, the light emitting element LD may be aligned between the electrodes ALE. After the light emitting element LD is aligned, the solvent may be removed by volatilization or other processes so that the light emitting element LD may be stably arranged between the electrodes ALE.

[0269] The second insulating layer INS2 may be disposed on the light emitting element LD. For example, the second insulating layer INS2 may be partially disposed on the light emitting element LD and expose the first end EP1 and the second end EP2 of the light emitting element LD. In the case where the second insulating layer INS2 is formed on the light emitting element LD after the alignment of the light emitting element LD is completed, the light emitting element LD may be prevented from being separated from the position where the light emitting element LD is aligned.

[0270] The second insulating layer INS2 may be formed as a single layer or multiple layers and include various kinds of inorganic insulating materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0271] The connection electrode ELT may be disposed on the first and second ends EP1 and EP2 of the light emitting element LD exposed by the second insulating layer INS2. The first connection electrode ELT1 may be disposed (eg, directly disposed) on the first end EP1 of the first light emitting element LD1 to contact the first end EP1 of the first light emitting element LD1.

[0272] The second connection electrode ELT2 may be disposed (e.g., directly disposed) on the second end portion EP2 of the first light emitting element LD1 to contact the second end portion EP2 of the first light emitting element LD1. The second connection electrode ELT2 may be disposed (e.g., directly disposed) on the first end portion EP1 of the second light emitting element LD2 to contact the first end portion EP1 of the second light emitting element LD2. For example, the second connection electrode ELT2 may electrically connect the second end portion EP2 of the first light emitting element LD1 and the first end portion EP1 of the second light emitting element LD2 to each other.

[0273] For example, the third connection electrode ELT3 may be disposed (for example, directly disposed) on the second end portion EP2 of the second light emitting element LD2 to contact the second end portion EP2 of the second light emitting element LD2. The third connection electrode ELT3 may be disposed (for example, directly disposed) on the first end portion EP1 of the third light emitting element LD3 to contact the first end portion EP1 of the third light emitting element LD3. For example, the third connection electrode ELT3 may electrically connect the second end portion EP2 of the second light emitting element LD2 and the first end portion EP1 of the third light emitting element LD3 to each other.

[0274] For example, the fourth connection electrode ELT4 may be disposed (for example, directly disposed) on the second end EP2 of the third light emitting element LD3 to contact the second end EP2 of the third light emitting element LD3. The fourth connection electrode ELT4 may be disposed (for example, directly disposed) on the first end EP1 of the fourth light emitting element LD4 to contact the first end EP1 of the fourth light emitting element LD4. For example, the fourth connection electrode ELT4 may electrically connect the second end EP2 of the third light emitting element LD3 and the first end EP1 of the fourth light emitting element LD4 to each other.

[0275] For example, the fifth connection electrode ELT5 may be disposed (eg, directly disposed) on the second end portion EP2 of the fourth light emitting element LD4 to make contact with the second end portion EP2 of the fourth light emitting element LD4.

[0276] The first connection electrode ELT1 may be electrically connected to the first transistor electrode TE1 of the first transistor T1 through a contact hole passing through the first insulating layer INS1, the via layer VIA and the protective layer PSV. The fifth connection electrode ELT5 may be electrically connected to the horizontal power line PL2_2 through a contact hole passing through the first insulating layer INS1, the via layer VIA and the protective layer PSV.

[0277] In an embodiment, the connection electrode ELT may be formed of a conductive layer. Figures 9 to 12As shown in , the first connection electrode ELT1, the third connection electrode ELT3 and the fifth connection electrode ELT5 can be arranged in the same layer (for example, the fifth conductive layer) (or formed as the same layer (for example, the fifth conductive layer)). The second connection electrode ELT2 and the fourth connection electrode ELT4 can be arranged in the same layer (for example, the sixth conductive layer) (or formed as the same layer (for example, the sixth conductive layer)). The first connection electrode ELT1, the third connection electrode ELT3 and the fifth connection electrode ELT5 can be arranged on the second insulating layer INS2. The third insulating layer INS3 can be arranged on the first connection electrode ELT1, the third connection electrode ELT3 and the fifth connection electrode ELT5. The second connection electrode ELT2 and the fourth connection electrode ELT4 can be arranged on the third insulating layer INS3. Therefore, in the case where the third insulating layer INS3 is arranged between the connection electrodes ELT formed as different conductive layers, the connection electrodes ELT can be stably separated from each other by the third insulating layer INS3, and thus the electrical stability between the first end EP1 and the second end EP2 of the light emitting element LD can be ensured.

[0278] The third insulating layer INS3 may be formed as a single layer or multiple layers and include various kinds of inorganic insulating materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0279] In another embodiment, the connection electrodes ELT may be formed as the same conductive layer. Fig.13 and Fig.14 As shown in , the first connection electrode ELT1, the second connection electrode ELT2, the third connection electrode ELT3, the fourth connection electrode ELT4 and the fifth connection electrode ELT5 can be arranged in the same layer (or formed as the same layer). In the example, the first connection electrode ELT1, the second connection electrode ELT2, the third connection electrode ELT3, the fourth connection electrode ELT4 and the fifth connection electrode ELT5 can be formed simultaneously by the same process. Therefore, in the case of forming the connection electrodes ELT at the same time, the number of masks can be reduced and the manufacturing process can be simplified.

[0280] The connection electrode ELT may be made of various transparent conductive materials. In an example, the connection electrode ELT may include at least one of various transparent conductive materials, including indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO), and the connection electrode ELT may be substantially transparent or translucent to meet the selected transmittance. Therefore, the light emitted from the first end EP1 and the second end EP2 of the light emitting element LD may be emitted to the outside of the display panel PNL while passing through the connection electrode ELT.

[0281] Fig.15 2 is a schematic cross-sectional view showing first to third pixels PXL1 to PXL3 according to an embodiment. Fig.16 is a schematic cross-sectional view showing a pixel PXL according to an embodiment.

[0282] Fig.15 A color conversion layer CCL, an optical layer OPL and / or a color filter layer CFL are shown. Fig.15 For ease of description, except Figures 9 to 14 Components other than the base layer BSL and the bank BNK shown in FIG. 1 will be omitted. Fig.16 The stacked structure of the pixel PXL associated with the color conversion layer CCL, the optical layer OPL, and / or the color filter layer CFL is shown in detail.

[0283] refer to Fig.15 and Fig.16 The bank BNK may be disposed between the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 or at a boundary of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 and include an opening overlapping each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The opening of the bank BNK may provide a space in which the color conversion layer CCL may be disposed.

[0284] The color conversion layer CCL may be disposed over the light emitting element LD in the opening of the bank BNK. The color conversion layer CCL may include a first color conversion layer CCL1 disposed in the first pixel PXL1, a second color conversion layer CCL2 disposed in the second pixel PXL2, and a light scattering layer LSL disposed in the third pixel PXL3.

[0285] The first color conversion layer CCL1 may include first color conversion particles for converting the third color light emitted from the light emitting element LD into the first color light. For example, the first color conversion layer CCL1 may include first quantum dots QD1 dispersed in a matrix material such as a base resin.

[0286] In an embodiment, when the light emitting element LD is a blue light emitting element emitting blue light and the first pixel PXL1 is a red pixel, the first color conversion layer CCL1 may include a first quantum dot QD1 for converting the blue light emitted from the blue light emitting element into red light. The first quantum dot QD1 may absorb the blue light and emit red light by shifting the wavelength of the blue light according to energy transition. For example, when the first pixel PXL1 is a pixel of another color, the first color conversion layer CCL1 may include a first quantum dot QD1 corresponding to the color of the first pixel PXL1.

[0287] The second color conversion layer CCL2 may include second color conversion particles for converting the third color light emitted from the light emitting element LD into the second color light. For example, the second color conversion layer CCL2 may include second quantum dots QD2 dispersed in a matrix material such as a base resin.

[0288] In an embodiment, when the light emitting element LD is a blue light emitting element emitting blue light and the second pixel PXL2 is a green pixel, the second color conversion layer CCL2 may include a second quantum dot QD2 for converting the blue light emitted from the blue light emitting element into green light. The second quantum dot QD2 may absorb the blue light and emit green light by shifting the wavelength of the blue light according to energy transition. For example, when the second pixel PXL2 is a pixel of another color, the second color conversion layer CCL2 may include a second quantum dot QD2 corresponding to the color of the second pixel PXL2.

[0289] In an embodiment, blue light having a relatively short wavelength in the visible light band may be incident into the first quantum dot QD1 and the second quantum dot QD2, so that the absorption coefficient of the first quantum dot QD1 and the second quantum dot QD2 may be increased. Therefore, the efficiency of light finally emitted from the first pixel PXL1 and the second pixel PXL2 may be improved, and good color reproducibility may be ensured. The light emitting unit EMU of each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be formed by using a light emitting element of the same color (e.g., a blue light emitting element), so that the manufacturing efficiency of the display device may be improved.

[0290] The light scattering layer LSL may be configured to effectively utilize the light of the third color (or blue) emitted from the light emitting element LD. In an example, when the light emitting element LD is a blue light emitting element emitting blue light, and the third pixel PXL3 is a blue pixel, the light scattering layer LSL may include at least one kind of light scattering particles SCT to effectively utilize the light emitted from the light emitting element LD. In an example, the light scattering particles SCT of the light scattering layer LSL may include barium sulfate (BaSO 4 ), calcium carbonate (CaCO 3 ), titanium dioxide (TiO 2 ), silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ) and at least one of zinc oxide (ZnO). For example, the light scattering particles SCT may not be provided only in the third pixel PXL3, and may be selectively included in the first color conversion layer CCL1 or the second color conversion layer CCL2. In some embodiments, the light scattering particles SCT may be omitted, thereby providing a light scattering layer LSL formed of a transparent polymer.

[0291] The first cover layer CPL1 may be disposed on the color conversion layer CCL. The first cover layer CPL1 may be provided (or disposed) throughout the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The first cover layer CPL1 may cover the color conversion layer CCL. The first cover layer CPL1 may protect the color conversion layer CCL from being damaged or contaminated due to infiltration (or penetration) of impurities such as moisture or air from the outside.

[0292] The first capping layer CPL1 may be an inorganic layer and may include silicon nitride (SiN x ), aluminum nitride (AlN x ), titanium nitride (TiN x ), silicon oxide (SiO x ), aluminum oxide (AlO x ), titanium oxide (TiO x ), Silicon Oxycarbide (SiO x C y ), silicon oxynitride (SiO x N y )wait.

[0293] The optical layer OPL may be disposed on the first cover layer CPL1. The optical layer OPL may be used to improve light extraction efficiency by recycling light provided from the color conversion layer CCL through total reflection. For example, the optical layer OPL may have a refractive index relatively lower than that of the color conversion layer CCL. For example, the refractive index of the color conversion layer CCL may be about 1.6 to about 2.0, and the refractive index of the optical layer OPL may be about 1.1 to about 1.3.

[0294] The second cover layer CPL2 may be disposed on the optical layer OPL. The second cover layer CPL2 may be provided (or disposed) throughout the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The second cover layer CPL2 may cover the optical layer OPL. The second cover layer CPL2 may protect the optical layer OPL from being damaged or contaminated due to infiltration (or penetration) of impurities such as moisture or air from the outside.

[0295] The second capping layer CPL2 may be an inorganic layer and may include silicon nitride (SiN x ), aluminum nitride (AlN x ), titanium nitride (TiN x ), silicon oxide (SiO x ), aluminum oxide (AlO x ), titanium oxide (TiO x ), Silicon Oxycarbide (SiO x C y ), silicon oxynitride (SiO x N y )wait.

[0296] The planarization layer PLL may be disposed on the second cover layer CPL2 . The planarization layer PLL may be provided (or disposed) throughout the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 .

[0297] The planarization layer PLL may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the embodiment is not limited thereto, and the planarization layer PLL may include various kinds of inorganic insulating materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiOx ).

[0298] The color filter layer CFL may be disposed on the planarization layer PLL. The color filter layer CFL may include color filters CF1, CF2, and CF3 according to the color of each pixel PXL. The color filters CF1, CF2, and CF3 according to the colors of the corresponding first pixel PXL1, second pixel PXL2, and third pixel PXL3 may be disposed so that a full-color image may be displayed.

[0299] The color filter layer CFL may include a first color filter CF1 disposed in the first pixel PXL1 so that light emitted from the first pixel PXL1 can be selectively transmitted therethrough, a second color filter CF2 disposed in the second pixel PXL2 so that light emitted from the second pixel PXL2 can be selectively transmitted therethrough, and a third color filter CF3 disposed in the third pixel PXL3 so that light emitted from the third pixel PXL3 can be selectively transmitted therethrough.

[0300] In an embodiment, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be a red filter, a green filter, and a blue filter, respectively, but the embodiment is not limited thereto. Hereinafter, in the case of specifying any color filter among the first color filter CF1, the second color filter CF2, and the third color filter CF3, or in the case of inclusively specifying two or more types of color filters, the corresponding color filter is referred to as a "color filter".

[0301] The first color filter CF1 may overlap the first color conversion layer CCL1 of the first pixel PXL1 in a third direction (e.g., Z-axis direction). The first color filter CF1 may include a color filter material for selectively transmitting light of a first color (or red). For example, when the first pixel PXL1 is a red pixel, the first color filter CF1 may include a red color filter material.

[0302] The second color filter CF2 may overlap the second color conversion layer CCL2 of the second pixel PXL2 in a third direction (e.g., the Z-axis direction). The second color filter CF2 may include a color filter material for selectively transmitting light of the second color (or green). For example, when the second pixel PXL2 is a green pixel, the second color filter CF2 may include a green color filter material.

[0303] The third color filter CF3 may overlap the light scattering layer LSL of the third pixel PXL3 in a third direction (e.g., Z-axis direction). The third color filter CF3 may include a color filter material for selectively transmitting light of a third color (or blue). For example, when the third pixel PXL3 is a blue pixel, the third color filter CF3 may include a blue color filter material.

[0304] In some embodiments, a light blocking layer BM may also be provided between the first color filter CF1, the second color filter CF2, and the third color filter CF3. Therefore, when the light blocking layer BM is formed between the first color filter CF1, the second color filter CF2, and the third color filter CF3, a color mixing defect observed at the front or side of the display device may be prevented. The material of the light blocking layer BM is not limited, and the light blocking layer BM may be formed of various light blocking materials. In an example, the light blocking layer BM may be implemented by stacking the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0305] An overcoat layer OC may be provided on the color filter layer CFL. The overcoat layer OC may be provided (or provided) throughout the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The overcoat layer OC may cover the lower component including the color filter layer CFL. The overcoat layer OC may prevent moisture or air from penetrating (or permeating) the lower component. The overcoat layer OC may protect the lower component from foreign matter such as dust.

[0306] The outer coating layer OC may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the embodiment is not limited thereto, and the outer coating layer OC may include various kinds of inorganic insulating materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ).

[0307] Next, a method of manufacturing the display device according to the above-described embodiment will be described.

[0308] Figures 17 to 25 are schematic plan views and cross-sectional views illustrating process steps of a method of manufacturing a display device according to an embodiment. Fig.18 and Fig.19 Along the Fig.17 The cross-sectional view taken along the line EE' and the line FF' shown in FIG. Fig.21 and Fig. 22 Along the Fig. 20 A cross-sectional view taken along the line EE' and the line FF' shown in FIG. Fig.24and Fig.25 Along the Fig.23 The cross-sectional view taken along the line EE' and the line FF' shown in FIG. Figures 1 to 16 Those components which are substantially the same as those shown in FIG. 1 are denoted by the same reference numerals, and the detailed reference numerals are omitted.

[0309] refer to Figures 17 to 19 First, an electrode ALE may be formed in the pixel PXL. The first electrode ALE1, the second electrode ALE2, and the third electrode ALE3 may extend in the second direction (eg, the Y-axis direction) and be spaced apart from each other in the first direction (eg, the X-axis direction).

[0310] Electrodes ALE may be formed over the signal lines SG1, SG2, and SG3. Each of the signal lines SG1, SG2, and SG3 may be connected to a reference Figure 5 The described first scan line S1, the second scan line S2, the data lines D1, D2 and D3, the power line PL, the initialization power line IPL and / or the storage capacitor Cst correspond to some of them.

[0311] The signal lines SG1, SG2, and SG3 may at least partially overlap with the alignment areas ALA1 and ALA2 in a third direction (e.g., the Z-axis direction). The first alignment area ALA1 may refer to an area between the first electrode ALE1 and the second electrode ALE2, and the second alignment area ALA2 may refer to an area between the second electrode ALE2 and the third electrode ALE3.

[0312] exist Fig.18 and Fig.19 In the embodiment, the first signal line SG1 may overlap the second alignment area ALA2 in a third direction (e.g., the Z-axis direction), the second signal line SG2 may overlap the first alignment area ALA1 in the third direction (e.g., the Z-axis direction), and the third signal line SG3 may overlap the second alignment area ALA2 in the third direction (e.g., the Z-axis direction). However, the embodiment is not limited thereto.

[0313] The first signal line SG1 may be formed as a single layer. In an example, the first signal line SG1 may be formed of the above-mentioned first conductive layer. However, the embodiment is not limited thereto, and the first signal line SG1 may be formed of the above-mentioned second conductive layer or the above-mentioned third conductive layer.

[0314] The second signal line SG2 may be formed of a double layer. In an example, the second signal line SG2 may be formed of a first conductive layer and a second conductive layer. The first conductive layer and the second conductive layer of the second signal line SG2 may overlap each other in a third direction (e.g., a Z-axis direction). However, the embodiment is not limited thereto, and the second signal line SG2 may be formed of a first conductive layer and a third conductive layer, or may be formed of a second conductive layer and a third conductive layer.

[0315] The third signal line SG3 may be formed of three layers. In an example, the third signal line SG3 may be formed of a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer, the second conductive layer, and the third conductive layer of the third signal line SG3 may overlap each other in a third direction (eg, Z-axis direction).

[0316] The signal lines SG1, SG2, and SG3 may be electrically separated from the electrode ALE. Therefore, the electrode ALE and the signal lines SG1, SG2, and SG3 may be separated from each other, thereby providing different alignment voltages to the electrode ALE and the signal lines SG1, SG2, and SG3.

[0317] refer to Figure 20 to Figure 22 , the light emitting element LD may be aligned between the electrodes ALE (or in the alignment areas ALA1 and ALA2).

[0318] The light emitting element LD may be prepared in a form in which the light emitting element LD is dispersed in a light emitting element ink to provide the light emitting element LD by an inkjet printing process, etc. In an example, the light emitting element LD may be provided while being dispersed in a volatile solvent.

[0319] Subsequently, an alignment voltage may be applied to the electrodes ALE and the signal lines SG1, SG2, and SG3 to align the light emitting element LD. In the step of aligning the light emitting element LD, a first alignment voltage may be applied between the electrodes ALE, a second alignment voltage may be applied to the first signal line SG1, a third alignment voltage may be applied to the second signal line SG2, and a fourth alignment voltage may be applied to the third signal line SG3, wherein applying the first alignment voltage between the electrodes ALE may mean applying alignment voltages to the electrodes ALE adjacent to each other so that the voltage difference between the electrodes ALE adjacent to each other is equal to the first alignment voltage, for example, may mean applying an alignment voltage to the first electrode ALE1 and the second electrode ALE2 so that the voltage difference between the first electrode ALE1 and the second electrode ALE2 is equal to the first alignment voltage, and applying an alignment voltage to the third electrode ALE3 and the second electrode ALE2 so that the voltage difference between the third electrode ALE3 and the second electrode ALE2 is equal to the first alignment voltage, and for example, in the case where the second electrode ALE2 is grounded, applying the first alignment voltage between the electrodes ALE may mean applying the first alignment voltage to the first electrode ALE1 and the third electrode ALE3.

[0320] In an embodiment, the first alignment voltage may be higher than the second alignment voltage. The second alignment voltage may be higher than the third alignment voltage. The third alignment voltage may be higher than the fourth alignment voltage. In an example, the second alignment voltage may be equal to or lower than about 65% of the first alignment voltage, the third alignment voltage may be equal to or lower than about 60% of the first alignment voltage, and the fourth alignment voltage may be equal to or lower than about 55% of the first alignment voltage.

[0321] In the step of aligning the light-emitting element LD, a first alignment voltage, a second alignment voltage, a third alignment voltage and / or a fourth alignment voltage may be applied simultaneously. Therefore, in the case where the first alignment voltage is applied between the electrodes ALE and the second to fourth alignment voltages are applied to the first signal line SG1, the second signal line SG2 and the third signal line SG3 respectively, the asymmetry of the electric field formed in the alignment areas ALA1 and ALA2 may be reduced or prevented. Generally, in the case where only the first alignment voltage is applied between the electrodes ALE, the difference in the electric field strength between the alignment areas ALA1 and ALA2 may be 6.9% on average. In the case where the first alignment voltage is applied between the electrodes ALE and the second alignment voltage is applied to the first signal line SG1, the difference in the electric field strength between the alignment areas ALA1 and ALA2 may be improved to an average of 0.4%. In the case where the first alignment voltage is applied between the electrodes ALE and the third alignment voltage is applied to the second signal line SG2, the difference in the electric field strength between the alignment areas ALA1 and ALA2 may be improved to an average of 0.1%. In the case where the first alignment voltage is applied between the electrodes ALE and the fourth alignment voltage is applied to the third signal line SG3, the difference in electric field strength between the alignment areas ALA1 and ALA2 can be improved to an average of 1.4%. For example, since the first alignment voltage is applied between the electrodes ALE and the second to fourth alignment voltages are applied to the first, second, and third signal lines SG1, SG2, and SG3, respectively, the asymmetry of the electric fields in the alignment areas ALA1 and ALA2 can be reduced or prevented, thereby improving the alignment of the light emitting element LD.

[0322] refer to Figure 23 to Figure 25 , then, a connection electrode ELT may be formed on the light emitting element LD. In an embodiment, the connection electrode ELT may be electrically connected to the first end EP1 and the second end EP2 of the light emitting element LD. Some of the connection electrodes ELT may be electrically connected to some of the first signal line SG1, the second signal line SG2, and the third signal line SG3 described above.

[0323] As reference Fig. 9 and Fig.11 As described, the connection electrode ELT may be formed of different conductive layers. For example, the second insulating layer INS2 may be formed on the light emitting element LD, and the first connection electrode ELT1, the third connection electrode ELT3, and the fifth connection electrode ELT5 may be formed on the second insulating layer INS2. The third insulating layer INS3 may be formed over the first connection electrode ELT1, the third connection electrode ELT3, and the fifth connection electrode ELT5. The second connection electrode ELT2 and the fourth connection electrode ELT4 may be formed on the third insulating layer INS3. However, the embodiment is not limited thereto, and as described with reference to Fig.13 and Fig.14 As described, the first connection electrode ELT1, the second connection electrode ELT2, the third connection electrode ELT3, the fourth connection electrode ELT4, and the fifth connection electrode ELT5 may be formed of the same conductive layer.

[0324] Hereinafter, another embodiment will be described. In the following embodiment, the same components as those already described are denoted by the same reference numerals, and overlapping descriptions will be omitted or simplified.

[0325] Figure 26 to Figure 34 are schematic plan views and cross-sectional views illustrating process steps of a method of manufacturing a display device according to an embodiment.

[0326] refer to Figure 26 to Figure 34 , an electrode layer MTL may be further formed below the electrode ALE. The electrode layer MTL may be formed of the fourth conductive layer.

[0327] The electrode layer MTL may at least partially overlap the alignment areas ALA1 and ALA2 in a third direction (e.g., the Z-axis direction). The electrode layer MTL may at least partially overlap the electrode ALE in a third direction (e.g., the Z-axis direction). The electrode layer MTL may at least partially overlap the first signal line SG1, the second signal line SG2, and the third signal line SG3 in a third direction (e.g., the Z-axis direction). For example, the electrode layer MTL may overlap the first signal line SG1 or the second signal line SG2 in a third direction (e.g., the Z-axis direction).

[0328] The electrode layer MTL may be electrically separated from the electrode ALE. The electrode layer MTL may be electrically separated from the first signal line SG1, the second signal line SG2, and the third signal line SG3. Therefore, since the electrode ALE, the signal lines SG1, SG2, and SG3, and the electrode layer MTL are electrically separated from each other, different alignment voltages may be applied to the electrode ALE, the signal lines SG1, SG2, and SG3, and the electrode layer MTL.

[0329] refer to Figure 29 to Figure 31 , the light emitting element LD may be aligned between the electrodes ALE (or in the alignment areas ALA1 and ALA2).

[0330] Alignment voltages may be applied to the electrodes ALE, the signal lines SG1, SG2, and SG3, and the electrode layer MTL, thereby aligning the light emitting element LD. In the step of aligning the light emitting element LD, a first alignment voltage may be applied between the electrodes ALE, a second alignment voltage may be applied to the first signal line SG1, a third alignment voltage may be applied to the second signal line SG2, a fourth alignment voltage may be applied to the third signal line SG3, and a fifth alignment voltage may be applied to the electrode layer MTL.

[0331] In the step of aligning the light emitting element LD, a first alignment voltage, a second alignment voltage, a third alignment voltage, a fourth alignment voltage and / or a fifth alignment voltage may be applied simultaneously. Therefore, in the case where the first alignment voltage is applied between the electrodes ALE and the second to fifth alignment voltages are applied to the signal lines SG1, SG2 and SG3 and the electrode layer MTL, respectively, the asymmetry of the electric field formed in the alignment areas ALA1 and ALA2 may be reduced or prevented, thereby improving the alignment of the light emitting element LD, which has been described above.

[0332] refer to Figure 32 to Figure 34 , then, the connection electrodes ELT may be formed on the light emitting element LD. Some of the connection electrodes ELT may be electrically connected to some of the first signal line SG1, the second signal line SG2, and the third signal line SG3 described above.

[0333] According to the present disclosure, the alignment voltage is applied to the electrode and the signal line at the same time, so that the asymmetry of the electric field in the alignment area can be reduced or prevented, thereby improving the alignment degree of the light emitting element.

[0334] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the principles, spirit and scope of the present disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A method for manufacturing a display device, the method comprising: aligning the light emitting element in an alignment region between the electrodes spaced apart from each other, Wherein, aligning the light emitting element comprises: applying a first alignment voltage between the electrodes, applying a second alignment voltage to the first signal line overlapping the alignment area, and applying a third alignment voltage to a second signal line overlapping the alignment region, the first signal line being formed of the first conductive layer, and The second signal line is formed by the first conductive layer and the second conductive layer.

2. The method according to claim 1, wherein: The first alignment voltage, the second alignment voltage, and the third alignment voltage are applied simultaneously.

3. The method according to claim 1, wherein: The first alignment voltage is higher than the second alignment voltage.

4. The method according to claim 1, wherein: The second alignment voltage is higher than the third alignment voltage.

5. The method according to claim 1, wherein: The electrode is electrically separated from the first signal line and the second signal line.

6. The method according to claim 1, wherein: aligning the light emitting element further comprises applying a fourth alignment voltage to a third signal line overlapping the alignment region, and The third signal line is formed by the first conductive layer, the second conductive layer and the third conductive layer.

7. The method according to claim 6, wherein: The first alignment voltage, the second alignment voltage, the third alignment voltage, and the fourth alignment voltage are applied simultaneously.

8. The method according to claim 6, wherein: The third alignment voltage is higher than the fourth alignment voltage.

9. The method according to claim 6, wherein: The electrode is electrically separated from the third signal line.

10. The method according to claim 1, wherein: Aligning the light emitting element further comprises applying a fifth alignment voltage to the electrode layer overlapping the alignment region, and Wherein, the electrode layer is formed by a fourth conductive layer.

11. The method according to claim 10, wherein: The electrode layer overlaps with the first signal line or the second signal line.

12. The method according to claim 10, wherein: The first alignment voltage, the second alignment voltage, the third alignment voltage, and the fifth alignment voltage are applied simultaneously.

13. The method according to claim 10, wherein: The first alignment voltage is higher than the fifth alignment voltage.

14. The method according to claim 10, wherein: The electrode is electrically separated from the electrode layer.

15. The method according to claim 10, wherein: The electrode layer is electrically separated from the first signal line and the second signal line.

16. The method according to claim 10, wherein: The electrode layer overlaps with the electrode, The method further comprises: forming a connecting electrode on the light emitting element, and Wherein, the connection electrode is electrically connected to the first signal line or the second signal line.

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