Detection substrate and detection chip

Abstract

A detection substrate and a detection chip, relating to the technical field of biological detection, the detection substrate comprising a plurality of detection units (11), each detection unit (11) comprising a sensing portion (11B) and a signal generating portion (11A), the sensing portion (11B) being electrically connected with the signal generating portion (11A); the induction part (11B) is configured to react with a sample to be detected and generate an electric signal, and the signal generation part (11A) is configured to receive the electric signal and generate a detection current; wherein the sensing part (11B) comprises a pair of sensing electrodes (11B-1, 11B-2), and the pair of sensing electrodes (11B-1, 11B-2) are both electrically connected with the signal generation part (11A); the outer contours of the induction electrodes comprise arc lines (11B-1 and 11B-2). The detection substrate is used for preparing a high-sensitivity and high-accuracy detection chip.

Description

Detection substrate, detection chip Technical Field

[0001] The present application relates to the field of biological detection technology, and in particular to a detection substrate and a detection chip. Background Art

[0002] Acute myeloid leukemia (AML) is a common acute leukemia in adults, with an annually increasing incidence rate (1.62 / 100,000). AML is highly heterogeneous, and currently, there are no effective methods for early detection.

[0003] Complete blood counts and peripheral blood smears are the most common tests for AML. Most AML patients have an abundance of immature white blood cells and insufficient red blood cells or platelets. However, these findings are only suggestive and cannot be definitively confirmed. A bone marrow biopsy is required for a definitive diagnosis, which can be painful for patients. Therefore, non-invasive, rapid, and highly sensitive detection methods are currently a hot research topic for the early diagnosis and prognosis of AML.

[0004] Summary of the Invention

[0005] The embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a detection substrate, comprising a base; the base comprising a sample testing area;

[0007] The sample testing area includes: a plurality of detection units, each of which includes a sensing portion and a signal generating portion, wherein the sensing portion and the signal generating portion are electrically connected; the sensing portion is configured to react with the sample to be tested and generate an electrical signal, and the signal generating portion is configured to receive the electrical signal and generate a detection current;

[0008] The sensing portion includes a pair of sensing electrodes, both of which are electrically connected to the signal generating portion; and the contours of the sensing electrodes include arcs.

[0009] In at least one embodiment of the present application, the signal generating unit includes a dual-gate transistor, and a first gate and a second gate of the dual-gate transistor are configured to connect to different conductive structures.

[0010] In at least one embodiment of the present application, the sensing portion further includes an antibody located on each pair of the sensing electrodes, wherein the antibody and the sensing electrode are configured to be covalently bonded; the antibodies on each pair of the sensing electrodes are of different types; and the sensing portion further includes a surface treatment layer, wherein the surface treatment layer covers each pair of the sensing electrodes, and wherein the surface treatment layer is configured to form the covalent bond with the antibody.

[0011] In at least one embodiment of the present application, the sensing electrode includes a plurality of extensions and a connecting portion connecting the extensions; in the same sensing electrode, the connecting portion is located on the same side of the extensions;

[0012] The sensing portion includes a first sensing electrode and a second sensing electrode. The orthographic projection of the connecting portion of the first sensing electrode and the two extending portions connected at both ends of the connecting portion on the substrate forms a first arch shape. The orthographic projection of the connecting portion of the second sensing electrode and the two extending portions connected at both ends of the connecting portion on the substrate forms a second arch shape. Both ends of the first arch extend into the area enclosed by the second arch.

[0013] In at least one embodiment of the present application, the number of the extending portions of the first sensing electrode is at least two, the number of the extending portions of the second sensing electrode is at least three, and the extending portions of the first sensing electrode and the extending portions of the second sensing electrode are alternately arranged;

[0014] The shape of the orthographic projection of the connecting portion on the base includes an arc shape.

[0015] In at least one embodiment of the present application, the orthographic projection of the first sensing electrode on the substrate is U-shaped; the orthographic projection of the connecting portion of the second sensing electrode on the substrate is arc-shaped; and the orthographic projection of the extending portion of the second sensing electrode on the substrate is rectangular.

[0016] In at least one embodiment of the present application, the first gate of the dual-gate transistor is electrically connected to a constant voltage signal input terminal, and the first gate is configured to control the opening and closing of the dual-gate transistor;

[0017] The second gate of the dual-gate transistor is electrically connected to the pair of sensing electrodes, and the second gate is configured to control the change of the current in the dual-gate transistor according to the electrical signal generated in the sensing electrodes and simultaneously generate the detection current.

[0018] In at least one embodiment of the present application, the substrate further includes a signal detection area located on at least one side of the sample detection area, and the signal detection area includes at least one negative electrode terminal; the negative electrode terminal is electrically connected to the second gate through the sensing electrode.

[0019] In at least one embodiment of the present application, the negative electrode terminal is electrically connected to a correction line, and the negative electrode terminal is configured to release charges inside the dual-gate transistor to correct the dual-gate transistor.

[0020] In at least one embodiment of the present application, the signal detection area includes: a plurality of first signal acquisition terminals, the first signal acquisition terminals are electrically connected to the signal generating unit, and the number of the first signal acquisition terminals and the number of the signal generating unit are the same,

[0021] The signal detection area also includes a plurality of second signal acquisition terminals,

[0022] In the detection unit, the drain of the dual-gate transistor is electrically connected to the first signal acquisition terminal, and the source of the dual-gate transistor is electrically connected to the second signal acquisition terminal. The first signal acquisition terminal, the drain of the dual-gate transistor, the source of the dual-gate transistor and the second signal acquisition terminal are configured to form a conductive loop, and the detection current is the current in the loop during the detection time period.

[0023] In at least one embodiment of the present application, the sample testing area includes at least one reference cell, and the reference cell includes a reference electrode and the dual-gate transistor;

[0024] In the reference unit, the first gate of the dual-gate transistor is electrically connected to the constant voltage signal input terminal, the first gate is configured to control the opening and closing of the dual-gate transistor, the second gate of the dual-gate transistor is electrically connected to the reference electrode, the drain of the dual-gate transistor is electrically connected to the first signal acquisition terminal, and the source of the dual-gate transistor is electrically connected to the second signal acquisition terminal.

[0025] In at least one embodiment of the present application, the sample testing area includes a first sub-area and a second sub-area; the substrate includes a first signal detection sub-area and a second signal detection sub-area located on both sides of the sample testing area; the first sub-area and the second sub-area each include eight detection units;

[0026] In the first sub-area, four of the detection units are arranged along a first direction, and the other four of the detection units are arranged along a second direction, the first direction and the second direction intersect; an acute angle is formed between the first direction and the direction from the first sub-area to the second sub-area, and an acute angle is formed between the second direction and the direction from the first sub-area to the second sub-area;

[0027] The arrangement of the detection units in the second sub-area is symmetrical to the arrangement of the detection units in the first sub-area.

[0028] In at least one embodiment of the present application, the first sub-area includes a first routing line, the second sub-area includes a second routing line, the first routing line and the second routing line have the same length and are symmetrically arranged; the first routing line and the second routing line both extend in a direction from the first sub-area to the second sub-area;

[0029] The first wiring is configured to connect the eight detection units in the first sub-area in series, and the second wiring is configured to connect the eight detection units in the second sub-area in series.

[0030] In at least one embodiment of the present application, the first signal detection sub-region is located on a side of the first sub-region away from the second sub-region, and the second signal detection sub-region is located on a side of the second sub-region away from the first sub-region;

[0031] The first signal detection sub-region includes a first negative electrode terminal, and the second detection sub-region includes a second negative electrode terminal. The second gates of all the dual-gate transistors in the first sub-region are electrically connected to the first negative electrode terminal in sequence through the sensing electrode and the first wiring, and the second gates of all the dual-gate transistors in the second sub-region are electrically connected to the second negative electrode terminal in sequence through the sensing electrode and the second wiring.

[0032] In at least one embodiment of the present application, in the first sub-area or the second sub-area, along a direction parallel to the plane where the substrate is located, a minimum distance between any two adjacent sensing portions is greater than or equal to 1.2 cm.

[0033] In at least one embodiment of the present application, the detection substrate further includes a plurality of third routing lines, wherein the extension direction of the third routing lines intersects with the first routing lines; a portion of the third routing lines is configured to connect the first routing lines and the detection units in the first sub-area, and another portion of the third routing lines is configured to connect the second routing lines and the detection units in the second sub-area;

[0034] The length of the wiring connecting the detection unit and the first negative electrode terminal in the first sub-area and the length of the wiring connecting the detection unit and the second negative electrode terminal in the second sub-area are both in the range of 0.5 cm to 5 cm.

[0035] In at least one embodiment of the present application, the detection substrate includes a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a source-drain conductive layer, a fourth insulating layer, and a third conductive layer, which are sequentially arranged on the base;

[0036] The first conductive layer includes a first gate of each of the dual-gate transistors, the semiconductor layer includes an active portion of each of the dual-gate transistors, the second conductive layer includes a second gate of each of the dual-gate transistors and a plurality of first connecting electrodes, and the source-drain conductive layer includes a source, a drain, and a plurality of second connecting electrodes of each of the dual-gate transistors;

[0037] The sensing electrode is electrically connected to the second gate of the dual-gate transistor via the second connecting electrode and the first connecting electrode in sequence.

[0038] In the second aspect, an embodiment of the present application provides a detection chip, which includes a detection substrate as described in any one of the first aspects, and also includes a cover plate and an adhesive layer, the cover plate covers the sample testing area of ​​the detection substrate, and a sample inlet hole and a sample outlet hole are provided on the cover plate. The adhesive layer is located between the detection substrate and the cover plate, and a cavity structure is formed between the detection substrate, the cover plate and the adhesive layer.

[0039] In at least one embodiment of the present application, all the detection units on the detection substrate are located in the same cavity structure.

[0040] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0042] FIG1 is a schematic diagram of a planar structure of a detection substrate provided in an embodiment of the present application;

[0043] FIG2 is a schematic diagram of the cross-sectional structure along the M1M2 direction in FIG1 ;

[0044] 3 and 4 are schematic planar structural diagrams of two sensing parts provided in embodiments of the present application;

[0045] 5 and 6 are schematic planar structural diagrams of two other detection substrates provided in embodiments of the present application;

[0046] FIG7 is a schematic diagram of a cross-sectional structure of a sensing portion provided in an embodiment of the present application;

[0047] FIG8 is a diagram illustrating the inspection principle of a detection substrate provided in an embodiment of the present application;

[0048] FIG9 is a curve showing the change in detection current of a detection unit according to an embodiment of the present application and the change in concentration of a protein marker;

[0049] FIG10 is a schematic diagram of a planar structure of a detection chip provided in an embodiment of the present application;

[0050] FIG11 is a scatter plot of the detection results of a detection chip provided in an embodiment of the present application;

[0051] 12A-12L are intermediate structural diagrams of the method for preparing the detection chip provided in an embodiment of the present application. Specific embodiments

[0052] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0053] In the embodiments of the present application, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0054] In the embodiments of the present application, the terms "upper" and "lower" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0055] Throughout the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present application. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0056] In the embodiments of the present application, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0057] The features "parallel," "perpendicular," and "identical" used in the embodiments of the present application include features such as "parallel," "perpendicular," and "identical" in the strict sense, as well as "approximately parallel," "approximately perpendicular," and "approximately identical" that include certain tolerances, taking into account the measurement and tolerances associated with the measurement of a particular quantity (e.g., limitations of the measurement system), and represent within an acceptable range of deviation for a particular value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the stated value.

[0058] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, that is, meaning "including, but not limited to."

[0059] In the embodiments of this application, "same layer" refers to the relationship between multiple film layers formed from the same material after the same step (e.g., a one-step patterning process). "Same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same. Polygons in this specification are not strictly defined and can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, etc., and some small deformations due to tolerances may exist.

[0060] It should be noted that the organism-related samples to be tested, testing processes, etc. involved in this application are obtained and conducted with the permission of the individual or guardian and in compliance with laws and regulations.

[0061] Unless otherwise specified, “nM” refers to “n mol / L,” “μM” refers to “μmol / L,” and “mM” refers to “m mol / L.”

[0062] Acute myeloid leukemia (AML) is a common acute leukemia, with an annually increasing incidence rate (1.62 / 100,000). AML is a malignant disease of myeloid hematopoietic stem / progenitor cells characterized by abnormal proliferation of primitive and immature myeloid cells in the bone marrow and peripheral blood. Clinical manifestations include anemia, bleeding, infection and fever, organ infiltration, and metabolic abnormalities. Most cases present with severe illness and a dismal prognosis, often leading to life-threatening consequences if not promptly treated. AML accounts for 30% of pediatric leukemia. Molecular biological changes and chemotherapy responses in children with AML are similar to those in adults (<50 years old). AML in infants and young children is more likely to develop extramedullary leukemia than in adults.

[0063] AML is highly heterogeneous, and currently, there are no effective methods for early detection. Complete blood counts and peripheral blood smears are the most common tests for AML. Most AML patients have many immature white blood cells in their blood, but not enough red blood cells or platelets. However, these findings can only serve as a hint and cannot be used as a definitive diagnosis. A bone marrow biopsy is required for a definitive diagnosis, which is painful for patients. Therefore, non-invasive, rapid, and highly sensitive detection methods are currently a hot research topic for the early diagnosis and prognosis of AML.

[0064] Protein tumor marker detection is crucial for cancer diagnosis, therapeutic efficacy assessment, recurrence, metastasis, and prognosis. Most solid tumors originate from epithelial cells. As tumor cells rapidly differentiate and proliferate, cell types or components not found in normal tissues appear in large numbers. For example, keratin, which serves as a cellular scaffold, becomes a tumor marker. Tumor markers that are chemically protein-based include: ① enzymes; ② protein or peptide hormones; and ③ other proteins that do not fall into the first two categories.

[0065] Based on this, an embodiment of the present application provides a detection substrate and a detection chip, wherein the detection substrate includes a base; the base includes a sample testing area, the sample testing area includes multiple detection units, the detection unit includes a sensing part and a signal generating part, and the sensing part and the signal generating part are electrically connected; the sensing part is configured to react with the sample to be detected and generate an electrical signal, and the signal generating part is configured to receive the electrical signal and generate a detection current; wherein the sensing part includes a pair of sensing electrodes, and the pair of sensing electrodes are both electrically connected to the signal generating part; the outline of the sensing electrode includes an arc.

[0066] In the detection substrate provided in the embodiments of the present application, multiple detection units are provided to simultaneously identify different AML-related protein markers in the same sample to be tested, significantly improving diagnostic accuracy, providing a highly efficient AML monitoring and detection platform for clinical practice, and promoting the development of personalized treatment. Furthermore, the outer contours of the sensing electrodes are all curved, which increases the contact area between the active ingredients in the sample to be tested and the sensing portion, thereby improving the detection sensitivity of the detection unit.

[0067] The detection substrate and detection chip provided in the embodiments of the present application are described and introduced in detail below with reference to the accompanying drawings.

[0068] As shown in FIG1 , an embodiment of the present application provides a detection substrate, which includes a base 100 ; the base 100 includes a sample testing area A;

[0069] The sample testing area A includes: a plurality of detection units 11, each including a sensing unit 11B and a signal generating unit 11A, wherein the sensing unit 11B and the signal generating unit 11A are electrically connected; the sensing unit 11B is configured to react with the sample to be tested and generate an electrical signal, and the signal generating unit 11A is configured to receive the electrical signal and generate a detection current;

[0070] As shown in FIG. 3 or FIG. 4 , the sensing portion 11B includes a pair of sensing electrodes (e.g., sensing electrode 11B- 1 and sensing electrode 11B- 2 ). Both the pair of sensing electrodes (e.g., sensing electrode 11B- 1 and sensing electrode 11B- 2 ) are electrically connected to the signal generating portion 11A. The outer contours of the sensing electrodes (e.g., sensing electrode 11B- 1 and sensing electrode 11B- 2 ) include arcs.

[0071] In an exemplary embodiment, the base 100 of the detection substrate may be a flexible base, or a rigid base.

[0072] In some examples, the substrate 100 may be made of one or more materials selected from the group consisting of glass, polyimide, polycarbonate, polyacrylate, polyetherimide, and polyethersulfone, and this embodiment includes but is not limited thereto.

[0073] When the substrate 100 is a flexible substrate, the substrate 100 may include a single flexible material layer; or the substrate 100 may include a first flexible material layer, a first inorganic non-metallic material layer, a second flexible material layer, and a second inorganic non-metallic material layer stacked in sequence.

[0074] When the substrate 100 is a rigid substrate, the substrate 100 may include glass or silicon material.

[0075] The shape of the plane pattern of the detection substrate is not limited here, and the shape of the plane pattern of the detection substrate is the same as the shape of the plane pattern of the base 100. For example, the shape of the plane pattern of the detection substrate can be a circle, a square, a rectangle, a parallelogram, a pentagon, a hexagon, etc.

[0076] In the embodiment of the present application, an example is given in which the shapes of the plane figures of the detection substrate and the base 100 are both rectangles.

[0077] Illustratively, the plurality of detection units 11 are located in the same cavity structure (for example, a cavity structure formed by a detection substrate and a cover plate, not shown in FIG1 ).

[0078] Here, there is no limitation on whether the types of protein markers identified by the plurality of detection units 11 are the same.

[0079] Illustratively, multiple detection units 11 can be used to identify the same AML-related protein marker; or, multiple detection units 11 can be used to identify different types of AML-related protein markers in the same sample to be detected.

[0080] There is no limit on the number of detection units 11 in the above-mentioned inspection substrate. When multiple detection units 11 can be used to identify different types of AML-related protein markers in the same sample to be detected, the number of detection units 11 is greater than or equal to the number of protein markers that can be detected in the same sample to be detected.

[0081] For example, taking AML protein markers as an example, if the sample to be tested contains 14 protein markers related to acute myeloid leukemia, the number of detection units 11 is greater than or equal to 14, and each detection unit 11 is used to detect a different protein marker.

[0082] In an exemplary embodiment, sensing unit 11B is used to sense the sample to be tested and generate a corresponding electrical signal, and signal generating unit 11A is used to generate a detection current based on the electrical signal generated by the sensing unit. Users of the detection substrate can calculate the concentration of the corresponding protein marker based on the change in detection current before and after the addition of the sample to be tested.

[0083] Among them, each detection unit 11 can detect different types of protein markers in the sample to be detected, so that the concentrations of different protein markers can be detected using the same sample to be detected in the same detection substrate, thereby improving the detection efficiency and accuracy.

[0084] It should be noted that in order to enable each detection unit 11 to detect different types of protein markers in the sample to be detected, the detection unit 11 is also embedded with antibody molecules that match different types of protein markers. In this way, each detection unit 11 is embedded with an antibody molecule, and each antibody molecule matches a protein marker, so that the concentrations of different types of protein markers can be detected using the same sample to be detected.

[0085] In an exemplary embodiment, a signal detection area B is provided on at least one side of the sample detection area A, and a plurality of first signal acquisition terminals 12 for a user to obtain a detection current are provided in the signal detection area B. The first signal acquisition terminals 12 and the signal generating units 11A correspond one to one. Specifically, one first signal acquisition terminal 12 is electrically connected to one of the signal generating units 11A, and is used to transmit the detection current generated by a signal generating unit 11A, so that the user can obtain the detection current of different detection units 11, thereby calculating the concentration of the corresponding protein marker.

[0086] For example, as shown in FIG. 3 or FIG. 4 , the two sensing electrodes 11B- 1 and the sensing electrode 11B- 2 in the sensing portion 11B are not connected to each other (here, mechanical connection, not electrical connection).

[0087] For example, as shown in FIG3 or FIG4 , the structures of sensing electrode 11B-1 and sensing electrode 11B-2 in sensing portion 11B are not identical, but the outer contours of both sensing electrodes include arcs. It should be noted that FIG3 and FIG4 depict not only the two sensing electrodes in the same sensing portion 11B, but also the leads connecting the two sensing electrodes. This is specifically noted.

[0088] The specific materials of the sensing electrodes 11B- 1 and 11B- 2 in the sensing portion 11B are not limited here.

[0089] Exemplarily, the material of the sensing electrode 11B-1 and the sensing electrode 11B-2 in the sensing portion 11B can be a metal, such as a single-layer structure of gold (Au), or a stacked structure of chromium (Cr) / gold (Au). In the detection substrate provided in the embodiment of the present application, as shown in Figure 1, by providing multiple detection units 11, different AML-related protein markers in the same sample to be detected can be simultaneously identified, or the same AML-related protein marker can be identified multiple times, significantly improving diagnostic accuracy, providing a clinically efficient AML monitoring and detection platform, and promoting the development of personalized treatment.

[0090] In practical applications, a surface treatment layer (details of the surface treatment layer will be described later) is provided on the sensing electrode to connect the sensing electrode and the antibody. The antibody then recognizes the corresponding protein marker. During the formation of the surface treatment layer, the material of the surface treatment layer is prone to a coffee ring effect, causing the active ingredients of the surface treatment layer to be primarily distributed in an arc shape at the edge of the sensing electrode, and consequently, the antibodies are also primarily distributed at the edge of the sensing electrode. By providing arcs as the outer contours of the sensing electrodes (e.g., sensing electrodes 11B-1 and 11B-2 in FIG. 3 or FIG. 4 ), the contact area between the active ingredients in the sample to be detected and the sensing portion 11B can be increased, thereby improving the detection sensitivity of the detection unit 11.

[0091] In at least one embodiment of the present application, as shown in conjunction with Figures 1 and 2 , the signal generating unit 11A includes a dual-gate transistor (e.g., a TFT or MOS), wherein the first gate Gate1 and the second gate Gate2 of the dual-gate transistor are configured to connect to different conductive structures. Figure 2 is a schematic cross-sectional view of the structure along the M1M2 direction in Figure 1 .

[0092] In an exemplary embodiment, since the first gate Gate1 and the second gate Gate2 of the dual-gate transistor are configured to connect to different conductive structures, the potentials on the first gate Gate1 and the second gate Gate2 of the dual-gate transistor are different at least during the detection period.

[0093] Exemplarily, the dual-gate transistor may be a thin film transistor (TFT); or the dual-gate transistor may be a metal-oxide semiconductor field effect transistor (MOSFET), MOS tube for short.

[0094] Exemplarily, as shown in FIG. 2 , the dual-gate transistor includes a first gate Gate1 , a second gate Gate2 , an active portion AL, a source S, and a drain D.

[0095] In the embodiments and drawings of the present application, a dual-gate transistor is drawn and described as a TFT transistor as an example.

[0096] It should be noted that, unlike conventional methods of using a dual-gate transistor, in general, both gates of a dual-gate transistor are connected to the same conductive structure, i.e., the two gates of the dual-gate transistor are electrically connected together and always have the same potential. In the embodiment of the present application, the two gates of the dual-gate transistor are connected to different conductive structures, so that at least during the detection time period, the potentials of the first gate Gate1 and the second gate Gate2 of the dual-gate transistor are different, thereby causing the current passing through the dual-gate transistor to be different during the detection time period and the non-detection time period, thereby calculating the concentration of the corresponding protein marker detected by the detection unit 11 based on the change in the detection current.

[0097] In at least one embodiment of the present application, as shown in FIG. 7 , the sensing portion 11B further includes antibodies 16 located on each pair of sensing electrodes ( 11B- 1 and 11B- 2 ). The antibodies 16 and the sensing electrodes ( 11B- 1 and 11B- 2 ) are configured to be covalently bonded. The antibodies on each pair of sensing electrodes ( 11B- 1 and 11B- 2 ) are of different types.

[0098] Antibodies are proteins produced by the body in response to antigens, which have a protective effect. They (immunoglobulins are more than just antibodies) are large, Y-shaped proteins secreted by plasma cells (effector B cells) and used by the immune system to identify and neutralize foreign substances such as bacteria and viruses. Antibodies recognize a unique characteristic of a specific foreign substance, called an antigen.

[0099] In an embodiment of the present application, an antibody is connected to a sensing electrode through a covalent bond (the corresponding antibody 16 on each detection unit 11 is of a different type). When the detection substrate is used for disease detection, the antibody can undergo a biochemical reaction with the protein marker to generate an electrical signal (current), and the current is transmitted to the second gate Gate2 of the dual-gate transistor through the sensing electrode (the sensing electrode and the second gate Gate2 of the dual-gate transistor are electrically connected). At this time, the current passing through the dual-gate transistor changes. According to the change value of the current passing through the dual-gate transistor, the concentration of the corresponding protein marker can be calculated, and then the detection result is determined to be "negative" or "positive" based on the concentration.

[0100] In an embodiment of the present application, protein markers may include protein markers related to acute myeloid leukemia, for example, milk fat globule surface growth factor (MFC-E8), interleukin 20 (IL-20), IL-3, IL-2 R alpha, IL-2 R beta / CD122, IL-1 R6 / IL-1 Rrp2, tumor necrosis factor alpha (TNF-alpha), osteoactivin, glucocorticoid-induced tumor necrosis factor receptor (GITR / TNFRF18), insulin receptor (Insulin R), macrophage colony-stimulating factor (M-CSF), macrophage colony-stimulating factor receptor (M-CSF R), specific hepatocyte proliferation factor (Hepassocin), and secondary lymphoid tissue chemokine (6Ckine).

[0101] The above-mentioned "covalent bond" is a type of chemical bond. Two or more atoms share their outer electrons and, ideally, reach a state of electron saturation, thereby forming a relatively stable chemical structure. Such a strong interaction formed by several adjacent atoms through sharing electrons and with the shared electrons is called a covalent bond.

[0102] In practical applications, since the sensing electrodes are made of conductive materials, such as metals or metal oxides, it is difficult to directly form covalent bonds with the antibodies 16 . Therefore, as shown in FIG7 , in at least one embodiment of the present application, the sensing portion 11B further includes a surface treatment layer 15 , which covers each pair of sensing electrodes ( 11B- 1 and 11B- 2 ). The surface treatment layer 15 is configured to form a covalent bond with the antibodies 16 .

[0103] In practical applications, the sensing electrode and the antibody are connected together by a surface treatment layer provided on the sensing electrode, and the corresponding protein marker is then recognized by the antibody. During the formation of the surface treatment layer, the material of the surface treatment layer is prone to a coffee ring effect, causing the active ingredients of the surface treatment layer material to be mainly distributed at the edge of the sensing electrode, and thus the antibodies are also mainly distributed at the edge of the sensing electrode.

[0104] It's important to note that the coffee ring effect refers to the phenomenon where a drop of coffee or tea leaves a stain on a tabletop, with the particles forming an uneven stain, darker at the edges than in the center, forming a ring-shaped stain. To maintain a constant droplet size, a flow from the center outward occurs, carrying the solute to the contact line where it settles, ultimately forming a ring-shaped deposit. This "coffee ring effect" also occurs when the surface treatment layer's material solution drips onto the sensing electrode.

[0105] In at least one embodiment of the present application, the material of the surface treatment layer 15 includes mercaptopropylamine or ethylamine.

[0106] Antibodies are proteins with protective effects produced by the body in response to antigenic stimulation. Proteins in organisms are composed of several α-amino acids (e.g., 20 types) that undergo dehydration condensation to form one or more peptide chains, which are then folded to form a complex spatial structure. Proteins do not have a fixed chemical formula. They are a type of nitrogen-containing biopolymer with a large molecular weight and complex structure. They are usually composed of elements such as C, H, O, N, and S.

[0107] By setting the material of the surface treatment layer 15 to include mercaptopropylamine or ethylamine, the amine groups in mercaptopropylamine or ethylamine can form a covalent bond with the antibody, thereby tightly connecting the antibody 16 to the surface of the sensing electrodes ( 11B- 1 and 11B- 2 ) through the surface treatment layer 15 .

[0108] For example, in practical applications, a mercaptopropylamine or ethylamine solution can be applied to the surfaces of the sensing electrodes (11B-1 and 11B-2) and incubated at approximately 4°C (±2°C) for 20 to 28 hours (e.g., 24 hours). The electrodes are then washed with PBS buffer at varying concentrations (e.g., 10× and 1× concentrations), followed by a rinse with clean water (e.g., distilled or deionized water). The 14 antibodies corresponding to the 14 protein markers mentioned above are mixed with a 1:1 solution of EDC and NHS, and the mixture is dropped onto 14 different sensing portions 11B and incubated at approximately 15°C (±2°C) for 30 min ± 10 min. Finally, the electrodes are rinsed with PBS buffer at varying concentrations (e.g., 10× and 1× concentrations), followed by a rinse with clean water (e.g., distilled or deionized water). This successfully links different types of antibodies to each sensing portion 11B.

[0109] PBS, the most widely used buffer in biochemical research, is primarily composed of Na₂HPO₄, KH₂PO₄, NaCl, and KCl. It generally serves as a solvent, dissolving protective reagents. EDC stands for 1-(3-dimethylaminopropyl)-3-ethylcarbodiimide hydrochloride, also known as EDC hydrochloride. NHS stands for N-hydroxysuccinimide.

[0110] In at least one embodiment of the present application, as shown in FIG3 or FIG4 , the sensing electrodes 11B- 1 and 11B- 2 include a plurality of extension portions YS and a connection portion LJ connecting the extension portions YS. In the same sensing electrode 11B- 1 or 11B- 2 , the connection portion LJ is located on the same side of the extension portions YS.

[0111] In FIG. 3 or FIG. 4 , in the same sensing electrode, the extension portion YS refers to a structure extending in the vertical direction of the sensing electrode, and the connection portion LJ refers to a structure whose extension direction intersects with the extension direction of the extension portion YS and connects all the extension portions YS together.

[0112] The sensing portion includes a first sensing electrode 11B-2 and a second sensing electrode 11B-1. The orthographic projections of the connecting portion LJ of the first sensing electrode 11B-2 and the two extending portions YS connected at both ends of the connecting portion LJ on the substrate 100 form a first arch shape. The orthographic projections of the connecting portion LJ of the second sensing electrode 11B-1 and the two extending portions YS connected at both ends of the connecting portion LJ on the substrate 100 form a second arch shape. Both ends of the first arch extend into the area enclosed by the second arch.

[0113] By way of example, taking the structure of the sensing portion 11B shown in FIG. 3 , the orthographic projection of the combination of the two extension portions YS and one connecting portion LJ of the first sensing electrode 11B-2 on the substrate 100 is a first arch shape, and the orthographic projection of the combination of the two extension portions YS and one connecting portion LJ on both sides of the second sensing electrode 11B-1 on the substrate 100 is a second arch shape. A dimension of the second arch along a direction perpendicular to the extension portion YS of the second sensing electrode 11B-1 is greater than a dimension of the first arch along a direction perpendicular to the extension portion YS of the first sensing electrode 11B-2. The extension direction of the extension portion YS of the first sensing electrode 11B-2 is the same as the extension direction of the extension portion YS of the second sensing electrode 11B-1.

[0114] In some embodiments, the first arch does not completely include arcs, and may include arcs or straight lines; the second arch does not completely include arcs, and may include arcs or straight lines.

[0115] The two ends of the first arch extend into the area enclosed by the second arch. Combined with FIG. 3 and FIG. 4 , it can be understood that at least part of the two extension portions YS of the first sensing electrode 11B- 2 extend into the area enclosed by the second arch.

[0116] In at least one embodiment of the present application, the number of extension portions YS of the first sensing electrode (e.g., 11B-2) is at least two, the number of extension portions YS of the second sensing electrode (e.g., 11B-1) is at least three, and the extension portions YS of the first sensing electrode (e.g., 11B-2) and the extension portions YS of the second sensing electrode (e.g., 11B-1) are alternately arranged. The orthographic projection of the connection portion LJ on the substrate 100 includes an arc shape.

[0117] For example, as shown in FIG3 and FIG4 , each sensing electrode 11B- 1 includes three extending portions YS, and each sensing electrode 11B- 2 includes two extending portions YS.

[0118] Here, there is no limitation on whether the shape of the orthographic projection of the extension portion YS on the substrate 100 includes an arc.

[0119] For example, as shown in FIG3 , for the sensing electrodes 11B- 1 and 11B- 2 , the orthographic projection shape of the connecting portion LJ on the substrate 100 is an arc, and the orthographic projection shape of the extending portion YS on the substrate 100 is a rectangle.

[0120] For example, as shown in FIG. 4 , the orthographic projection shape of the connecting portion LJ on the substrate 100 is an arc, and the orthographic projection shape of the extending portion YS on the substrate 100 is also an arc.

[0121] Specifically, for the sensing electrode 11B-1, the orthographic projection of the combination of its connecting portion LJ and the two outer extension portions YS on the substrate 100 is a semicircular ring (or a semi-elliptical ring); for the sensing electrode 11B-2, the orthographic projection of the combination of its connecting portion LJ and the two outer extension portions YS on the substrate 100 is a semicircular ring (or a semi-elliptical ring).

[0122] In at least one embodiment of the present application, as shown in FIG. 3 or FIG. 4 , the orthographic projection of the first sensing electrode 11B- 2 on the substrate 100 is U-shaped, the orthographic projection of the connecting portion LJ of the second sensing electrode 11B- 1 on the substrate 100 is arc-shaped, and the orthographic projection of the extending portion YS of the second sensing electrode 11B- 1 on the substrate 100 is rectangular.

[0123] It should be noted that the above-mentioned "U-shape" is a U-shape in a broad sense, not a U-shape in a strict sense. A U-shape obtained by deformation based on the U-shape also falls within the scope of protection of this application.

[0124] It should also be noted that the orthographic projection of the second sensing electrode 11B- 1 on the substrate 100 is an "E-shape". The above "E-shape" is a broad E-shape, not a strict E-shape. E-shapes obtained by deformation based on the E-shape also fall within the scope of protection of this application.

[0125] In the embodiment of the present application, based on the coffee ring effect of the solution of the material of the surface treatment layer 15 described above, the orthographic projection of the first sensing electrode 11B-2 on the substrate 100 is U-shaped, while the orthographic projection of the connecting portion LJ of the second sensing electrode 11B-1 on the substrate 100 is arc-shaped. This increases the contact area between the active ingredients in the sample to be detected and the sensing portion 11B, thereby improving the detection sensitivity of the detection unit 11. Furthermore, the second sensing electrode 11B-1 and the first sensing electrode 11B-2 provided in the embodiment of the present application have a simple structural design, low design cost, and a low manufacturing process difficulty.

[0126] When used for detecting and diagnosing acute myeloid leukemia, the sample to be detected may be "blood", including but not limited to whole blood or a separation obtained from blood.

[0127] In at least one embodiment of the present application, as shown in conjunction with Figures 1 and 2, a first gate Gate1 of the dual-gate transistor is electrically connected to a constant voltage signal input terminal (not shown in the figures), and the first gate Gate1 is configured to control the opening and closing of the dual-gate transistor; a second gate Gate2 of the dual-gate transistor is electrically connected to a pair of sensing electrodes (11B-1 and 11B-2), and the second gate Gate2 is configured to control the change of current in the dual-gate transistor and simultaneously generate a detection current based on the electrical signal generated in the sensing electrodes (11B-1 and 11B-2).

[0128] It should be noted that in the actual detection process, the first gate Gate1 controls the conduction of the dual-gate transistor, and the channel region of the dual-gate transistor generates an initial current I0. When the protein marker reacts with the antibody and generates current, the current is transmitted to the second gate Gate2 through the sensing electrode. The potential on the second gate Gate2 changes, thereby causing the current value of the current flowing through the channel region of the dual-gate transistor to change (detection current I-initial current I0). The concentration of the corresponding protein marker is calculated based on the change in current value.

[0129] In an exemplary embodiment, the planar graphic area of ​​the second gate Gate2 of the dual-gate transistor is larger than the planar graphic area of ​​the pair of sensing electrodes. The larger the difference between the two areas, the more the second gate Gate2 can amplify the electrical signal transmitted by the pair of sensing electrodes during electrical signal transmission, thereby improving detection accuracy.

[0130] In at least one embodiment of the present application, as shown in FIG1 , the signal detection region B further includes at least one negative electrode terminal 13 ; the negative electrode terminal 13 is electrically connected to the second gate Gate2 through the sensing electrodes ( 11B- 1 and 11B- 2 ).

[0131] The specific electrical connection method of the negative electrode terminal 13 and the second gate Gate2 through the sensing electrodes ( 11B- 1 and 11B- 2 ) is not limited here.

[0132] Illustratively, the negative electrode terminal 13 can be electrically connected to the sensing electrode through a wire provided in the same layer as the sensing electrode. The sensing electrode and the second gate Gate2 are located in different conductive film layers. The sensing electrode and the second gate Gate can be electrically connected together through a via (also known as a through hole, Via).

[0133] It should be noted that, in some examples, the negative electrode terminal 13 may be electrically connected to one of the sensing electrodes in one sensing portion 11B.

[0134] In actual applications, when voltage is applied to the first gate Gate1 and the second gate Gate2 of the dual-gate transistor at the same time, as shown in Figure 2, a built-in capacitor is formed between the first gate Gate1 and the second gate Gate2. As the time of applying the voltage on the second gate Gate2 increases, more charge accumulates inside the dual-gate transistor, thereby interfering with the current of the dual-gate transistor. For this reason, in at least one embodiment of the present application, the negative electrode terminal 13 is electrically connected to the correction line, and the negative electrode terminal 13 is configured to release the charge inside the dual-gate transistor to correct the dual-gate transistor.

[0135] In an exemplary embodiment, when a large amount of positive charge accumulates within the dual-gate transistor, the correction line may include a ground line; when a large amount of negative charge accumulates within the dual-gate transistor, the correction line may include a positive signal line. It should be noted that in the embodiments of this application and the subsequent description, the case where a large amount of positive charge accumulates within the dual-gate transistor is used as an example.

[0136] In the embodiment of the present application, the second gate Gate2 is grounded in sequence through one of the sensing electrodes in the sensing portion 11B and the negative electrode terminal 13, so that the charges inside all the dual-gate transistors can be discharged, and the dual-gate transistors can be calibrated simply and quickly, thereby avoiding interference of the charges inside the dual-gate transistors with the current flowing through the dual-gate transistors, thereby avoiding interference with the change value of the detection current, thereby improving the detection accuracy of the detection unit 11 and improving the detection efficiency.

[0137] In at least one embodiment of the present application, as shown in FIG5 , the substrate 100 further includes a signal detection area B located on at least one side of the sample detection area A. The signal detection area B includes: a plurality of first signal acquisition terminals 12 , the first signal acquisition terminals 12 being electrically connected to the signal generating unit 11A, and the number of the first signal acquisition terminals 12 and the number of the signal generating unit 11A being the same;

[0138] The signal detection area B also includes multiple second signal acquisition terminals. As shown in Figure 8, in the detection unit 11, the drain D of the dual-gate transistor is electrically connected to the first signal acquisition terminal 12, and the source S of the dual-gate transistor is electrically connected to the second signal acquisition terminal (unmarked). The first signal acquisition terminal 12, the drain D of the dual-gate transistor, the source S of the dual-gate transistor, and the second signal acquisition terminal are configured to form a conductive loop, and the detection current is the current in the loop during the detection time period.

[0139] It should be noted that, as shown in FIG5 , FIG5 only illustrates the schematic diagram of the wires electrically connecting the dual-gate transistor to the first signal acquisition terminal 12, and does not illustrate the schematic diagram of the wires electrically connecting the dual-gate transistor to the second signal acquisition terminal. The location and arrangement of the plurality of second signal acquisition terminals in the detection substrate are not limited here and can be designed based on the actual space. The location and arrangement of the plurality of first signal acquisition terminals 12 in the detection substrate are not limited here and can be designed based on the actual space.

[0140] Exemplarily, as shown in FIG. 5 and FIG. 6 , the plurality of first signal acquisition terminals 12 may be evenly distributed.

[0141] In FIG5 , multiple first signal acquisition terminals 12 and negative electrode terminals 13 may be distributed at equal intervals; or, as shown in FIG6 , multiple first signal acquisition terminals 12 may be distributed at equal intervals, and the minimum distance between the negative electrode terminal 13 and the first signal acquisition terminal 12 is greater than the minimum distance between two adjacent first signal acquisition terminals 12 .

[0142] In addition, the film layer location of the wire between the source S and the second signal acquisition terminal of the dual-gate transistor is not limited here, and the film layer location of the wire between the drain D and the first signal acquisition terminal 12 of the dual-gate transistor is also not limited. It can be located in any conductive layer of the detection substrate. As shown in Figure 2, the wire can be located in at least one of the first conductive layer 2, the second conductive layer 6, the source-drain conductive layer 8, and the third conductive layer 10. The specific location can be determined based on the design space and the manufacturing process.

[0143] In at least one embodiment of the present application, as shown in FIG5 , the sample testing area B includes at least one reference cell 14 , and the reference cell 14 includes a reference electrode 14B and a dual-gate transistor 11A;

[0144] In the reference unit 14, the first gate Gate1 of the dual-gate transistor is electrically connected to the constant voltage signal input terminal, the first gate Gate1 is configured to control the opening and closing of the dual-gate transistor, and the second gate Gate2 of the dual-gate transistor is electrically connected to the reference electrode 14B. In addition, similar to the dual-gate transistor in the previous detection unit 11, the drain D of the dual-gate transistor in the reference unit 14 is electrically connected to the first signal acquisition terminal, and the source S of the dual-gate transistor is electrically connected to the second signal acquisition terminal.

[0145] In an exemplary embodiment, the reference unit 14 serves as a blank control group in the detection process, and is used to detect background signals to improve the accuracy of the detection and eliminate interference from other external factors.

[0146] In some embodiments, the reference electrode 14B can be configured to have the same structure, dimensions, and material as the sensing portion 11B. For example, the structure of the reference electrode 14B can be similar to the pair of sensing electrodes shown in FIG3 or FIG4 , and the material can be the same as that of the sensing electrodes, namely, gold (Au).

[0147] In other embodiments, in order to simplify the design, the plane shape of the reference electrode 14B can be set to a polygon, such as a quadrilateral; the material of the reference electrode 14B can be set to a stacked silver (Ag) / silver chloride (AgCl). Since silver chloride (AgCl) is unstable, a protective layer can be further covered on the silver chloride (AgCl), and the material of the protective layer can be a resin, such as polyvinyl butyral.

[0148] In practical applications, the second gate of the dual-gate transistor, Gate2, can be in direct contact with the reference electrode 14B. Specifically, during the preparation process, silver colloid can be directly dip-coated onto the second gate, Gate2, and heated at 75°C for approximately 15 minutes to evaporate the solvent. A 0.1 M FeCl3 solution is then dripped onto the silver colloid and allowed to react for approximately 4 minutes to form an AgCl layer. The surface of the AgCl electrode is then treated with a PVB methanol solution at room temperature for 3 hours to form a protective layer.

[0149] In the embodiments of the present application, the main function of the reference electrode 14B is to provide a stable electrode potential. Whether the reference electrode 14B is made of the same material and structure as the sensing electrode is not limited. To simplify the design and improve the stability of the potential of the reference electrode 14B, it is preferred that the reference electrode 14B be made of a laminated silver (Ag) / silver chloride (AgCl) material and covered with a protective layer. This is specifically noted.

[0150] In at least one embodiment of the present application, as shown in FIG5 and FIG6 , the sample testing area A includes a first sub-area A1 and a second sub-area A2; the substrate 100 includes a first signal detection sub-area B1 and a second signal detection sub-area B2 located on both sides of the sample testing area A; the first sub-area A1 and the second sub-area A2 each include eight detection units 11;

[0151] In the first sub-area A1, four detection units 11 are arranged along the first direction F1, and the other four detection units 11 are arranged along the second direction F2, and the first direction F1 and the second direction F2 intersect; an acute angle is formed between the first direction F1 and the direction from the first sub-area A1 to the second sub-area A2 (the direction indicated by the dotted arrow in Figure 5), and an acute angle is formed between the second direction F2 and the direction from the first sub-area A1 to the second sub-area A2 (the direction indicated by the dotted arrow in Figure 5); the angle between the first direction F1 and the second direction F2 is also an acute angle.

[0152] The arrangement of the detection units 11 in the second sub-area A2 is symmetrical to the arrangement of the detection units 11 in the first sub-area A1.

[0153] In at least one embodiment of the present application, as shown in FIG5 and FIG6 , the first sub-area A1 includes a first line L1, and the second sub-area A2 includes a second line L2. The first line L1 and the second line L2 have the same length and are symmetrically arranged. The first line L1 and the second line L2 both extend in a direction from the first sub-area A1 to the second sub-area A2 (the direction indicated by the dotted arrow in FIG5 ).

[0154] The first line L1 is configured to connect the eight detection units 11 in the first sub-area A1 in series, and the second line L2 is configured to connect the eight detection units 11 in the second sub-area A2 in series.

[0155] In at least one embodiment of the present application, as shown in FIG5 and FIG6 , the first signal detection sub-area B1 is located on a side of the first sub-area A1 away from the second sub-area A2, and the second signal detection sub-area B2 is located on a side of the second sub-area A2 away from the first sub-area A1;

[0156] The first signal detection sub-area B1 includes a first negative electrode terminal (the negative electrode terminal 13 located in the first signal detection sub-area B1 is called the first negative electrode terminal), the second detection sub-area B2 includes a second negative electrode terminal (the negative electrode terminal 13 located in the second signal detection sub-area B2 is called the second negative electrode terminal), the second gate Gate2 of all dual-gate transistors in the first sub-area A1 are electrically connected to the first negative electrode terminal in sequence through the sensing electrode and the first routing line L1, and the second gate Gate2 of all dual-gate transistors in the second sub-area A2 are electrically connected to the second negative electrode terminal in sequence through the sensing electrode and the second routing line L2.

[0157] In an exemplary embodiment, as shown in FIG. 5 or FIG. 6 , the first trace L1 and the second trace L2 are traces extending in the horizontal direction. In addition, a plurality of third traces L3 extending in the vertical direction are provided on the detection substrate for connecting the first trace L1 (or the second trace L2) and the sensing electrodes.

[0158] Exemplarily, the first trace L1 and the second trace L2 may be provided on the same layer.

[0159] Exemplarily, the first wiring L1 and the second wiring L2 may be provided on the same layer as the sensing electrodes ( 11B- 1 and 11B- 2 ).

[0160] In an embodiment of the present application, the eight detection units 11 in the first sub-area A1 are connected in series through the first line L1, and the second gates Gate2 of all the dual-gate transistors in the eight detection units 11 are electrically connected to the first negative electrode terminal in turn through the sensing electrode and the first line L1, and the first negative electrode terminal is then connected to the ground end, thereby reducing the number of lines in the detection substrate, uniformly discharging the accumulated charges in all the dual-gate transistors, eliminating static electricity, ensuring the stability of the characteristics of all the dual-gate transistors, reducing the number of lines set, and saving the design space of the detection substrate.

[0161] In at least one embodiment of the present application, as shown in FIG5 , in the first sub-area A1 or the second sub-area A2 , along a direction parallel to the plane of the substrate 100 , the minimum distance H between any two adjacent sensing portions 11 is greater than or equal to 1.2 cm.

[0162] In an exemplary embodiment, in the first sub-area A1 , the minimum distance between any two adjacent sensing portions 11 is substantially equal.

[0163] In an exemplary embodiment, in the second sub-area A2 , the minimum distance between any two adjacent sensing portions 11 is substantially equal.

[0164] Exemplarily, the minimum distance H between any two adjacent sensing portions 11 may be 1.3 cm, 1.4 cm, 1.5 cm, 1.6 cm, 1.7 cm, 1.8 cm, 1.9 cm, or 2.0 cm.

[0165] Table 1: Minimum distance H between two adjacent sensing parts when interference does not occur at the same time

[0166] In the embodiments of the present application, according to the data in Table 1, by setting the minimum distance H between two adjacent sensing portions 11 to be greater than or equal to 1.2 cm, interference between different types of antibodies can be avoided during the preparation of the detection substrate, for example, when connecting the antibodies 16, thereby improving the preparation yield of the detection substrate and reducing the difficulty of the preparation process.

[0167] In at least one embodiment of the present application, as shown in FIG5 , the detection substrate further includes a plurality of third lines L3 , wherein the extension direction of the third lines L3 intersects with the first lines L1 ; a portion of the third lines L3 is configured to connect the first lines L1 and the detection units 11 in the first sub-area A1 , and another portion of the third lines L3 is configured to connect the second lines L2 and the detection units 11 in the second sub-area A2 ;

[0168] The length of the wiring between each detection unit 11 in the first sub-area A1 and the first negative electrode terminal and the length of the wiring between each detection unit 11 in the second sub-area A2 and the second negative electrode terminal are both in the range of 0.5 cm to 5 cm.

[0169] In an exemplary embodiment, as shown in FIG. 5 or FIG. 6 , the first trace L1 and the second trace L2 are traces extending in the horizontal direction. In addition, a plurality of third traces L3 extending in the vertical direction are provided on the detection substrate for connecting the first trace L1 (or the second trace L2) and the sensing electrodes.

[0170] Exemplarily, the third line L3 may be provided on the same layer as the first line L1 and the second line L2.

[0171] Exemplarily, the lengths of the first line L1 and the second line L2 are equal.

[0172] Illustratively, the length of the wiring connecting the detection unit 11 and the first negative electrode terminal in the first sub-area A1 and the length of the wiring connecting the detection unit 11 and the second negative electrode terminal in the second sub-area A2 can be 0.6 cm, 1.0 cm, 1.3 cm, 1.5 cm, 1.8 cm, 2.0 cm, 2.5 cm, 2.8 cm, 3.0 cm, 3.5 cm, 3.8 cm, 4.0 cm, 4.3 cm, 4.5 cm or 4.8 cm.

[0173] Here, there is no limitation on whether the wiring lengths between each detection unit 11 in the first sub-area A1 and the first negative electrode terminal and the wiring lengths between each detection unit 11 in the second sub-area A2 and the second negative electrode terminal are the same, and the specific lengths can be determined based on actual conditions.

[0174] For example, the lengths of two symmetrical routing portions may be substantially the same.

[0175] Table 2: Effect of the wiring length between each detection unit in the first sub-area and the first negative electrode terminal on sensitivity

[0176] According to Table 2, the shorter the wiring length between the detection unit 11 and the first negative electrode terminal, the better the calibration effect on the dual-gate transistor. In the actual detection process, the higher the detection sensitivity is. From the data in Table 2, it can be seen that when the wiring length between the detection unit 11 and the first negative electrode terminal is greater than 5.0 cm, the detection sensitivity of the detection unit 11 is reduced due to the influence of the wiring resistance itself on the discharge effect of the dual-gate transistor. Therefore, the upper limit value of the wiring length between the detection unit 11 and the first negative electrode terminal is set to 5 cm.

[0177] Table 3 Effect of the difference in wiring length between each detection unit and the first negative electrode terminal in the first sub-area on the detection sensitivity of different detection units

[0178] The length difference in Table 3 refers to the difference between the wiring length between one detection unit and the first negative electrode terminal in the first sub-area and the wiring length between another detection unit and the first negative electrode terminal. The greater the length difference, the greater the sensitivity difference between the two detection units, and it is difficult to take into account the sensitivity of each detection unit in the detection substrate. From the length difference data in Table 3, it can be seen that when the length difference is greater than 4.5cm, the sensitivity difference of the detection unit is relatively large. Combined with the upper limit value of the wiring length between the detection unit 11 and the first negative electrode terminal set to 5cm in the previous text, the lower limit value of the wiring length between the detection unit 11 and the first negative electrode terminal is set to 0.5cm.

[0179] In addition, the wiring length between each detection unit 11 and the second negative electrode terminal in the second sub-area A2 is similar to that in the first sub-area A1 and will not be described in detail.

[0180] In an embodiment of the present application, by setting the wiring length between each detection unit 11 in the first sub-area A1 and the first negative electrode terminal and the wiring length between each detection unit 11 in the second sub-area A2 and the second negative electrode terminal to be in the range of 0.5 cm to 5 cm, excessive differences in wiring distances between different detection units 11 and the negative electrode terminal 13 are avoided, thereby reducing the negative impact of wiring length differences on the detection sensitivity of the detection unit 11.

[0181] In at least one embodiment of the present application, as shown in FIG2 , the detection substrate includes a first conductive layer 2, a first insulating layer 3, a semiconductor layer 4, a second insulating layer 5, a second conductive layer 6, a third insulating layer 7, a source-drain conductive layer 8, a fourth insulating layer 9, and a third conductive layer 10, which are sequentially arranged on a base 100; wherein the first conductive layer 2 includes a first gate Gate1 of each dual-gate transistor, the semiconductor layer 4 includes an active portion AL of each dual-gate transistor, the second conductive layer 6 includes a second gate Gate2 of each dual-gate transistor and a plurality of first connection electrodes DJ1, and the source-drain conductive layer 8 includes a source S, a drain D, and a plurality of second connection electrodes DJ2 of each dual-gate transistor;

[0182] The sensing electrodes 11B- 1 and 11B- 2 are electrically connected to the second gate Gate of the dual-gate transistor via the second connection electrode DJ2 and the first connection electrode DJ1 in sequence.

[0183] Exemplarily, the material of the first conductive layer 2 may be metal, such as molybdenum (Mo).

[0184] Illustratively, the material of the first insulating layer 3 may be an inorganic material, such as at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0185] Exemplarily, the material of the semiconductor layer 4 may be a metal oxide, such as indium gallium zinc oxide (IGZO).

[0186] Exemplarily, the material of the second insulating layer 5 may be an inorganic material, such as at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0187] Exemplarily, the material of the second conductive layer 6 may be metal, such as aluminum (Al).

[0188] Illustratively, the material of the third insulating layer 7 may be an organic material, such as resin.

[0189] For example, the source-drain conductive layer 8 may be made of metal, such as a stacked layer of chromium (Cr) and gold (Au), wherein the thickness of Cr is approximately 20±5 nm and the thickness of Au is approximately 40±5 nm.

[0190] Exemplarily, the material of the fourth insulating layer 9 may be an inorganic material, such as at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0191] Exemplarily, the material of the third conductive layer 10 may be metal, such as gold (Au), and the thickness thereof is approximately 40±5 nm.

[0192] It should be noted that in FIG2 , the sensing electrodes 11B-1 and 11B-2 are electrically connected to the first connection electrode DJ1 via the second connection electrode DJ2. The first connection electrode DJ1 and the second gate Gate2 of the dual-gate transistor are both located in the second conductive layer 6. The first connection electrode DJ1 and the second gate Gate2 of the dual-gate transistor are connected together via a wire located in the second conductive layer 6. The wire between the first connection electrode DJ1 and the second gate Gate2 of the dual-gate transistor is not shown in FIG2 .

[0193] In at least one embodiment of the present application, the first wiring L1 and the second wiring L2 are both provided on the same layer as the sensing electrodes 11B- 1 and 11B- 2 .

[0194] In at least one embodiment of the present application, the first wiring L1 and the second wiring L2 may be provided on any one of the source-drain conductive layer 8 , the second conductive layer 6 and the first conductive layer 2 .

[0195] 2 , the third trace L3 mentioned above (ie, the wire used to connect the sensing electrode and the first trace L1 or the wire used to connect the sensing electrode and the second trace L2 ) may also be provided on the second conductive layer 6 .

[0196] In the detection substrate provided in the embodiments of the present application, compared with external transistors, a transistor structure is provided within the film layer of the detection substrate, which can reduce the resistance between the sensing electrode and the second gate Gate2 of the dual-gate transistor, reduce the connection of external wires, reduce charge migration loss, and improve detection sensitivity.

[0197] Below, taking interleukin 20 (IL-20) as an example, how to determine the concentration of the protein marker in the sample to be detected based on the change in the detection current is explained as follows:

[0198] First, a reference standard variation curve of the detection current change value as the interleukin 20 (IL-20) concentration changes is determined, and a regression equation formula of the curve is obtained.

[0199] The following describes in detail how to obtain the reference standard change curve:

[0200] 1. When the first gate of the dual-gate transistor, Gate1, controls the dual-gate transistor to be open and no test sample is added, record the initial current value I0 of the detection unit 11; -1 IL-20 was added at 20 μL min -1 After the solution was passed into the detection unit at a speed of 100 nm for 30 seconds, it was washed with 0.005 nM sulfuric acid, and the detection current passing through the double-gate transistor was measured after a response time of 60 seconds.

[0201] 2. When the first gate of the dual-gate transistor Gate1 controls the dual-gate transistor to be open and no test sample is added, the initial current value I0 of the detection unit 11 is recorded; 2 pg·mL -1 IL-20 was added at 20 μL min -1 After the solution was passed into the detection unit at a speed of 100 nm for 30 seconds, it was washed with 0.005 nM sulfuric acid, and the detection current passing through the double-gate transistor was measured after a response time of 60 seconds.

[0202] 3. Measure the detection current at different concentration gradients after IL-20 is introduced into the detection cell for 30 seconds (similar to the previous two steps). A curve showing the change in detection current with changing IL-20 concentration is obtained, as shown in Figure 9. This curve was fitted to the resulting regression equation: y = -0.5972*x - 11.434, where x represents the abscissa and y represents the ordinate in Figure 9.

[0203] In addition, it should be noted that according to the curve data in Figure 9, when the interleukin 20 (IL-20) concentration is 5 to 30 pg·mL -1 The regression equation has high accuracy in the range of 5 pg·mL. -1 , greater than 30 pg·mL -1 In the case of IL-20, the curves fluctuate greatly. Therefore, in the actual measurement range, when the concentration of interleukin 20 (IL-20) exceeds 5-30 pg·mL -1 The test results are not used as a practical reference.

[0204] Second, during the actual detection process, the above curve and / or regression equation formula is used as a reference, and the interleukin 20 (IL-20) concentration in the sample to be detected is calculated according to the actual change value of the detection current.

[0205] It should be noted that the concentration calculation methods of other protein markers are similar to that of interleukin 20 (IL-20) and will not be described in detail.

[0206] An embodiment of the present application provides a detection chip, as shown in Figure 10, including the detection substrate as described above, and also including a cover plate 200 and an adhesive layer (not drawn), the cover plate 200 covers the sample test area A of the detection substrate, and the cover plate 200 is provided with a sample inlet hole (at the position marked A3) and a sample outlet hole (at the position marked A4), the adhesive layer is located between the detection substrate and the cover plate 200, and a cavity structure is formed between the detection substrate, the cover plate 200 and the adhesive layer.

[0207] For example, the cover plate 200 may be made of resin or glass.

[0208] Illustratively, the material of the bonding layer may be glue, adhesive or glue.

[0209] In the actual process of preparing the detection chip, a dispensing machine is used to evenly apply the adhesive layer material on the area near the edge of the sample test area A of the detection substrate, cover it with a cover plate 200, bake it at 100℃ for 5 minutes, then program the temperature to 150℃ and bake it for about 10 minutes.

[0210] Exemplarily, the thickness of the adhesive layer is 100 μm±10 μm, and the thickness of the detection chip is substantially the same as the thickness of the adhesive layer.

[0211] In at least one embodiment of the present application, all detection units 11 on the detection substrate are located in the same cavity structure.

[0212] In the chip provided in the embodiment of the present application, as shown in FIG10 , by arranging multiple detection units 11 in the same cavity structure (not drawn in FIG10 ), different AML-related protein markers in the same sample to be detected can be identified simultaneously, significantly improving diagnostic accuracy, providing an efficient AML monitoring and detection platform for the clinic, and promoting the development of personalized treatment. In addition, according to the coffee ring effect of the solution, the outer contours of the two sensing electrodes (such as the sensing electrode 11B-1 and the sensing electrode 11B-2 in FIG3 or FIG4 ) in the same sensing portion 11B are both arc-shaped. In this way, the contact area between the effective ingredients in the sample to be detected and the sensing portion 11B can be increased, thereby improving the detection sensitivity of the detection unit 11.

[0213] A method for detecting acute myeloid leukemia using the above-mentioned detection chip is provided below to verify the detection effect of the detection chip provided in the embodiments of the present application, as follows:

[0214] 1. Select 10 AML patients and 10 healthy individuals. (All 10 AML patients and 10 healthy individuals are volunteers)

[0215] 2. Record the initial current value Io. Pre-treat blood samples from 10 AML patients and 10 healthy individuals. The treated serum samples were washed with water at a rate of 20 μL / min. -1 The detection chip was passed through for 30 seconds, washed with 0.005 nM sulfuric acid, and the current response was measured for 60 seconds. The concentrations of 14 protein markers were calculated based on the linear range of the calibrated response curve (i.e., the reference standard change curve mentioned above); the protein marker concentration level distribution diagram of 10 AML patients and 10 healthy individuals was obtained as shown in Figure 11.

[0216] As shown in Figure 7, the concentrations of multiple AML-related protein markers are generally higher in AML patients than in healthy individuals. This multi-indicator approach not only ensures the accuracy of test results for patients, preventing false negatives, but also avoids false positives due to misdiagnosis caused by a single indicator.

[0217] Compared to the related art of measuring a single protein marker to diagnose a patient's disease, the detection chip provided by the embodiment of the present application can specifically identify multiple AML-related protein markers at the same time, significantly improving diagnostic accuracy. Even in the case of abnormal detection of a single protein marker in an individual, the test structure of 14 AML-related protein markers can be integrated to provide a more accurate diagnostic result, providing a clinically efficient AML monitoring platform and promoting the development of personalized treatment. In addition, compared with traditional chips, the present application greatly improves detection sensitivity; and the preparation cost is low, and it is a disposable consumable, avoiding residual contamination.

[0218] The present invention also provides a method for preparing a detection chip, which is as follows:

[0219] 1. Provide a substrate 100 as shown in FIG12A .

[0220] For example, the substrate 100 is made of glass.

[0221] 2. As shown in FIG12B , a first conductive layer 2 is formed on the substrate 100 , wherein the first conductive layer includes a first gate Gate1 of the dual-gate transistor.

[0222] Before forming the first conductive layer 2 , the substrate 100 is cleaned.

[0223] 3. As shown in FIG12C , a first insulating layer 3 is formed.

[0224] 4. As shown in FIG12D , a semiconductor layer 4 is formed.

[0225] Exemplarily, the thickness of the semiconductor layer 4 is 30 nm±5 nm.

[0226] The semiconductor layer 4 includes an active portion AL of the dual-gate transistor, which forms a channel region of the transistor. The length L of the channel region is approximately 450±50 μm, and the width W of the channel region is approximately 500±50 μm.

[0227] 5. As shown in FIG12E , a second insulating layer 5 is formed.

[0228] 6. As shown in FIG12F , a second conductive layer 6 is formed. The second conductive layer 6 includes a second gate Gate2 of the dual-gate transistor.

[0229] 7. As shown in FIG12G , a third insulating layer 7 is formed, and an etching process (eg, a wet etching process) is used to form a via hole Via as shown in FIG12H .

[0230] 8. As shown in FIG12I , a source-drain conductive layer 8 is formed; the source-drain conductive layer 8 includes the source S, the drain D and a plurality of second connection electrodes DJ2 of each dual-gate transistor.

[0231] 9. As shown in FIG12J , a fourth insulating layer 9 is formed, and an etching process (eg, a wet etching process) is used to form a via hole Via as shown in FIG12J .

[0232] 10. As shown in FIG12K , a third conductive layer 10 is formed. The third conductive layer 10 includes a sensing portion 11B (including a sensing electrode 11B- 1 and a sensing electrode 11B- 2 ).

[0233] 11. Use a dispensing process to apply the material of the bonding layer 15, cover the upper cover plate 200, bake at 100°C for 5 minutes, then program the temperature to 150°C and bake for about 10 minutes to obtain the bonding layer 15 and cover plate 200 as shown in Figure 12L, wherein the detection substrate, cover plate 200 and bonding layer 15 form a cavity structure.

[0234] For example, along a plane parallel to the substrate 100 , the planar shape of the adhesive layer 15 is a ring, and the width of the ring is approximately 1.2 mm±1 mm.

[0235] Exemplarily, the size of the cover plate 200 is approximately 7 cm*2 cm*0.3 cm.

[0236] All detection units 11 are located in the same cavity structure. In order to simplify the drawings, only one detection unit 11 is drawn in the cavity structure in the drawings provided in the embodiments of the present application, which does not represent a limitation on the number of detection units 11 in the cavity structure.

[0237] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A detection substrate, wherein: comprising a substrate; the substrate comprising a sample testing area; The sample testing area includes: a plurality of detection units, each detection unit includes a sensing part and a signal generating part, wherein the sensing part and the signal generating part are electrically connected; the sensing part is configured to react with the sample to be detected and generate an electrical signal, and the signal generating part is configured to receive the electrical signal and generate a detection current; The sensing part includes a pair of sensing electrodes, and both of the pair of sensing electrodes are electrically connected to the signal generating part; and the contours of the sensing electrodes include arc lines.

2. The detection substrate according to claim 1, wherein: The signal generating section includes a double-gate transistor, and a first gate and a second gate of the double-gate transistor are configured to be connected to different conductive structures.

3. The detection substrate according to claim 2, wherein: The sensing unit further includes an antibody located on each pair of the sensing electrodes, wherein the antibody and the sensing electrodes are configured to be connected via a covalent bond; the antibodies on each pair of the sensing electrodes are of different types; The sensing portion further includes a surface treatment layer, wherein the surface treatment layer covers each pair of the sensing electrodes, and the surface treatment layer is configured to form the covalent bond with the antibody.

4. The detection substrate according to claim 3, wherein: The sensing electrode comprises a plurality of extensions and a connecting portion connecting the extensions; in the same sensing electrode, the connecting portion is located on the same side of the extensions; The sensing portion includes a first sensing electrode and a second sensing electrode, the connecting portion of the first sensing electrode and the two extending portions connected at both ends of the connecting portion being an orthographic projection shape on the substrate being a first arch, the connecting portion of the second sensing electrode and the two extending portions connected at both ends of the connecting portion being an orthographic projection shape on the substrate being a second arch, and both ends of the first arch extend into an area surrounded by the second arch.

5. The detection substrate according to claim 4, wherein: The number of the extending portions of the first sensing electrode is at least two, the number of the extending portions of the second sensing electrode is at least three, and the extending portions of the first sensing electrode and the extending portions of the second sensing electrode are alternately arranged; The shape of the orthographic projection of the connecting portion on the base includes an arc.

6. The detection substrate according to any one of claims 5, wherein The orthographic projection shape of the first sensing electrode on the substrate is U-shaped; the orthographic projection shape of the connecting portion of the second sensing electrode on the substrate is arc-shaped, and the orthographic projection shape of the extending portion of the second sensing electrode on the substrate is rectangular.

7. The detection substrate according to claim 2, wherein: The first gate of the dual-gate transistor is electrically connected to a constant voltage signal input terminal, and the first gate is configured to control the opening and closing of the dual-gate transistor; The second gate of the double-gate transistor is electrically connected to the pair of sensing electrodes, and the second gate is configured to control the change of the current in the double-gate transistor according to the electrical signal generated in the sensing electrodes and generate the detection current at the same time.

8. The detection substrate according to claim 7, wherein: The substrate further comprises a signal detection area located at least on one side of the sample detection area, and the signal detection area comprises at least one negative electrode terminal; the negative electrode terminal is electrically connected to the second grid through the sensing electrode.

9. The detection substrate according to claim 8, wherein: The negative electrode terminal is electrically connected to a correction line, and the negative electrode terminal is configured to release charges inside the dual-gate transistor to correct the dual-gate transistor.

10. The detection substrate according to claim 8, wherein: The signal detection area includes: a plurality of first signal acquisition terminals, the first signal acquisition terminals are electrically connected to the signal generating unit, and the number of the first signal acquisition terminals and the number of the signal generating unit are the same, The signal detection area also includes a plurality of second signal acquisition terminals, In the detection unit, the drain of the dual-gate transistor is electrically connected to the first signal acquisition terminal, the source of the dual-gate transistor is electrically connected to the second signal acquisition terminal, the first signal acquisition terminal, the drain of the dual-gate transistor, the source of the dual-gate transistor and the second signal acquisition terminal are configured to form a conductive loop, and the detection current is the current in the loop during the detection time period.

11. The detection substrate according to claim 8, wherein: The sample testing area includes at least one reference unit, and the reference unit includes a reference electrode and the dual-gate transistor; In the reference unit, the first gate of the dual-gate transistor is electrically connected to the constant voltage signal input terminal, and the first gate is configured to control the opening of the dual-gate transistor. and closed, the second gate of the double-gate transistor is electrically connected to the reference electrode, the drain of the double-gate transistor is electrically connected to the first signal acquisition terminal, and the source of the double-gate transistor is electrically connected to the second signal acquisition terminal.

12. The detection substrate according to claim 11, wherein: The sample testing area includes a first sub-area and a second sub-area; the substrate includes a first signal detection sub-area and a second signal detection sub-area located on both sides of the sample testing area; the first sub-area and the second sub-area each include eight detection units; In the first sub-area, four of the detection units are arranged along a first direction, and another four of the detection units are arranged along a second direction, the first direction and the second direction intersect; an acute angle is formed between the first direction and a direction from the first sub-area to the second sub-area, and an acute angle is formed between the second direction and a direction from the first sub-area to the second sub-area; The arrangement of the detection units in the second sub-area is symmetrical to the arrangement of the detection units in the first sub-area.

13. The detection substrate according to claim 12, wherein: The first sub-area includes a first routing line, the second sub-area includes a second routing line, the first routing line and the second routing line have the same length and are symmetrically arranged; the first routing line and the second routing line both extend in a direction from the first sub-area to the second sub-area; The first wiring is configured to connect the eight detection units in the first sub-area in series, and the second wiring is configured to connect the eight detection units in the second sub-area in series.

14. The detection substrate according to claim 13, wherein: The first signal detection sub-region is located at a side of the first sub-region away from the second sub-region, and the second signal detection sub-region is located at a side of the second sub-region away from the first sub-region; The first signal detection sub-area includes a first negative electrode terminal, the second detection sub-area includes a second negative electrode terminal, the second gates of all the dual-gate transistors in the first sub-area are electrically connected to the first negative electrode terminal through the sensing electrode and the first wiring in sequence, and the second gates of all the dual-gate transistors in the second sub-area are electrically connected to the second negative electrode terminal through the sensing electrode and the second wiring in sequence.

15. The detection substrate according to claim 12, wherein: In the first sub-area or the second sub-area, along a direction parallel to the plane where the substrate is located, a minimum distance between any two adjacent sensing parts is greater than or equal to 1.2 cm.

16. The detection substrate according to claim 14, wherein: The detection substrate further includes a plurality of third routing lines, the extension direction of the third routing lines intersects with the first routing lines; a portion of the third routing lines is configured to connect the first routing lines and the detection units in the first sub-area, and another portion of the third routing lines is configured to connect the second routing lines and the detection units in the second sub-area; The length of the wiring connecting the detection unit and the first negative electrode terminal in the first sub-area and the length of the wiring connecting the detection unit and the second negative electrode terminal in the second sub-area are both in the range of 0.5 cm to 5 cm.

17. The detection substrate according to any one of claims 13 to 14 and 16, wherein The detection substrate comprises a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a source-drain conductive layer, a fourth insulating layer and a third conductive layer which are sequentially arranged on the base; The first conductive layer includes a first gate of each of the double-gate transistors, the semiconductor layer includes an active portion of each of the double-gate transistors, the second conductive layer includes a second gate of each of the double-gate transistors and a plurality of first connecting electrodes, and the source-drain conductive layer includes a source, a drain and a plurality of second connecting electrodes of each of the double-gate transistors; The sensing electrode is electrically connected to the second gate of the dual-gate transistor via the second connecting electrode and the first connecting electrode in sequence.

18. A detection chip, wherein: It includes a detection substrate as described in any one of claims 1 to 17, and also includes a cover plate and an adhesive layer, the cover plate covers the sample testing area of ​​the detection substrate, the cover plate is provided with a sample inlet hole and a sample outlet hole, the adhesive layer is located between the detection substrate and the cover plate, and a cavity structure is formed between the detection substrate, the cover plate and the adhesive layer; all the detection units on the detection substrate are located in the same cavity structure.

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