Bandwidth maximization
By designing a method of coordinating data transmission between sub-blocks in an integrated circuit, using a specific signal and a third signal in a clock cycle to transmit continuous messages, the problem of efficient data transmission between sub-blocks is solved, and the effect of maximizing communication bandwidth and reducing the logic complexity of receiving sub-blocks is achieved.
Patent Information
- Application Number
- CN202280100492.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-29
- Publication Date
- 2025-05-06
AI Technical Summary
In integrated circuits, it is difficult for the prior art to achieve efficient data transmission between sub-blocks, especially to maintain low logical complexity of receiving sub-blocks while maximizing communication bandwidth.
By designing a method in an integrated circuit, the method includes transmitting a specific signal between sub-blocks to coordinate data transmission and transmitting a continuous message through a third signal in a clock cycle, the first signal containing information at the end of the message transmission that enables the receiving sub-block to determine the end position of the message.
This method allows sub-blocks to continuously transmit messages, maximizing communication bandwidth between sub-blocks while avoiding increasing the logical complexity of receiving sub-blocks.
Smart Images
Figure CN119948468A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to methods and systems for transmitting data in an integrated circuit. Background Art
[0002] Electronic devices containing system-on-chip (SoC) circuits have become very common in recent years. This trend has been driven by the demand for small consumer electronic devices such as smartphones and tablets, and the use of SoCs in embedded systems such as Internet of Things (IoT) devices and Wi-Fi routers.
[0003] SoC devices are integrated circuits that combine computing components onto a single substrate or microchip. These components may include one or more processor cores, memory, input / output interfaces, a graphics processing unit (GPU), and secondary storage interfaces. SoC architectures offer many benefits, including power savings, space savings, lower latency, and reduced costs. Summary of the invention
[0004] An object of the present disclosure is to provide a method for transmitting data in an integrated circuit.
[0005] The above-mentioned and other objects are achieved by the features of the independent claims. Other embodiments are evident from the dependent claims, the description and the drawings.
[0006] According to a first aspect, a method for transmitting data in an integrated circuit is provided, the integrated circuit comprising at least two interconnected sub-blocks in a system-on-chip (SoC) arrangement. The method comprises: transmitting a first signal from a first sub-block to a second sub-block, the first signal indicating that the first sub-block is ready to transmit data to the second sub-block; receiving a second signal from the second sub-block at the first sub-block, the second signal indicating that the second sub-block is ready to receive data from the first sub-block; and transmitting data from the first sub-block to the second sub-block via a third signal during one or more clock cycles of the integrated circuit, the data comprising one or more consecutive messages. The first signal comprises information at the end of the transmission of the one or more consecutive messages that enables the second sub-block to determine the position of the end of the last message in the one or more consecutive messages.
[0007] The method according to the first aspect allows a sub-block to continuously transmit a message to another sub-block. The method maximizes the communication bandwidth between sub-blocks without increasing the logic complexity at the receiving sub-block.
[0008] According to a second aspect, an integrated circuit is provided, the integrated circuit comprising at least two sub-blocks in a system-on-chip (SoC) arrangement. A first sub-block of the at least two sub-blocks is configured to: transmit a first signal, the first signal indicating that the first sub-block is ready to transmit data to a second sub-block; receive a second signal from the second sub-block, the second signal indicating that the second sub-block is ready to receive data from the first sub-block; and transmit data via a third signal during one or more clock cycles of the integrated circuit, the data comprising one or more consecutive messages. The first signal includes information at the end of the transmission of the one or more consecutive messages that enables the second sub-block to determine the position of the end of the last message in the one or more consecutive messages.
[0009] In a first implementation form of the method according to the first aspect, the position of the end of the last message comprises a byte position in the third signal during a clock cycle containing the end of said transmission.
[0010] In a second embodiment, the end of the last message comprises the last byte in the third signal during the clock cycle containing the end of the transmission.
[0011] In a third embodiment, the information enabling the second sub-block to determine the position of the end of the last message comprises information indicating that the end of the message is the last byte of the third signal.
[0012] The method according to the third embodiment enables the receiving sub-block to determine that the byte position of the end of the message is the last byte of the third signal. This enables the receiving sub-block to determine that all bytes received in a clock cycle are valid data bytes of the message from the transmitting sub-block.
[0013] In a fourth embodiment, the position is provided in a last byte of the third signal during a clock cycle containing the end of the transfer.
[0014] In a fifth embodiment, the information enabling the second sub-block to determine the position of the end of the last message comprises information indicating the position where the end of the message is provided in the last byte of the third signal during the clock cycle containing the end of the transmission.
[0015] The method according to the fifth embodiment enables the receiving sub-block to determine the position in the last byte of the third signal providing the end of the message.This enables the receiving sub-block to determine the period containing the end of the transmission when the messages are transmitted continuously.
[0016] In a sixth embodiment, the first signal includes information indicating that the event message is transmitted from the first sub-block.
[0017] These and other aspects of the present disclosure will become apparent from the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:
[0019] Figure 1 A schematic diagram of an integrated circuit according to an example is shown.
[0020] Figure 2 A flow chart of a method for transmitting data according to an example is shown.
[0021] Figure 3 A signal diagram according to an example is shown. DETAILED DESCRIPTION
[0022] The exemplary embodiments are described in sufficient detail below to enable those skilled in the art to implement and practice the systems and processes described herein.It is important to understand that the embodiments can be provided in many alternative forms and should not be construed as limited to the examples set forth herein.
[0023] Accordingly, although the embodiments may be modified in various ways and take various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. It is not intended to be limited to the specific forms disclosed. On the contrary, all modifications, equivalents and substitutions falling within the scope of the appended claims should be included. In all drawings and appropriate detailed descriptions, the elements of the exemplary embodiments are consistently marked with the same reference numerals.
[0024] The terms used to describe the embodiments in this application are not intended to limit the scope. The articles "a", "an" and "the" are singular because they have a single referent, but the singular form used in this application should not exclude the presence of more than one referent. In other words, the elements mentioned in the singular can represent one or more, unless the context clearly indicates otherwise. The terms "include", "comprise", "have" and / or "contain" when used in this application express the presence of stated features, items, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, items, steps, operations, elements, parts and / or groups thereof.
[0025] Unless otherwise defined, all terms used in this application, including technical and scientific terms, should be interpreted according to the conventions in the art. Unless explicitly defined herein, commonly used terms should also be interpreted as the conventions in the relevant art, rather than idealized or overly formal meanings.
[0026] Figure 1 is a simplified schematic diagram illustrating an integrated circuit 100 according to one example. Figure 1The illustrated integrated circuit 100 may be used in conjunction with other methods and systems described herein.
[0027] The integrated circuit 100 includes sub-blocks 110, 120 in a system-on-chip (SoC) arrangement. The sub-blocks 110, 120 are fully integrated into the circuit 100 on a single substrate or microchip. Each of the sub-blocks 110, 120 may be a central processing unit (CPU), a memory device, an input / output device, a secondary storage device, a graphics processing unit (GPU), custom logic, or any other type of component suitable for a SoC architecture. Figure 1 In the example shown, the integrated circuit 100 includes two sub-blocks 110, 120. In other examples, more than two sub-blocks may be provided on the integrated circuit 100.
[0028] According to an example, sub-blocks 110, 120 include communication interfaces 130, 140. Interfaces 130, 140 are connected via interconnection circuit 150. Sub-blocks 110, 120 can transmit data via interfaces 130, 140 and interconnection circuit 150. Data can be transmitted as messages. The message includes a data payload and a message header. The message header may include addressing information, which can be used to route the message to a destination address specified in the addressing information. The message may also include additional metadata. For example, the message may include a timestamp and identification information generated at the same source as the message.
[0029] According to an example, the interconnect circuit 150, which may include a data bus, is limited to communicating at a maximum amount of data per clock cycle of the integrated circuit 100. In some cases, a message may span one or more cycles. If the transmitting sub-block is limited to sending a single message per clock cycle, a valid / ready handshake protocol may be used to convey information that enables the receiving sub-block to determine whether the message continues to a subsequent cycle or whether the cycle contains the end of the message. In other examples, the message may be shorter than the available data bus bandwidth. If a single message is transmitted using a valid / ready protocol per clock cycle, some bits may not be used in the clock cycle, resulting in a lower effective bandwidth.
[0030] The method described in the present application is used to continuously transmit messages in a bit stream. The transmitting sub-block communicates information that enables the receiving sub-block to determine the position of the end of the last message in the transmission of messages from the transmitting sub-block. The information provided by the transmitting sub-block allows efficient use of processing power and available bandwidth throughout the integrated circuit. For example, the receiving sub-block can use the information to effectively pack messages into a buffer for on-chip storage or on-chip communication, or for off-chip data communication, and waste fewer available bits.
[0031] Figure 21 is a block diagram of a method 200 for transmitting data in an integrated circuit according to an example, the integrated circuit comprising at least two interconnected sub-blocks in a SoC arrangement. The method 200 can be used to transmit data between sub-blocks 110, 120 on the integrated circuit 100 in the form of one or more consecutive messages.
[0032] At block 210, method 200 includes transmitting a first signal from a first sub-block of an integrated circuit to a second sub-block. The first signal indicates that the first sub-block is ready to transmit data to the second sub-block.
[0033] At block 220, the method 200 includes receiving, at the first sub-block, a second signal from the second sub-block. The second signal indicates that the second sub-block is ready to receive data from the first sub-block.
[0034] At block 230, method 200 includes transmitting data including one or more consecutive messages from the first sub-block to the second sub-block via a third signal during one or more clock cycles of the integrated circuit. At the end of the transmission of the one or more consecutive messages, the first signal includes information that enables the second sub-block to determine the location of the end of the last message of the one or more consecutive messages.
[0035] According to an example of method 200, the position of the end of the last message may include the byte position in the third signal during the clock cycle that includes the end of the transmission. For example, in the case where all bytes in the clock cycle are "valid" message data, the byte position of the end of the last message includes the last byte in the third signal. In this case, the first signal provides information indicating that the end of the message is the last byte of the third signal.
[0036] In the case where not all available bytes are used for message data, the last byte in the third signal during the clock cycle containing the end of the transmission can be used to indicate the position of the end of the message data in the clock cycle. In this case, the first signal includes information indicating that the position of the end of the message is provided in the last byte of the third signal. In some examples, the first signal can indicate that the position of the end of the last message is provided in the N most significant bits. For example, the first signal can include information indicating that the position of the end of the last message is indicated in the last four bits of the third signal instead of the last byte.
[0037] Table 1 below shows a coding scheme that may be used to convey information in the first signal in method 200 .
[0038]
[0039] Table 1
[0040] This information allows one or more consecutive messages to be transmitted to the receiving sub-block, while also signaling to the sub-block where the end of the one or more messages is located relative to the clock cycle.
[0041] The coding scheme in Table 1 is based on the use of a three-bit logical signal. The receiving sub-block can decode the received signal and interpret the signal accordingly. This three-bit signal can be provided by three physical cables that convey single-bit information to the receiving sub-block. A coding scheme different from that shown in Table 1 can be used to convey information. In some cases, additional bits can be used to encode additional information.
[0042] The first column in Table 1 shows different encodings, and the second column shows the meaning of the codes transmitted by the first sub-block and interpreted by the second sub-block when the third signal is received. In Table 1, code 000 is used to convey that no message data is being transmitted. Code 001 is reserved for event messages. Event messages can be cross-trigger messages that are communicated in response to events on an integrated circuit. If the code is 100, the receiving sub-block knows that one or more messages will continue until the next clock cycle. If the code is 101, the receiving sub-block knows that the cycle contains the end of the message and only one message is sent. If the code is 110, the sub-block receiving the first signal knows that the position of the last valid byte of the message is provided in the most significant byte, that is, in the last byte of the third signal in the clock cycle. If the code is 111, this signals to the receiving sub-block that all bytes on the data bus are valid. Codes 010 and 011 are not used. In some examples, for example, these codes can be used to specify different types of events.
[0043] Figure 3 A signal diagram 300 is shown. The signal diagram 300 includes a clock signal 310 and signals 320, 330, 340. These signals correspond to the first signal, the second signal and the third signal of the method 200. The clock signal 310 includes three clock cycles 350, 360, 370. For example, this may correspond to the clock signal of the integrated circuit 100. Figure 3 In the method 200, signal 320 corresponding to the first signal is represented as three separate signals, each having a 0 / 1 state of three bits representing the logic signal of Table 1. Signal 330 has a 0 / 1 state, which corresponds to the signal sent from the second sub-block to the first sub-block in the method 200, indicating when the second sub-block is ready to receive data from the first sub-block. Signal 340 corresponds to a third signal that transmits data from the first sub-block to the second sub-block.
[0044] exist Figure 3In the first clock cycle 350, initially all signals are in the 0 state. In the first clock cycle 350, signal 330 transmits "1", indicating that the second sub-block is ready to receive data from the first sub-block. Signal 340 transmits data beats D1, D2 and D3. In the first clock cycle 350, signal 320 transmits code 100, which indicates that all data transmitted in the first data beat D1 are part of the same message and that the message will continue until the next clock cycle. In the second clock cycle 330, signal 320 transmits code 111, which indicates that the data transmitted in the second data beat D2 contains the end of the message and that all data bytes are valid message bytes. In the third clock cycle 370, signal 110 is transmitted, indicating that the data transmitted in the third data beat D3 contains the end of the message, and the byte position of the last valid byte of the last message is indicated in the most significant byte of the data beat D3.
[0045] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices and systems according to the examples of the present disclosure. Although the flowcharts described above show a specific execution order, the execution order may be different from that described. The blocks described for the flowchart may be combined with blocks of another flowchart. In some examples, some blocks of the flowchart may not be necessary and / or additional blocks may be added.
[0046] The present disclosure may be implemented in other specific devices and / or methods. The described embodiments are considered to be illustrative rather than restrictive in all aspects. In particular, the scope of the present disclosure is indicated by the appended claims rather than by the description and drawings of the present application. All modifications within the equivalent meaning and scope of the claims are included within the scope of the claims.
Claims
1. A method for transmitting data in an integrated circuit, the integrated circuit comprising at least two interconnected sub-blocks in a system-on-chip (SoC) arrangement, the method comprising: transmitting a first signal from a first sub-block to a second sub-block, the first signal indicating that the first sub-block is ready to transmit data to the second sub-block; receiving, at the first sub-block, a second signal from the second sub-block, the second signal indicating that the second sub-block is ready to receive data from the first sub-block; as well as transferring data from the first sub-block to the second sub-block via a third signal during one or more clock cycles of the integrated circuit, the data comprising one or more consecutive messages, Therein, the first signal includes, at the end of the transmission of the one or more consecutive messages, information that enables the second sub-block to determine the position of the end of the last message in the one or more consecutive messages.
2. The method according to claim 1, wherein: The location of the end of the last message comprises a byte position in the third signal during a clock cycle that includes the end of the transmission.
3. The method according to claim 2, wherein: The end of the last message includes the last byte in the third signal during the clock cycle that includes the end of the transmission.
4. The method according to claim 3, wherein: The information enabling the second sub-block to determine the position of the end of the last message includes information indicating that the end of the last message is the last byte of the third signal.
5. The method according to claim 1, wherein: The location of the end of the last message is provided in the last byte in the third signal during the clock cycle that includes the end of the transmission.
6. The method according to claim 5, wherein: The information enabling the second sub-block to determine the location of the end of the last message comprises information indicating the location where the end of the last message is provided in the last byte of the third signal during the clock cycle containing the end of the transmission.
7. The method according to claim 1, wherein: The first signal includes information indicating that an event message is transmitted from the first sub-block.
8. An integrated circuit comprising at least two sub-blocks in a system-on-chip (SoC) arrangement, wherein: The first sub-block of the at least two sub-blocks is configured as: transmitting a first signal indicating that the first sub-block is ready to transmit data to a second sub-block; receiving a second signal from the second sub-block, the second signal indicating that the second sub-block is ready to receive data from the first sub-block; as well as transmitting data via a third signal during one or more clock cycles of the integrated circuit, the data comprising one or more consecutive messages; Therein, the first signal includes, at the end of the transmission of the one or more consecutive messages, information that enables the second sub-block to determine the position of the end of the last message in the one or more consecutive messages.
9. The integrated circuit of claim 8, wherein: The location of the end of the last message comprises a byte position in the third signal during a clock cycle that includes the end of the transmission.
10. The integrated circuit of claim 9, wherein: The end of the last message includes the last byte in the third signal during the clock cycle that includes the end of the transmission.
11. The integrated circuit of claim 10, wherein: The information enabling the second sub-block to determine the position of the end of the last message includes information indicating that the end of the last message is the last byte of the third signal.
12. The integrated circuit of claim 8, wherein: The location of the end of the last message is provided in the last byte in the third signal during the clock cycle that includes the end of the transmission.
13. The integrated circuit of claim 12, wherein: The information enabling the second sub-block to determine the location of the end of the last message comprises information indicating the location where the end of the last message is provided in the last byte of the third signal during the clock cycle containing the end of the transmission.
14. The integrated circuit of claim 8, wherein: The first signal includes information indicating that an event message is transmitted from the first sub-block.