Solid-state imaging device

Abstract

A solid-state imaging device includes: a semiconductor layer including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type located in an imaging region in which a plurality of first photoelectric conversion elements that convert light into charges are arranged, the second conductive type is opposite to the first conductive type; an insulator provided on a first surface of the semiconductor layer on a light incident side; a first guard ring disposed in the insulator along an outer periphery of the imaging region, including a metal material, and electrically connected to the first semiconductor region of the semiconductor layer; and a separation insulator provided in the semiconductor layer along an outer periphery of the imaging region and along an inner periphery of the first guard ring, and electrically separating the first guard ring from the second semiconductor region.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device. Background Art

[0002] Patent document 1 discloses a back-illuminated solid-state imaging device. In the solid-state imaging device, a photoelectric conversion unit that converts incident light into electric charge is arranged in an imaging area of ​​a semiconductor layer. On the incident light side, a lens material or the like is formed via a passivation film. In addition, in the solid-state imaging device, a protective ring is provided along the outer periphery of the imaging area and along the inner periphery of a cutting line. The protective ring is formed in the passivation film using a metal material formed in the imaging area. Then, the protective ring is electrically connected to the semiconductor layer, and the protective ring has a fixed potential. According to a solid-state imaging device having such a structure, it is possible to effectively suppress or prevent moisture from intruding from the cutting line side to the imaging area side, thereby increasing moisture resistance. Citation list Patent Literature

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-61476 Summary of the invention

[0004] In the solid-state imaging device disclosed in the above-mentioned patent document 1, an n-type semiconductor substrate is used as a semiconductor layer. A p-type semiconductor region (p-type well region) constituting a photoelectric conversion unit is formed in the imaging region of the n-type semiconductor substrate. In addition, a p-type carrier region (hole layer) as a pinning layer is formed on the surface of the semiconductor layer located on the light incident side from the imaging region to the outer periphery of the imaging region. At the same time, the guard ring is electrically connected to the n-type semiconductor substrate, and there is no p-type carrier region in the middle. When the solid-state imaging device is on standby, power with a voltage below 0V is provided to the p-type semiconductor region, and power with a voltage exceeding 0V is provided to the n-type semiconductor substrate. Therefore, it is hoped that short circuits between different power sources can be effectively suppressed or prevented when the n-type semiconductor region, the guard ring, and the p-type semiconductor region (p-type carrier region) act as short-circuit paths.

[0005] According to the first embodiment of the present disclosure, a solid-state imaging device includes: a semiconductor layer, which includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type located in an imaging region, in which a plurality of first photoelectric conversion elements for converting light into electric charges are arranged, and the second conductivity type is a type opposite to the first conductivity type; an insulator, which is arranged on a first surface of the semiconductor layer located on the light incident side; a first guard ring, which is arranged in the insulator along the outer periphery of the imaging region, includes a metal material, and is electrically connected to the first semiconductor region of the semiconductor layer; and a separation insulator, which is arranged in the semiconductor layer along the outer periphery of the imaging region and along the inner periphery of the first guard ring, and electrically separates the first guard ring from the second semiconductor region.

[0006] In a solid-state imaging device according to a second embodiment of the present disclosure, in the solid-state imaging device according to the first embodiment, a carrier region of the second conductivity type is formed in a portion of the first surface of the semiconductor layer and is located between the second semiconductor region and the first guard ring, a junction depth of the carrier region is shallower than a junction depth of the second semiconductor region, and the separation insulator is formed to have a depth that at least divides the carrier region.

[0007] In a solid-state imaging device according to a third embodiment of the present disclosure, in the solid-state imaging device according to the first embodiment, the separation insulator is provided to penetrate from the first surface of the semiconductor layer to a second surface opposite to the first surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a longitudinal sectional view (along the direction of the axis) showing a main part of the solid-state imaging device according to the first embodiment of the present disclosure Figure 2 AA section line as shown). Figure 2 It is shown Figure 1 A plan view showing the overall configuration of a solid-state imaging device shown. Figure 3 It is shown by Figure 1 An enlarged longitudinal cross-sectional view of a region B surrounded by a dotted line is shown. Figure 4 It is shown Figure 1 Shown is a longitudinal cross-sectional view of a main portion of a solid-state imaging device during a wafer manufacturing process (before a scribing process). Figure 5 is a diagram showing a main part of a solid-state imaging device according to a second embodiment of the present disclosure and corresponding to Figure 1 Longitudinal section of Figure 6 sectional view along the CC section line shown). Figure 6 It is shown Figure 5 The overall structure of the solid-state imaging device shown corresponds to Figure 2 Plan structure diagram. Figure 7 is a diagram showing a main part of a solid-state imaging device according to a third embodiment of the present disclosure and corresponding to Figure 1 Longitudinal section of Figure 8 DD section line shown). Figure 8 It is shown Figure 7 The overall structure of the solid-state imaging device shown corresponds to Figure 2 Plan structure diagram. Fig. 9 is a diagram showing a main part of a solid-state imaging device according to a fourth embodiment of the present disclosure and corresponding to Figure 1 Longitudinal section of Fig.10 EE section line shown). Fig.10 It is shown Fig. 9 The overall structure of the solid-state imaging device shown corresponds to Figure 2 Plan structure diagram. Fig.11 is a diagram showing a main part of a solid-state imaging device according to a fifth embodiment of the present disclosure and corresponding to Figure 1 Longitudinal section of Fig.12 FF section line shown). Fig.12 It is shown Fig.11 The overall structure of the solid-state imaging device shown corresponds to Figure 2 Plan structure diagram. Fig.13 is a diagram showing a main part of a solid-state imaging device according to a sixth embodiment of the present disclosure and corresponding to Figure 1 Longitudinal section of Fig.14 sectional view along the GG section line shown). Fig.14 It is shown Fig.13 The overall structure of the solid-state imaging device shown corresponds to Figure 2 Plan structure diagram. Fig.15 is a diagram showing a main part of a solid-state imaging device according to a seventh embodiment of the present disclosure and corresponding to Figure 1 Longitudinal section of Fig.16 sectional view along the HH section line shown). Fig.16 It is shown Fig.15 The overall structure of the solid-state imaging device shown corresponds to Figure 2 Plan structure diagram. Fig.17 is a block diagram illustrating a schematic configuration example of a vehicle control system. Fig.18 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0009] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the description will be made in the following order. 1. First Embodiment In the first embodiment, a first example in which the present technology is applied to a solid-state imaging device will be described. In the first embodiment, the solid-state imaging device is a back-illuminated solid-state imaging device. In addition, in the first embodiment, a longitudinal cross-sectional configuration including a guard ring, a planar configuration, and a longitudinal cross-sectional configuration during a manufacturing process in the solid-state imaging device will be described. 2. Second Embodiment In the second embodiment, a second example in which the structure of the guard ring is changed in the solid-state imaging device according to the first embodiment will be described. 3. Third embodiment In the third embodiment, a third example in which the structure of the guard ring is changed in the solid-state imaging device according to the first embodiment will be described. 4. Fourth embodiment In the fourth embodiment, a fourth example in which the first semiconductor element is mounted on the light incident surface side in the solid-state imaging device according to the second embodiment will be described. 5. Fifth embodiment In the fifth embodiment, a fifth example in which the second semiconductor element is mounted on the opposite side to the light incident surface side in the solid-state imaging device according to the second embodiment will be described. 6. Sixth embodiment In the sixth embodiment, a sixth example in which a third semiconductor element is further mounted on the second semiconductor element in the solid-state imaging device according to the fifth embodiment will be described. 7. Seventh embodiment In the seventh embodiment, a seventh example in which the semiconductor device according to the fifth embodiment further includes two types of photoelectric conversion elements in the imaging region will be described. 8. Application examples for mobile objects In this application example, an example in which the present technology is applied to a vehicle control system as one example of a mobile body control system will be described. 9. Other embodiments

[0010] <1. First Embodiment> Reference Figures 1 to 4To illustrate the solid-state imaging device 1 according to the first embodiment of the present disclosure. For convenience, the X-arrow direction shown in the accompanying drawings appropriately represents a planar direction of the solid-state imaging device 1 placed on a plane. The Y-arrow direction represents another planar direction orthogonal to the X-arrow direction. In addition, the Z-arrow direction represents an upward direction orthogonal to the X-arrow direction and the Y-arrow direction. That is, the X-arrow direction, the Y-arrow direction, and the Z-arrow direction coincide with the X-axis direction, the Y-axis direction, and the Z-axis direction in the three-dimensional coordinate system, respectively. Note that each of these directions is shown for easier understanding of the description and does not limit the direction of the present technology.

[0011] [Configuration of Solid-State Imaging Device 1] (1) Overall Configuration of Solid-State Imaging Device 1 Figure 1 An example of a longitudinal sectional configuration of a peripheral area of ​​the solid-state imaging device 1 according to the first embodiment is shown. Figure 2 Shows Figure 1 An example of the overall planar configuration of the solid-state imaging device 1 is shown. Figure 3 Shows Figure 1 An example of a longitudinal cross-sectional structure of the main parts shown. Figure 4 An example of a longitudinal cross-sectional configuration of a peripheral area during a manufacturing process of the solid-state imaging device 1 (before a step of dicing a semiconductor wafer) is shown.

[0012] like Figures 1 to 3 As shown, the solid-state imaging device 1 according to the first embodiment is configured as a back-illuminated solid-state imaging device. More specifically, the solid-state imaging device 1 is configured as a complementary metal oxide semiconductor (CMOS) image sensor. The solid-state imaging device 1 includes a semiconductor layer 2, an insulator 4, a first guard ring 5, and a separation insulator 26 as main components. Details are as follows.

[0013] (2) Structure of semiconductor layer 2 like Figures 1 to 3 As shown, the solid-state imaging device 1 includes a semiconductor layer 2. The semiconductor layer 2 is formed, for example, including a single crystal silicon (Si) substrate. More specifically, the semiconductor layer 2 uses, for example, an n-type semiconductor substrate of a first conductivity type having a low impurity concentration.

[0014] like Figure 2 As shown, when viewed from the Z arrow direction (hereinafter referred to as "in a plan view"), the semiconductor layer 2 is formed into a rectangular shape. Although the shape is not particularly limited, the semiconductor layer 2 is formed to have a rectangular planar shape. The solid-state imaging device 1 as a final product is formed to have a planar shape substantially the same as the planar shape of the semiconductor layer 2.

[0015] The imaging area IA is provided in the middle portion of the solid-state imaging device 1. The imaging area IA occupies most of the solid-state imaging device 1, and is formed to have a planar shape similar to and slightly smaller than that of the semiconductor layer 2 in a planar view.

[0016] like Figure 1 As shown, in the imaging area IA, a plurality of first photoelectric conversion elements PE1 that convert light into electric charges are arranged in the semiconductor layer 2. Although a detailed description of the arrangement structure is omitted, the plurality of first photoelectric conversion elements PE1 are regularly arranged in each of the X-arrow direction and the Y-arrow direction. Although a detailed description of the cross-sectional structure is omitted, the first photoelectric conversion element PE1 is formed to include, for example, a photodiode. Therefore, in the semiconductor layer 2, a p-type semiconductor region (p-type well region) 22 constituting a photodiode is formed in the imaging area IA. The p-type semiconductor region 22 has a second conductivity type opposite to the first conductivity type. The p-type semiconductor region 22, the p-type well region, or the carrier region 23 described below corresponds to a "second semiconductor region of a second conductivity type" according to the present technology. When the solid-state imaging device 1 is on standby, a power supply VSS is supplied to the p-type semiconductor region 22. For example, the power supply VSS uses a power supply having a voltage of 0 [V] or less.

[0017] like Figure 1 and 2 As shown, in the solid-state imaging device 1, a guard ring area GA is provided in the outer periphery of the imaging area IA. The guard ring area GA is formed at the outermost edge portion of the semiconductor layer 2 along each side of the planar rectangle. In other words, the guard ring area GA is formed to have a rectangular ring shape in a planar view. In other words, the guard ring area GA is provided along the outer periphery of the imaging area IA, and is provided in the inner periphery of the scribe area SA present during the manufacturing process of the solid-state imaging device 1.

[0018] Figure 4 The semiconductor layer 2 during the manufacturing process of the solid-state imaging device 1 is shown. The semiconductor layer 2 is in the state of the semiconductor wafer SW before the scribing process (before the cutting process). A plurality of solid-state imaging devices 1 are formed in the semiconductor layer 2 with the scribing area SA interposed therebetween. For example, the electrical characteristics of the plurality of solid-state imaging devices 1 are checked in the state of the semiconductor wafer SW. Thereafter, the semiconductor layer 2 is cut in the scribing area SA and singulated into individual solid-state imaging devices 1 as bare chips or semiconductor chips.

[0019] In the guard ring area GA, an n-type semiconductor region (n-type well region) 21 is provided in the semiconductor layer 2. The n-type semiconductor region 21 is formed to have the same conductivity type as that of the semiconductor layer 2, but is formed to have an impurity concentration higher than that of the semiconductor layer 2. The n-type semiconductor region 21 or the n-type semiconductor substrate corresponds to the "first semiconductor region of the first conductivity type" according to the present technology. The power supply VDD is supplied to the n-type semiconductor region 21 when the solid-state imaging device 1 is on standby. For example, the power supply VDD uses a power supply having a voltage exceeding 0 [V]. Note that the constituent elements provided in the guard ring GA, such as the first guard ring 5, will be described later.

[0020] like Figure 2 and 3 As shown, the pinning film (fixed charge film) 3 is provided on the first surface 2A on the light incident side of the semiconductor layer 2 from the imaging area IA to the guard ring area GA. The carrier region (carrier accumulation region) 23 is formed on the portion of the first surface 2A of the semiconductor layer 2 in contact with the pinning film 3.

[0021] In the pinning film 3, for example, a metal oxide material containing one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2) and tantalum oxide (Ta2O5) is used. The carrier region 23 is electrically connected to the p-type semiconductor region 22 formed in the imaging region IA of the semiconductor layer 2 and extends to the guard ring region GA. The carrier region 23 mentioned herein is a hole accumulation region. The junction depth of the carrier region 23 is shallower than the junction depth of the p-type semiconductor region 22. In addition, the impurity concentration in the carrier region 23 is higher than the impurity concentration in the p-type semiconductor region 22.

[0022] (2) Structure of Insulator 4 like Figure 2 As shown, the insulator 4 is provided on the first surface 2A of the semiconductor layer 2 via the pinning film 3. The insulator 4 is actually formed to include a plurality of insulating layers. The insulator 4 is used as an interlayer insulating film or a passivation film for insulating and separating the wiring 41, the metal layer 42, and the metal layer 43, etc. In other words, the insulator 4 is used as a waveguide that guides the incident light to the first photoelectric conversion element PE1 in the imaging area IA, and also constitutes a wiring layer. The insulator 4 contains, for example, silicon oxide (SiO2) or the like.

[0023] Figure 2The metal layers 42 and 43 shown are provided in the peripheral area of ​​the imaging area IA and on the inner periphery of the guard ring area GA. The metal layer 43 is formed to be in contact with the metal layer 42 and electrically connected to the metal layer 42. The metal layers 42 and 43 are used as connection terminals CP. For example, when the first semiconductor element 31 of the solid-state imaging device 1 according to the fourth embodiment is mounted, the connection terminal CP is used. The first semiconductor element 31 will be described later. For example, the metal layer 42 uses a metal material such as cobalt (Co). In addition, the metal layer 43 uses a metal material such as copper (Cu).

[0024] The wiring 41 is formed in contact with the metal layer 42. The metal layer 42 is electrically connected to the wiring 41. The wiring 41 includes a through wiring that penetrates the semiconductor layer 2 in the thickness direction and is connected to the pixel circuit PC provided on the second surface 2B side of the semiconductor layer 2. For example, the wiring 41 uses a metal material such as Cu.

[0025] (4) Structure of Pixel P like Figure 1 and 2 As shown, a plurality of pixels P are provided in the imaging area IA. Although the detailed structure is not shown, the pixel P includes a first photoelectric conversion element PE1, an optical filter 8, and an optical lens 9 as main components.

[0026] The optical filter 8 is arranged on the first surface 2A side of the semiconductor layer 2 via the insulator 4, the insulating film 6 and the protective film 7. The optical filter 8 includes, for example, filters of three colors in total, and the colors of these filters are different for each pixel P. That is, the optical filter 8 includes a red light filter that allows light in the red light wavelength range to pass, a green light filter that allows light in the green light wavelength range to pass, and a blue light filter that allows light in the blue light wavelength range to pass. The optical filter 8 includes, for example, a resin material containing a dye. The insulating film 6 mentioned herein includes, for example, an insulating material such as silicon nitride (SiN). In addition, the protective film 7 includes, for example, an insulating material such as SiO2.

[0027] The optical lens 9 is disposed on the optical filter 8 and is located on the opposite side of the first photoelectric conversion element PE1. In other words, the optical lens 9 is disposed on the optical filter 8 and is located on the light incident side. Although not shown in the plan view, the optical lens 9 is formed into a circular shape for each pixel P. In addition, when observed along the Y arrow direction for each pixel P (hereinafter referred to as the "side view"), the optical lens 9 is formed to have a curved shape that is curved toward the light incident side, and focuses the incident light in the first photoelectric conversion element PE1. The optical lens 9 is formed as a so-called on-chip lens, and is formed for each pixel P or formed integrally on a plurality of pixels P. The optical lens 9 includes, for example, a transparent resin material.

[0028] In addition, in the imaging area, an inter-pixel separator 53 is provided between the pixels P. The inter-pixel separator 53 is formed on the pinning film 3 and on the opposite side of the semiconductor layer 2, and is formed as a light shielding member for optically separating between the pixels P. For example, the inter-pixel separator 53 uses a metal material having excellent light shielding performance such as tungsten (W).

[0029] (5) Structure of pixel circuit PC like Figure 1 As shown, the pixel circuit PC is electrically connected to one pixel P or multiple pixels P through a transfer transistor not shown. Although the detailed circuit structure of the pixel circuit PC and the longitudinal cross-sectional structure of the pixel circuit PC in a plan view are neither described nor shown, the pixel circuit PC is configured to include multiple transistors. For example, the pixel circuit PC includes transistors for resetting transistors, amplifying transistors, and selecting transistors. The transistors including the transfer transistors and constituting the pixel circuit PC include, for example, n-channel conductive insulated gate field effect transistors (IGFETs). The pixel circuit PC is disposed on the main surface portion of the semiconductor layer 2 located on the second surface 2B side.

[0030] (6) Structure of Wiring Layer 10 The wiring layer 10 is provided on the second surface 2B side of the semiconductor layer 2 to cover the pixel circuit PC. For example, a multilayer wiring 101 and the like are formed in the wiring layer 10. The multilayer wiring 101 connects a plurality of transistors constituting the pixel circuit PC. For example, the wiring 101 uses a metal wiring material such as copper (Cu). Although the illustration is simplified, an insulator 103 is formed between the multilayer wiring 101 and the multilayer wiring 101 and the like. The insulator 103 is actually formed to include a multilayer insulating film. The insulator 103 includes, for example, SiO2.

[0031] In the solid-state imaging device 1, the pixel circuit PC and its connection wiring (for example, wiring 101, etc.) are arranged on the second surface 2B side of the semiconductor layer 2. In contrast, the optical lens 9, the optical filter 8, and the first photoelectric conversion element PE1 are arranged on the light incident side, and a structure that does not block the incident light is used. That is, the solid-state imaging device 1 is configured as a back-illuminated solid-state imaging device.

[0032] (7) Configuration of the Second Guard Ring 25 and the Third Guard Rings 11 to 13 like Figure 1 , 2 As shown in FIGS. 4 and 5 , the solid-state imaging device 1 according to the first embodiment includes a second guard ring 25 and third guard rings 11 to 13 in addition to the first guard ring 5. First, the second guard ring 25 will be described.

[0033] (7-1) Structure of the Second Guard Ring 25 The second guard ring 25 is disposed in the semiconductor layer 2 along the outer periphery of the first guard ring 5. More specifically, the second guard ring 25 is disposed closer to the scribe area SA and along the inner periphery of the scribe area SA. The second guard ring 25 is configured to include a through groove 251 and a buried insulator 252.

[0034] The through groove 251 is formed as a groove that extends in each of the X-arrow direction and the Y-arrow direction along the outer periphery of the first guard ring 5 and surrounds the imaging area IA in an annular shape. The through groove 251 is formed as a through groove that penetrates from the first surface 2A of the semiconductor layer 2 to the second surface 2B of the semiconductor layer 2 along the thickness direction of the semiconductor layer 2. The groove width of the through groove 251 is, for example, greater than 0.1 μm and less than 0.5 μm. The buried insulator 252 is buried in the through groove 251. The buried insulator 252 includes, for example, an inorganic insulating material such as SiO2 or SiN. Note that in the area where the second guard ring 25 is provided, the pinning film 3, the insulator 4, the insulating film 6, and the protective film 7 are removed before the cutting process and do not exist as a final product.

[0035] By including the second guard ring 25 configured in this manner, it is possible to effectively suppress or prevent the breakage of the cut end face during the cutting process. In addition, by including the second guard ring 25, it is possible to effectively suppress or prevent moisture from penetrating through the first surface 2A of the semiconductor layer 2. In addition, by including the second guard ring 25, the semiconductor layer 2 on the scribe area SA side and the semiconductor layer 2 on the imaging area IA side can be electrically separated with the second guard ring 25 as a boundary.

[0036] (7-2) Structure of the Third Guard Rings 11 to 13 The third guard rings 11 to 13 are sequentially disposed in the wiring layer 10 from the scribe area SA to the imaging area IA. The third guard rings 11 to 13 are disposed along the outer periphery of the imaging area IA.

[0037] The third guard ring 11 is provided in the wiring layer 10 so as to be closest to the scribe line area SA. The third guard ring 11 is formed by stacking the multilayer wirings 101 and 102 in the thickness direction of the wiring layer 10 using the multilayer wirings 101 and 102 respectively provided in the imaging area IA. For example, the wiring 102 uses a metal wiring material such as an aluminum (Al)-Cu alloy. The use of the wirings 101 and 102 mentioned herein means that the third guard ring 11 is formed using the same wiring material in the same layer of each of the wirings 101 and 102 in the same manufacturing process.

[0038] The third guard ring 12 is provided in the wiring layer 10 along the inner periphery of the third guard ring 11. Similar to the third guard ring 11, the third guard ring 11 is formed by stacking the multilayer wirings 101 and 102 in the thickness direction of the wiring layer 10 using the multilayer wirings 101 and 102 respectively provided in the imaging area IA.

[0039] The third guard ring 13 is provided in the wiring layer 10 and closest to the imaging area IA along the inner periphery of the third guard ring 12. Similar to the third guard ring 11, the third guard ring 13 is formed by stacking the multilayer wirings 101 and 102 in the thickness direction of the wiring layer 10 using the multilayer wirings 101 and 102 respectively provided in the imaging area IA.

[0040] By including the third guard rings 11 to 13 configured in this manner, it is possible to effectively suppress or prevent moisture from particularly penetrating the inside of the wiring layer 10 and entering the imaging area IA side.

[0041] (7-3) Structure of the First Guard Ring 5 like Figures 1 to 4 As shown, the first guard ring 5 is disposed in the insulator 4 along the outer periphery of the imaging area IA. More specifically, the first guard ring 5 is disposed closer to the imaging area IA than the second guard ring 25, the third guard ring 11, and the third guard ring 12, and is disposed in an area equivalent to the third guard ring 13. The first guard ring 5 is configured to include a first metal layer 51 and a second metal layer 52.

[0042] The first metal layer 51 is formed on the pinning film 3 and on the opposite side of the semiconductor layer 2 using the inter-pixel separator 53. Since the inter-pixel separator 53 is used for the first metal layer 51, the first metal layer 51 includes a metal material such as W. A portion of the first metal layer 51 is electrically connected to the n-type semiconductor substrate serving as the semiconductor layer 2 through a contact hole formed in the pinning film 3 (see in particular Figure 3 ). The reference numerals of the contact holes are omitted. Since the pinning film 3 is removed in the connection region between the first metal layer 51 and the semiconductor layer 2, the carrier region 23 is not formed in this region.

[0043] The second metal layer 52 is disposed in the insulator 4, connected to the first metal layer 51, and extends along the thickness direction of the insulator 4. The second metal layer 52 here includes a metal material similar to that of the first metal layer 51.

[0044] By including the first guard ring 5 configured in this manner, it is possible to effectively suppress or prevent moisture from penetrating particularly the interior of the insulator 4 and the interface between the insulator 4 and the semiconductor layer 2 and intruding into the imaging area IA side.

[0045] (8) Structure of the separation insulator 26 like Figures 1 to 4 As shown, especially Figure 3 As shown, the separation insulator 26 is provided in the semiconductor layer 2 along the outer periphery of the imaging region IA and along the inner periphery of the first guard ring 5. The separation insulator 26 is formed from the first surface 2A to have a depth of at least dividing the carrier region 23. In other words, the separation insulator 26 is formed to have a depth that is the same as or greater than the depth of the pn junction between the carrier region 23 and the n-type semiconductor substrate in the semiconductor layer 2.

[0046] In the solid-state imaging device 1 according to the first embodiment, the separation insulator 26 is configured to include a penetration groove 261 and a buried insulator 262. The penetration groove 261 is formed as a groove that extends in either the X-arrow direction or the Y-arrow direction along the inner periphery of the first guard ring 5 and annularly surrounds the imaging area IA. The penetration groove 261 is formed as a penetration groove that penetrates from the first surface 2A of the semiconductor layer 2 to the second surface 2B of the semiconductor layer 2 along the thickness direction of the semiconductor layer 2. The groove width of the penetration groove 261 is, for example, 0.1 μm or more and 0.5 μm or less.

[0047] The through groove 261 mentioned here is formed to have the same or substantially the same groove width from the first surface 2A of the semiconductor layer 2 to the second surface 2B of the semiconductor layer 2. That is, in a side view, the separation insulator 26 is formed to have a rectangular cross-sectional shape, more specifically, a rectangular parallelepiped plane shape. In the present technology, the through groove 261 can be formed to have a groove width that decreases linearly or gradually from the first surface 2A of the semiconductor layer 2 to the second surface 2B of the semiconductor layer 2. The separation insulator 26 formed in this way is formed to have an inverted trapezoidal cross-sectional shape in a side view. The buried insulator 262 is buried in the through groove 261. The buried insulator 262, for example, contains an inorganic insulating material such as SiO2 or SiN.

[0048] That is, in the solid-state imaging device 1 according to the first embodiment, the separation insulator 26 is formed to have the same cross-sectional configuration as that of the second guard ring 25. In other words, in the manufacturing method of the solid-state imaging device 1, the formation process of the separation insulator 26 is the same as the formation process of the second guard ring 25. Note that the groove width of the penetration groove 261 in the separation insulator 26 and the groove width of the penetration groove 251 of the second guard ring 25 may also be different sizes.

[0049] [Function and Effect] like Figures 1 to 4As shown, the solid-state imaging device 1 according to the first embodiment includes a semiconductor layer 2, an insulator 4, a first guard ring 5, and a separation insulator 26. In the imaging area IA where a plurality of first photoelectric conversion elements PE1 that convert light into electric charges are arranged, the semiconductor layer 2 includes an n-type semiconductor region (first semiconductor region) 21 of a first conductivity type and a p-type semiconductor region (second semiconductor region) 22 of a second conductivity type, the second conductivity type being a type opposite to the first conductivity type. The insulator 4 is provided on the first surface 2A of the semiconductor layer 2 located on the light incident side. The first guard ring 5 is provided in the insulator 4 along the outer periphery of the imaging area IA. The first guard ring 5 includes a metal material and is electrically connected to the n-type semiconductor region 21 of the semiconductor layer 2. Here, the separation insulator 26 is provided in the semiconductor layer 2 along the outer periphery of the imaging area IA and along the inner periphery of the first guard ring 5. The separation insulator 26 electrically separates the first guard ring 5 from the p-type semiconductor region 22. In the solid-state imaging device 1 constructed in this way, when it is in a standby state, a power supply VSS with a voltage of 0 [V] or less is supplied to the p-type semiconductor region 22, and a power supply VDD with a voltage exceeding 0 [V] is supplied to the n-type semiconductor region (n-type semiconductor substrate) 21. The separation insulator 26 is provided between the imaging region IA and the first guard ring 5, and electrically separates the first guard ring 5 from the p-type semiconductor region 22. Therefore, when the n-type semiconductor region 21, the first guard ring 5, and the p-type semiconductor region 22 act as a short-circuit path, a short circuit between different power supplies (VSS-VDD) can be effectively suppressed or prevented.

[0050] Furthermore, in the solid-state imaging device 1, in particular, Figure 3 As shown, a carrier region 23 of the second conductivity type is formed in a portion of the first surface 2A of the semiconductor layer 2 between the p-type semiconductor region 22 and the first guard ring 5. The junction depth of the carrier region 23 is shallower than the junction depth of the p-type semiconductor region 22. Then, a separation insulator 26 is formed to have a depth that at least divides the carrier region 23. Thus, the separation insulator 26 can electrically separate the first guard ring 5 from the p-type semiconductor region 22. Therefore, it is possible to effectively suppress or prevent a short circuit between different power sources when the n-type semiconductor region 21, the first guard ring 5, and the p-type semiconductor region 22 act as a short-circuit path.

[0051] In addition, in the solid-state imaging device 1, in particular, Figure 3 As shown, the separation insulator 26 is provided to penetrate from the first surface 2A of the semiconductor layer 2 to the second surface 2B opposite to the first surface 2A. Thus, the separation insulator 26 can electrically and physically separate the first guard ring 5 from the p-type semiconductor region 22, thereby effectively suppressing or preventing a short circuit between different power sources when the n-type semiconductor region 21, the first guard ring 5 and the p-type semiconductor region 22 act as a short-circuit path.

[0052] In addition, if Figure 1 , 2 As shown in FIGS. 4 and 5 , the solid-state imaging device 1 includes a second guard ring 25. The second guard ring 25 is provided in the semiconductor layer 2 along the outer periphery of the first guard ring 5. In other words, the second guard ring 25 is provided along the inner periphery of the scribe area SA. In addition, the second guard ring 25 is provided to penetrate from the first surface 2A to the second surface 2B of the semiconductor layer 2. Figures 1 to 4 As shown, the separation insulator 26 is formed to have the same cross-sectional structure as that of the second guard ring 25. Therefore, by forming the separation insulator 26 using the second guard ring 25, the separation insulator 26 can be easily formed.

[0053] In other words, the formation process of the separation insulator 26 is the same as the formation process of the second guard ring 25 of the solid-state imaging device 1. Therefore, compared with the case where the formation process of the separation insulator 26 is different from the formation process of the second guard ring 25, the number of manufacturing processes of the solid-state imaging device 1 can be reduced.

[0054] In addition, if Figure 1 , 3 As shown in FIG. 4, in the solid-state imaging device 1, the first guard ring 5 includes W. Since W is used as a separator between the pixels 53 in the imaging area IA, the first guard ring 5 can be easily formed. In other words, since the first guard ring 5 is formed by utilizing the formation process of the inter-pixel separator 53, the number of processes for manufacturing the solid-state imaging device 1 can be reduced.

[0055] In addition, especially Figure 3 As shown, in the solid-state imaging device 1, the separation insulator 26 includes at least one inorganic insulating material selected from SiO2 and SiN. Since the inorganic insulating material is an insulating material with high reliability in semiconductor technology, the separation insulator 26 can be easily formed.

[0056] In addition, if Figure 1 and 4 As shown, the solid-state imaging device 1 includes a pixel P, in which an optical filter 8 and an optical lens 9 are sequentially arranged on the first surface 2A of the semiconductor layer 2 via an insulator 4 and located in a region corresponding to the first photoelectric conversion element PE1. At the same time, the solid-state imaging device 1 includes a pixel circuit PC on the second surface 2B side of the semiconductor layer 2 opposite to the first surface 2A. The pixel circuit PC processes the charge transferred from the first photoelectric conversion element PE1. That is, the solid-state imaging device 1 has a back-illuminated structure. As a result, it is possible to effectively suppress or prevent a short circuit between different power sources when the n-type semiconductor region 21, the first guard ring 5, and the p-type semiconductor region 22 act as a short-circuit path.

[0057] <2. Second Embodiment> Reference Figure 5 and 6 Note that in the second embodiment and subsequent embodiments, the same or substantially same constituent elements as those of the solid-state imaging device 1 according to the first embodiment are denoted by the same reference numerals, and repeated descriptions are omitted.

[0058] [Configuration of Solid-State Imaging Device 1] Figure 5 An example of a longitudinal sectional configuration of a peripheral area of ​​the solid-state imaging device 1 according to the second embodiment is shown. Figure 6 Shows Figure 5 An example of the overall planar configuration of the solid-state imaging device 1 is shown.

[0059] (1) Structure of the Second Guard Ring 27 like Figure 5 and 6 As shown, in the solid-state imaging device 1 according to the second embodiment, a plurality of second guard rings 25 and 27 are arranged along the outer periphery of the first guard ring 5 in the solid-state imaging device 1 according to the first embodiment.

[0060] More specifically, the second guard ring 25 is adjacent to the scribe area SA and is disposed along the inner periphery of the scribe area SA. Meanwhile, the second guard ring 27 is disposed along the inner periphery of the second guard ring 25. The second guard ring 27 is disposed in the insulator 4 and is configured to include a through groove 271 and a buried insulator 272.

[0061] The through groove 271 is formed as a groove that extends in each of the X-arrow direction and the Y-arrow direction along the outer periphery of the first guard ring 5 and annularly surrounds the imaging area IA. Similar to the through groove 251, the through groove 271 is formed as a through groove that penetrates from the first surface 2A of the semiconductor layer 2 to the second surface 2B of the semiconductor layer 2 along the thickness direction of the semiconductor layer 2. The buried insulator 272 is buried in the through groove 271. Similar to the buried insulator 252, the buried insulator 272 includes, for example, an inorganic insulating material. That is, the second guard ring 27 is formed to have a longitudinal sectional configuration that is the same as or substantially the same as that of the second guard ring 25.

[0062] By including the second guard rings 25 and 27 configured in this manner, the chipping can be further effectively suppressed or prevented. In addition, by including the second guard rings 25 and 27, the intrusion of moisture through the first surface 2A of the semiconductor layer 2 can be further effectively suppressed or prevented. In addition, by including the second guard rings 25 and 27, the semiconductor layer 2 on the side of the scribe area SA can be electrically separated from the semiconductor layer 2 on the side of the imaging area IA with the second guard rings 25 and 27 acting as a boundary. In addition, the second guard ring 27 can also be used as a guard ring surrounding the outer periphery of the connection terminal CP.

[0063] (2) Structure of the separation insulator 26 In addition, in the solid-state imaging device 1 according to the second embodiment, the separation insulator 26 is configured to include a groove 263 and a buried insulator 262. The details are as follows. The groove 263 is formed as a groove that extends in each of the X-arrow direction and the Y-arrow direction along the inner periphery of the first guard ring 5 and surrounds the imaging area IA in an annular shape. The groove 263 is dug deep from the first surface 2A of the semiconductor layer 2 toward the second surface 2B of the semiconductor layer 2 along the thickness direction of the semiconductor layer 2, but does not penetrate to the second surface 2B. The groove 263 is formed from the first surface 2A to have a depth that at least divides the carrier region 23. That is, the separation insulator 26 is formed to have a depth that is the same as or greater than the depth of the pn junction between the carrier region 23 in the semiconductor layer 2 and the n-type semiconductor substrate. The buried insulator 262 is buried in the groove 263. Similar to the buried insulator 262 of the solid-state imaging device 1 according to the first embodiment, the buried insulator 262 contains an inorganic insulating material.

[0064] Here, the groove 263 is formed to have the same or substantially the same groove width from the first surface 2A of the semiconductor layer 2 toward the second surface 2B side of the semiconductor layer 2. That is, the separation insulator 26 is formed to have a rectangular cross-sectional shape in a side view, more specifically, a rectangular parallelepiped plane shape. In the present technology, the groove 263 can be formed to have a groove width that decreases linearly or stepwise from the first surface 2A of the semiconductor layer 2 toward the second surface 2B side of the semiconductor layer 2. The separation insulator 26 formed in this way is formed to have an inverted trapezoidal cross-sectional shape in a side view.

[0065] Constituent elements other than the above-described constituent elements are the same as or substantially the same as those of the above-described solid-state imaging device 1 according to the first embodiment.

[0066] [Function and Effect] In the solid-state imaging device 1 according to the second embodiment, operations and effects similar to those of the solid-state imaging device 1 according to the first embodiment can be obtained.

[0067] <3. Third embodiment> Reference Figure 7 and 8 A solid-state imaging device 1 according to a third embodiment of the present disclosure will be described.

[0068] [Configuration of Solid-State Imaging Device 1] Figure 7 An example of a longitudinal sectional configuration of a peripheral area of ​​the solid-state imaging device 1 according to the third embodiment is shown. Figure 8 Shows Figure 7 An example of the overall planar configuration of the solid-state imaging device 1 is shown. like Figure 7 and 8 As shown, the solid-state imaging device 1 according to the third embodiment includes a component element that combines the solid-state imaging device 1 according to the first embodiment and the solid-state imaging device 1 according to the second embodiment. The details are as follows. In the solid-state imaging device 1, similar to the solid-state imaging device 1 according to the second embodiment, a plurality of second guard rings 25 and 27 are provided in the semiconductor layer 2 along the outer periphery of the first guard ring 5.

[0070] Meanwhile, the separation insulator 26 is provided in the semiconductor layer 2 along the inner periphery of the first guard ring 5. Similar to the separation insulator 26 of the solid-state imaging device 1 according to the first embodiment, the separation insulator 26 is configured to include a through groove 261 and a buried insulator 262. In other words, the separation insulator 26 is formed to have a longitudinal sectional configuration that is the same as or substantially the same as that of the second guard ring 25.

[0071] Constituent elements other than the above-described constituent elements are the same as or substantially the same as those of the solid-state imaging device 1 according to the first embodiment or the second embodiment.

[0072] [Function and Effect] In the solid-state imaging device 1 according to the third embodiment, it is possible to obtain the actions and effects of the solid-state imaging device 1 according to the first embodiment and the solid-state imaging device 1 according to the second embodiment combined.

[0073] <4. Fourth embodiment> Reference Fig. 9 and 10 A solid-state imaging device 1 according to a fourth embodiment of the present disclosure will be described.

[0074] [Configuration of Solid-State Imaging Device 1] Fig. 9 An example of a longitudinal sectional configuration of a peripheral area of ​​the solid-state imaging device 1 according to the fourth embodiment is shown. Fig.10 Shows Fig. 9 An example of the overall planar configuration of the solid-state imaging device 1 is shown.

[0075] like Fig. 9 and 10 As shown, in the solid-state imaging device 1 according to the fourth embodiment, the first semiconductor element 31 is mounted on the first surface 2A of the semiconductor layer 2 via the insulator 4 in the outer periphery of the imaging area IA. Details are as follows.

[0076] like Fig.10 As shown, the first semiconductor element 31 is formed to have a rectangular planar shape in a plan view. The planar area (planar size) of the first semiconductor element 31 is smaller than the planar area (planar size) of the semiconductor layer 2 serving as a mounting base. In the fourth embodiment, a total of two first semiconductor elements 31 are installed along two opposite sides of the rectangular semiconductor layer 2 in the Y arrow direction. Due to this layout, the first semiconductor element 31 is formed in a rectangular shape with the X arrow direction as the long side direction in a plan view. In addition, the number of first semiconductor elements 31 is not limited to two, and one or more than three first semiconductor elements 31 may be installed.

[0077] like Fig. 9 As shown, the first semiconductor element 31 (terminals whose illustrations and reference numerals are omitted) is electrically and mechanically connected to the connection terminal CP provided on the first surface 2A side of the semiconductor layer 2. The bump electrode 301 is used for connection. The bump electrode 301 uses a micro bump electrode here. For example, the bump electrode 301 uses a Sn type solder such as a tin (Sn)-silver (Ag) alloy. As a method for mounting the first semiconductor element 31, a face-up method or a face-down method can be used.

[0078] A circuit electrically connected to the pixel circuit PC is mounted on the first semiconductor element 31. The circuit is not shown. The circuit includes, for example, a peripheral circuit constituting the back-illuminated solid-state imaging device 1 and one or more logic circuits selected from a vertical drive circuit, a column signal processing circuit, a horizontal drive circuit, an output circuit, and a control circuit. Similar to the pixel circuit PC, the circuit is constructed to include transistors, resistors, capacitors, and the like.

[0079] Since two first semiconductor elements 31 are mounted, the logic circuit constituting the peripheral circuit is mounted in a divided manner in the respective circuits of the two first semiconductor elements 31. In addition, a part of the logic circuit in the peripheral circuit may be mounted in the circuit of one of the two first semiconductor elements 31, and another part of the logic circuit in the peripheral circuit may be mounted in the circuit of the other of the first semiconductor elements 31.

[0080] Although a detailed description of the circuit configuration of the logic circuit is omitted, the above-mentioned control circuit receives an input clock and data for indicating an operation mode, etc., and outputs data such as internal information of the solid-state imaging device. That is, the control circuit generates a clock signal and a control signal based on a vertical synchronization signal, a horizontal synchronization signal, and a main clock to serve as an operation standard for a vertical drive circuit, a column signal processing circuit, a horizontal drive circuit, etc. Then, these signals are input to the vertical drive circuit, the column signal processing circuit, and the horizontal drive circuit.

[0081] The vertical drive circuit is configured to include, for example, a shift register. The vertical drive circuit selects a pixel drive wiring and supplies a pulse for driving the pixel P to the selected pixel drive wiring. The pixel P is driven for each row. That is, the vertical drive circuit selectively scans the pixels P in the imaging area IA in a sequential manner in the vertical direction for each row. Through the vertical signal line, a signal charge generated according to the amount of received light in the first photoelectric conversion element PE1 in each pixel P is supplied as a pixel signal to the column signal processing circuit.

[0082] For example, a column signal processing circuit is provided for each column of pixels P. The column signal processing circuit performs signal processing, such as noise elimination, on the signal output from the pixels P in a row for each pixel. That is, the column signal processing circuit performs signal processing such as correlated double sampling (CDS) (for eliminating fixed pattern noise inherent in the pixel P), signal amplification, or analog-to-digital (AD) conversion. The horizontal selection switch is connected to the output stage of the column signal processing circuit between the horizontal signal lines. The horizontal selection switch is not shown.

[0083] The horizontal drive circuit is configured to include, for example, a shift register. The horizontal drive circuit sequentially outputs horizontal scanning pulses to sequentially select each column signal processing circuit, and outputs a pixel signal from each column signal processing circuit to a horizontal signal line.

[0084] The output circuit processes the signal sequentially provided from each column signal processing circuit through the horizontal signal line and outputs the signal. For example, in the case of only buffering, the output circuit may perform black level adjustment, column difference correction or various digital signal processing, etc. In addition, each logic circuit includes input / output terminals not shown. These input / output terminals transmit signals between the solid-state imaging device 1 and the outside of the solid-state imaging device 1.

[0085] Note that a memory circuit may be mounted on at least a part of the circuit of the first semiconductor element 31. The memory circuit functions as a shift register, for example.

[0086] Constituent elements other than the above-described constituent elements are the same as or substantially the same as those of the above-described solid-state imaging device 1 according to the second embodiment.

[0087] [Function and Effect] In the solid-state imaging device 1 according to the fourth embodiment, operations and effects similar to those of the solid-state imaging device 1 according to the second embodiment can be obtained.

[0088] In addition, if Fig. 9 and 10 As shown, in the solid-state imaging device 1, the first semiconductor element 31 is mounted in the outer periphery of the imaging area IA and is located on the first surface 2A side of the semiconductor layer 2. The circuit electrically connected to the pixel circuit PC is mounted on the first semiconductor element 31. Therefore, the packaging density of the first semiconductor element 31 in the thickness direction can be increased, so that the packaging density of the peripheral circuit including the circuit can be increased while expanding the imaging area IA.

[0089] In addition, in the solid-state imaging device 1, as Fig. 9 and 10 As shown, when viewed from the thickness direction of the semiconductor layer 2, the plane area of ​​the first semiconductor element 31 is smaller than the plane area of ​​the semiconductor layer 2. Therefore, the imaging area IA of the solid-state imaging device 1 can be further expanded.

[0090] In addition, if Fig. 9 As shown, in the solid-state imaging device 1, the first semiconductor element 31 is mounted on the semiconductor layer 2 via the bump electrode 301. In the solid-state imaging device 1 having such a configuration, the first semiconductor element 31 is mounted using the bump electrode 301, thereby making the mounting area smaller than the area in the case of mounting using, for example, a wire bonding method. Therefore, the packaging density of the peripheral circuit including the circuit can be increased while expanding the imaging area IA.

[0091] <5. Fifth embodiment> Reference Fig.11 and 12 A solid-state imaging device 1 according to a fifth embodiment of the present disclosure will be described.

[0092] [Configuration of Solid-State Imaging Device 1] Fig.11 An example of a longitudinal sectional configuration of a peripheral area of ​​the solid-state imaging device 1 according to the fifth embodiment is shown. Fig.12 Shows Fig.11 An example of the overall planar configuration of the solid-state imaging device 1 is shown.

[0093] like Fig.11 and 12As shown, the solid-state imaging device 1 according to the fifth embodiment is an application example of the solid-state imaging device 1 according to the fourth embodiment. The details are as follows. In the solid-state imaging device 1, the second semiconductor element 32 is installed in the area overlapping with the imaging area IA on the second surface 2B side of the semiconductor layer 2.

[0094] The second semiconductor element 32 is configured to include a semiconductor layer (semiconductor substrate) 321 and a wiring layer 322. In addition, a circuit similar to the circuit mounted on the first semiconductor element 31 of the solid-state imaging device 1 according to the fourth embodiment is mounted on the second semiconductor element 32. This circuit is not shown. That is, the circuit is electrically connected to the pixel circuit PC.

[0095] This circuit, not shown, is formed on the pixel circuit PC side of the semiconductor layer 321. Multilayer wiring 323 is provided in the wiring layer 322. Terminal 324 is provided on the top layer of the wiring layer 322 in the direction of the Z arrow. The terminal 324 includes a wiring material such as Cu. An insulator 325 is formed in the wiring layer 322 to electrically separate the multilayer wiring 323 and the terminal 324, etc. from each other.

[0096] Here, the terminal 104 is provided on the top layer of the wiring layer 10 on the semiconductor layer 2 side, which is located on the second semiconductor element 32 side. The terminal 104 contains, for example, a wiring material such as Cu. The terminal 324 in the second semiconductor element 32 is bonded to the terminal 104, the second semiconductor element 32 is mounted on the terminal 104, and the circuit in the second semiconductor element 32 is electrically connected to the pixel circuit. The bonding between the terminal 104 and the terminal 324 is a so-called Cu-Cu bonding.

[0097] Constituent elements other than the above-described constituent elements are the same as or substantially the same as those of the above-described solid-state imaging device 1 according to the fourth embodiment.

[0098] [Function and Effect] In the solid-state imaging device 1 according to the fifth embodiment, operations and effects similar to those of the solid-state imaging device 1 according to the fourth embodiment can be obtained.

[0099] In addition, in the solid-state imaging device 1, as Fig.11 and 12 As shown, the second semiconductor element 32 is mounted in a region overlapping the imaging area IA on the second surface 2B side of the semiconductor layer 2. A circuit electrically connected to the pixel circuit PC is mounted on the second semiconductor element 32. Therefore, it is possible to increase the packaging density of the peripheral circuit including the circuit while expanding the imaging area IA.

[0100] <6. Sixth embodiment> Reference Fig.13 and 14A solid-state imaging device 1 according to a sixth embodiment of the present disclosure will be described.

[0101] [Structure of Solid-State Imaging Device] Fig.13 An example of a longitudinal sectional configuration of a peripheral area of ​​the solid-state imaging device 1 according to the sixth embodiment is shown. Fig.14 Shows Fig.13 An example of the overall planar configuration of the solid-state imaging device 1 is shown.

[0102] like Fig.13 and 14 As shown, the solid-state imaging device 1 according to the sixth embodiment is an application example of the solid-state imaging device 1 according to the fifth embodiment. The details are as follows. In the solid-state imaging device 1, the third semiconductor element 33 is further mounted on the second semiconductor element 32. The third semiconductor element 33 is mounted on the second semiconductor element 32 and is located on the opposite side of the semiconductor layer 2. In other words, the second semiconductor element 32 and the third semiconductor element 33 are sequentially stacked and mounted on the semiconductor layer 2.

[0103] The third semiconductor element 33 is configured to include a semiconductor layer (semiconductor substrate) 331 and a wiring layer 332. The specific configuration of the wiring layer 322 is the same or substantially the same as that of the wiring layer 322, and thus a description thereof is omitted.

[0104] In addition, a circuit similar to the circuit mounted on the first semiconductor element 31 of the solid-state imaging device 1 according to the fourth embodiment is mounted on the third semiconductor element 33. This circuit is not shown. That is, the circuit is electrically connected to the pixel circuit PC. The logic circuit constituting the peripheral circuit is mounted in the circuit in the second semiconductor element 32 and the circuit in the third semiconductor element 33 in a divided manner. In addition, a part of the logic circuit in the peripheral circuit can be mounted in the circuit in the second semiconductor element 32, and another part of the logic circuit in the peripheral circuit can be mounted in the circuit in the third semiconductor element 33. Note that, although not shown, the circuit in the second semiconductor element 32 and the circuit in the third semiconductor element are electrically connected to each other via a through wiring that penetrates the semiconductor layer 321 of the second semiconductor element 32 in the thickness direction. In addition, in the present technology, the logic circuit can be mounted on the second semiconductor element 32, and the memory circuit can be mounted on the third semiconductor element 33.

[0105] Constituent elements other than the above-described constituent elements are the same as or substantially the same as those of the above-described solid-state imaging device 1 according to the fifth embodiment.

[0106] [Function and Effect] In the solid-state imaging device 1 according to the sixth embodiment, operations and effects similar to those of the solid-state imaging device 1 according to the fifth embodiment can be obtained.

[0107] In addition, if Fig.13 and 14 As shown, in the solid-state imaging device 1, the third semiconductor element 33 is mounted on the second semiconductor element 32. The circuit electrically connected to the pixel circuit PC is mounted on the third semiconductor element 33. Therefore, the packaging density of the peripheral circuit including the circuit can be further improved while expanding the imaging area IA.

[0108] <7. Seventh embodiment> Reference Fig.15 and 16 A solid-state imaging device 1 according to a sixth embodiment of the present disclosure will be described.

[0109] [Configuration of Solid-State Imaging Device 1] Fig.15 An example of a longitudinal cross-sectional configuration of a peripheral area of ​​the solid-state imaging device 1 is shown. Fig.16 Shows Fig.15 An example of the overall planar configuration of the solid-state imaging device 1 is shown.

[0110] like Fig.15 and 16 As shown, the solid-state imaging device 1 according to the seventh embodiment is an application example of the solid-state imaging device 1 according to the fifth embodiment. The details are as follows. In addition to the first photoelectric conversion element PE1, the solid-state imaging device 1 also includes a second photoelectric conversion element PE2 located between the first photoelectric conversion element PE1 in the insulator 4 and the optical filter 8 in the imaging area IA. The second photoelectric conversion element PE2 is formed by a first electrode 45, a photoelectric conversion layer 46, and a second electrode 47 sequentially stacked in the Z arrow direction.

[0111] The first electrode 45 is provided for each pixel P, and includes, for example, a transparent electrode material. The photoelectric conversion layer 46 converts incident light into electric charge. The photoelectric conversion layer 46 includes, for example, an organic photoelectric conversion material. That is, the second photoelectric conversion element PE2 mentioned here is an organic photoelectric conversion element. The second electrode 47 is provided in each of the plurality of pixels P, and is formed to include, for example, a transparent electrode material. In addition, a charge accumulation transport layer may be provided between the first electrode 45 and the photoelectric conversion layer 46. The charge accumulation transport layer includes, for example, an oxide semiconductor material. The oxide semiconductor material uses, for example, IGZO containing indium (In), gallium (Ga), zinc (Zn) and oxygen (O). Alternatively, the oxide semiconductor material may use IGSiO containing In, Ga, Si and O or IAZO containing In, Al, Zn and O, etc.

[0112] Constituent elements other than the above-described constituent elements are the same as or substantially the same as those of the above-described solid-state imaging device 1 according to the fifth embodiment.

[0113] [Function and Effect] In the solid-state imaging device 1 according to the seventh embodiment, operations and effects similar to those of the solid-state imaging device 1 according to the fifth embodiment can be obtained.

[0114] Furthermore, in the solid-state imaging device 1, in particular, Fig.15 As shown, a back-illuminated solid-state imaging device is constructed, which includes two types of first photoelectric conversion element PE1 and second photoelectric conversion element PE2. In this solid-state imaging device 1, short circuits between different power sources can be effectively suppressed or prevented.

[0115] <8. Application examples to mobile objects> The technology of the present disclosure (the present technology) can be applied to various products. For example, the technology of the present disclosure can be implemented in the form of a device installed on any type of mobile body, and the mobile body is any type of automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, robot, etc.

[0116] Fig.17 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0117] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.17 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and an in-vehicle network interface (I / F) 12053 are shown as a functional configuration of the integrated control unit 12050.

[0118] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 acts as a control device for the following devices: a drive force generating device (such as an internal combustion engine or a drive motor, etc.) for generating a vehicle drive force, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a vehicle braking force, etc.

[0119] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal, or a fog light. In this case, a radio wave or a signal of various switches transmitted from a portable device as a key substitute may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, or the lights of the vehicle.

[0120] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 may perform processing for detecting objects such as people, vehicles, obstacles, signs, or characters on the road surface, or processing for detecting their distances.

[0121] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may also output an electrical signal as an image, or may output an electrical signal as measured distance information. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0122] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. The driver state detection unit 12041 includes, for example, a camera for imaging the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0123] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside and outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control of functions intended to implement an advanced driver assistance system (ADAS), including collision avoidance or shock absorption of the vehicle, following driving based on vehicle spacing, speed maintenance driving, vehicle collision warning, or vehicle lane departure warning, etc.

[0124] In addition, based on the environmental information about the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control for automatic driving by controlling the driving force generating device, steering mechanism or braking device, etc., which enables the vehicle to drive automatically without relying on the driver's operation, etc.

[0125] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the external information about the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control intended for preventing glare by, for example, controlling the headlights to change from high beam to low beam according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0126] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig.17 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0127] Fig.18 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0128] exist Fig.18 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0129] The imaging units 12101, 12102, 12103, 12104 and 12105 are, for example, disposed at locations such as the front nose, rearview mirror, rear bumper, rear door and upper portion of the windshield inside the vehicle 12100. The imaging unit 12101 disposed at the front nose and the imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 disposed at the rearview mirror mainly acquire images on both sides of the vehicle 12100. The imaging unit 12104 disposed at the rear bumper or rear door mainly acquires images behind the vehicle 12100. The imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signal lights, traffic signs or lanes, etc.

[0130] Notice, Fig.18 An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirror. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 is obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0131] At least one of the imaging units 12101 to 12104 may have a function for obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0132] For example, the microcomputer 12051 can determine the distance of each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and extract the nearest three-dimensional object as the preceding vehicle, which is particularly present on the driving path of the vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in the substantially same direction as the vehicle 12100. In addition, the microcomputer 12051 is capable of presetting the following distance to be maintained in front of the preceding vehicle, and performing automatic braking control (including following stop control), automatic acceleration control (including following start control), etc. Therefore, it is possible to perform coordinated control for automatic driving so that the vehicle can travel automatically without relying on the operation of the driver, etc.

[0133] For example, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult to be visually identified by the driver of the vehicle 12100. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0134] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. This pedestrian recognition is performed, for example, by the following process: a process of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras; and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so as to display a square contour line for emphasis superimposed on the identified pedestrian. In addition, the sound / image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

[0135] An example of a vehicle control system to which the technology of the present disclosure can be applied is described above. The technology of the present disclosure can be applied to the imaging unit 12031 in the above configuration. By applying the technology of the present disclosure to the imaging unit 12031, short circuits between different power supplies can be effectively suppressed or prevented via the guard ring.

[0136] <9. Other embodiments> The present technology is not limited to the above-described embodiments and can be changed in various ways without departing from the gist of the present technology. For example, two or more of the solid-state imaging devices according to the above-described first to seventh embodiments can be combined.

[0137] In addition, in the present technology, in the solid-state imaging device according to the fourth embodiment, a plurality of first semiconductor elements may be stacked and mounted in the thickness direction of the first semiconductor element. In addition, in the present technology, in the solid-state imaging device according to the sixth embodiment, at least a fourth semiconductor element may be further mounted on the third semiconductor element. In addition, in the present technology, the separation insulator may be a separation insulator in which polycrystalline Si as a buried insulator is buried via an inorganic insulating material.

[0138] According to the first embodiment of the present disclosure, a solid-state imaging device includes a semiconductor layer, an insulator, a first guard ring and a separation insulator. The semiconductor layer includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type located in an imaging region where a plurality of first photoelectric conversion elements for converting light into electric charges are arranged. The second conductivity type is a type opposite to the first conductivity type. The insulator is disposed on a first surface of the semiconductor layer located on the light incident side. The first guard ring is disposed in the insulator along the outer periphery of the imaging region. The first guard ring includes a metal material and is electrically connected to the first semiconductor region of the semiconductor layer. Here, the separation insulator is disposed in the semiconductor layer along the outer periphery of the imaging region and along the inner periphery of the first guard ring. The separation insulator electrically separates the first guard ring from the second semiconductor region. Thus, it is possible to effectively suppress or prevent short circuits between different power sources when the first semiconductor region, the first guard ring and the second semiconductor region act as short circuit paths.

[0139] In addition, in a solid-state imaging device according to a second embodiment of the present disclosure, in the solid-state imaging device of the first embodiment, a carrier layer of a second conductivity type is formed in a portion of the first surface of the semiconductor layer between the second semiconductor region and the first guard ring, and the junction depth of the carrier layer is shallower than the junction depth of the second semiconductor region. Then, a separation insulator is formed to have a depth that at least divides the carriers. Thus, the separation insulator can electrically separate the first guard ring from the carrier layer connected to the second semiconductor region, thereby effectively suppressing or preventing a short circuit between different power sources when the first semiconductor region, the first guard ring, and the second semiconductor region act as a short-circuit path.

[0140] In addition, in the solid-state imaging device according to the third embodiment of the present disclosure, in the solid-state imaging device according to the first embodiment, the separation insulator is provided to penetrate from the first surface of the semiconductor layer to the second surface opposite to the first surface. Thus, the separation insulator can electrically and physically separate the first guard ring from the second semiconductor region, thereby effectively suppressing or preventing a short circuit between different power supplies when the first semiconductor region, the first guard ring, and the second semiconductor region act as a short-circuit path.

[0141] <Structure of this technology> The present technology includes the following configuration. According to the present technology having the following configuration, in the solid-state imaging device, a short circuit between different power supplies can be effectively suppressed or prevented via the guard ring. (1) A solid-state imaging device comprising: a semiconductor layer including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type located in an imaging region in which a plurality of first photoelectric conversion elements for converting light into electric charges are arranged, the second conductivity type being a type opposite to the first conductivity type; An insulator is provided on a first surface of the semiconductor layer on a light incident side; a first guard ring, which is disposed in the insulator along an outer periphery of the imaging region, comprises a metal material, and is electrically connected to the first semiconductor region of the semiconductor layer; and A separation insulator is disposed in the semiconductor layer along an outer periphery of the imaging region and along an inner periphery of the first guard ring and electrically separates the first guard ring from the second semiconductor region. (2) The solid-state imaging device according to (1), wherein A carrier region of the second conductivity type is formed in a portion of the first surface of the semiconductor layer and is located between the second semiconductor region and the first guard ring, and a junction depth of the carrier region is shallower than a junction depth of the second semiconductor region, and The separation insulator is formed to have a depth that at least divides the carrier region. (3) The solid-state imaging device according to (1) or (2), wherein the separation insulator is provided so as to penetrate from the first surface of the semiconductor layer to a second surface opposite to the first surface. (4) The solid-state imaging device according to (3), further comprising a second guard ring provided in the semiconductor layer along an outer periphery of the first guard ring and provided so as to penetrate from the first surface to the second surface of the semiconductor layer, The separation insulator is formed to have the same cross-sectional structure as that of the second guard ring. (5) The solid-state imaging device according to (4), wherein the second guard ring is provided along an inner periphery of the cutting region. (6) The solid-state imaging device according to (4) or (5), wherein a plurality of the second guard rings are provided along an outer periphery of the first guard ring. (7) The solid-state imaging device according to any one of (1) to (6), wherein the first guard ring contains tungsten (W). (8) The solid-state imaging device according to any one of (1) to (7), wherein the separation insulator includes at least one inorganic insulating material selected from SiO 2 and SiN. (9) The solid-state imaging device according to any one of (1) to (8), wherein The first semiconductor region includes an n-type semiconductor region or an n-type semiconductor substrate, and The second semiconductor region includes a p-type semiconductor region or a p-type well region. It also includes: a pixel in which, in a region corresponding to the first photoelectric conversion element, an optical filter and an optical lens are sequentially provided on the first surface of the semiconductor layer via the insulator; and A pixel circuit is provided on a second surface side of the semiconductor layer opposite to the first surface and processes charges transferred from the plurality of first photoelectric conversion elements. (11) The solid-state imaging device according to (10), further comprising a backside illumination structure. (12) A solid-state imaging device according to (10) or (11), wherein, in the outer periphery of the imaging area, a first semiconductor element is mounted on the first surface of the semiconductor layer via the insulator and includes a circuit electrically connected to the pixel circuit. (13) The solid-state imaging device according to (12), wherein a plane area of ​​the first semiconductor element is smaller than a plane area of ​​the semiconductor layer when viewed from a thickness direction of the semiconductor layer. (14) The solid-state imaging device according to (12) or (13), wherein the first semiconductor element is mounted on the semiconductor layer via a bump electrode. (15) The solid-state imaging device according to any one of (10) to (14), wherein a second semiconductor element is mounted on the second surface of the semiconductor layer and includes a circuit electrically connected to the pixel circuit. (16) The solid-state imaging device according to (15), wherein a third semiconductor element is further mounted on the second semiconductor element and includes a circuit electrically connected to the pixel circuit. (17) The solid-state imaging device according to any one of (1) to (16), further comprising a second photoelectric conversion element located in the insulator in the imaging region. (18) The solid-state imaging device according to (17), wherein the second photoelectric conversion element includes an organic photoelectric conversion element.

[0142] This application claims the benefit of Japanese Priority Patent Application JP2022-181092 filed in the Japan Patent Office on November 11, 2022, the entire contents of which are incorporated herein by reference.

[0143] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may be made depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. A solid-state imaging device, comprising: a semiconductor layer including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type located in an imaging region in which a plurality of first photoelectric conversion elements for converting light into electric charges are arranged, the second conductivity type being a type opposite to the first conductivity type; An insulator is provided on a first surface of the semiconductor layer on a light incident side; a first guard ring, which is disposed in the insulator along an outer periphery of the imaging region, comprises a metal material, and is electrically connected to the first semiconductor region of the semiconductor layer; as well as A separation insulator is disposed in the semiconductor layer along an outer periphery of the imaging region and along an inner periphery of the first guard ring and electrically separates the first guard ring from the second semiconductor region.

2. The solid-state imaging device according to claim 1, wherein A carrier region of the second conductivity type is formed in a portion of the first surface of the semiconductor layer and is located between the second semiconductor region and the first guard ring, and a junction depth of the carrier region is shallower than a junction depth of the second semiconductor region, and The separation insulator is formed to have a depth that at least divides the carrier region.

3. The solid-state imaging device according to claim 1, wherein The separation insulator is provided to penetrate from the first surface of the semiconductor layer to a second surface opposite to the first surface.

4. The solid-state imaging device according to claim 3, further comprising a second guard ring provided in the semiconductor layer along an outer periphery of the first guard ring and provided to penetrate from the first surface to the second surface of the semiconductor layer, in, The separation insulator is formed to have the same cross-sectional structure as that of the second guard ring.

5. The solid-state imaging device according to claim 4, wherein The second protection ring is disposed along the inner periphery of the cutting area.

6. The solid-state imaging device according to claim 4, wherein A plurality of the second guard rings are arranged along the outer periphery of the first guard ring.

7. The solid-state imaging device according to claim 1, wherein The first guard ring includes tungsten (W).

8. The solid-state imaging device according to claim 1, wherein The separation insulator includes at least one inorganic insulating material selected from SiO2 and SiN.

9. The solid-state imaging device according to claim 1, wherein The first semiconductor region includes an n-type semiconductor region or an n-type semiconductor substrate, and The second semiconductor region includes a p-type semiconductor region or a p-type well region.

10. The solid-state imaging device according to claim 1, further comprising: a pixel in which, in a region corresponding to the first photoelectric conversion element, an optical filter and an optical lens are sequentially disposed on the first surface of the semiconductor layer via the insulator; as well as A pixel circuit is provided on a second surface side of the semiconductor layer opposite to the first surface and processes charges transferred from the plurality of first photoelectric conversion elements. The solid-state imaging device according to claim 10 , further comprising a back-side illumination configuration.

12. The solid-state imaging device according to claim 10, wherein In the outer periphery of the imaging region, a first semiconductor element is mounted on the first surface of the semiconductor layer via the insulator, and includes a circuit electrically connected to the pixel circuit.

13. The solid-state imaging device according to claim 12, wherein: When viewed from the thickness direction of the semiconductor layer, the planar area of ​​the first semiconductor element is smaller than the planar area of ​​the semiconductor layer.

14. The solid-state imaging device according to claim 12, wherein: The first semiconductor element is mounted on the semiconductor layer via a bump electrode.

15. The solid-state imaging device according to claim 10, wherein The second semiconductor element is mounted on the second surface of the semiconductor layer and includes a circuit electrically connected to the pixel circuit.

16. The solid-state imaging device according to claim 15, wherein A third semiconductor element is further mounted on the second semiconductor element and includes a circuit electrically connected to the pixel circuit. 17 . The solid-state imaging device according to claim 1 , further comprising a second photoelectric conversion element located in the insulator in the imaging region.

18. The solid-state imaging device according to claim 17, wherein The second photoelectric conversion element includes an organic photoelectric conversion element.

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