Semiconductor heterojunction composite substrate and preparation method thereof

Abstract

The present application discloses a semiconductor heterojunction composite substrate and a preparation method thereof. The composite substrate comprises: an epitaxial layer; a first buffer layer, located on one side of the epitaxial layer, wherein the material of the first buffer layer comprises a two-dimensional van der Waals material; and a first substrate, located on a side of the first buffer layer facing away from the epitaxial layer, wherein the first substrate and the epitaxial layer have different crystal forms, so as to solve the problem in related technologies that heterojunction epitaxy reduces the performance of power devices due to crystal defects.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor heterojunction composite substrate and a method for preparing the semiconductor heterojunction composite substrate. Background Art

[0002] Currently, silicon carbide homoepitaxial growth technology is relatively mature, generally utilizing a step-flow growth method. However, heteroepitaxial growth technology still presents certain challenges. For example, 3C / 4H heterojunctions are typically achieved by growing 3C crystals on 4H substrates. However, this method struggles to produce high-quality epitaxial material at the wafer level. Epitaxial layers produced using this method often exhibit double-position boundary (DPB) crystal defects. This is because the surface layer of a 4H substrate can have either ABC or ACB arrangements, resulting in 3C crystals with either ABC or ACB patterns. When grains with these two different arrangements come into contact, DPBs form. Because these defects are thermodynamically stable, there are currently no methods to eliminate them. The presence of DPBs increases carrier scattering and reduces channel mobility. Therefore, obtaining high-quality wafer-scale 3C-SiC epitaxial layers through heteroepitaxial growth remains technically challenging, and existing solutions are unable to achieve this goal. With advances in liquid-phase growth technology, growth techniques for large-scale 3C substrates will gradually advance. Currently, 4-inch N-type 3C-SiC has begun commercialization. Summary of the Invention

[0003] The present application provides a semiconductor heterojunction composite substrate and a method for preparing the semiconductor heterojunction composite substrate, so as to solve the problem in the related art that heterojunction epitaxy reduces the performance of power devices due to crystal defects.

[0004] According to one aspect of the present application, a semiconductor heterojunction composite substrate is provided, comprising: an epitaxial layer; a first buffer layer, located on one side of the epitaxial layer, the material of the first buffer layer comprising a two-dimensional van der Waals material; and a first substrate, located on a side of the first buffer layer facing away from the epitaxial layer, wherein the first substrate and the epitaxial layer have different crystal forms.

[0005] Optionally, the two-dimensional van der Waals material includes graphene and / or transition metal chalcogenides.

[0006] Optionally, the first buffer layer and the first substrate form a composite layer, and the semiconductor heterojunction composite substrate includes multiple layers of the composite layer.

[0007] Optionally, the thickness of the first buffer layer is less than or equal to 0.5 μm.

[0008] According to another aspect of the present application, a method for preparing a semiconductor heterojunction composite substrate is provided, which is used to prepare any one of the semiconductor heterojunction composite substrates, and the preparation method includes the following steps: providing an epitaxial layer, forming a first buffer layer on one side of the epitaxial layer, wherein the material of the first buffer layer is a two-dimensional van der Waals material; providing a wafer, wherein the wafer and the epitaxial layer have different crystal forms, and modifying a partial area on one side of the wafer so that the wafer forms a first film layer and a second film layer that are stacked, wherein the first film layer is the area of ​​the wafer that has undergone the modification treatment, and the second film layer is the area of ​​the wafer that has not undergone the modification treatment; bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer to obtain a first composite structure; and peeling the first film layer from the first composite structure, wherein the second film layer constitutes a first substrate.

[0009] Optionally, the step of forming the first buffer layer on one side of the epitaxial layer includes: covering the two-dimensional van der Waals material with a polymer to obtain a first composite layer; covering the first composite layer on the epitaxial layer, wherein the two-dimensional van der Waals material is in contact with the epitaxial layer; after the first composite layer and the epitaxial layer are bonded, the polymer is peeled off, and the remaining two-dimensional van der Waals material constitutes the first buffer layer.

[0010] Optionally, the modification process includes ion implantation or laser heating modification.

[0011] Optionally, the step of bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer includes: bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer to obtain a preliminary composite structure; applying pressure to the epitaxial layer in the preliminary composite structure along a second direction, wherein the second direction is the direction from the epitaxial layer to the first buffer layer; and performing a first annealing treatment on the preliminary composite structure to obtain the first composite structure.

[0012] Optionally, the step of peeling off the first film layer includes: performing a second annealing treatment on the first composite structure to obtain a second composite structure; peeling off the first film layer from the second composite structure to obtain a third composite structure; and performing a third annealing treatment on the third composite structure, wherein the second film layer constitutes a first substrate.

[0013] Optionally, the temperature of the first annealing treatment is less than or equal to the temperature of the second annealing treatment, and the temperature of the second annealing treatment is less than or equal to the temperature of the third annealing treatment.

[0014] The technical solution of the present invention is applied to provide a semiconductor heterojunction composite substrate. In this composite substrate structure, a first buffer layer is added between a first substrate of different crystal forms and an epitaxial layer. The material of the buffer layer is a two-dimensional van der Waals material. Since the two-dimensional van der Waals material has an adjustable band structure and extremely high carrier mobility, the atomic layers are connected by van der Waals forces without dangling bonds, and an atomically smooth interface can be obtained. At the same time, the problem of lattice constant mismatch and thermal expansion coefficient mismatch of the materials on both sides of the heterojunction can be solved by slipping between material layers, and the interface stress release can be significantly improved. Combined with the extremely high carrier mobility between layers, the on-state resistance of a vertical structure power device manufactured using the heterojunction can be greatly reduced, thereby improving the performance of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of this application. The exemplary embodiments and descriptions of this application are intended to explain this application and do not constitute an improper limitation on this application. In the accompanying drawings:

[0016] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor heterojunction composite substrate provided according to an embodiment of the present application;

[0017] Figure 2 is a schematic cross-sectional structure diagram of another semiconductor heterojunction composite substrate provided according to an embodiment of the present application;

[0018] Figure 3 is a schematic cross-sectional structure diagram of another semiconductor heterojunction composite substrate provided according to an embodiment of the present application;

[0019] Figure 4 is a schematic cross-sectional structure diagram of another semiconductor heterojunction composite substrate provided according to an embodiment of the present application;

[0020] Figure 5 This is a flow chart of a method for preparing a semiconductor heterojunction composite substrate provided in accordance with an embodiment of the present application;

[0021] Figure 6 This is a flow chart of another method for preparing a semiconductor heterojunction composite substrate provided according to an embodiment of the present application.

[0022] The above drawings include the following reference numerals:

[0023] 10. Epitaxial layer; 11. Second substrate; 12. Second buffer layer; 13. Drift layer; 20. First buffer layer; 30. First substrate; 50. Composite layer. DETAILED DESCRIPTION

[0024] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0025] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] As described in the background technology, there are still certain problems in the prior art of silicon carbide heteroepitaxial technology. 3C / 4H heterojunctions are usually obtained by epitaxially growing 3C crystals on 4H substrates. Since the arrangement order of the surface layer of the 4H substrate can be ABC or ACB, the 3C crystals formed can be ABC or ACB. When the grains of two different arrangement orders come into contact, DPB will be formed. Since this defect is thermodynamically stable, there is currently no relevant means to eliminate it. The presence of DPB will increase the scattering of carriers and reduce channel mobility. In order to solve the above technical problems, the present application provides a semiconductor heterojunction composite substrate and a method for preparing a semiconductor heterojunction composite substrate.

[0028] According to one aspect of the present application, a semiconductor heterojunction composite substrate is provided, such as Figures 1 to 4 As shown, the heterojunction composite substrate includes: an epitaxial layer 10; a first buffer layer 20, located on one side of the epitaxial layer 10, and the material of the first buffer layer 20 includes a two-dimensional van der Waals material; a first substrate 30, located on the side of the first buffer layer 20 away from the epitaxial layer 10, wherein the first substrate 30 and the epitaxial layer 10 have different crystal forms.

[0029] In the above-mentioned heterojunction composite substrate structure, a first buffer layer is added between the first substrate of different crystal forms and the epitaxial layer. The material of the first buffer layer includes a two-dimensional van der Waals material. Since the two-dimensional van der Waals material has an adjustable band structure and extremely high carrier mobility, the first substrate and the atomic layer of the epitaxial layer are connected by van der Waals forces without dangling bonds, and an atomically smooth interface can be obtained. At the same time, the matching of the lattice constants and the thermal expansion coefficients of the materials on both sides of the heterojunction of different materials can be improved through slip between the material layers, and the interface stress release between the first substrate of different crystal forms and the epitaxial layer can be significantly improved. Combined with the extremely high carrier mobility between the layers, the on-state resistance of the vertical structure power device manufactured using the heterojunction can be greatly reduced, thereby improving the performance of the power device.

[0030] In some optional embodiments, the material of the epitaxial layer and the first substrate may include silicon carbide material.

[0031] Power devices are a core component of modern energy systems. Silicon carbide (SiC), a representative material for third-generation semiconductors, is widely used in power devices due to its excellent properties. Applications include electric vehicles, data centers, smart grids, and renewable energy systems. 4H-SiC, the most widely used SiC in industry, has a large band gap (Eg) of 3.2 eV and high thermal conductivity. Compared to the band gap of silicon (Si) (1.1 eV), devices fabricated with 4H-SiC can reduce the thickness of the drift layer and increase the doping concentration while maintaining a constant withstand voltage, thereby reducing the device's forward on-resistance and reverse leakage current. Because commercially available substrates are prone to defects, all device active regions are fabricated in SiC epitaxial layers. This makes the quality of the epitaxial layer crucial to device performance. The step flow growth technique, in particular, achieves high surface quality and low defect density while maintaining high epitaxial growth rates.

[0032] In some optional embodiments, the crystal type of the epitaxial layer may include a 4H crystal type, and the crystal type of the first substrate is a 3C crystal type.

[0033] Specifically, in the hexagonal structure of silicon carbide, the C-Si diatomic layer exists in three non-equivalent positions: A, B, and C. Due to the different arrangement orders of the C-Si diatomic layer in the silicon carbide structure, silicon carbide can appear in a variety of polymorphs with different structures. For example, the 3C crystal form follows <111> The order of arrangement of directions is ABC, and the 4H crystal form is along <0001> The order of orientation is ABCB, and the band gap of SiC polytypes increases with the percentage of hexagonal lattice structure. Among them, 3C silicon carbide has a cubic structure and the smallest band gap of 2.3eV. While the small band gap reduces the critical breakdown electric field, it also reduces the SiC / SiO2 interface attitude by two orders of magnitude. The gate oxide channel mobility of 3C-SiC can reach 100-370cm 2 / Vs. At the same time, the barrier height between 3C-SiC and SiO2 is much greater than that between 4H-SiC and SiO2, which significantly reduces the gate-drain tunneling current under large gate drive voltage.

[0034] Furthermore, if Figure 1 As shown, the first substrate 30 is a 3C crystal type, the epitaxial layer 10 is a 4H crystal type, and the crystal orientation of the 3C crystal type is <111> , the crystal orientation of 4H crystal form is <0001> , due to the 3C crystal form <111> The lattice constant of the direction is similar to that of the 4H crystal form. <0001> The lattice constants of the directions are basically consistent, which makes the interface stress on both sides of the first buffer layer 20 small and there is basically no lattice mismatch. Therefore, an atomically flat plane can be formed at the interface of the epitaxial 3C crystal on the 4H substrate, reducing the scattering of carriers and reducing the channel resistance, so that the device has better stability and reliability. In addition, for 3C crystal silicon carbide (3C-SiC), the close-packed plane is the (111) crystal plane, and the selection of <111> The crystal orientation helps in the subsequent peeling of 3C-SiC, reduces the difficulty of peeling, and obtains a complete single crystal film.

[0035] Without considering SiC's spontaneous polarization, the 3C / 4H heterojunction forms an ideal quantum well structure. Due to the strong electron affinity of 3C, electrons are concentrated at the interface of the 3C / 4H heterojunction near the 3C junction, separating the electrons from the charge centers. This drastically reduces Coulomb scattering and forms a two-dimensional electron gas with extremely high mobility. However, when considering SiC's spontaneous polarization, 3C-SiC epitaxy on the interface between 4H-SiC and Si yields a two-dimensional hole gas, while epitaxy on the C-surface yields a two-dimensional electron gas. Compared to AlGaN / GaN, the 3C / 4H quantum well structure avoids the lattice mismatch and composition diffusion issues. The resulting two-dimensional electron or hole gas experiences minimal scattering and has extremely high mobility, significantly improving the low carrier mobility at the gate oxide interface, reducing the channel resistance and switching losses of power devices, and improving their frequency response. Furthermore, during reverse blocking, the depletion layer resides within the 4H drift layer, which does not affect the device's withstand voltage capability.

[0036] Among them, carrier mobility determines the on-resistance and frequency characteristics of power devices. Power devices with high carrier mobility have large current capacity and frequency response. For planar 4H-SiC MOSFET, due to the high temperature (about 1300℃) when manufacturing gate oxide, SiC / SiO2 has C residues and dangling bonds, resulting in a high density of interface states, which makes the channel carrier mobility low (20~40cm 2 / Vs), the threshold voltage of the device drifts, which seriously affects the on-resistance, frequency characteristics and reliability of the device. If the channel is annealed in an atmosphere containing N or P to achieve the effect of passivating the interface state, this method has limited elimination of the interface state and is incompatible with existing process lines. It requires additional equipment to carry out, resulting in increased costs. In addition, increasing the thickness of the gate oxide layer can reduce the electric field strength and tunneling current inside the gate oxide, improve the reliability of the gate oxide, but reduce the driving capability of the transistor and damage the switching speed and power characteristics of the device. Another commonly used method is to use a trench gate structure, which reduces the channel interface state by placing the gate oxide interface in a trench inside the epitaxial layer, thereby increasing the channel mobility (60~90cm 2 / Vs), but the device manufactured by this method is expensive, has lower uniformity than the planar gate structure, and its mobility is still far lower than its intrinsic mobility.

[0037] In some optional embodiments, such as Figures 1 to 4 As shown, the epitaxial layer 10 may include a second substrate 11, a second buffer layer 12, and a drift layer 13, wherein the drift layer 13 is in contact with the first buffer layer 20. Figure 2As shown, a first buffer layer 20 and a first substrate 30 are sequentially stacked on a side of the drift layer 13 facing away from the second substrate 11 .

[0038] Specifically, at least the second substrate and the drift layer have a 4H crystal type.

[0039] In some alternative embodiments, the two-dimensional van der Waals material includes graphene and / or a transition metal chalcogenide.

[0040] Specifically, graphene is composed of a single layer of carbon atoms tightly arranged into a two-dimensional honeycomb lattice. Its surface is relatively flat and has no dangling bonds, which helps to form an atomically flat interface, reduce interface roughness, thereby reducing carrier scattering and improving mobility. The graphene layers are connected by van der Waals forces, have good flexibility and slip properties, and can effectively release the stress generated by the difference in lattice constant and thermal expansion coefficient between 3C-SiC and 4H-SiC, avoiding the formation of cracks or dislocations at the interface, thereby improving the integrity and reliability of the composite structure. In addition, graphene has an extremely high electron mobility (up to 10 4 ~10 6 cm 2 / Vs), which can significantly improve the conductivity of vertical power devices fabricated on heterojunction composite substrates, reduce on-state resistance, increase frequency response speed, and reduce switching losses. Introducing graphene between epitaxial layers of different crystal types and the first substrate can reduce the interface state density at the interface between the epitaxial layer and the first substrate, improve the interface quality of the gate oxide layer, reduce threshold voltage drift and reverse leakage current, and enhance device stability and reliability.

[0041] Furthermore, transition metal dichalcogenides (TMDs) possess excellent interlayer slip and flexibility, effectively modulating the lattice mismatch between different crystalline semiconductor materials and relieving stress at the interface. This can reduce crystal defects such as dislocations, cracks, and double-position boundaries (DPBs) at the interface, thereby maintaining the integrity of the composite structure and improving device performance. As the first buffer layer, TMDs not only reduce the interface state density, minimize carrier scattering at the interface, and increase channel carrier mobility, but can also, under specific conditions, form a two-dimensional electron gas (2DEG) or hole gas, significantly reducing the forward on-resistance of power devices and improving frequency response, thereby increasing device switching speed and reducing switching losses. TMDs inherently possess high carrier mobility, providing a high-mobility channel for carriers, enabling rapid carrier passage even at heterojunction interfaces, thus avoiding mobility degradation caused by interface defects. In addition, the thermal expansion coefficient of TMDs is closer to that of 4H-SiC and 3C-SiC, which helps reduce thermal stress during temperature changes, avoid structural damage caused by thermal mismatch, and improve the stability and reliability of the composite substrate under different temperature conditions. In addition, TMDs can form stable chemical bonds with SiC materials, enhance the bonding strength between the upper and lower materials, improve the uniformity and stability of the bonding interface, and help maintain the integrity of the composite substrate structure and the long-term reliability of the device.

[0042] In some optional embodiments, such as Figure 3 As shown, the first buffer layer 20 and the first substrate 30 form a composite layer 50 , and the semiconductor heterojunction composite substrate includes multiple composite layers 50 .

[0043] Specifically, there is a multilayer composite layer between the epitaxial layer and the first substrate, and the multilayer composite layer includes a first buffer layer composed of a two-dimensional van der Waals material such as graphene and TMDs. Since the two-dimensional van der Waals material has excellent interlayer slip, this means that each layer of material can slide slightly relative to its adjacent layer. This sliding ability allows stress to be released and dispersed between layers instead of being concentrated at a single interface, thereby reducing the accumulation of interfacial stress and avoiding the formation of cracks and the generation of dislocations. The interlayer distance of the multilayer composite layer can be adjusted by selecting different materials, growth conditions or applied stress. Different interlayer distances mean that the material can have a larger adaptability when thermally expanding or contracting, which helps to release thermal stress caused by the mismatch of thermal expansion coefficients of different materials during temperature changes. Multilayer composite layers can absorb and transform the stress generated during the bonding process. When stress acts on the composite structure, some layers or interlayer interfaces in the multilayer composite layer can transform the lateral stress into interlayer slip or lattice changes. This transformation process can effectively relieve and absorb stress, prevent it from being transferred to the interface or active layer, and maintain the electrical and mechanical properties of the material. At the same time, the multilayer composite layer can optimize stress release by adjusting the chemical bond properties between the layers.

[0044] In other optional embodiments, such as Figure 4 As shown, the semiconductor heterojunction composite substrate includes multiple layers of first buffer layer 20 .

[0045] Specifically, a multilayer first buffer layer 20 is provided between the epitaxial layer 10 and the first substrate 30. This multilayer first buffer layer 20, particularly one made of a two-dimensional van der Waals material with interlayer slip, reduces the accumulation of interfacial stress, avoids the formation of cracks and the generation of dislocations, and helps release thermal stress caused by the mismatch of thermal expansion coefficients of different materials during temperature changes. When stress acts on the composite structure, some layers or interlayer interfaces in the multilayer first buffer layer 20 can convert lateral stress into interlayer slip or lattice changes, preventing its transfer to the interface or active layer, thereby maintaining the electrical and mechanical properties of the material. Furthermore, the multilayer first buffer layer 20 can optimize stress release by adjusting the chemical bond properties between the layers.

[0046] In some optional embodiments, the thickness of the first buffer layer is less than or equal to 0.5 μm.

[0047] Specifically, the epitaxial layer and the first substrate have different crystal forms and different doping concentrations. Moreover, the greater the difference in doping concentration between the epitaxial layer and the first substrate, the greater the difference in lattice constant, and the greater the thickness of the first buffer layer should be. However, the maximum thickness of the first buffer layer shall not exceed 0.5µm to avoid affecting the electrical properties of the semiconductor heterojunction composite substrate.

[0048] Furthermore, the primary function of the first buffer layer is to improve the electrical properties of the interface between the epitaxial layer and the first substrate, reducing the interface state density and increasing carrier mobility. However, if the first buffer layer is too thick, it introduces additional resistance, increasing the series resistance of the entire structure, thereby affecting the device's conduction performance and switching speed, increasing power loss, and reducing efficiency. Specifically, a thinner first buffer layer, less than 0.5µm, improves device conduction performance and switching speed while more flexibly adapting to the lattice mismatch and thermal expansion coefficient difference between the upper and lower materials, effectively relieving stress and reducing the occurrence of cracks or dislocations. Furthermore, a thinner first buffer layer avoids the introduction of more defects at the interface, such as dangling bonds, impurities, or impure phases, thereby reducing the interface state density and improving the interface purity, thereby improving carrier transport efficiency near the interface. In terms of fabricating the first buffer layer, a thinner buffer layer ensures good interface bonding at a lower temperature, reducing the thermal budget of the first substrate behind the epitaxial layer and minimizing the probability of material performance degradation or even damage.

[0049] According to another aspect of the present application, a method for preparing a semiconductor heterojunction composite substrate is provided, which is used to prepare any semiconductor heterojunction composite substrate, such as Figure 5 As shown, the preparation method comprises the following steps:

[0050] Step S401: providing an epitaxial layer, and forming a first buffer layer on one side of the epitaxial layer, wherein the material of the first buffer layer is a two-dimensional van der Waals material;

[0051] Step S402: providing a wafer, wherein the wafer and the epitaxial layer have different crystal forms, and performing a modification treatment on a portion of one side of the wafer to form a first film layer and a second film layer stacked on the wafer, wherein the first film layer is the region of the wafer that has been modified, and the second film layer is the region of the wafer that has not been modified;

[0052] Step S403: bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer to obtain a first composite structure;

[0053] Step S404: peeling the second film layer from the first composite structure, wherein the first film layer constitutes the first substrate.

[0054] Using the above-mentioned preparation method of the embodiment of the present application, a first buffer layer is formed on the epitaxial layer. The material of the buffer layer is a two-dimensional van der Waals material. Since the two-dimensional van der Waals material has an adjustable band structure and extremely high carrier mobility, the atomic layers are connected by van der Waals forces without dangling bonds, and an atomically flat interface can be obtained. At the same time, the lattice constant mismatch and thermal expansion coefficient mismatch of the materials on both sides of the heterojunction can be solved by slipping between the material layers, significantly improving the interface stress release. Combined with the extremely high carrier mobility between the layers, the on-state resistance of the vertical structure power device manufactured using the heterojunction can be greatly reduced, thereby improving the performance of the power device. In addition, after the wafer is modified and bonded to the epitaxial layer, the wafer is directly peeled off under low temperature conditions, and the wafer portion is transferred to the epitaxial layer to form the first substrate. This can avoid the direct epitaxy of different crystal substrate film layers on the substrate and the generation of various structural defects, overcome the lattice constant mismatch and insufficient processing accuracy problems in the heterojunction substrate, and obtain a high-quality semiconductor heterojunction composite substrate at the wafer level.

[0055] Among them, the above-mentioned preparation method can avoid the various defects caused by directly epitaxially growing a 3C crystal on a 4H substrate. At the same time, the thermal budget is small, and a wafer-level 3C / 4H heterojunction composite substrate can be obtained, which is suitable for large-scale industrial production. At the same time, considering the problem of processing accuracy, a first buffer layer is added to the 3C / 4H heterojunction composite substrate. The presence of the first buffer layer can significantly improve the tolerance of process errors and solve the problems of stress and defects caused by the mismatch of lattice parameters and thermal expansion coefficients of the current heterojunction epitaxy. In addition, the first buffer layer can also increase the number of two-dimensional electron gas conductive channels, further improving the current handling capacity of the device. The composite substrate is compatible with existing process lines. When using the composite substrate to manufacture devices, the existing process can be fully utilized, and the device development cost is low. Furthermore, the use of a low-temperature exfoliation bonding technique (less than 1000°C) instead of the existing high-temperature chemical vapor deposition (1400-1650°C) yields a (3C / buffer layer) n / 4H-SiC heterojunction composite substrate structure. This significantly reduces the thermal budget and improves the quality of the heterojunction. This overcomes the issues of polycrystallization and scalability of the heterojunction epitaxial material previously encountered in related patents using high-temperature chemical vapor deposition technology, enabling the production of wafer-scale (3C / buffer layer) n / 4H-SiC heterojunction composite structures. In contrast, the 3C film in the resulting 3C / 4H heterojunction using high-temperature chemical vapor deposition is typically polycrystalline and contains numerous defects, making it impossible to achieve uniform wafer-scale material. The inclusion of a first buffer layer in the heterojunction structure overcomes the high stress and defects associated with the limited processing capabilities of existing processes, improves the tolerance to machining accuracy, and significantly improves the quality and reliability of the heterojunction interface.

[0056] The following is a more detailed description of exemplary embodiments of the method for preparing a trench power device provided by the present application. However, these exemplary embodiments can be implemented in a variety of different forms and should be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0057] In some optional embodiments, the step of forming a first buffer layer on one side of the epitaxial layer includes: step S4011, covering the two-dimensional van der Waals material with a polymer to obtain a first composite layer; step S4012, covering the first composite layer on the epitaxial layer, wherein the two-dimensional van der Waals material is in contact with the epitaxial layer; step S4013, after the first composite layer and the epitaxial layer are bonded, the polymer is peeled off, and the remaining two-dimensional van der Waals material constitutes the first buffer layer.

[0058] Specifically, the material transfer technique requires lower temperatures, which can reduce the thermal budget and the generation of thermal stress in the composite structure, thereby improving the integrity of the composite substrate. Transferring two-dimensional van der Waals materials through polymers avoids the difficulty of growing TMDs directly on the epitaxial layer, reduces the limitations of the epitaxial layer's surface quality and the complexity of growth conditions, and simplifies the process flow. Using polymers for two-dimensional van der Waals material transfer technology can produce a high-quality first substrate while avoiding the formation of DPB defects directly during the epitaxial growth process, thereby improving device performance and reliability.

[0059] In some specific implementation methods, during the process of bonding the first composite layer to the epitaxial layer, pressure is applied to the epitaxial layer to reduce the gap between the two, increase the bonding strength between the two-dimensional van der Waals material and the epitaxial layer, and make the two-dimensional van der Waals film and the epitaxial layer more closely contacted, thereby reducing the interface stray particles and defects between the two and improving the carrier migration efficiency of the composite substrate.

[0060] Specifically, the pressure may be 0.1N to 100kN, and the time for maintaining the pressure may be 0.5 to 10 minutes, which is not specifically limited in this application.

[0061] Furthermore, by making the diameter of the first composite layer larger than the diameter of the epitaxial layer, a complete first buffer layer is formed on the entire epitaxial layer.

[0062] In some optional implementations, the polymer may include polydimethylsiloxane (PDMS). The method for transferring a two-dimensional van der Waals material to an epitaxial layer using PDMS specifically includes: first, covering the TMDs material with a polymer (such as PDMS) for bonding; then, after bonding is complete, lifting the polymer and covering it on the treated epitaxial layer, wherein the diameter of the TMDs material must be larger than the diameter of the epitaxial layer to ensure complete bonding; then, applying pressure to increase the bonding strength between the TMDs material and the epitaxial layer, wherein the pressure is 0.1N to 100kN and maintained for 0.5 to 10 minutes; then, after the pressure is maintained, peeling off the polymer to complete the transfer of the TMDs material to the epitaxial layer.

[0063] In some optional embodiments, the first buffer layer is a two-dimensional van der Waals material, preferably graphene or transition metal chalcogenides (TMDs). For example, when using a transition metal chalcogenide material as the buffer layer, the crystal structure of the transition metal chalcogenide material should be hexagonal or rhombohedral. The dimensions of the first buffer layer should be no smaller than those of the epitaxial layer. Depending on the doping type, doping concentration, and exfoliation thickness of 3C-SiC and 4H-SiC, the first buffer layer can be a single buffer layer formed of a transition metal chalcogenide material or a composite buffer layer formed of two or more materials. The greater the difference in doping concentration between 4H-SiC and 3C-SiC, the greater the difference in lattice constant, and the greater the thickness of the composite buffer layer. However, the maximum thickness of the composite buffer layer must not exceed 0.5µm to avoid affecting the electrical properties of the composite substrate. Fabrication of single-layer or multi-layer composite buffer layers based on transition metal chalcogenides is accomplished using material transfer or metal organic chemical vapor deposition (MPCVD). The material transfer method is preferred because the quality of wafer-scale TMD materials grown directly on 4H-SiC is currently poor.

[0064] In another example, when graphene is used as the first buffer layer, <0001> The epitaxial layer is annealed in an argon atmosphere to directly form a graphene buffer layer by evaporating Si atoms from the surface of the epitaxial layer material. The argon pressure during annealing is 0.5-2 bar, the annealing temperature is 1300-1600°C, and the annealing time is 1-60 minutes. Because this method undergoes a high-temperature process, the graphene buffer layer obtained using this method can only be used for a single buffer layer or the bottom layer of a multi-layer buffer layer. The buffer layer above the graphene cannot withstand such high temperatures. The same method as steps S4011 to S4013 can be used to transfer the graphene material so that the graphene is formed on the side of the TMDs material facing away from the epitaxial layer.

[0065] In some optional implementation methods, the modification process includes ion implantation or laser heating modification.

[0066] Specifically, the wafer may include high-quality <111> A 3C-SiC wafer with an ABC-ordered C-Si diatomic layer is prepared by ion implantation or laser heating to create microcracks and form a defect layer. Under high vacuum conditions, the 3C-SiC wafer can be bonded to the first buffer layer. The defect layer serves as the peeling interface for the 3C-SiC thin film to be peeled off from the original wafer, providing a microcrack path for subsequent peeling without damaging the wafer. This results in a high-quality 3C-SiC film layer, which reduces carrier scattering at the interface, improves carrier mobility, and directly enhances device performance.

[0067] In some optional embodiments, the surface of the 3C-SiC wafer is polished before the wafer is subjected to ion implantation or laser heating modification to planarize the processed surface.

[0068] Specifically, the flatness of the wafer surface directly affects the energy loss of the implanted particles and the uniformity of the implantation depth. A flat surface can ensure consistent implantation conditions in all areas, avoiding ion beam deviation or divergence caused by surface undulations, thereby achieving more uniform and controllable implantation dose and depth. Ion implantation or laser heating modification treatment will produce defects on the wafer surface. The density of surface defects is positively correlated with the surface roughness. Reducing the surface roughness by polishing can reduce the generation of these defects, improve the crystal quality of the 3C-SiC film after stripping, and reduce the instability of electrical properties. Moreover, whether it is ion implantation or laser heating, the purpose is to form microcracks inside the wafer to facilitate the subsequent stripping process. The flattened surface helps the microcracks to expand evenly along the expected depth, ensuring the controllability of the stripping process and the integrity of the stripped film, and avoiding breakage or discontinuity of the film during the stripping process.

[0069] Furthermore, ion implantation is the process of accelerating charged particles and injecting them below the surface of the material to change the chemical composition or introduce defects. After the ions are implanted into the wafer, the wafer is heated to promote the expansion of microcracks. This process is usually carried out in an inert gas atmosphere, and the heating temperature and time need to be carefully designed to ensure that the microcracks can effectively extend while avoiding excessive damage to the wafer. The ion implantation depth is 50~3000nm, and the ion implantation depth is less than the thickness of the wafer, so that the wafer forms a modified first film layer and an unmodified second film layer. Through the precisely controlled ion implantation and stripping process, the DPB defects commonly seen in high-temperature growth of 3C-SiC are avoided, and other types of defects caused by lattice mismatch, such as dislocations and stacking faults, are reduced, significantly improving the crystal quality of the thin film layer.

[0070] In addition, the wafer is subjected to laser heating modification treatment, using a high-energy laser to locally heat the 3C-SiC wafer. Through the energy and focus of the laser, the heat is concentrated at a predetermined depth of the wafer, usually between 50 and 3000nm, to induce modification of the lattice structure without damaging the deeper parts of the wafer. During the laser heating process, the temperature of the wafer will increase significantly, resulting in enhanced atomic activity in the lattice and the formation of a defect layer. Laser heating modification stripping technology avoids thermal stress during high-temperature chemical vapor deposition through heat input, reduces the formation of defects such as DPB, significantly reduces the defect density of the stripped film, and improves the electrical properties of the material. Laser heating modification stripping technology can achieve wafer-scale film preparation, ensuring the thickness uniformity and lattice consistency of the film material over a large size range.

[0071] In some optional embodiments, the step of bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer includes: first, bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer to obtain a preliminary composite structure; then, applying pressure to the epitaxial layer in the preliminary composite structure along a second direction, wherein the second direction is the direction of the epitaxial layer pointing to the first buffer layer; then, performing a first annealing treatment on the preliminary composite structure to obtain a first composite structure.

[0072] Specifically, the existing technology uses high-temperature chemical vapor deposition (preparation temperature of 1400-1650°C) to form the buffer layer and the first substrate. Due to the high temperature during the growth process, high-temperature chemical vapor deposition can generate crystal defects such as double-position boundary (DPB) defects, dislocations, and stacking faults. This can lead to lattice mismatch and other problems during the growth of the buffer layer and the first substrate due to thermodynamic instability. The above-mentioned preparation method uses a low-temperature bonding process (preparation temperature less than 1000°C) to form the heterojunction composite substrate. Since the bonding process is carried out at low temperature, the impact of high temperature on thermal stress is reduced, thereby reducing the generation of defects. The bonding process achieves an atomically flat interface, reduces dangling bonds and stress at the interface, and improves the electrical performance of the interface. This is in stark contrast to the inevitable interface defects in direct epitaxial growth processes. The bonding process is more conducive to the formation of high-quality heterojunctions. The bonding technology can produce wafer-scale 3C-SiC thin films, which is more difficult to achieve using high-temperature epitaxial growth, especially when addressing lattice mismatch. Wafer-scale material preparation facilitates large-scale industrial production, reduces manufacturing costs, and improves device uniformity and consistency. The bonding process is performed at a lower temperature, significantly reducing the thermal budget and avoiding potential damage to materials and structures caused by high temperatures. This is crucial for maintaining material performance stability and extending device life. Because the bonding process enables the use of thinner 3C-SiC wafers, it reduces the consumption of expensive silicon carbide material and lowers manufacturing costs. Furthermore, the simplified process flow and reduced thermal budget also reduce energy consumption and equipment investment.

[0073] In some optional embodiments, before bonding the first buffer layer on the epitaxial layer and the second film layer on the wafer, chemical mechanical polishing is performed on the surfaces of the first buffer layer and the second film layer to be bonded.

[0074] Specifically, the surface roughness of the bonding surface can be less than 0.2 nm. As the roughness of the bonding surface decreases, the vacuum bonding strength increases. Setting the surface roughness to less than 0.2 nm is beneficial to improving the structural strength of the prepared composite substrate.

[0075] In some optional embodiments, the step of peeling off the second film layer includes: first, performing a second annealing treatment on the first composite structure to obtain a second composite structure; then, peeling off the second film layer from the second composite structure to obtain a third composite structure; then, performing a third annealing treatment on the third composite structure, wherein the second annealing treatment can accelerate the expansion of microcracks generated by the ion implantation layer or the laser heating layer, which is conducive to peeling off the second film layer, so that the second film layer constitutes the first substrate.

[0076] Specifically, the first composite structure undergoes a second annealing treatment to accelerate the propagation of microcracks generated in the ion-implanted layer or laser-heated layer. During the second annealing, the composite structure is heated to a higher temperature, increasing the thermal energy of the atoms within the material. This increased thermal energy increases their mobility and vibration amplitude, making it easier for atoms at the edge of the microcrack to overcome energy barriers, thereby promoting crack propagation. At high temperatures, atomic diffusion is accelerated, allowing them to move more quickly from the crack tip, leading to crack extension. Ion implantation or laser heating, while simultaneously forming microcracks in the wafer, also generates localized stress fields within the material. Furthermore, as the temperature increases, the elastic modulus and hardness of the material decrease, which helps release stress caused by lattice damage and lattice mismatch. This stress release creates a more flexible environment for microcrack propagation, promoting uniform crack growth from the damaged layer until it completely penetrates the 3C-SiC film, facilitating film debonding. During the second annealing process, defects in the damaged layer (either the ion-implanted layer or the laser-heated modified layer) further aggregate and degrade, forming crack paths that are more susceptible to propagation. The degradation of the damaged layer reduces the local strength of the material, making it easier for microcracks to propagate along the damage path until they completely penetrate the film.

[0077] Furthermore, the third composite structure undergoes a third annealing treatment to repair lattice damage in the film. Heating provides sufficient energy to rearrange atoms in the damaged area, repairing lattice defects introduced by the exfoliation process. This thermally activated repair mechanism allows defects such as dislocations, vacancies, or dangling bonds to be eliminated or minimized through diffusion, recombination, or other microscopic mechanisms during the annealing process. The exfoliation process generates stress in the second film layer, which can cause lattice damage. During the annealing process at the third temperature, the stress is released due to the thermal expansion of the material and the enhanced thermal motion of atoms, thereby helping to repair the lattice damage caused by stress. Stress release helps restore the lattice structure and reduce the density of cracks and dislocations. The annealing treatment allows defects within the material to aggregate and eliminate, and the repair of lattice damage directly improves the material's electrical properties. Carrier migration in a material with a complete lattice and no high-density defects faces less resistance and higher mobility, which helps reduce the on-state resistance of the device, reduce switching losses, and improve the frequency response characteristics of the power device.

[0078] In some specific embodiments, the third annealing process is performed in a hydrogen atmosphere.

[0079] Specifically, hydrogen molecules can diffuse into the damaged areas of the material and react chemically with dangling bonds or defects. Hydrogen combines with carbon or silicon atoms in the silicon carbide material to form hydrides. These hydrides are unstable at high temperatures and will decompose or rearrange, which helps to repair lattice damage, reduce dangling bonds, thereby reducing interface state density and improving carrier mobility. At the same time, annealing is carried out in a hydrogen atmosphere, which not only promotes the repair of lattice damage, but also prevents oxidation of the material at high temperatures. The protective atmosphere ensures the chemical stability of the material during the repair process and avoids additional damage caused by high-temperature oxidation.

[0080] In some optional embodiments, the temperature of the first annealing treatment is less than or equal to the temperature of the second annealing treatment, and the temperature of the second annealing treatment is less than or equal to the temperature of the third annealing treatment.

[0081] Specifically, the temperature of the first annealing treatment can be 300-600°C, the temperature of the second annealing treatment can be 600-800°C, and the temperature of the third annealing treatment can be 800-1000°C. The temperature of the first annealing treatment is less than or equal to the temperature of the second annealing treatment. The lower temperature of the first annealing treatment helps reduce thermal damage introduced during the bonding process. While high-temperature annealing can effectively relieve stress, it also accelerates atomic diffusion and phase transformation, leading to increased interface damage at lattice mismatch sites. By performing the first annealing treatment at a lower temperature, initial damage can be minimized, maintaining the structural stability and electrical properties of the material. Due to the lower temperature of the first annealing treatment, while optimizing the interfacial bonding between the 3C-SiC film and the buffer layer, it does not significantly change the internal structure of the material. This ensures that chemical bonding at the interface occurs under mild conditions, reduces interfacial reactions or phase transformations caused by high temperatures, and maintains the purity and stability of the interface. The lower temperature of the first annealing treatment provides the material with an appropriate preconditioning state, enabling more efficient and controllable microcrack propagation in the subsequent second annealing treatment. This provides a more stable and stress-relieving starting point for the subsequent exfoliation process, helping to ensure uniformity and controllability. By setting the first annealing temperature at a lower range, the physical and chemical properties of the material can be protected from the effects of high-temperature annealing. For example, buffer layer materials such as graphene are sensitive to high temperatures, and a lower first annealing temperature can avoid adverse effects on these materials' properties, preserving their high carrier mobility and low defect density.

[0082] Furthermore, the temperature of the second annealing process can be lower than or equal to that of the third annealing process. The second annealing process is performed at a relatively low temperature primarily to accelerate and control the growth of microcracks generated in the ion-implanted or laser-heated layer. The temperature range of 600-800°C provides sufficient thermal energy to promote the extension of microcracks from the damaged layer toward the surface, while avoiding excessively high temperatures that could lead to uncontrolled crack growth or cause unwanted phase changes in the material. Annealing within this temperature range helps ensure uniform and complete debonding of the 3C-SiC film from the original substrate. During the second annealing process, increased thermal motion within the material helps initially repair lattice damage, such as microcracks and dislocations, induced during the debonding process. Although more thorough repair occurs during the third annealing process, this initial repair at the second annealing temperature improves the material's initial state and reduces the damage required for subsequent high-temperature annealing. The high-temperature treatment of the second annealing process prior to debonding helps release interfacial stresses accumulated during the bonding process, reducing additional damage caused by uneven stress during debonding. Annealing at the second temperature manages the stress distribution within the material, ensuring a smoother and more controllable debonding process. During the third annealing process, the material is placed in a hydrogen atmosphere and heated to 800-1000°C. This higher temperature range, combined with hydrogen chemical reactions, deeply repairs the lattice damage within the 3C-SiC film after exfoliation. The presence of hydrogen can react with dangling bonds in the damaged area to form stable hydrides, which helps eliminate these dangling bonds, further reducing the interface state density and increasing carrier mobility. By maintaining the second annealing temperature lower than the third annealing temperature, the material can be ensured to be in a purer and more stable state during the third annealing, which is conducive to further optimizing the material's electrical properties, improving carrier mobility, reducing the device's on-state resistance and switching losses, and enhancing the stability of the composite substrate structure.

[0083] The first annealing treatment time, the second annealing treatment time, and the third annealing treatment time are all 1 to 120 minutes, and the specific annealing time is not specifically limited in this application.

[0084] This embodiment relates to a specific method for preparing a semiconductor heterojunction composite substrate, such as Figure 6 As shown, the following steps are included:

[0085] Step S1: Provide N-type or P-type doping <111> Oriented 3C-SiC wafers and <0001> 4H-SiC epitaxial material with a crystal orientation or off-axis angle less than or equal to 4°;

[0086] Step S2: injecting hydrogen ions and / or helium ions into the 3C-SiC wafer to a preset depth, or using a laser to heat the material at a predetermined depth to form a defect layer;

[0087] Step S3: The 4H-SiC epitaxial layer obtained in step S1 is subjected to chemical mechanical polishing, cleaning, and plasma treatment, and a single layer or composite buffer layer composed of a two-dimensional van der Waals material is transferred onto the 4H-SiC conventional epitaxial material in step S1 using a material transfer technique, or a TMDs material is directly grown on the 4H-SiC epitaxial layer using a MOCVD method;

[0088] Step S4: chemically mechanically polishing, cleaning, and plasma treating the unbonded side of the 3C-SiC wafer, applying pressure under vacuum conditions and performing a first annealing treatment to bond the unbonded side to the upper surface of the first buffer layer to form a 3C-SiC / buffer layer / 4H-SiC epitaxial layer bonded wafer;

[0089] Step S5: After performing a second annealing treatment on the 3C-SiC / buffer layer / 4H-SiC epitaxial layer bonded wafer, the 3C-SiC film is peeled off to obtain a composite substrate.

[0090] In step S1 of the above embodiment, the <111> Orient the 3C-SiC wafer and transfer it to <0001> The axial 4H-SiC epitaxial layer can avoid various structural defects caused by direct epitaxy on the substrate. Among them, due to the limitations of the silicon carbide cutting process, the orientation of the 3C-SiC wafer is different from that of the 4H-SiC epitaxial layer. <111> There will be a certain deviation in direction, but the deviation cannot exceed 1°.

[0091] In step S2 of the above embodiment, atoms will generate microcrack defects after being heated, and the defects will expand during the heating process. The depth of the defect layer is less than the depth of the wafer. The defect layer is used as a peeling interface to peel the 3C-SiC thin film layer from the original wafer, providing a microcrack path for subsequent peeling without damaging the wafer, thereby forming a high-quality 3C-SiC film layer, reducing carrier scattering at the interface, improving carrier mobility, and directly improving device performance.

[0092] In addition, the implanted surface of the 3C-SiC wafer is polished for planarization before hydrogen and / or helium ion implantation or laser heating modification. Subsequently, hydrogen and / or helium ions are implanted into the 3C-SiC wafer to form an implanted defect layer, thereby generating microcracks. The ion implantation depth is 50 to 3000 nm, and the ion implantation depth is set to be less than the thickness of the 3C-SiC wafer. Alternatively, laser heating is used to generate microcracks in the material at a specific depth to form the defect layer, and the laser heating depth is less than the thickness of the 3C-SiC wafer.

[0093] In step S3 of the above embodiment, the plasma includes one or more of nitrogen, oxygen, and helium, and the vacuum degree of the vacuum treatment is 1×10-7 ~1×10 -8 mbar. The specific plasma and vacuum levels are not limited in this application. Common wafer-level high-quality TMDs materials are grown on substrate materials such as Cu, Ni, Pt, Au, Si, and SiO2. The specific steps for transferring TMDs materials to the 4H-SiC epitaxial layer may include:

[0094] First, a polymer such as PDMS is used to cover the TMDs material;

[0095] Then, after the bonding is completed, the polymer is lifted up and covered on the treated 4H-SiC substrate. The diameter of the TMDs material must be larger than that of the 4H-SiC substrate to ensure complete bonding.

[0096] Then, pressure is applied to increase the bonding strength between the TMDs material and the 4H-SiC substrate. The pressure ranges from 0.1N to 100kN, and the holding time ranges from 0.5 to 10 minutes.

[0097] Finally, after the pressure holding is completed, the polymer is peeled off, and the TMDs material is transferred to the 4H-SiC epitaxial layer.

[0098] If graphene is used as the material of the first buffer layer, <0001> The off-axis epitaxial 4H-SiC material with different crystal orientations is annealed in an argon atmosphere to directly form a graphene buffer layer by evaporating Si atoms on the SiC surface. The argon pressure during annealing is 0.5~2 bar and the annealing temperature is 1300~1600℃. The transition layer process manufactured by this method is simpler than the material transfer technology.

[0099] In step S4 of the above embodiment, applying pressure during the bonding process can reduce the distance between the interfaces of the bonding materials, increase the temperature to increase the energy of the atoms, promote the formation of chemical bonds at the interface of the first buffer layer, and ensure the bonding strength of the bonding surface. No dangling bonds are formed between the chemical bonds at the interface of the first buffer layer and the TMDs material. In the first buffer layer structure, the upper and lower surfaces of the transition layer need to form chemical bonds with 3C-SiC and 4H-SiC respectively, and there are no chemical bonds between the TMDs layers inside the first buffer layer that can be used to release stress.

[0100] In step S5 of the above embodiment, the second annealing is to promote the expansion of microcracks generated by ion implantation or laser heating to facilitate subsequent stripping. After stripping, a third annealing is performed in a hydrogen atmosphere.

[0101] In some specific embodiments, steps S3 to S5 can be repeated multiple times to obtain a (3C / buffer layer)n / 4H structure (n=1, 2, 3, ...). The thickness and period n of the buffer layer sublayers can be determined based on process accuracy and design parameters such as the material's doping concentration and thickness. The thickness of the buffer layer sublayers can be made uniform, or they can be increased or decreased to achieve a gradient buffer layer.

[0102] Specifically, each bonding surface of the heterojunction is chemically mechanically polished through steps S3 and S4, and vacuum bonding is performed after plasma treatment to form a bonded wafer. Through step S5, the composite wafer is placed in an atmosphere of an inert gas such as nitrogen, a certain pressure is applied, and the bonded wafer is annealed at a first temperature to improve the interface bonding strength of the buffer layer. After the annealing is completed, the pressure is unloaded and a second annealing is performed at a second temperature. This annealing is to accelerate the expansion of microcracks generated by the ion implantation layer or the laser heating layer, so as to peel off the remaining 3C substrate to obtain a 3C-SiC film, and the surface of the composite substrate is ground and polished to remove the surface lattice damage layer. Thereafter, annealing is performed again in a hydrogen atmosphere at a third temperature to repair the lattice damage of the film. The temperature of the third annealing is 600~900℃. Thus, the following is obtained. Figure 1 The semiconductor heterojunction composite substrate structure shown.

[0103] Specifically, the first annealing temperature may be 300-600° C., the pressure applied during annealing may be 0.1-100 kN, the second annealing temperature may be 600-800° C., and the third annealing temperature may be 800-1000° C., no pressure is applied during the second and third annealings, and the three annealing treatment times are all 1-120 min.

[0104] In addition, after the chemical mechanical polishing treatment in steps S3 and S4 in the above embodiment, the surface roughness of the bonding surface can be less than 0.2 nm. As the surface roughness decreases, the vacuum bonding strength increases. Setting the surface roughness to less than 0.2 nm helps to improve the structural strength of the prepared composite substrate.

[0105] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0106] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A semiconductor heterojunction composite substrate, characterized in that: include: epitaxial layer; a first buffer layer, located on one side of the epitaxial layer, wherein the material of the first buffer layer comprises a two-dimensional van der Waals material; a first substrate, located on a side of the first buffer layer away from the epitaxial layer, wherein the first substrate and the epitaxial layer have different crystal types; The material of the epitaxial layer and the first substrate includes silicon carbide, the crystal type of the epitaxial layer includes 4H crystal type, the crystal type of the first substrate is 3C crystal type, and the crystal orientation of the 3C crystal type is <111> The crystal orientation of the 4H crystal form is <0001> , the epitaxial layer is bonded to the first substrate through the first buffer layer, The first buffer layer and the first substrate form a composite layer, and the semiconductor heterojunction composite substrate includes multiple layers of the composite layer.

2. The semiconductor heterojunction composite substrate according to claim 1, characterized in that The two-dimensional van der Waals material includes graphene and / or transition metal chalcogenides.

3. The semiconductor heterojunction composite substrate according to claim 1, characterized in that The thickness of the first buffer layer is less than or equal to 0.5 μm.

4. A method for preparing a semiconductor heterojunction composite substrate, characterized in that: For preparing the semiconductor heterojunction composite substrate according to any one of claims 1 to 3, the preparation method comprises the following steps: Providing an epitaxial layer, and forming a first buffer layer on one side of the epitaxial layer, wherein the material of the first buffer layer is a two-dimensional van der Waals material; Providing a wafer, wherein the wafer and the epitaxial layer have different crystal forms, and performing a modification treatment on a portion of one side of the wafer so that the wafer forms a first film layer and a second film layer that are stacked, wherein the first film layer is the region of the wafer that has undergone the modification treatment, and the second film layer is the region of the wafer that has not undergone the modification treatment; bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer to obtain a first composite structure; The first film layer is peeled off from the first composite structure, wherein the second film layer constitutes a first substrate.

5. The preparation method according to claim 4, characterized in that The step of forming the first buffer layer on one side of the epitaxial layer includes: Covering the two-dimensional van der Waals material with a high molecular weight polymer to obtain a first composite layer; covering the first composite layer on the epitaxial layer, wherein the two-dimensional van der Waals material is in contact with the epitaxial layer; After the first composite layer and the epitaxial layer are bonded together, the high molecular polymer is peeled off, and the remaining two-dimensional van der Waals material constitutes the first buffer layer.

6. The preparation method according to claim 4, characterized in that The modification process includes ion implantation or laser heating modification.

7. The preparation method according to claim 4, characterized in that The step of bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer includes: Laminating the first buffer layer on the epitaxial layer and the second film layer on the wafer to obtain a preliminary composite structure; Applying pressure to the epitaxial layer in the prepared composite structure along a second direction, wherein the second direction is a direction from the epitaxial layer to the first buffer layer; A first annealing treatment is performed on the preliminary composite structure to obtain the first composite structure.

8. The preparation method according to claim 7, characterized in that The step of peeling off the second film layer includes: performing a second annealing treatment on the first composite structure to obtain a second composite structure; peeling the second film layer from the second composite structure to obtain a third composite structure; A third annealing treatment is performed on the third composite structure, wherein the second film layer constitutes a first substrate.

9. The preparation method according to claim 8, characterized in that The temperature of the first annealing treatment is lower than or equal to the temperature of the second annealing treatment, and the temperature of the second annealing treatment is lower than or equal to the temperature of the third annealing treatment.

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