Method for optimizing overlay mark signal

Abstract

The invention discloses a method for optimizing an overlay mark signal, and the method comprises the steps: forming a filler pattern in a first region of a bottom material layer, enabling the reflectivity of a filling material of the filler pattern to be greater than that of the bottom material layer, enabling the first region to intersect with at least part of a formation region of an overlay mark, the pattern density of the filler pattern ensures that the top surface of the first region is flat. And forming a front-layer material layer and forming a front-layer overlay mark in the formation area of the overlay mark of the front-layer material layer. Forming a current-layer material layer and forming a current-layer overlay mark in the formation area of the overlay mark of the current-layer material layer; the overlay marks of the front layer and the current layer form an overlay mark combination structure, and overlay mark signals are improved through the flat structure of the top surface of the first area and the large reflectivity of the filling material. According to the invention, the adverse effect of a large-area area at the bottom of the front-layer overlay mark on an overlay mark signal can be prevented, so that the overlay mark signal can be optimized, and the precision of overlay measurement is improved.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for optimizing an overlay mark signal. Background Art

[0002] Advanced semiconductor processes have two limiting parameters for photolithography, critical dimension (CD) and overlay. As the critical dimension becomes smaller and smaller, the requirements for overlay error become higher and higher. The pattern remaining in the photoresist after exposure and development must be aligned with the existing pattern on the wafer substrate to prevent short circuits and open circuits in the device. The relative position between the current pattern and the reference pattern is the overlay error. The overlay error is a parameter to measure the alignment quality, which directly measures the position deviation between the current layer and the reference layer. Since the photolithography OVL mark signal is easily affected by the previous layer process, as the precision requirements of advanced technology become higher and higher, the process becomes more and more complex, and the unstable photolithography OVL Mark signal introduces overlay error, so the OVL Mark signal is particularly important for measurement.

[0003] With the development of technology, the application of chips is becoming more and more extensive. With the increasing requirements for process precision, the accuracy and precision of measurement are becoming higher and higher. As the process becomes more and more complex, affected by the lower film, that is, the film formed by the previous process, in the existing method, the signal of the mark can be improved by designing multiple segments, but the problem of the mark signal cannot be completely solved.

[0004] Each layer of Mark occupies a position, which can ensure that all Marks do not interfere with each other (except IMP layer). Therefore, only when the layer has a Mark, other layers are blank areas, such as a blank area of ​​30 microns * 30 microns in size. The blank area is an area without graphics. The multiple layers at the bottom of the Mark include superimposed layers of photoresist or film.

[0005] like Figure 1 As shown, it is a layout of the existing overlay mark; the overlay mark 102 is usually located in the cutting path 101. When there is no other overlay mark pattern at the bottom of the layer overlay mark 102, there is no blank area. The overlay marks of other layers can be set in other areas such as area 103.

[0006] The measurement signal of the overlay mark measurement machine is realized by optical signal. The diffraction intensity of the optical signal will be affected by the side wall angle of the grating of the bottom overlay mark, which will affect the overlay accuracy. The side wall angle of the grating of the bottom overlay mark needs to go through etching, film deposition and chemical mechanical planarization grinding and other processes. The bottom overlay mark here is also the front layer overlay mark, which will form an overlay mark combination structure with the current layer overlay mark. The offset between the front layer overlay mark and the current layer overlay mark can be obtained by measurement, thereby obtaining the overlay mark signal.

[0007] The material of the metal wire in the back-end process is often copper, which is formed by the Damascus process. In the dual Damascus process, through holes and top metal wires are formed at the same time. In the Damascus process, grooves are first engraved, then copper is filled, and finally polished. Due to the fluctuation of local polishing rate in chemical mechanical planarization, the fluctuation is more obvious for large areas, resulting in erosion and wear. When the Damascus process is used to form the bottom layer overlay mark at the same time, the bottom layer overlay mark will also be eroded and worn. Figure 2 FIG. 1 is a cross-sectional structural diagram of a front layer overlay mark in an existing overlay mark combination, including:

[0008] Bottom substrate 201, front material layer 203 corresponding to the front overlay mark. The material of the front material layer 203 includes a low dielectric constant material, and a nitrogen-doped silicon nitride (NDC) layer 202 is also formed at the bottom of the front material layer 203. A plurality of copper strips 204 are used to form the front overlay mark. The copper strips 204 are all formed by the Damascus process, so erosion defects shown in the dotted circle 206 and wear defects shown in the dotted circle 207 will be formed. Erosion and wear defects will lead to: when measuring the overlay mark, the unevenness of the lower layer pattern will cause the reflected light to be messy, or even asymmetric on the left and right, and the left and right asymmetry introduced by the reflected light will cause deviation in the overlay measurement.

[0009] In the prior art, the bottom layers of the previous layer with the overlay mark are all blank structures. Figure 3 As shown, it is a cross-sectional structure diagram of the existing overlay mark combination structure after it is formed, and the overlay marks corresponding to the metal line and the bottom through hole are as follows:

[0010] The bottom substrate 201 includes a bottom structure 301 , an NDC layer 302 and a bottom interlayer film 303 . Figure 3 Only the formation area of ​​the overlay mark is shown. It can be seen that no graphic structure is formed in the bottom interlayer film 303, which is a blank area.

[0011] The front material layer 203 includes an interlayer film 305 , an NDC layer 306 , an NFDARC layer 307 , a TiN layer 308 , and an oxide layer 309 . Figure 3 In the embodiment, the patterned TiN layer 308 and the oxide layer 309 are used as the front layer overlay marks. Figure 3 The structure shown is the structure in the dual damascene process. If the single damascene process is used, Figure 2 The copper stripe 204 shown constitutes the front layer overlay mark.

[0012] The current material layer includes a SOC layer 310 , a silicon bottom anti-reflective coating 311 and a photoresist 304 .

[0013] The photoresist 304 of the current material layer is patterned, and the current layer overlay mark is composed of the patterned photoresist 304 . Summary of the invention

[0014] The technical problem to be solved by the present invention is to provide a method for optimizing the overlay mark signal, which can prevent the large area at the bottom of the front layer overlay mark from adversely affecting the overlay mark signal, thereby optimizing the overlay mark signal and improving the accuracy of overlay measurement.

[0015] In order to solve the above technical problems, the method for optimizing the overlay mark signal provided by the present invention comprises the steps of:

[0016] A bottom material layer is provided, and a filler pattern is formed in a first area of ​​the bottom material layer. The reflectivity of the filling material of the filler pattern is greater than the reflectivity of the bottom material layer. The first area intersects with at least a portion of the area where the overlay mark is formed. The pattern density of the filler pattern meets the requirements of plasma etching and chemical mechanical polishing processes for pattern density to ensure that the top surface of the first area is flat. The top surface of the first area includes the top surface of the bottom material layer and the top surface of the filler pattern.

[0017] A front material layer is formed and a front overlay mark is formed in a formation region of the overlay mark of the front material layer.

[0018] A current material layer is formed and a current overlay mark is formed in the overlay mark formation area of ​​the current material layer; the front layer overlay mark and the current layer overlay mark form an overlay mark combination structure, and the flat structure of the top surface of the first area and the high reflectivity of the filling material are used to improve the overlay mark signal.

[0019] A further improvement is that the material of the bottom material layer includes a low dielectric constant material; and the filling material includes metal.

[0020] A further improvement is that the material of the front material layer includes a low dielectric constant material, and the front material layer is used to form a through hole or a metal line.

[0021] The front layer overlay mark and the through hole pattern are defined simultaneously.

[0022] A further improvement is that a metal hard mask layer is formed on the top surface or inside the front material layer, the front overlay mark is composed of the patterned metal hard mask layer or the front overlay mark is composed of a through hole in the formation area of ​​the overlay mark.

[0023] A further improvement is that the material of the metal hard mask layer includes TiN.

[0024] A further improvement is that the current material layer includes photoresist, and the current overlay mark and metal line pattern are defined simultaneously.

[0025] The current layer overlay mark is composed of the patterned current layer material layer.

[0026] A further improvement is that the current material layer also includes a SOC layer and a silicon bottom anti-reflection coating.

[0027] A further improvement is that the metal material of the filling material, the through hole and the metal line is the same.

[0028] A further improvement is that the metal material of the filling material includes copper.

[0029] A further improvement is that the filler pattern is formed by densely arranging first strips, the size of which meets the requirements of the design rules and is smaller than the minimum wavelength of the signal received by the measuring machine of the overlay mark, so as to ensure that the signal of the bottom material layer will not be absorbed by the measuring machine, thereby avoiding interference with the measurement result of the overlay mark signal.

[0030] This avoids interference with the measurement result of the overlay mark signal.

[0031] A further improvement is that the wavelength range of the signal received by the measuring machine for overlay marking is 300nm-700nm, and the width of the first strip is less than 300nm.

[0032] A further improvement is that the first stripe and the pattern of the front layer overlay mark are perpendicular.

[0033] A further improvement is that the first area is completely located directly below the area where the overlay mark is formed.

[0034] A further improvement is that the first region and the region where the overlay mark is formed are located within a dicing street or within a chip.

[0035] A further improvement is that the maximum value of the formation area of ​​the overlay mark is more than 30 microns*30 microns.

[0036] Unlike the prior art, in which the bottom layers of the front-layer overlay marks constituting the overlay mark combination structure are all large blank areas, in the present invention, a filler pattern is set in the underlying material layer at the bottom of the front-layer overlay mark, and the pattern density of the existing large blank area and the reflectivity of the material are changed by the filler pattern, wherein the setting of the pattern density of the filler pattern is compatible with the requirements of the plasma etching and chemical mechanical polishing processes for pattern density, and combined with the setting of the width of the line of the filler pattern, i.e., the first bar, can improve the ability to suppress random noise, which is beneficial to improve the tolerance to flattening of the etching or chemical mechanical polishing process in the process of forming the front-layer overlay mark, and prevent the pattern of the front-layer overlay mark from erosion or wear defects, thereby preventing the reflected light of the overlay mark measurement caused by erosion and wear defects from being disordered or even asymmetric, thereby preventing the disorder or asymmetry of the reflected light used for measurement from adversely affecting the overlay measurement accuracy.

[0037] The material of the filler pattern of the present invention has a higher reflectivity, so it can prevent the measurement signal from being transmitted from the underlying material layer, thus preventing the measurement signal from being reduced, that is, it can increase the measurement signal, thereby further optimizing the overlay mark signal and improving the measurement accuracy.

[0038] In addition, since the size of the filler pattern of the present invention is set independently, the size of the filler pattern can be set relatively small, such as less than 300nm, so that the substrate signal, i.e., the signal of the underlying material layer and the bottom of the underlying material layer, will not be absorbed by the measuring machine, thereby preventing the substrate signal from interfering with the measurement signal, thereby further improving the measurement result.

[0039] Therefore, the present invention can prevent the large area at the bottom of the front layer overlay mark from adversely affecting the overlay mark signal, thereby optimizing the overlay mark signal and improving the accuracy of overlay measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0041] Figure 1 It is a layout of existing overlay marks;

[0042] Figure 2 It is a cross-sectional structural diagram of a front layer overlay mark in an existing overlay mark combination;

[0043] Figure 3 It is a cross-sectional structural diagram of the existing overlay mark combination structure after it is formed;

[0044] Figure 4 is a flow chart of a method for optimizing an overlay mark signal according to an embodiment of the present invention;

[0045] Figure 5It is a cross-sectional structural diagram after the overlay mark combination structure is formed by the method for optimizing the overlay mark signal according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] like Figure 4 As shown in FIG. 1 , it is a flow chart of a method for optimizing an overlay mark signal according to an embodiment of the present invention; Figure 5 FIG. 1 is a cross-sectional structural diagram of an overlay mark combination structure formed by a method for optimizing an overlay mark signal according to an embodiment of the present invention; the method for optimizing an overlay mark signal according to an embodiment of the present invention comprises the following steps:

[0047] Step S101, providing a bottom material layer 403, forming a filler pattern 413 in a first area of ​​the bottom material layer 403, the reflectivity of the filling material of the filler pattern 413 is greater than the reflectivity of the bottom material layer 403, the first area intersects with at least a portion of the area where the overlay mark is formed, the pattern density of the filler pattern 413 meets the requirements of plasma etching and chemical mechanical polishing processes for pattern density to ensure that the top surface of the first area is flat, and the top surface of the first area includes the top surface of the bottom material layer 403 and the top surface of the filler pattern 413.

[0048] In the embodiment of the present invention, the material of the bottom material layer 403 includes a low dielectric constant material; and the filling material includes metal.

[0049] The filler pattern 413 is formed by densely arranged first bars 414, the size of which meets the requirements of the design rules and is smaller than the minimum wavelength of the signal received by the measuring machine of the overlay mark, so as to ensure that the signal of the underlying material layer 403 will not be absorbed by the measuring machine, thereby avoiding interference with the measurement result of the overlay mark signal.

[0050] The first area is completely located directly below the area where the overlay mark is formed.

[0051] The first area and the formation area of ​​the overlay mark are located in the dicing road or in the chip. When located in the dicing road, the chip area will not be occupied. However, when the chip has a large size, the dicing road is too small to place enough overlay marks, so part of the overlay marks can be placed in the chip.

[0052] In some embodiments, the wavelength range of the signal received by the overlay mark measuring machine is 300 nm to 700 nm, and the width of the first strip 414 is less than 300 nm.

[0053] In some embodiments, the maximum size of the formation area of ​​the overlay mark is greater than 30 micrometers*30 micrometers.

[0054] Figure 5 In the embodiment, an NDC layer 402 and a bottom structure 401 are formed at the bottom of the bottom material layer 403. The bottom structure 401 may include a semiconductor substrate and a multi-layer interlayer film formed on the top of the semiconductor substrate.

[0055] Step S102 , forming a front material layer and forming a front layer overlay mark in the overlay mark formation region of the front material layer.

[0056] In the embodiment of the present invention, the material of the front material layer includes a low dielectric constant material. Figure 5 In the figure, the low dielectric constant material layer of the front material layer is indicated by reference numeral 405. A nitrogen-doped silicon carbide (NDC) layer 404 is formed at the bottom of the low dielectric constant material layer 405 to prevent the bottom metal layer from adversely affecting the low dielectric constant layer 405; an NDC layer 406 and a NFDARC layer 407 are formed on the top of the low dielectric constant layer 405. NFDARC represents fluorine-free DARC.

[0057] The front material layer is used to form through holes or metal lines.

[0058] The front layer overlay mark and the through hole pattern are defined simultaneously.

[0059] In the embodiment of the present invention, a metal hard mask layer is formed on the top surface or inside of the front material layer, and the front overlay mark is composed of the patterned metal hard mask layer. In other embodiments, the front overlay mark is composed of a through hole in the formation area of ​​the overlay mark.

[0060] The material of the metal hard mask layer includes a TiN layer 408 and an oxide layer 409 formed on the top of the TiN layer 408 . Figure 5 The structure of the formation area of ​​the overlay mark is shown in FIG. 1 . No chip structure is formed in the formation area of ​​the overlay mark, so the through hole pattern is not shown. Figure 5 It can be seen that the TiN layer 408 and the oxide layer 409 of the metal hard mask layer have been patterned, and these patterned structures serve as the front layer overlay marks.

[0061] In the embodiment of the present invention, the first bar 414 and the pattern of the front layer overlay mark can be at any angle, and the measurement signal can be optimized when the first bar 414 is set. In some preferred embodiments, the first bar 414 and the pattern of the front layer overlay mark are perpendicular, which can achieve the best optimization of the measurement signal.

[0062] Step S103, forming a current material layer and forming a current layer overlay mark in the formation area of ​​the overlay mark of the current material layer; the front layer overlay mark and the current layer overlay mark form an overlay mark combination structure, and the flat structure of the top surface of the first area and the high reflectivity of the filling material are used to improve the overlay mark signal.

[0063] In the embodiment of the present invention, the current material layer includes photoresist 412 .

[0064] The current material layer also includes a SOC layer 410 and a silicon bottom anti-reflective coating 411. The current layer overlay mark and the metal line pattern are defined simultaneously. Figure 5 Only the formation area of ​​the overlay mark is shown, and the chip structure is not shown, so the metal line pattern is not shown.

[0065] The current layer overlay mark is composed of the patterned current layer material layer. Figure 5 In the embodiment, the photoresist 412 of the current material layer is patterned, and the current layer overlay mark is composed of the patterned photoresist 412.

[0066] In the embodiment of the present invention, the metal material of the filling material, the through hole and the metal line is the same.

[0067] The metal material of the filling material includes copper.

[0068] In some embodiments, the via and the metal line of the top layer are formed simultaneously using a dual damascene process.

[0069] Different from the prior art in which the bottom layers of the front-layer overlay marks constituting the overlay mark combination structure are all large blank areas, in the embodiment of the present invention, a filler pattern 413 is set in the bottom material layer 403 at the bottom of the front-layer overlay mark, and the pattern density of the existing large blank area and the reflectivity of the material are changed by the filler pattern 413, wherein the setting of the pattern density of the filler pattern 413 is compatible with the requirements of the plasma etching and chemical mechanical polishing processes for pattern density, and combined with the setting of the width of the line of the filler pattern 413, i.e., the first bar 414, can improve the ability to suppress random noise, which is beneficial to improve the tolerance to flattening of the etching or chemical mechanical polishing process in the process of forming the front-layer overlay mark, and prevent the pattern of the front-layer overlay mark from erosion or wear defects, thereby preventing the reflected light of the overlay mark measurement caused by erosion and wear defects from being disordered or even asymmetric, thereby preventing the disorder or asymmetry of the reflected light used for measurement from adversely affecting the overlay measurement accuracy.

[0070] The material of the filler pattern 413 of the embodiment of the present invention has a higher reflectivity, so it can prevent the measurement signal from being transmitted from the underlying material layer 403, thereby preventing the measurement signal from being reduced, that is, increasing the measurement signal, thereby further optimizing the overlay mark signal and improving the measurement accuracy.

[0071] In addition, since the size of the filler pattern 413 of the embodiment of the present invention is independently set, the size of the filler pattern 413 can be set relatively small, such as less than 300nm, so that the substrate signal, i.e., the signal of the underlying material layer 403 and the bottom of the underlying material layer 403 will not be absorbed by the measuring machine, thereby preventing the substrate signal from interfering with the measurement signal, thereby further improving the measurement result.

[0072] Therefore, the embodiment of the present invention can prevent the large area at the bottom of the front layer overlay mark from adversely affecting the overlay mark signal, thereby optimizing the overlay mark signal and improving the accuracy of overlay measurement.

[0073] The Damascus technology production leads to large-area unevenness, even left-right asymmetry, resulting in deviation in overlay measurement. In order to improve the asymmetry of overlay marks in large areas introduced in the process, a filler substrate is added to the front layer in the embodiment of the present invention. The bottom layer of the front layer is a low dielectric constant material. In order to improve the reflectivity of the bottom layer, the front layer photolithography uses dense line patterns to replace the original photoresist completely covered area, where the original photoresist completely covered area is a blank area, which is subsequently etched, filled with copper and polished to form Figure 5 The filler pattern 413 in the figure. The dense lines are easily compatible with the grinding pattern density requirements of many plasma etching and chemical mechanical planarization processes. By improving the line width of the filler lines, the ability to suppress random noise is improved, and its tolerance to etching and chemical mechanical planarization can also be improved. The design of the filler uses the minimum specification, does not violate the minimum size of the design, and is close to the chip specification. The pattern width is less than 300nm, and the signal of the substrate will not be absorbed by the measurement machine. Therefore, the design with a size less than 300nm will not interfere with the measurement result signal.

[0074] Using ASML D4C (design for control) analog signal to add filler Figure 5 The contrast signal of the filler pattern 413 shown in the figure shows that, for example, the signal strength (SS) of the fourth layer via (Via4) to the fifth layer metal line (M5) varies with the wavelength. It can be seen that inserting dense lines or DBO style fillers can significantly increase SS. When the first strip 414 is perpendicular to the pattern of the front layer overlay mark, the corresponding SS increases from 0.2 to about 1.0, and the wavelength also changes greatly. The larger the SS, the stronger the sensitivity of the measurement, so inserting fillers can improve the detection sensitivity of the Via layer.

[0075] The SS measured on the product's V4, or Via4, is affected by different wavelengths. By combining actual measurement data and other important parameter analysis, it can be seen that the 90-degree measurement condition in the polarization direction is more advantageous. Its SS increases from the original 0.2 to 0.8, and the wavelength also fluctuates slightly, but the SS shows obvious peaks and troughs, which means it is more sensitive to detection.

[0076] The present invention has been described in detail above through specific embodiments, but these do not constitute a limitation of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A method for optimizing an overlay mark signal, characterized in that: Includes steps: Providing a bottom material layer, forming a filler pattern in a first region of the bottom material layer, wherein the reflectivity of the filler material of the filler pattern is greater than the reflectivity of the bottom material layer, and the first region intersects at least a portion of a region where an overlay mark is formed; the pattern density of the filler pattern meets the requirements of plasma etching and chemical mechanical polishing processes for pattern density, so as to ensure that the top surface of the first region is flat, and the top surface of the first region includes the top surface of the bottom material layer and the top surface of the filler pattern; forming a front material layer and forming a front overlay mark in a formation region of the overlay mark of the front material layer; forming a current material layer and forming a current overlay mark in a formation region of the overlay mark of the current material layer; The front layer overlay mark and the current layer overlay mark form an overlay mark combination structure, and the flat structure of the top surface of the first region and the high reflectivity of the filling material are used to improve the overlay mark signal.

2. The method for optimizing an overlay mark signal according to claim 1, wherein: The material of the bottom material layer includes a low dielectric constant material; and the filling material includes a metal.

3. The method for optimizing an overlay mark signal according to claim 2, wherein: The material of the front material layer includes a low dielectric constant material, and the front material layer is used to form a through hole or a metal line; The front layer overlay mark and the through hole pattern are defined simultaneously.

4. The method for optimizing an overlay mark signal according to claim 3, wherein: A metal hard mask layer is formed on the top surface or inside of the front material layer, and the front overlay mark is composed of the patterned metal hard mask layer or the front overlay mark is composed of a through hole in the formation area of ​​the overlay mark.

5. The method for optimizing an overlay mark signal according to claim 4, characterized in that: The material of the metal hard mask layer includes TiN.

6. The method for optimizing an overlay mark signal according to claim 4, wherein: The layer material layer includes photoresist, and the layer overlay mark and metal line pattern are defined simultaneously; The current layer overlay mark is composed of the patterned current layer material layer.

7. The method for optimizing an overlay mark signal according to claim 6, wherein: The current material layer also includes a SOC layer and a silicon bottom anti-reflection coating.

8. The method for optimizing an overlay mark signal according to claim 6, wherein: The filling material, the through hole and the metal line are made of the same metal material.

9. The method for optimizing an overlay mark signal according to claim 8, characterized in that: The metal material of the filling material includes copper.

10. The method for optimizing an overlay mark signal according to claim 1, wherein: The filler pattern is formed by densely arranging first bars, the size of which meets the requirements of design rules and is smaller than the minimum wavelength of the signal received by the measuring machine of the overlay mark, so as to ensure that the signal of the underlying material layer will not be absorbed by the measuring machine, thereby avoiding interference with the measurement result of the overlay mark signal.

11. The method for optimizing an overlay mark signal according to claim 10, wherein: The wavelength range of the signal received by the measuring machine for overlay marking is 300nm-700nm, and the width of the first strip is less than 300nm.

12. The method for optimizing an overlay mark signal according to claim 10, wherein: The first stripe is perpendicular to the pattern of the front layer overlay mark.

13. The method for optimizing an overlay mark signal according to claim 1, wherein: The first area is completely located directly below the area where the overlay mark is formed.

14. The method for optimizing an overlay mark signal according to claim 13, wherein: The first region and the region where the overlay mark is formed are located within a dicing street or within a chip.

15. The method for optimizing an overlay mark signal according to claim 14, wherein: The maximum value of the formation area of ​​the overlay mark is more than 30 microns*30 microns.

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